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c7b95171 MC |
1 | /* |
2 | * RISC-V Control and Status Registers. | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017-2018 SiFive, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2 or later, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
21 | #include "qemu/log.h" | |
22 | #include "cpu.h" | |
23 | #include "qemu/main-loop.h" | |
24 | #include "exec/exec-all.h" | |
25 | ||
c7b95171 MC |
26 | /* CSR function table public API */ |
27 | void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) | |
28 | { | |
29 | *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)]; | |
30 | } | |
31 | ||
32 | void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) | |
33 | { | |
34 | csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops; | |
35 | } | |
36 | ||
a88365c1 | 37 | /* Predicates */ |
0e62f92e | 38 | static RISCVException fs(CPURISCVState *env, int csrno) |
a88365c1 MC |
39 | { |
40 | #if !defined(CONFIG_USER_ONLY) | |
8e3a1f18 | 41 | /* loose check condition for fcsr in vector extension */ |
e91a7227 | 42 | if ((csrno == CSR_FCSR) && (env->misa_ext & RVV)) { |
0e62f92e | 43 | return RISCV_EXCP_NONE; |
8e3a1f18 | 44 | } |
b345b480 | 45 | if (!env->debugger && !riscv_cpu_fp_enabled(env)) { |
0e62f92e | 46 | return RISCV_EXCP_ILLEGAL_INST; |
a88365c1 MC |
47 | } |
48 | #endif | |
0e62f92e | 49 | return RISCV_EXCP_NONE; |
a88365c1 MC |
50 | } |
51 | ||
0e62f92e | 52 | static RISCVException vs(CPURISCVState *env, int csrno) |
8e3a1f18 | 53 | { |
e91a7227 | 54 | if (env->misa_ext & RVV) { |
0e62f92e | 55 | return RISCV_EXCP_NONE; |
8e3a1f18 | 56 | } |
0e62f92e | 57 | return RISCV_EXCP_ILLEGAL_INST; |
8e3a1f18 LZ |
58 | } |
59 | ||
0e62f92e | 60 | static RISCVException ctr(CPURISCVState *env, int csrno) |
a88365c1 MC |
61 | { |
62 | #if !defined(CONFIG_USER_ONLY) | |
0a13a5b8 AF |
63 | CPUState *cs = env_cpu(env); |
64 | RISCVCPU *cpu = RISCV_CPU(cs); | |
0a13a5b8 AF |
65 | |
66 | if (!cpu->cfg.ext_counters) { | |
67 | /* The Counters extensions is not enabled */ | |
0e62f92e | 68 | return RISCV_EXCP_ILLEGAL_INST; |
0a13a5b8 | 69 | } |
e39a8320 AF |
70 | |
71 | if (riscv_cpu_virt_enabled(env)) { | |
72 | switch (csrno) { | |
73 | case CSR_CYCLE: | |
db70794e BM |
74 | if (!get_field(env->hcounteren, COUNTEREN_CY) && |
75 | get_field(env->mcounteren, COUNTEREN_CY)) { | |
0e62f92e | 76 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
e39a8320 AF |
77 | } |
78 | break; | |
79 | case CSR_TIME: | |
db70794e BM |
80 | if (!get_field(env->hcounteren, COUNTEREN_TM) && |
81 | get_field(env->mcounteren, COUNTEREN_TM)) { | |
0e62f92e | 82 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
e39a8320 AF |
83 | } |
84 | break; | |
85 | case CSR_INSTRET: | |
db70794e BM |
86 | if (!get_field(env->hcounteren, COUNTEREN_IR) && |
87 | get_field(env->mcounteren, COUNTEREN_IR)) { | |
0e62f92e | 88 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
e39a8320 AF |
89 | } |
90 | break; | |
91 | case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: | |
92 | if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) && | |
93 | get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) { | |
0e62f92e | 94 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
e39a8320 AF |
95 | } |
96 | break; | |
8987cdc4 | 97 | } |
db23e5d9 | 98 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
8987cdc4 AF |
99 | switch (csrno) { |
100 | case CSR_CYCLEH: | |
db70794e BM |
101 | if (!get_field(env->hcounteren, COUNTEREN_CY) && |
102 | get_field(env->mcounteren, COUNTEREN_CY)) { | |
0e62f92e | 103 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
8987cdc4 AF |
104 | } |
105 | break; | |
106 | case CSR_TIMEH: | |
db70794e BM |
107 | if (!get_field(env->hcounteren, COUNTEREN_TM) && |
108 | get_field(env->mcounteren, COUNTEREN_TM)) { | |
0e62f92e | 109 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
8987cdc4 AF |
110 | } |
111 | break; | |
112 | case CSR_INSTRETH: | |
db70794e BM |
113 | if (!get_field(env->hcounteren, COUNTEREN_IR) && |
114 | get_field(env->mcounteren, COUNTEREN_IR)) { | |
0e62f92e | 115 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
8987cdc4 AF |
116 | } |
117 | break; | |
118 | case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: | |
119 | if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) && | |
120 | get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) { | |
0e62f92e | 121 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
8987cdc4 AF |
122 | } |
123 | break; | |
e39a8320 | 124 | } |
e39a8320 AF |
125 | } |
126 | } | |
a88365c1 | 127 | #endif |
0e62f92e | 128 | return RISCV_EXCP_NONE; |
a88365c1 MC |
129 | } |
130 | ||
0e62f92e | 131 | static RISCVException ctr32(CPURISCVState *env, int csrno) |
8987cdc4 | 132 | { |
db23e5d9 | 133 | if (riscv_cpu_mxl(env) != MXL_RV32) { |
0e62f92e | 134 | return RISCV_EXCP_ILLEGAL_INST; |
8987cdc4 AF |
135 | } |
136 | ||
137 | return ctr(env, csrno); | |
138 | } | |
139 | ||
a88365c1 | 140 | #if !defined(CONFIG_USER_ONLY) |
0e62f92e | 141 | static RISCVException any(CPURISCVState *env, int csrno) |
a88365c1 | 142 | { |
0e62f92e | 143 | return RISCV_EXCP_NONE; |
a88365c1 MC |
144 | } |
145 | ||
0e62f92e | 146 | static RISCVException any32(CPURISCVState *env, int csrno) |
8987cdc4 | 147 | { |
db23e5d9 | 148 | if (riscv_cpu_mxl(env) != MXL_RV32) { |
0e62f92e | 149 | return RISCV_EXCP_ILLEGAL_INST; |
8987cdc4 AF |
150 | } |
151 | ||
152 | return any(env, csrno); | |
153 | ||
154 | } | |
155 | ||
0e62f92e | 156 | static RISCVException smode(CPURISCVState *env, int csrno) |
a88365c1 | 157 | { |
0e62f92e AF |
158 | if (riscv_has_ext(env, RVS)) { |
159 | return RISCV_EXCP_NONE; | |
160 | } | |
161 | ||
162 | return RISCV_EXCP_ILLEGAL_INST; | |
a88365c1 MC |
163 | } |
164 | ||
0e62f92e | 165 | static RISCVException hmode(CPURISCVState *env, int csrno) |
ff2cc129 AF |
166 | { |
167 | if (riscv_has_ext(env, RVS) && | |
168 | riscv_has_ext(env, RVH)) { | |
169 | /* Hypervisor extension is supported */ | |
170 | if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || | |
171 | env->priv == PRV_M) { | |
0e62f92e | 172 | return RISCV_EXCP_NONE; |
e39a8320 | 173 | } else { |
0e62f92e | 174 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
ff2cc129 AF |
175 | } |
176 | } | |
177 | ||
0e62f92e | 178 | return RISCV_EXCP_ILLEGAL_INST; |
ff2cc129 AF |
179 | } |
180 | ||
0e62f92e | 181 | static RISCVException hmode32(CPURISCVState *env, int csrno) |
8987cdc4 | 182 | { |
db23e5d9 | 183 | if (riscv_cpu_mxl(env) != MXL_RV32) { |
d6f20dac AF |
184 | if (riscv_cpu_virt_enabled(env)) { |
185 | return RISCV_EXCP_ILLEGAL_INST; | |
186 | } else { | |
187 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; | |
188 | } | |
8987cdc4 AF |
189 | } |
190 | ||
191 | return hmode(env, csrno); | |
192 | ||
193 | } | |
194 | ||
0e62f92e | 195 | static RISCVException pmp(CPURISCVState *env, int csrno) |
a88365c1 | 196 | { |
0e62f92e AF |
197 | if (riscv_feature(env, RISCV_FEATURE_PMP)) { |
198 | return RISCV_EXCP_NONE; | |
199 | } | |
200 | ||
201 | return RISCV_EXCP_ILLEGAL_INST; | |
a88365c1 | 202 | } |
2582a95c HW |
203 | |
204 | static RISCVException epmp(CPURISCVState *env, int csrno) | |
205 | { | |
206 | if (env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) { | |
207 | return RISCV_EXCP_NONE; | |
208 | } | |
209 | ||
210 | return RISCV_EXCP_ILLEGAL_INST; | |
211 | } | |
a88365c1 MC |
212 | #endif |
213 | ||
c7b95171 | 214 | /* User Floating-Point CSRs */ |
605def6e AF |
215 | static RISCVException read_fflags(CPURISCVState *env, int csrno, |
216 | target_ulong *val) | |
c7b95171 | 217 | { |
fb738839 | 218 | *val = riscv_cpu_get_fflags(env); |
605def6e | 219 | return RISCV_EXCP_NONE; |
c7b95171 MC |
220 | } |
221 | ||
605def6e AF |
222 | static RISCVException write_fflags(CPURISCVState *env, int csrno, |
223 | target_ulong val) | |
c7b95171 MC |
224 | { |
225 | #if !defined(CONFIG_USER_ONLY) | |
c7b95171 MC |
226 | env->mstatus |= MSTATUS_FS; |
227 | #endif | |
fb738839 | 228 | riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT)); |
605def6e | 229 | return RISCV_EXCP_NONE; |
c7b95171 MC |
230 | } |
231 | ||
605def6e AF |
232 | static RISCVException read_frm(CPURISCVState *env, int csrno, |
233 | target_ulong *val) | |
c7b95171 | 234 | { |
c7b95171 | 235 | *val = env->frm; |
605def6e | 236 | return RISCV_EXCP_NONE; |
c7b95171 MC |
237 | } |
238 | ||
605def6e AF |
239 | static RISCVException write_frm(CPURISCVState *env, int csrno, |
240 | target_ulong val) | |
c7b95171 MC |
241 | { |
242 | #if !defined(CONFIG_USER_ONLY) | |
c7b95171 MC |
243 | env->mstatus |= MSTATUS_FS; |
244 | #endif | |
245 | env->frm = val & (FSR_RD >> FSR_RD_SHIFT); | |
605def6e | 246 | return RISCV_EXCP_NONE; |
c7b95171 MC |
247 | } |
248 | ||
605def6e AF |
249 | static RISCVException read_fcsr(CPURISCVState *env, int csrno, |
250 | target_ulong *val) | |
c7b95171 | 251 | { |
fb738839 | 252 | *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) |
c7b95171 | 253 | | (env->frm << FSR_RD_SHIFT); |
8e3a1f18 LZ |
254 | if (vs(env, csrno) >= 0) { |
255 | *val |= (env->vxrm << FSR_VXRM_SHIFT) | |
256 | | (env->vxsat << FSR_VXSAT_SHIFT); | |
257 | } | |
605def6e | 258 | return RISCV_EXCP_NONE; |
c7b95171 MC |
259 | } |
260 | ||
605def6e AF |
261 | static RISCVException write_fcsr(CPURISCVState *env, int csrno, |
262 | target_ulong val) | |
c7b95171 MC |
263 | { |
264 | #if !defined(CONFIG_USER_ONLY) | |
c7b95171 MC |
265 | env->mstatus |= MSTATUS_FS; |
266 | #endif | |
267 | env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; | |
8e3a1f18 LZ |
268 | if (vs(env, csrno) >= 0) { |
269 | env->vxrm = (val & FSR_VXRM) >> FSR_VXRM_SHIFT; | |
270 | env->vxsat = (val & FSR_VXSAT) >> FSR_VXSAT_SHIFT; | |
271 | } | |
fb738839 | 272 | riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT); |
605def6e | 273 | return RISCV_EXCP_NONE; |
c7b95171 MC |
274 | } |
275 | ||
605def6e AF |
276 | static RISCVException read_vtype(CPURISCVState *env, int csrno, |
277 | target_ulong *val) | |
8e3a1f18 LZ |
278 | { |
279 | *val = env->vtype; | |
605def6e | 280 | return RISCV_EXCP_NONE; |
8e3a1f18 LZ |
281 | } |
282 | ||
605def6e AF |
283 | static RISCVException read_vl(CPURISCVState *env, int csrno, |
284 | target_ulong *val) | |
8e3a1f18 LZ |
285 | { |
286 | *val = env->vl; | |
605def6e | 287 | return RISCV_EXCP_NONE; |
8e3a1f18 LZ |
288 | } |
289 | ||
605def6e AF |
290 | static RISCVException read_vxrm(CPURISCVState *env, int csrno, |
291 | target_ulong *val) | |
8e3a1f18 LZ |
292 | { |
293 | *val = env->vxrm; | |
605def6e | 294 | return RISCV_EXCP_NONE; |
8e3a1f18 LZ |
295 | } |
296 | ||
605def6e AF |
297 | static RISCVException write_vxrm(CPURISCVState *env, int csrno, |
298 | target_ulong val) | |
8e3a1f18 LZ |
299 | { |
300 | env->vxrm = val; | |
605def6e | 301 | return RISCV_EXCP_NONE; |
8e3a1f18 LZ |
302 | } |
303 | ||
605def6e AF |
304 | static RISCVException read_vxsat(CPURISCVState *env, int csrno, |
305 | target_ulong *val) | |
8e3a1f18 LZ |
306 | { |
307 | *val = env->vxsat; | |
605def6e | 308 | return RISCV_EXCP_NONE; |
8e3a1f18 LZ |
309 | } |
310 | ||
605def6e AF |
311 | static RISCVException write_vxsat(CPURISCVState *env, int csrno, |
312 | target_ulong val) | |
8e3a1f18 LZ |
313 | { |
314 | env->vxsat = val; | |
605def6e | 315 | return RISCV_EXCP_NONE; |
8e3a1f18 LZ |
316 | } |
317 | ||
605def6e AF |
318 | static RISCVException read_vstart(CPURISCVState *env, int csrno, |
319 | target_ulong *val) | |
8e3a1f18 LZ |
320 | { |
321 | *val = env->vstart; | |
605def6e | 322 | return RISCV_EXCP_NONE; |
8e3a1f18 LZ |
323 | } |
324 | ||
605def6e AF |
325 | static RISCVException write_vstart(CPURISCVState *env, int csrno, |
326 | target_ulong val) | |
8e3a1f18 LZ |
327 | { |
328 | env->vstart = val; | |
605def6e | 329 | return RISCV_EXCP_NONE; |
8e3a1f18 LZ |
330 | } |
331 | ||
c7b95171 | 332 | /* User Timers and Counters */ |
605def6e AF |
333 | static RISCVException read_instret(CPURISCVState *env, int csrno, |
334 | target_ulong *val) | |
c7b95171 | 335 | { |
c7b95171 | 336 | #if !defined(CONFIG_USER_ONLY) |
740b1759 | 337 | if (icount_enabled()) { |
8191d368 | 338 | *val = icount_get(); |
c7b95171 MC |
339 | } else { |
340 | *val = cpu_get_host_ticks(); | |
341 | } | |
342 | #else | |
343 | *val = cpu_get_host_ticks(); | |
344 | #endif | |
605def6e | 345 | return RISCV_EXCP_NONE; |
c7b95171 MC |
346 | } |
347 | ||
605def6e AF |
348 | static RISCVException read_instreth(CPURISCVState *env, int csrno, |
349 | target_ulong *val) | |
c7b95171 | 350 | { |
c7b95171 | 351 | #if !defined(CONFIG_USER_ONLY) |
740b1759 | 352 | if (icount_enabled()) { |
8191d368 | 353 | *val = icount_get() >> 32; |
c7b95171 MC |
354 | } else { |
355 | *val = cpu_get_host_ticks() >> 32; | |
356 | } | |
357 | #else | |
358 | *val = cpu_get_host_ticks() >> 32; | |
359 | #endif | |
605def6e | 360 | return RISCV_EXCP_NONE; |
c7b95171 | 361 | } |
c7b95171 MC |
362 | |
363 | #if defined(CONFIG_USER_ONLY) | |
605def6e AF |
364 | static RISCVException read_time(CPURISCVState *env, int csrno, |
365 | target_ulong *val) | |
c7b95171 MC |
366 | { |
367 | *val = cpu_get_host_ticks(); | |
605def6e | 368 | return RISCV_EXCP_NONE; |
c7b95171 MC |
369 | } |
370 | ||
605def6e AF |
371 | static RISCVException read_timeh(CPURISCVState *env, int csrno, |
372 | target_ulong *val) | |
c7b95171 MC |
373 | { |
374 | *val = cpu_get_host_ticks() >> 32; | |
605def6e | 375 | return RISCV_EXCP_NONE; |
c7b95171 | 376 | } |
c7b95171 MC |
377 | |
378 | #else /* CONFIG_USER_ONLY */ | |
379 | ||
605def6e AF |
380 | static RISCVException read_time(CPURISCVState *env, int csrno, |
381 | target_ulong *val) | |
c6957248 AP |
382 | { |
383 | uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; | |
384 | ||
385 | if (!env->rdtime_fn) { | |
605def6e | 386 | return RISCV_EXCP_ILLEGAL_INST; |
c6957248 AP |
387 | } |
388 | ||
a47ef6e9 | 389 | *val = env->rdtime_fn(env->rdtime_fn_arg) + delta; |
605def6e | 390 | return RISCV_EXCP_NONE; |
c6957248 AP |
391 | } |
392 | ||
605def6e AF |
393 | static RISCVException read_timeh(CPURISCVState *env, int csrno, |
394 | target_ulong *val) | |
c6957248 AP |
395 | { |
396 | uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; | |
397 | ||
398 | if (!env->rdtime_fn) { | |
605def6e | 399 | return RISCV_EXCP_ILLEGAL_INST; |
c6957248 AP |
400 | } |
401 | ||
a47ef6e9 | 402 | *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32; |
605def6e | 403 | return RISCV_EXCP_NONE; |
c6957248 | 404 | } |
c6957248 | 405 | |
c7b95171 MC |
406 | /* Machine constants */ |
407 | ||
ff2cc129 AF |
408 | #define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP) |
409 | #define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP) | |
410 | #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) | |
c7b95171 | 411 | |
d0e53ce3 AF |
412 | static const target_ulong delegable_ints = S_MODE_INTERRUPTS | |
413 | VS_MODE_INTERRUPTS; | |
bc083a51 | 414 | static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS; |
d0e53ce3 AF |
415 | static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | |
416 | VS_MODE_INTERRUPTS; | |
bc083a51 JM |
417 | #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \ |
418 | (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \ | |
419 | (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \ | |
420 | (1ULL << (RISCV_EXCP_BREAKPOINT)) | \ | |
421 | (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | \ | |
422 | (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | \ | |
423 | (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | \ | |
424 | (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | \ | |
425 | (1ULL << (RISCV_EXCP_U_ECALL)) | \ | |
426 | (1ULL << (RISCV_EXCP_S_ECALL)) | \ | |
427 | (1ULL << (RISCV_EXCP_VS_ECALL)) | \ | |
428 | (1ULL << (RISCV_EXCP_M_ECALL)) | \ | |
429 | (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | \ | |
430 | (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | \ | |
431 | (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | \ | |
432 | (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | \ | |
433 | (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | \ | |
434 | (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | \ | |
435 | (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))) | |
436 | static const target_ulong vs_delegable_excps = DELEGABLE_EXCPS & | |
437 | ~((1ULL << (RISCV_EXCP_S_ECALL)) | | |
438 | (1ULL << (RISCV_EXCP_VS_ECALL)) | | |
439 | (1ULL << (RISCV_EXCP_M_ECALL)) | | |
440 | (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | | |
441 | (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | | |
442 | (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | | |
443 | (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))); | |
c7b95171 MC |
444 | static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | |
445 | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | | |
5f10e6d8 | 446 | SSTATUS_SUM | SSTATUS_MXR; |
087b051a | 447 | static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP; |
e89b631c GK |
448 | static const target_ulong hip_writable_mask = MIP_VSSIP; |
449 | static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; | |
8747c9ee | 450 | static const target_ulong vsip_writable_mask = MIP_VSSIP; |
c7b95171 | 451 | |
8987cdc4 | 452 | static const char valid_vm_1_10_32[16] = { |
c7b95171 MC |
453 | [VM_1_10_MBARE] = 1, |
454 | [VM_1_10_SV32] = 1 | |
455 | }; | |
8987cdc4 AF |
456 | |
457 | static const char valid_vm_1_10_64[16] = { | |
c7b95171 MC |
458 | [VM_1_10_MBARE] = 1, |
459 | [VM_1_10_SV39] = 1, | |
460 | [VM_1_10_SV48] = 1, | |
461 | [VM_1_10_SV57] = 1 | |
462 | }; | |
c7b95171 MC |
463 | |
464 | /* Machine Information Registers */ | |
605def6e AF |
465 | static RISCVException read_zero(CPURISCVState *env, int csrno, |
466 | target_ulong *val) | |
c7b95171 | 467 | { |
605def6e AF |
468 | *val = 0; |
469 | return RISCV_EXCP_NONE; | |
c7b95171 MC |
470 | } |
471 | ||
605def6e AF |
472 | static RISCVException read_mhartid(CPURISCVState *env, int csrno, |
473 | target_ulong *val) | |
c7b95171 MC |
474 | { |
475 | *val = env->mhartid; | |
605def6e | 476 | return RISCV_EXCP_NONE; |
c7b95171 MC |
477 | } |
478 | ||
479 | /* Machine Trap Setup */ | |
b550f894 RH |
480 | |
481 | /* We do not store SD explicitly, only compute it on demand. */ | |
482 | static uint64_t add_status_sd(RISCVMXL xl, uint64_t status) | |
483 | { | |
484 | if ((status & MSTATUS_FS) == MSTATUS_FS || | |
485 | (status & MSTATUS_XS) == MSTATUS_XS) { | |
486 | switch (xl) { | |
487 | case MXL_RV32: | |
488 | return status | MSTATUS32_SD; | |
489 | case MXL_RV64: | |
490 | return status | MSTATUS64_SD; | |
491 | default: | |
492 | g_assert_not_reached(); | |
493 | } | |
494 | } | |
495 | return status; | |
496 | } | |
497 | ||
605def6e AF |
498 | static RISCVException read_mstatus(CPURISCVState *env, int csrno, |
499 | target_ulong *val) | |
c7b95171 | 500 | { |
b550f894 | 501 | *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus); |
605def6e | 502 | return RISCV_EXCP_NONE; |
c7b95171 MC |
503 | } |
504 | ||
505 | static int validate_vm(CPURISCVState *env, target_ulong vm) | |
506 | { | |
db23e5d9 | 507 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
8987cdc4 AF |
508 | return valid_vm_1_10_32[vm & 0xf]; |
509 | } else { | |
510 | return valid_vm_1_10_64[vm & 0xf]; | |
511 | } | |
c7b95171 MC |
512 | } |
513 | ||
605def6e AF |
514 | static RISCVException write_mstatus(CPURISCVState *env, int csrno, |
515 | target_ulong val) | |
c7b95171 | 516 | { |
284d697c YJ |
517 | uint64_t mstatus = env->mstatus; |
518 | uint64_t mask = 0; | |
c7b95171 MC |
519 | |
520 | /* flush tlb on mstatus fields that affect VM */ | |
1a9540d1 AF |
521 | if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | |
522 | MSTATUS_MPRV | MSTATUS_SUM)) { | |
523 | tlb_flush(env_cpu(env)); | |
c7b95171 | 524 | } |
1a9540d1 AF |
525 | mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | |
526 | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | | |
527 | MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | | |
528 | MSTATUS_TW; | |
8987cdc4 | 529 | |
db23e5d9 | 530 | if (riscv_cpu_mxl(env) != MXL_RV32) { |
8987cdc4 AF |
531 | /* |
532 | * RV32: MPV and GVA are not in mstatus. The current plan is to | |
533 | * add them to mstatush. For now, we just don't support it. | |
534 | */ | |
535 | mask |= MSTATUS_MPV | MSTATUS_GVA; | |
536 | } | |
c7b95171 MC |
537 | |
538 | mstatus = (mstatus & ~mask) | (val & mask); | |
539 | ||
b550f894 | 540 | if (riscv_cpu_mxl(env) == MXL_RV64) { |
92371bd9 RH |
541 | /* SXL and UXL fields are for now read only */ |
542 | mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64); | |
543 | mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64); | |
4fd7455b | 544 | } |
c7b95171 MC |
545 | env->mstatus = mstatus; |
546 | ||
605def6e | 547 | return RISCV_EXCP_NONE; |
c7b95171 MC |
548 | } |
549 | ||
605def6e AF |
550 | static RISCVException read_mstatush(CPURISCVState *env, int csrno, |
551 | target_ulong *val) | |
551fa7e8 | 552 | { |
284d697c | 553 | *val = env->mstatus >> 32; |
605def6e | 554 | return RISCV_EXCP_NONE; |
551fa7e8 AF |
555 | } |
556 | ||
605def6e AF |
557 | static RISCVException write_mstatush(CPURISCVState *env, int csrno, |
558 | target_ulong val) | |
551fa7e8 | 559 | { |
284d697c YJ |
560 | uint64_t valh = (uint64_t)val << 32; |
561 | uint64_t mask = MSTATUS_MPV | MSTATUS_GVA; | |
562 | ||
563 | if ((valh ^ env->mstatus) & (MSTATUS_MPV)) { | |
551fa7e8 AF |
564 | tlb_flush(env_cpu(env)); |
565 | } | |
566 | ||
284d697c | 567 | env->mstatus = (env->mstatus & ~mask) | (valh & mask); |
551fa7e8 | 568 | |
605def6e | 569 | return RISCV_EXCP_NONE; |
551fa7e8 | 570 | } |
551fa7e8 | 571 | |
605def6e AF |
572 | static RISCVException read_misa(CPURISCVState *env, int csrno, |
573 | target_ulong *val) | |
c7b95171 | 574 | { |
e91a7227 RH |
575 | target_ulong misa; |
576 | ||
577 | switch (env->misa_mxl) { | |
578 | case MXL_RV32: | |
579 | misa = (target_ulong)MXL_RV32 << 30; | |
580 | break; | |
581 | #ifdef TARGET_RISCV64 | |
582 | case MXL_RV64: | |
583 | misa = (target_ulong)MXL_RV64 << 62; | |
584 | break; | |
585 | #endif | |
586 | default: | |
587 | g_assert_not_reached(); | |
588 | } | |
589 | ||
590 | *val = misa | env->misa_ext; | |
605def6e | 591 | return RISCV_EXCP_NONE; |
c7b95171 MC |
592 | } |
593 | ||
605def6e AF |
594 | static RISCVException write_misa(CPURISCVState *env, int csrno, |
595 | target_ulong val) | |
f18637cd MC |
596 | { |
597 | if (!riscv_feature(env, RISCV_FEATURE_MISA)) { | |
598 | /* drop write to misa */ | |
605def6e | 599 | return RISCV_EXCP_NONE; |
f18637cd MC |
600 | } |
601 | ||
602 | /* 'I' or 'E' must be present */ | |
603 | if (!(val & (RVI | RVE))) { | |
604 | /* It is not, drop write to misa */ | |
605def6e | 605 | return RISCV_EXCP_NONE; |
f18637cd MC |
606 | } |
607 | ||
608 | /* 'E' excludes all other extensions */ | |
609 | if (val & RVE) { | |
610 | /* when we support 'E' we can do "val = RVE;" however | |
611 | * for now we just drop writes if 'E' is present. | |
612 | */ | |
605def6e | 613 | return RISCV_EXCP_NONE; |
f18637cd MC |
614 | } |
615 | ||
e91a7227 RH |
616 | /* |
617 | * misa.MXL writes are not supported by QEMU. | |
618 | * Drop writes to those bits. | |
619 | */ | |
620 | ||
f18637cd | 621 | /* Mask extensions that are not supported by this hart */ |
e91a7227 | 622 | val &= env->misa_ext_mask; |
f18637cd MC |
623 | |
624 | /* Mask extensions that are not supported by QEMU */ | |
625 | val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU); | |
626 | ||
627 | /* 'D' depends on 'F', so clear 'D' if 'F' is not present */ | |
628 | if ((val & RVD) && !(val & RVF)) { | |
629 | val &= ~RVD; | |
630 | } | |
631 | ||
632 | /* Suppress 'C' if next instruction is not aligned | |
633 | * TODO: this should check next_pc | |
634 | */ | |
635 | if ((val & RVC) && (GETPC() & ~3) != 0) { | |
636 | val &= ~RVC; | |
637 | } | |
638 | ||
e91a7227 RH |
639 | /* If nothing changed, do nothing. */ |
640 | if (val == env->misa_ext) { | |
641 | return RISCV_EXCP_NONE; | |
4fd7455b | 642 | } |
f18637cd MC |
643 | |
644 | /* flush translation cache */ | |
e91a7227 RH |
645 | tb_flush(env_cpu(env)); |
646 | env->misa_ext = val; | |
605def6e | 647 | return RISCV_EXCP_NONE; |
f18637cd MC |
648 | } |
649 | ||
605def6e AF |
650 | static RISCVException read_medeleg(CPURISCVState *env, int csrno, |
651 | target_ulong *val) | |
c7b95171 MC |
652 | { |
653 | *val = env->medeleg; | |
605def6e | 654 | return RISCV_EXCP_NONE; |
c7b95171 MC |
655 | } |
656 | ||
605def6e AF |
657 | static RISCVException write_medeleg(CPURISCVState *env, int csrno, |
658 | target_ulong val) | |
c7b95171 | 659 | { |
bc083a51 | 660 | env->medeleg = (env->medeleg & ~DELEGABLE_EXCPS) | (val & DELEGABLE_EXCPS); |
605def6e | 661 | return RISCV_EXCP_NONE; |
c7b95171 MC |
662 | } |
663 | ||
605def6e AF |
664 | static RISCVException read_mideleg(CPURISCVState *env, int csrno, |
665 | target_ulong *val) | |
c7b95171 MC |
666 | { |
667 | *val = env->mideleg; | |
605def6e | 668 | return RISCV_EXCP_NONE; |
c7b95171 MC |
669 | } |
670 | ||
605def6e AF |
671 | static RISCVException write_mideleg(CPURISCVState *env, int csrno, |
672 | target_ulong val) | |
c7b95171 MC |
673 | { |
674 | env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints); | |
713d8363 AF |
675 | if (riscv_has_ext(env, RVH)) { |
676 | env->mideleg |= VS_MODE_INTERRUPTS; | |
677 | } | |
605def6e | 678 | return RISCV_EXCP_NONE; |
c7b95171 MC |
679 | } |
680 | ||
605def6e AF |
681 | static RISCVException read_mie(CPURISCVState *env, int csrno, |
682 | target_ulong *val) | |
c7b95171 MC |
683 | { |
684 | *val = env->mie; | |
605def6e | 685 | return RISCV_EXCP_NONE; |
c7b95171 MC |
686 | } |
687 | ||
605def6e AF |
688 | static RISCVException write_mie(CPURISCVState *env, int csrno, |
689 | target_ulong val) | |
c7b95171 MC |
690 | { |
691 | env->mie = (env->mie & ~all_ints) | (val & all_ints); | |
605def6e | 692 | return RISCV_EXCP_NONE; |
c7b95171 MC |
693 | } |
694 | ||
605def6e AF |
695 | static RISCVException read_mtvec(CPURISCVState *env, int csrno, |
696 | target_ulong *val) | |
c7b95171 MC |
697 | { |
698 | *val = env->mtvec; | |
605def6e | 699 | return RISCV_EXCP_NONE; |
c7b95171 MC |
700 | } |
701 | ||
605def6e AF |
702 | static RISCVException write_mtvec(CPURISCVState *env, int csrno, |
703 | target_ulong val) | |
c7b95171 MC |
704 | { |
705 | /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ | |
acbbb94e MC |
706 | if ((val & 3) < 2) { |
707 | env->mtvec = val; | |
c7b95171 | 708 | } else { |
acbbb94e | 709 | qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n"); |
c7b95171 | 710 | } |
605def6e | 711 | return RISCV_EXCP_NONE; |
c7b95171 MC |
712 | } |
713 | ||
605def6e AF |
714 | static RISCVException read_mcounteren(CPURISCVState *env, int csrno, |
715 | target_ulong *val) | |
c7b95171 | 716 | { |
c7b95171 | 717 | *val = env->mcounteren; |
605def6e | 718 | return RISCV_EXCP_NONE; |
c7b95171 MC |
719 | } |
720 | ||
605def6e AF |
721 | static RISCVException write_mcounteren(CPURISCVState *env, int csrno, |
722 | target_ulong val) | |
c7b95171 | 723 | { |
c7b95171 | 724 | env->mcounteren = val; |
605def6e | 725 | return RISCV_EXCP_NONE; |
c7b95171 MC |
726 | } |
727 | ||
c7b95171 | 728 | /* Machine Trap Handling */ |
605def6e AF |
729 | static RISCVException read_mscratch(CPURISCVState *env, int csrno, |
730 | target_ulong *val) | |
c7b95171 MC |
731 | { |
732 | *val = env->mscratch; | |
605def6e | 733 | return RISCV_EXCP_NONE; |
c7b95171 MC |
734 | } |
735 | ||
605def6e AF |
736 | static RISCVException write_mscratch(CPURISCVState *env, int csrno, |
737 | target_ulong val) | |
c7b95171 MC |
738 | { |
739 | env->mscratch = val; | |
605def6e | 740 | return RISCV_EXCP_NONE; |
c7b95171 MC |
741 | } |
742 | ||
605def6e AF |
743 | static RISCVException read_mepc(CPURISCVState *env, int csrno, |
744 | target_ulong *val) | |
c7b95171 MC |
745 | { |
746 | *val = env->mepc; | |
605def6e | 747 | return RISCV_EXCP_NONE; |
c7b95171 MC |
748 | } |
749 | ||
605def6e AF |
750 | static RISCVException write_mepc(CPURISCVState *env, int csrno, |
751 | target_ulong val) | |
c7b95171 MC |
752 | { |
753 | env->mepc = val; | |
605def6e | 754 | return RISCV_EXCP_NONE; |
c7b95171 MC |
755 | } |
756 | ||
605def6e AF |
757 | static RISCVException read_mcause(CPURISCVState *env, int csrno, |
758 | target_ulong *val) | |
c7b95171 MC |
759 | { |
760 | *val = env->mcause; | |
605def6e | 761 | return RISCV_EXCP_NONE; |
c7b95171 MC |
762 | } |
763 | ||
605def6e AF |
764 | static RISCVException write_mcause(CPURISCVState *env, int csrno, |
765 | target_ulong val) | |
c7b95171 MC |
766 | { |
767 | env->mcause = val; | |
605def6e | 768 | return RISCV_EXCP_NONE; |
c7b95171 MC |
769 | } |
770 | ||
605def6e AF |
771 | static RISCVException read_mtval(CPURISCVState *env, int csrno, |
772 | target_ulong *val) | |
c7b95171 | 773 | { |
ac12b601 | 774 | *val = env->mtval; |
605def6e | 775 | return RISCV_EXCP_NONE; |
c7b95171 MC |
776 | } |
777 | ||
605def6e AF |
778 | static RISCVException write_mtval(CPURISCVState *env, int csrno, |
779 | target_ulong val) | |
c7b95171 | 780 | { |
ac12b601 | 781 | env->mtval = val; |
605def6e | 782 | return RISCV_EXCP_NONE; |
c7b95171 MC |
783 | } |
784 | ||
605def6e AF |
785 | static RISCVException rmw_mip(CPURISCVState *env, int csrno, |
786 | target_ulong *ret_value, | |
787 | target_ulong new_value, target_ulong write_mask) | |
c7b95171 | 788 | { |
3109cd98 | 789 | RISCVCPU *cpu = env_archcpu(env); |
e3e7039c MC |
790 | /* Allow software control of delegable interrupts not claimed by hardware */ |
791 | target_ulong mask = write_mask & delegable_ints & ~env->miclaim; | |
71877e29 MC |
792 | uint32_t old_mip; |
793 | ||
71877e29 | 794 | if (mask) { |
71877e29 | 795 | old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask)); |
71877e29 | 796 | } else { |
7ec5d303 | 797 | old_mip = env->mip; |
71877e29 | 798 | } |
c7b95171 | 799 | |
71877e29 MC |
800 | if (ret_value) { |
801 | *ret_value = old_mip; | |
802 | } | |
c7b95171 | 803 | |
605def6e | 804 | return RISCV_EXCP_NONE; |
c7b95171 MC |
805 | } |
806 | ||
807 | /* Supervisor Trap Setup */ | |
605def6e AF |
808 | static RISCVException read_sstatus(CPURISCVState *env, int csrno, |
809 | target_ulong *val) | |
c7b95171 | 810 | { |
1a9540d1 | 811 | target_ulong mask = (sstatus_v1_10_mask); |
5f10e6d8 | 812 | |
b550f894 RH |
813 | /* TODO: Use SXL not MXL. */ |
814 | *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask); | |
605def6e | 815 | return RISCV_EXCP_NONE; |
c7b95171 MC |
816 | } |
817 | ||
605def6e AF |
818 | static RISCVException write_sstatus(CPURISCVState *env, int csrno, |
819 | target_ulong val) | |
c7b95171 | 820 | { |
1a9540d1 | 821 | target_ulong mask = (sstatus_v1_10_mask); |
c7b95171 MC |
822 | target_ulong newval = (env->mstatus & ~mask) | (val & mask); |
823 | return write_mstatus(env, CSR_MSTATUS, newval); | |
824 | } | |
825 | ||
605def6e AF |
826 | static RISCVException read_vsie(CPURISCVState *env, int csrno, |
827 | target_ulong *val) | |
9d5451e0 GK |
828 | { |
829 | /* Shift the VS bits to their S bit location in vsie */ | |
830 | *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1; | |
605def6e | 831 | return RISCV_EXCP_NONE; |
9d5451e0 GK |
832 | } |
833 | ||
605def6e AF |
834 | static RISCVException read_sie(CPURISCVState *env, int csrno, |
835 | target_ulong *val) | |
c7b95171 | 836 | { |
d0e53ce3 | 837 | if (riscv_cpu_virt_enabled(env)) { |
9d5451e0 | 838 | read_vsie(env, CSR_VSIE, val); |
d0e53ce3 AF |
839 | } else { |
840 | *val = env->mie & env->mideleg; | |
841 | } | |
605def6e | 842 | return RISCV_EXCP_NONE; |
c7b95171 MC |
843 | } |
844 | ||
605def6e AF |
845 | static RISCVException write_vsie(CPURISCVState *env, int csrno, |
846 | target_ulong val) | |
c7b95171 | 847 | { |
9d5451e0 GK |
848 | /* Shift the S bits to their VS bit location in mie */ |
849 | target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | | |
850 | ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS); | |
851 | return write_mie(env, CSR_MIE, newval); | |
852 | } | |
d0e53ce3 | 853 | |
9d5451e0 GK |
854 | static int write_sie(CPURISCVState *env, int csrno, target_ulong val) |
855 | { | |
d0e53ce3 | 856 | if (riscv_cpu_virt_enabled(env)) { |
9d5451e0 | 857 | write_vsie(env, CSR_VSIE, val); |
d0e53ce3 | 858 | } else { |
9d5451e0 GK |
859 | target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) | |
860 | (val & S_MODE_INTERRUPTS); | |
861 | write_mie(env, CSR_MIE, newval); | |
d0e53ce3 AF |
862 | } |
863 | ||
605def6e | 864 | return RISCV_EXCP_NONE; |
c7b95171 MC |
865 | } |
866 | ||
605def6e AF |
867 | static RISCVException read_stvec(CPURISCVState *env, int csrno, |
868 | target_ulong *val) | |
c7b95171 MC |
869 | { |
870 | *val = env->stvec; | |
605def6e | 871 | return RISCV_EXCP_NONE; |
c7b95171 MC |
872 | } |
873 | ||
605def6e AF |
874 | static RISCVException write_stvec(CPURISCVState *env, int csrno, |
875 | target_ulong val) | |
c7b95171 MC |
876 | { |
877 | /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ | |
acbbb94e MC |
878 | if ((val & 3) < 2) { |
879 | env->stvec = val; | |
c7b95171 | 880 | } else { |
acbbb94e | 881 | qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n"); |
c7b95171 | 882 | } |
605def6e | 883 | return RISCV_EXCP_NONE; |
c7b95171 MC |
884 | } |
885 | ||
605def6e AF |
886 | static RISCVException read_scounteren(CPURISCVState *env, int csrno, |
887 | target_ulong *val) | |
c7b95171 | 888 | { |
c7b95171 | 889 | *val = env->scounteren; |
605def6e | 890 | return RISCV_EXCP_NONE; |
c7b95171 MC |
891 | } |
892 | ||
605def6e AF |
893 | static RISCVException write_scounteren(CPURISCVState *env, int csrno, |
894 | target_ulong val) | |
c7b95171 | 895 | { |
c7b95171 | 896 | env->scounteren = val; |
605def6e | 897 | return RISCV_EXCP_NONE; |
c7b95171 MC |
898 | } |
899 | ||
900 | /* Supervisor Trap Handling */ | |
605def6e AF |
901 | static RISCVException read_sscratch(CPURISCVState *env, int csrno, |
902 | target_ulong *val) | |
c7b95171 MC |
903 | { |
904 | *val = env->sscratch; | |
605def6e | 905 | return RISCV_EXCP_NONE; |
c7b95171 MC |
906 | } |
907 | ||
605def6e AF |
908 | static RISCVException write_sscratch(CPURISCVState *env, int csrno, |
909 | target_ulong val) | |
c7b95171 MC |
910 | { |
911 | env->sscratch = val; | |
605def6e | 912 | return RISCV_EXCP_NONE; |
c7b95171 MC |
913 | } |
914 | ||
605def6e AF |
915 | static RISCVException read_sepc(CPURISCVState *env, int csrno, |
916 | target_ulong *val) | |
c7b95171 MC |
917 | { |
918 | *val = env->sepc; | |
605def6e | 919 | return RISCV_EXCP_NONE; |
c7b95171 MC |
920 | } |
921 | ||
605def6e AF |
922 | static RISCVException write_sepc(CPURISCVState *env, int csrno, |
923 | target_ulong val) | |
c7b95171 MC |
924 | { |
925 | env->sepc = val; | |
605def6e | 926 | return RISCV_EXCP_NONE; |
c7b95171 MC |
927 | } |
928 | ||
605def6e AF |
929 | static RISCVException read_scause(CPURISCVState *env, int csrno, |
930 | target_ulong *val) | |
c7b95171 MC |
931 | { |
932 | *val = env->scause; | |
605def6e | 933 | return RISCV_EXCP_NONE; |
c7b95171 MC |
934 | } |
935 | ||
605def6e AF |
936 | static RISCVException write_scause(CPURISCVState *env, int csrno, |
937 | target_ulong val) | |
c7b95171 MC |
938 | { |
939 | env->scause = val; | |
605def6e | 940 | return RISCV_EXCP_NONE; |
c7b95171 MC |
941 | } |
942 | ||
605def6e AF |
943 | static RISCVException read_stval(CPURISCVState *env, int csrno, |
944 | target_ulong *val) | |
c7b95171 | 945 | { |
ac12b601 | 946 | *val = env->stval; |
605def6e | 947 | return RISCV_EXCP_NONE; |
c7b95171 MC |
948 | } |
949 | ||
605def6e AF |
950 | static RISCVException write_stval(CPURISCVState *env, int csrno, |
951 | target_ulong val) | |
c7b95171 | 952 | { |
ac12b601 | 953 | env->stval = val; |
605def6e | 954 | return RISCV_EXCP_NONE; |
c7b95171 MC |
955 | } |
956 | ||
605def6e AF |
957 | static RISCVException rmw_vsip(CPURISCVState *env, int csrno, |
958 | target_ulong *ret_value, | |
959 | target_ulong new_value, target_ulong write_mask) | |
9d5451e0 GK |
960 | { |
961 | /* Shift the S bits to their VS bit location in mip */ | |
962 | int ret = rmw_mip(env, 0, ret_value, new_value << 1, | |
963 | (write_mask << 1) & vsip_writable_mask & env->hideleg); | |
33979526 RH |
964 | |
965 | if (ret_value) { | |
966 | *ret_value &= VS_MODE_INTERRUPTS; | |
967 | /* Shift the VS bits to their S bit location in vsip */ | |
968 | *ret_value >>= 1; | |
969 | } | |
9d5451e0 GK |
970 | return ret; |
971 | } | |
972 | ||
605def6e AF |
973 | static RISCVException rmw_sip(CPURISCVState *env, int csrno, |
974 | target_ulong *ret_value, | |
975 | target_ulong new_value, target_ulong write_mask) | |
c7b95171 | 976 | { |
a2e9f57d AF |
977 | int ret; |
978 | ||
979 | if (riscv_cpu_virt_enabled(env)) { | |
9d5451e0 | 980 | ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask); |
a2e9f57d AF |
981 | } else { |
982 | ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value, | |
087b051a | 983 | write_mask & env->mideleg & sip_writable_mask); |
a2e9f57d AF |
984 | } |
985 | ||
33979526 RH |
986 | if (ret_value) { |
987 | *ret_value &= env->mideleg; | |
988 | } | |
087b051a | 989 | return ret; |
c7b95171 MC |
990 | } |
991 | ||
992 | /* Supervisor Protection and Translation */ | |
605def6e AF |
993 | static RISCVException read_satp(CPURISCVState *env, int csrno, |
994 | target_ulong *val) | |
c7b95171 MC |
995 | { |
996 | if (!riscv_feature(env, RISCV_FEATURE_MMU)) { | |
997 | *val = 0; | |
605def6e | 998 | return RISCV_EXCP_NONE; |
1a9540d1 AF |
999 | } |
1000 | ||
1001 | if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { | |
605def6e | 1002 | return RISCV_EXCP_ILLEGAL_INST; |
c7b95171 | 1003 | } else { |
1a9540d1 | 1004 | *val = env->satp; |
c7b95171 | 1005 | } |
1a9540d1 | 1006 | |
605def6e | 1007 | return RISCV_EXCP_NONE; |
c7b95171 MC |
1008 | } |
1009 | ||
605def6e AF |
1010 | static RISCVException write_satp(CPURISCVState *env, int csrno, |
1011 | target_ulong val) | |
c7b95171 | 1012 | { |
15732b8e | 1013 | target_ulong vm, mask, asid; |
419ddf00 | 1014 | |
c7b95171 | 1015 | if (!riscv_feature(env, RISCV_FEATURE_MMU)) { |
605def6e | 1016 | return RISCV_EXCP_NONE; |
c7b95171 | 1017 | } |
419ddf00 | 1018 | |
db23e5d9 | 1019 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
419ddf00 AF |
1020 | vm = validate_vm(env, get_field(val, SATP32_MODE)); |
1021 | mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN); | |
1022 | asid = (val ^ env->satp) & SATP32_ASID; | |
1023 | } else { | |
1024 | vm = validate_vm(env, get_field(val, SATP64_MODE)); | |
1025 | mask = (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN); | |
1026 | asid = (val ^ env->satp) & SATP64_ASID; | |
1027 | } | |
1028 | ||
1029 | if (vm && mask) { | |
7f2b5ff1 | 1030 | if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { |
605def6e | 1031 | return RISCV_EXCP_ILLEGAL_INST; |
7f2b5ff1 | 1032 | } else { |
419ddf00 | 1033 | if (asid) { |
3109cd98 | 1034 | tlb_flush(env_cpu(env)); |
1e0d985f | 1035 | } |
7f2b5ff1 MC |
1036 | env->satp = val; |
1037 | } | |
c7b95171 | 1038 | } |
605def6e | 1039 | return RISCV_EXCP_NONE; |
c7b95171 MC |
1040 | } |
1041 | ||
ff2cc129 | 1042 | /* Hypervisor Extensions */ |
605def6e AF |
1043 | static RISCVException read_hstatus(CPURISCVState *env, int csrno, |
1044 | target_ulong *val) | |
ff2cc129 AF |
1045 | { |
1046 | *val = env->hstatus; | |
db23e5d9 | 1047 | if (riscv_cpu_mxl(env) != MXL_RV32) { |
8987cdc4 AF |
1048 | /* We only support 64-bit VSXL */ |
1049 | *val = set_field(*val, HSTATUS_VSXL, 2); | |
1050 | } | |
30f663b1 AF |
1051 | /* We only support little endian */ |
1052 | *val = set_field(*val, HSTATUS_VSBE, 0); | |
605def6e | 1053 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1054 | } |
1055 | ||
605def6e AF |
1056 | static RISCVException write_hstatus(CPURISCVState *env, int csrno, |
1057 | target_ulong val) | |
ff2cc129 AF |
1058 | { |
1059 | env->hstatus = val; | |
db23e5d9 | 1060 | if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) { |
f8dc878e AF |
1061 | qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options."); |
1062 | } | |
30f663b1 AF |
1063 | if (get_field(val, HSTATUS_VSBE) != 0) { |
1064 | qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests."); | |
1065 | } | |
605def6e | 1066 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1067 | } |
1068 | ||
605def6e AF |
1069 | static RISCVException read_hedeleg(CPURISCVState *env, int csrno, |
1070 | target_ulong *val) | |
ff2cc129 AF |
1071 | { |
1072 | *val = env->hedeleg; | |
605def6e | 1073 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1074 | } |
1075 | ||
605def6e AF |
1076 | static RISCVException write_hedeleg(CPURISCVState *env, int csrno, |
1077 | target_ulong val) | |
ff2cc129 | 1078 | { |
bc083a51 | 1079 | env->hedeleg = val & vs_delegable_excps; |
605def6e | 1080 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1081 | } |
1082 | ||
605def6e AF |
1083 | static RISCVException read_hideleg(CPURISCVState *env, int csrno, |
1084 | target_ulong *val) | |
ff2cc129 AF |
1085 | { |
1086 | *val = env->hideleg; | |
605def6e | 1087 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1088 | } |
1089 | ||
605def6e AF |
1090 | static RISCVException write_hideleg(CPURISCVState *env, int csrno, |
1091 | target_ulong val) | |
ff2cc129 | 1092 | { |
bc083a51 | 1093 | env->hideleg = val & vs_delegable_ints; |
605def6e | 1094 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1095 | } |
1096 | ||
605def6e AF |
1097 | static RISCVException rmw_hvip(CPURISCVState *env, int csrno, |
1098 | target_ulong *ret_value, | |
1099 | target_ulong new_value, target_ulong write_mask) | |
83028098 AF |
1100 | { |
1101 | int ret = rmw_mip(env, 0, ret_value, new_value, | |
e89b631c | 1102 | write_mask & hvip_writable_mask); |
83028098 | 1103 | |
33979526 RH |
1104 | if (ret_value) { |
1105 | *ret_value &= hvip_writable_mask; | |
1106 | } | |
83028098 AF |
1107 | return ret; |
1108 | } | |
1109 | ||
605def6e AF |
1110 | static RISCVException rmw_hip(CPURISCVState *env, int csrno, |
1111 | target_ulong *ret_value, | |
1112 | target_ulong new_value, target_ulong write_mask) | |
ff2cc129 AF |
1113 | { |
1114 | int ret = rmw_mip(env, 0, ret_value, new_value, | |
1115 | write_mask & hip_writable_mask); | |
1116 | ||
33979526 RH |
1117 | if (ret_value) { |
1118 | *ret_value &= hip_writable_mask; | |
1119 | } | |
ff2cc129 AF |
1120 | return ret; |
1121 | } | |
1122 | ||
605def6e AF |
1123 | static RISCVException read_hie(CPURISCVState *env, int csrno, |
1124 | target_ulong *val) | |
ff2cc129 AF |
1125 | { |
1126 | *val = env->mie & VS_MODE_INTERRUPTS; | |
605def6e | 1127 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1128 | } |
1129 | ||
605def6e AF |
1130 | static RISCVException write_hie(CPURISCVState *env, int csrno, |
1131 | target_ulong val) | |
ff2cc129 AF |
1132 | { |
1133 | target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS); | |
1134 | return write_mie(env, CSR_MIE, newval); | |
1135 | } | |
1136 | ||
605def6e AF |
1137 | static RISCVException read_hcounteren(CPURISCVState *env, int csrno, |
1138 | target_ulong *val) | |
ff2cc129 AF |
1139 | { |
1140 | *val = env->hcounteren; | |
605def6e | 1141 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1142 | } |
1143 | ||
605def6e AF |
1144 | static RISCVException write_hcounteren(CPURISCVState *env, int csrno, |
1145 | target_ulong val) | |
ff2cc129 AF |
1146 | { |
1147 | env->hcounteren = val; | |
605def6e | 1148 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1149 | } |
1150 | ||
605def6e AF |
1151 | static RISCVException write_hgeie(CPURISCVState *env, int csrno, |
1152 | target_ulong val) | |
83028098 | 1153 | { |
377cbb4b RH |
1154 | if (val) { |
1155 | qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); | |
1156 | } | |
605def6e | 1157 | return RISCV_EXCP_NONE; |
83028098 AF |
1158 | } |
1159 | ||
605def6e AF |
1160 | static RISCVException read_htval(CPURISCVState *env, int csrno, |
1161 | target_ulong *val) | |
ff2cc129 AF |
1162 | { |
1163 | *val = env->htval; | |
605def6e | 1164 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1165 | } |
1166 | ||
605def6e AF |
1167 | static RISCVException write_htval(CPURISCVState *env, int csrno, |
1168 | target_ulong val) | |
ff2cc129 AF |
1169 | { |
1170 | env->htval = val; | |
605def6e | 1171 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1172 | } |
1173 | ||
605def6e AF |
1174 | static RISCVException read_htinst(CPURISCVState *env, int csrno, |
1175 | target_ulong *val) | |
ff2cc129 AF |
1176 | { |
1177 | *val = env->htinst; | |
605def6e | 1178 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1179 | } |
1180 | ||
605def6e AF |
1181 | static RISCVException write_htinst(CPURISCVState *env, int csrno, |
1182 | target_ulong val) | |
ff2cc129 | 1183 | { |
605def6e | 1184 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1185 | } |
1186 | ||
605def6e AF |
1187 | static RISCVException write_hgeip(CPURISCVState *env, int csrno, |
1188 | target_ulong val) | |
83028098 | 1189 | { |
377cbb4b RH |
1190 | if (val) { |
1191 | qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); | |
1192 | } | |
605def6e | 1193 | return RISCV_EXCP_NONE; |
83028098 AF |
1194 | } |
1195 | ||
605def6e AF |
1196 | static RISCVException read_hgatp(CPURISCVState *env, int csrno, |
1197 | target_ulong *val) | |
ff2cc129 AF |
1198 | { |
1199 | *val = env->hgatp; | |
605def6e | 1200 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1201 | } |
1202 | ||
605def6e AF |
1203 | static RISCVException write_hgatp(CPURISCVState *env, int csrno, |
1204 | target_ulong val) | |
ff2cc129 AF |
1205 | { |
1206 | env->hgatp = val; | |
605def6e | 1207 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1208 | } |
1209 | ||
605def6e AF |
1210 | static RISCVException read_htimedelta(CPURISCVState *env, int csrno, |
1211 | target_ulong *val) | |
c6957248 AP |
1212 | { |
1213 | if (!env->rdtime_fn) { | |
605def6e | 1214 | return RISCV_EXCP_ILLEGAL_INST; |
c6957248 AP |
1215 | } |
1216 | ||
c6957248 | 1217 | *val = env->htimedelta; |
605def6e | 1218 | return RISCV_EXCP_NONE; |
c6957248 AP |
1219 | } |
1220 | ||
605def6e AF |
1221 | static RISCVException write_htimedelta(CPURISCVState *env, int csrno, |
1222 | target_ulong val) | |
c6957248 AP |
1223 | { |
1224 | if (!env->rdtime_fn) { | |
605def6e | 1225 | return RISCV_EXCP_ILLEGAL_INST; |
c6957248 AP |
1226 | } |
1227 | ||
db23e5d9 | 1228 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
8987cdc4 AF |
1229 | env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val); |
1230 | } else { | |
1231 | env->htimedelta = val; | |
1232 | } | |
605def6e | 1233 | return RISCV_EXCP_NONE; |
c6957248 AP |
1234 | } |
1235 | ||
605def6e AF |
1236 | static RISCVException read_htimedeltah(CPURISCVState *env, int csrno, |
1237 | target_ulong *val) | |
c6957248 AP |
1238 | { |
1239 | if (!env->rdtime_fn) { | |
605def6e | 1240 | return RISCV_EXCP_ILLEGAL_INST; |
c6957248 AP |
1241 | } |
1242 | ||
1243 | *val = env->htimedelta >> 32; | |
605def6e | 1244 | return RISCV_EXCP_NONE; |
c6957248 AP |
1245 | } |
1246 | ||
605def6e AF |
1247 | static RISCVException write_htimedeltah(CPURISCVState *env, int csrno, |
1248 | target_ulong val) | |
c6957248 AP |
1249 | { |
1250 | if (!env->rdtime_fn) { | |
605def6e | 1251 | return RISCV_EXCP_ILLEGAL_INST; |
c6957248 AP |
1252 | } |
1253 | ||
1254 | env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val); | |
605def6e | 1255 | return RISCV_EXCP_NONE; |
c6957248 | 1256 | } |
c6957248 | 1257 | |
8747c9ee | 1258 | /* Virtual CSR Registers */ |
605def6e AF |
1259 | static RISCVException read_vsstatus(CPURISCVState *env, int csrno, |
1260 | target_ulong *val) | |
8747c9ee AF |
1261 | { |
1262 | *val = env->vsstatus; | |
605def6e | 1263 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1264 | } |
1265 | ||
605def6e AF |
1266 | static RISCVException write_vsstatus(CPURISCVState *env, int csrno, |
1267 | target_ulong val) | |
8747c9ee | 1268 | { |
284d697c YJ |
1269 | uint64_t mask = (target_ulong)-1; |
1270 | env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val; | |
605def6e | 1271 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1272 | } |
1273 | ||
8747c9ee AF |
1274 | static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val) |
1275 | { | |
1276 | *val = env->vstvec; | |
605def6e | 1277 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1278 | } |
1279 | ||
605def6e AF |
1280 | static RISCVException write_vstvec(CPURISCVState *env, int csrno, |
1281 | target_ulong val) | |
8747c9ee AF |
1282 | { |
1283 | env->vstvec = val; | |
605def6e | 1284 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1285 | } |
1286 | ||
605def6e AF |
1287 | static RISCVException read_vsscratch(CPURISCVState *env, int csrno, |
1288 | target_ulong *val) | |
8747c9ee AF |
1289 | { |
1290 | *val = env->vsscratch; | |
605def6e | 1291 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1292 | } |
1293 | ||
605def6e AF |
1294 | static RISCVException write_vsscratch(CPURISCVState *env, int csrno, |
1295 | target_ulong val) | |
8747c9ee AF |
1296 | { |
1297 | env->vsscratch = val; | |
605def6e | 1298 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1299 | } |
1300 | ||
605def6e AF |
1301 | static RISCVException read_vsepc(CPURISCVState *env, int csrno, |
1302 | target_ulong *val) | |
8747c9ee AF |
1303 | { |
1304 | *val = env->vsepc; | |
605def6e | 1305 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1306 | } |
1307 | ||
605def6e AF |
1308 | static RISCVException write_vsepc(CPURISCVState *env, int csrno, |
1309 | target_ulong val) | |
8747c9ee AF |
1310 | { |
1311 | env->vsepc = val; | |
605def6e | 1312 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1313 | } |
1314 | ||
605def6e AF |
1315 | static RISCVException read_vscause(CPURISCVState *env, int csrno, |
1316 | target_ulong *val) | |
8747c9ee AF |
1317 | { |
1318 | *val = env->vscause; | |
605def6e | 1319 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1320 | } |
1321 | ||
605def6e AF |
1322 | static RISCVException write_vscause(CPURISCVState *env, int csrno, |
1323 | target_ulong val) | |
8747c9ee AF |
1324 | { |
1325 | env->vscause = val; | |
605def6e | 1326 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1327 | } |
1328 | ||
605def6e AF |
1329 | static RISCVException read_vstval(CPURISCVState *env, int csrno, |
1330 | target_ulong *val) | |
8747c9ee AF |
1331 | { |
1332 | *val = env->vstval; | |
605def6e | 1333 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1334 | } |
1335 | ||
605def6e AF |
1336 | static RISCVException write_vstval(CPURISCVState *env, int csrno, |
1337 | target_ulong val) | |
8747c9ee AF |
1338 | { |
1339 | env->vstval = val; | |
605def6e | 1340 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1341 | } |
1342 | ||
605def6e AF |
1343 | static RISCVException read_vsatp(CPURISCVState *env, int csrno, |
1344 | target_ulong *val) | |
8747c9ee AF |
1345 | { |
1346 | *val = env->vsatp; | |
605def6e | 1347 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1348 | } |
1349 | ||
605def6e AF |
1350 | static RISCVException write_vsatp(CPURISCVState *env, int csrno, |
1351 | target_ulong val) | |
8747c9ee AF |
1352 | { |
1353 | env->vsatp = val; | |
605def6e | 1354 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1355 | } |
1356 | ||
605def6e AF |
1357 | static RISCVException read_mtval2(CPURISCVState *env, int csrno, |
1358 | target_ulong *val) | |
34cfb5f6 AF |
1359 | { |
1360 | *val = env->mtval2; | |
605def6e | 1361 | return RISCV_EXCP_NONE; |
34cfb5f6 AF |
1362 | } |
1363 | ||
605def6e AF |
1364 | static RISCVException write_mtval2(CPURISCVState *env, int csrno, |
1365 | target_ulong val) | |
34cfb5f6 AF |
1366 | { |
1367 | env->mtval2 = val; | |
605def6e | 1368 | return RISCV_EXCP_NONE; |
34cfb5f6 AF |
1369 | } |
1370 | ||
605def6e AF |
1371 | static RISCVException read_mtinst(CPURISCVState *env, int csrno, |
1372 | target_ulong *val) | |
34cfb5f6 AF |
1373 | { |
1374 | *val = env->mtinst; | |
605def6e | 1375 | return RISCV_EXCP_NONE; |
34cfb5f6 AF |
1376 | } |
1377 | ||
605def6e AF |
1378 | static RISCVException write_mtinst(CPURISCVState *env, int csrno, |
1379 | target_ulong val) | |
34cfb5f6 AF |
1380 | { |
1381 | env->mtinst = val; | |
605def6e | 1382 | return RISCV_EXCP_NONE; |
34cfb5f6 AF |
1383 | } |
1384 | ||
c7b95171 | 1385 | /* Physical Memory Protection */ |
2582a95c HW |
1386 | static RISCVException read_mseccfg(CPURISCVState *env, int csrno, |
1387 | target_ulong *val) | |
1388 | { | |
1389 | *val = mseccfg_csr_read(env); | |
1390 | return RISCV_EXCP_NONE; | |
1391 | } | |
1392 | ||
1393 | static RISCVException write_mseccfg(CPURISCVState *env, int csrno, | |
1394 | target_ulong val) | |
1395 | { | |
1396 | mseccfg_csr_write(env, val); | |
1397 | return RISCV_EXCP_NONE; | |
1398 | } | |
1399 | ||
605def6e AF |
1400 | static RISCVException read_pmpcfg(CPURISCVState *env, int csrno, |
1401 | target_ulong *val) | |
c7b95171 MC |
1402 | { |
1403 | *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0); | |
605def6e | 1404 | return RISCV_EXCP_NONE; |
c7b95171 MC |
1405 | } |
1406 | ||
605def6e AF |
1407 | static RISCVException write_pmpcfg(CPURISCVState *env, int csrno, |
1408 | target_ulong val) | |
c7b95171 MC |
1409 | { |
1410 | pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val); | |
605def6e | 1411 | return RISCV_EXCP_NONE; |
c7b95171 MC |
1412 | } |
1413 | ||
605def6e AF |
1414 | static RISCVException read_pmpaddr(CPURISCVState *env, int csrno, |
1415 | target_ulong *val) | |
c7b95171 MC |
1416 | { |
1417 | *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0); | |
605def6e | 1418 | return RISCV_EXCP_NONE; |
c7b95171 MC |
1419 | } |
1420 | ||
605def6e AF |
1421 | static RISCVException write_pmpaddr(CPURISCVState *env, int csrno, |
1422 | target_ulong val) | |
c7b95171 MC |
1423 | { |
1424 | pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val); | |
605def6e | 1425 | return RISCV_EXCP_NONE; |
c7b95171 MC |
1426 | } |
1427 | ||
1428 | #endif | |
1429 | ||
1430 | /* | |
1431 | * riscv_csrrw - read and/or update control and status register | |
1432 | * | |
1433 | * csrr <-> riscv_csrrw(env, csrno, ret_value, 0, 0); | |
1434 | * csrrw <-> riscv_csrrw(env, csrno, ret_value, value, -1); | |
1435 | * csrrs <-> riscv_csrrw(env, csrno, ret_value, -1, value); | |
1436 | * csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value); | |
1437 | */ | |
1438 | ||
533c91e8 AF |
1439 | RISCVException riscv_csrrw(CPURISCVState *env, int csrno, |
1440 | target_ulong *ret_value, | |
1441 | target_ulong new_value, target_ulong write_mask) | |
c7b95171 | 1442 | { |
533c91e8 | 1443 | RISCVException ret; |
c7b95171 | 1444 | target_ulong old_value; |
591bddea | 1445 | RISCVCPU *cpu = env_archcpu(env); |
42109837 | 1446 | int read_only = get_field(csrno, 0xC00) == 3; |
c7b95171 | 1447 | |
65e728a2 | 1448 | /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */ |
c7b95171 | 1449 | #if !defined(CONFIG_USER_ONLY) |
0a42f4c4 | 1450 | int effective_priv = env->priv; |
0a42f4c4 AF |
1451 | |
1452 | if (riscv_has_ext(env, RVH) && | |
1453 | env->priv == PRV_S && | |
1454 | !riscv_cpu_virt_enabled(env)) { | |
1455 | /* | |
1456 | * We are in S mode without virtualisation, therefore we are in HS Mode. | |
1457 | * Add 1 to the effective privledge level to allow us to access the | |
1458 | * Hypervisor CSRs. | |
1459 | */ | |
1460 | effective_priv++; | |
e6e03dcf | 1461 | } |
0a42f4c4 | 1462 | |
42109837 | 1463 | if (!env->debugger && (effective_priv < get_field(csrno, 0x300))) { |
533c91e8 | 1464 | return RISCV_EXCP_ILLEGAL_INST; |
c7b95171 MC |
1465 | } |
1466 | #endif | |
42109837 LZ |
1467 | if (write_mask && read_only) { |
1468 | return RISCV_EXCP_ILLEGAL_INST; | |
1469 | } | |
c7b95171 | 1470 | |
591bddea PD |
1471 | /* ensure the CSR extension is enabled. */ |
1472 | if (!cpu->cfg.ext_icsr) { | |
533c91e8 | 1473 | return RISCV_EXCP_ILLEGAL_INST; |
591bddea PD |
1474 | } |
1475 | ||
a88365c1 | 1476 | /* check predicate */ |
e39a8320 | 1477 | if (!csr_ops[csrno].predicate) { |
533c91e8 | 1478 | return RISCV_EXCP_ILLEGAL_INST; |
a88365c1 | 1479 | } |
e39a8320 | 1480 | ret = csr_ops[csrno].predicate(env, csrno); |
0e62f92e | 1481 | if (ret != RISCV_EXCP_NONE) { |
533c91e8 | 1482 | return ret; |
e39a8320 | 1483 | } |
a88365c1 | 1484 | |
c7b95171 MC |
1485 | /* execute combined read/write operation if it exists */ |
1486 | if (csr_ops[csrno].op) { | |
533c91e8 | 1487 | return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask); |
c7b95171 MC |
1488 | } |
1489 | ||
1490 | /* if no accessor exists then return failure */ | |
1491 | if (!csr_ops[csrno].read) { | |
533c91e8 | 1492 | return RISCV_EXCP_ILLEGAL_INST; |
c7b95171 | 1493 | } |
c7b95171 MC |
1494 | /* read old value */ |
1495 | ret = csr_ops[csrno].read(env, csrno, &old_value); | |
605def6e | 1496 | if (ret != RISCV_EXCP_NONE) { |
533c91e8 | 1497 | return ret; |
c7b95171 MC |
1498 | } |
1499 | ||
1500 | /* write value if writable and write mask set, otherwise drop writes */ | |
1501 | if (write_mask) { | |
1502 | new_value = (old_value & ~write_mask) | (new_value & write_mask); | |
1503 | if (csr_ops[csrno].write) { | |
1504 | ret = csr_ops[csrno].write(env, csrno, new_value); | |
605def6e | 1505 | if (ret != RISCV_EXCP_NONE) { |
533c91e8 | 1506 | return ret; |
c7b95171 MC |
1507 | } |
1508 | } | |
1509 | } | |
1510 | ||
1511 | /* return old value */ | |
1512 | if (ret_value) { | |
1513 | *ret_value = old_value; | |
1514 | } | |
1515 | ||
533c91e8 | 1516 | return RISCV_EXCP_NONE; |
c7b95171 MC |
1517 | } |
1518 | ||
753e3fe2 JW |
1519 | /* |
1520 | * Debugger support. If not in user mode, set env->debugger before the | |
1521 | * riscv_csrrw call and clear it after the call. | |
1522 | */ | |
533c91e8 AF |
1523 | RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, |
1524 | target_ulong *ret_value, | |
1525 | target_ulong new_value, | |
1526 | target_ulong write_mask) | |
753e3fe2 | 1527 | { |
533c91e8 | 1528 | RISCVException ret; |
753e3fe2 JW |
1529 | #if !defined(CONFIG_USER_ONLY) |
1530 | env->debugger = true; | |
1531 | #endif | |
1532 | ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask); | |
1533 | #if !defined(CONFIG_USER_ONLY) | |
1534 | env->debugger = false; | |
1535 | #endif | |
1536 | return ret; | |
1537 | } | |
1538 | ||
c7b95171 | 1539 | /* Control and Status Register function table */ |
56118ee8 | 1540 | riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { |
c7b95171 | 1541 | /* User Floating-Point CSRs */ |
8ceac5dc BM |
1542 | [CSR_FFLAGS] = { "fflags", fs, read_fflags, write_fflags }, |
1543 | [CSR_FRM] = { "frm", fs, read_frm, write_frm }, | |
1544 | [CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr }, | |
8e3a1f18 | 1545 | /* Vector CSRs */ |
8ceac5dc BM |
1546 | [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart }, |
1547 | [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat }, | |
1548 | [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm }, | |
1549 | [CSR_VL] = { "vl", vs, read_vl }, | |
1550 | [CSR_VTYPE] = { "vtype", vs, read_vtype }, | |
c7b95171 | 1551 | /* User Timers and Counters */ |
8ceac5dc BM |
1552 | [CSR_CYCLE] = { "cycle", ctr, read_instret }, |
1553 | [CSR_INSTRET] = { "instret", ctr, read_instret }, | |
1554 | [CSR_CYCLEH] = { "cycleh", ctr32, read_instreth }, | |
1555 | [CSR_INSTRETH] = { "instreth", ctr32, read_instreth }, | |
1556 | ||
1557 | /* | |
1558 | * In privileged mode, the monitor will have to emulate TIME CSRs only if | |
1559 | * rdtime callback is not provided by machine/platform emulation. | |
1560 | */ | |
1561 | [CSR_TIME] = { "time", ctr, read_time }, | |
1562 | [CSR_TIMEH] = { "timeh", ctr32, read_timeh }, | |
c7b95171 MC |
1563 | |
1564 | #if !defined(CONFIG_USER_ONLY) | |
1565 | /* Machine Timers and Counters */ | |
8ceac5dc BM |
1566 | [CSR_MCYCLE] = { "mcycle", any, read_instret }, |
1567 | [CSR_MINSTRET] = { "minstret", any, read_instret }, | |
1568 | [CSR_MCYCLEH] = { "mcycleh", any32, read_instreth }, | |
1569 | [CSR_MINSTRETH] = { "minstreth", any32, read_instreth }, | |
c7b95171 MC |
1570 | |
1571 | /* Machine Information Registers */ | |
8ceac5dc BM |
1572 | [CSR_MVENDORID] = { "mvendorid", any, read_zero }, |
1573 | [CSR_MARCHID] = { "marchid", any, read_zero }, | |
1574 | [CSR_MIMPID] = { "mimpid", any, read_zero }, | |
1575 | [CSR_MHARTID] = { "mhartid", any, read_mhartid }, | |
c7b95171 MC |
1576 | |
1577 | /* Machine Trap Setup */ | |
8ceac5dc BM |
1578 | [CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus }, |
1579 | [CSR_MISA] = { "misa", any, read_misa, write_misa }, | |
1580 | [CSR_MIDELEG] = { "mideleg", any, read_mideleg, write_mideleg }, | |
1581 | [CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg }, | |
1582 | [CSR_MIE] = { "mie", any, read_mie, write_mie }, | |
1583 | [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec }, | |
1584 | [CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, write_mcounteren }, | |
c7b95171 | 1585 | |
8ceac5dc | 1586 | [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush }, |
551fa7e8 | 1587 | |
c7b95171 | 1588 | /* Machine Trap Handling */ |
8ceac5dc BM |
1589 | [CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch }, |
1590 | [CSR_MEPC] = { "mepc", any, read_mepc, write_mepc }, | |
1591 | [CSR_MCAUSE] = { "mcause", any, read_mcause, write_mcause }, | |
ac12b601 | 1592 | [CSR_MTVAL] = { "mtval", any, read_mtval, write_mtval }, |
8ceac5dc | 1593 | [CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip }, |
c7b95171 MC |
1594 | |
1595 | /* Supervisor Trap Setup */ | |
8ceac5dc BM |
1596 | [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus }, |
1597 | [CSR_SIE] = { "sie", smode, read_sie, write_sie }, | |
1598 | [CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec }, | |
1599 | [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren }, | |
c7b95171 MC |
1600 | |
1601 | /* Supervisor Trap Handling */ | |
8ceac5dc BM |
1602 | [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch }, |
1603 | [CSR_SEPC] = { "sepc", smode, read_sepc, write_sepc }, | |
1604 | [CSR_SCAUSE] = { "scause", smode, read_scause, write_scause }, | |
ac12b601 | 1605 | [CSR_STVAL] = { "stval", smode, read_stval, write_stval }, |
8ceac5dc | 1606 | [CSR_SIP] = { "sip", smode, NULL, NULL, rmw_sip }, |
c7b95171 MC |
1607 | |
1608 | /* Supervisor Protection and Translation */ | |
8ceac5dc BM |
1609 | [CSR_SATP] = { "satp", smode, read_satp, write_satp }, |
1610 | ||
1611 | [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus }, | |
1612 | [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg }, | |
1613 | [CSR_HIDELEG] = { "hideleg", hmode, read_hideleg, write_hideleg }, | |
1614 | [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip }, | |
1615 | [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip }, | |
1616 | [CSR_HIE] = { "hie", hmode, read_hie, write_hie }, | |
1617 | [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren }, | |
377cbb4b | 1618 | [CSR_HGEIE] = { "hgeie", hmode, read_zero, write_hgeie }, |
8ceac5dc BM |
1619 | [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval }, |
1620 | [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst }, | |
377cbb4b | 1621 | [CSR_HGEIP] = { "hgeip", hmode, read_zero, write_hgeip }, |
8ceac5dc BM |
1622 | [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp }, |
1623 | [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta }, | |
1624 | [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah }, | |
1625 | ||
1626 | [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus }, | |
1627 | [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip }, | |
1628 | [CSR_VSIE] = { "vsie", hmode, read_vsie, write_vsie }, | |
1629 | [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec }, | |
1630 | [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch }, | |
1631 | [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc }, | |
1632 | [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause }, | |
1633 | [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval }, | |
1634 | [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp }, | |
1635 | ||
1636 | [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2 }, | |
1637 | [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst }, | |
34cfb5f6 | 1638 | |
c7b95171 | 1639 | /* Physical Memory Protection */ |
2582a95c | 1640 | [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg }, |
8ceac5dc BM |
1641 | [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg }, |
1642 | [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, | |
1643 | [CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg }, | |
1644 | [CSR_PMPCFG3] = { "pmpcfg3", pmp, read_pmpcfg, write_pmpcfg }, | |
1645 | [CSR_PMPADDR0] = { "pmpaddr0", pmp, read_pmpaddr, write_pmpaddr }, | |
1646 | [CSR_PMPADDR1] = { "pmpaddr1", pmp, read_pmpaddr, write_pmpaddr }, | |
1647 | [CSR_PMPADDR2] = { "pmpaddr2", pmp, read_pmpaddr, write_pmpaddr }, | |
1648 | [CSR_PMPADDR3] = { "pmpaddr3", pmp, read_pmpaddr, write_pmpaddr }, | |
1649 | [CSR_PMPADDR4] = { "pmpaddr4", pmp, read_pmpaddr, write_pmpaddr }, | |
1650 | [CSR_PMPADDR5] = { "pmpaddr5", pmp, read_pmpaddr, write_pmpaddr }, | |
1651 | [CSR_PMPADDR6] = { "pmpaddr6", pmp, read_pmpaddr, write_pmpaddr }, | |
1652 | [CSR_PMPADDR7] = { "pmpaddr7", pmp, read_pmpaddr, write_pmpaddr }, | |
1653 | [CSR_PMPADDR8] = { "pmpaddr8", pmp, read_pmpaddr, write_pmpaddr }, | |
1654 | [CSR_PMPADDR9] = { "pmpaddr9", pmp, read_pmpaddr, write_pmpaddr }, | |
1655 | [CSR_PMPADDR10] = { "pmpaddr10", pmp, read_pmpaddr, write_pmpaddr }, | |
1656 | [CSR_PMPADDR11] = { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr }, | |
1657 | [CSR_PMPADDR12] = { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr }, | |
1658 | [CSR_PMPADDR13] = { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr }, | |
1659 | [CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr }, | |
1660 | [CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr }, | |
c7b95171 MC |
1661 | |
1662 | /* Performance Counters */ | |
8ceac5dc BM |
1663 | [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_zero }, |
1664 | [CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_zero }, | |
1665 | [CSR_HPMCOUNTER5] = { "hpmcounter5", ctr, read_zero }, | |
1666 | [CSR_HPMCOUNTER6] = { "hpmcounter6", ctr, read_zero }, | |
1667 | [CSR_HPMCOUNTER7] = { "hpmcounter7", ctr, read_zero }, | |
1668 | [CSR_HPMCOUNTER8] = { "hpmcounter8", ctr, read_zero }, | |
1669 | [CSR_HPMCOUNTER9] = { "hpmcounter9", ctr, read_zero }, | |
1670 | [CSR_HPMCOUNTER10] = { "hpmcounter10", ctr, read_zero }, | |
1671 | [CSR_HPMCOUNTER11] = { "hpmcounter11", ctr, read_zero }, | |
1672 | [CSR_HPMCOUNTER12] = { "hpmcounter12", ctr, read_zero }, | |
1673 | [CSR_HPMCOUNTER13] = { "hpmcounter13", ctr, read_zero }, | |
1674 | [CSR_HPMCOUNTER14] = { "hpmcounter14", ctr, read_zero }, | |
1675 | [CSR_HPMCOUNTER15] = { "hpmcounter15", ctr, read_zero }, | |
1676 | [CSR_HPMCOUNTER16] = { "hpmcounter16", ctr, read_zero }, | |
1677 | [CSR_HPMCOUNTER17] = { "hpmcounter17", ctr, read_zero }, | |
1678 | [CSR_HPMCOUNTER18] = { "hpmcounter18", ctr, read_zero }, | |
1679 | [CSR_HPMCOUNTER19] = { "hpmcounter19", ctr, read_zero }, | |
1680 | [CSR_HPMCOUNTER20] = { "hpmcounter20", ctr, read_zero }, | |
1681 | [CSR_HPMCOUNTER21] = { "hpmcounter21", ctr, read_zero }, | |
1682 | [CSR_HPMCOUNTER22] = { "hpmcounter22", ctr, read_zero }, | |
1683 | [CSR_HPMCOUNTER23] = { "hpmcounter23", ctr, read_zero }, | |
1684 | [CSR_HPMCOUNTER24] = { "hpmcounter24", ctr, read_zero }, | |
1685 | [CSR_HPMCOUNTER25] = { "hpmcounter25", ctr, read_zero }, | |
1686 | [CSR_HPMCOUNTER26] = { "hpmcounter26", ctr, read_zero }, | |
1687 | [CSR_HPMCOUNTER27] = { "hpmcounter27", ctr, read_zero }, | |
1688 | [CSR_HPMCOUNTER28] = { "hpmcounter28", ctr, read_zero }, | |
1689 | [CSR_HPMCOUNTER29] = { "hpmcounter29", ctr, read_zero }, | |
1690 | [CSR_HPMCOUNTER30] = { "hpmcounter30", ctr, read_zero }, | |
1691 | [CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_zero }, | |
1692 | ||
1693 | [CSR_MHPMCOUNTER3] = { "mhpmcounter3", any, read_zero }, | |
1694 | [CSR_MHPMCOUNTER4] = { "mhpmcounter4", any, read_zero }, | |
1695 | [CSR_MHPMCOUNTER5] = { "mhpmcounter5", any, read_zero }, | |
1696 | [CSR_MHPMCOUNTER6] = { "mhpmcounter6", any, read_zero }, | |
1697 | [CSR_MHPMCOUNTER7] = { "mhpmcounter7", any, read_zero }, | |
1698 | [CSR_MHPMCOUNTER8] = { "mhpmcounter8", any, read_zero }, | |
1699 | [CSR_MHPMCOUNTER9] = { "mhpmcounter9", any, read_zero }, | |
1700 | [CSR_MHPMCOUNTER10] = { "mhpmcounter10", any, read_zero }, | |
1701 | [CSR_MHPMCOUNTER11] = { "mhpmcounter11", any, read_zero }, | |
1702 | [CSR_MHPMCOUNTER12] = { "mhpmcounter12", any, read_zero }, | |
1703 | [CSR_MHPMCOUNTER13] = { "mhpmcounter13", any, read_zero }, | |
1704 | [CSR_MHPMCOUNTER14] = { "mhpmcounter14", any, read_zero }, | |
1705 | [CSR_MHPMCOUNTER15] = { "mhpmcounter15", any, read_zero }, | |
1706 | [CSR_MHPMCOUNTER16] = { "mhpmcounter16", any, read_zero }, | |
1707 | [CSR_MHPMCOUNTER17] = { "mhpmcounter17", any, read_zero }, | |
1708 | [CSR_MHPMCOUNTER18] = { "mhpmcounter18", any, read_zero }, | |
1709 | [CSR_MHPMCOUNTER19] = { "mhpmcounter19", any, read_zero }, | |
1710 | [CSR_MHPMCOUNTER20] = { "mhpmcounter20", any, read_zero }, | |
1711 | [CSR_MHPMCOUNTER21] = { "mhpmcounter21", any, read_zero }, | |
1712 | [CSR_MHPMCOUNTER22] = { "mhpmcounter22", any, read_zero }, | |
1713 | [CSR_MHPMCOUNTER23] = { "mhpmcounter23", any, read_zero }, | |
1714 | [CSR_MHPMCOUNTER24] = { "mhpmcounter24", any, read_zero }, | |
1715 | [CSR_MHPMCOUNTER25] = { "mhpmcounter25", any, read_zero }, | |
1716 | [CSR_MHPMCOUNTER26] = { "mhpmcounter26", any, read_zero }, | |
1717 | [CSR_MHPMCOUNTER27] = { "mhpmcounter27", any, read_zero }, | |
1718 | [CSR_MHPMCOUNTER28] = { "mhpmcounter28", any, read_zero }, | |
1719 | [CSR_MHPMCOUNTER29] = { "mhpmcounter29", any, read_zero }, | |
1720 | [CSR_MHPMCOUNTER30] = { "mhpmcounter30", any, read_zero }, | |
1721 | [CSR_MHPMCOUNTER31] = { "mhpmcounter31", any, read_zero }, | |
1722 | ||
1723 | [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_zero }, | |
1724 | [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_zero }, | |
1725 | [CSR_MHPMEVENT5] = { "mhpmevent5", any, read_zero }, | |
1726 | [CSR_MHPMEVENT6] = { "mhpmevent6", any, read_zero }, | |
1727 | [CSR_MHPMEVENT7] = { "mhpmevent7", any, read_zero }, | |
1728 | [CSR_MHPMEVENT8] = { "mhpmevent8", any, read_zero }, | |
1729 | [CSR_MHPMEVENT9] = { "mhpmevent9", any, read_zero }, | |
1730 | [CSR_MHPMEVENT10] = { "mhpmevent10", any, read_zero }, | |
1731 | [CSR_MHPMEVENT11] = { "mhpmevent11", any, read_zero }, | |
1732 | [CSR_MHPMEVENT12] = { "mhpmevent12", any, read_zero }, | |
1733 | [CSR_MHPMEVENT13] = { "mhpmevent13", any, read_zero }, | |
1734 | [CSR_MHPMEVENT14] = { "mhpmevent14", any, read_zero }, | |
1735 | [CSR_MHPMEVENT15] = { "mhpmevent15", any, read_zero }, | |
1736 | [CSR_MHPMEVENT16] = { "mhpmevent16", any, read_zero }, | |
1737 | [CSR_MHPMEVENT17] = { "mhpmevent17", any, read_zero }, | |
1738 | [CSR_MHPMEVENT18] = { "mhpmevent18", any, read_zero }, | |
1739 | [CSR_MHPMEVENT19] = { "mhpmevent19", any, read_zero }, | |
1740 | [CSR_MHPMEVENT20] = { "mhpmevent20", any, read_zero }, | |
1741 | [CSR_MHPMEVENT21] = { "mhpmevent21", any, read_zero }, | |
1742 | [CSR_MHPMEVENT22] = { "mhpmevent22", any, read_zero }, | |
1743 | [CSR_MHPMEVENT23] = { "mhpmevent23", any, read_zero }, | |
1744 | [CSR_MHPMEVENT24] = { "mhpmevent24", any, read_zero }, | |
1745 | [CSR_MHPMEVENT25] = { "mhpmevent25", any, read_zero }, | |
1746 | [CSR_MHPMEVENT26] = { "mhpmevent26", any, read_zero }, | |
1747 | [CSR_MHPMEVENT27] = { "mhpmevent27", any, read_zero }, | |
1748 | [CSR_MHPMEVENT28] = { "mhpmevent28", any, read_zero }, | |
1749 | [CSR_MHPMEVENT29] = { "mhpmevent29", any, read_zero }, | |
1750 | [CSR_MHPMEVENT30] = { "mhpmevent30", any, read_zero }, | |
1751 | [CSR_MHPMEVENT31] = { "mhpmevent31", any, read_zero }, | |
1752 | ||
1753 | [CSR_HPMCOUNTER3H] = { "hpmcounter3h", ctr32, read_zero }, | |
1754 | [CSR_HPMCOUNTER4H] = { "hpmcounter4h", ctr32, read_zero }, | |
1755 | [CSR_HPMCOUNTER5H] = { "hpmcounter5h", ctr32, read_zero }, | |
1756 | [CSR_HPMCOUNTER6H] = { "hpmcounter6h", ctr32, read_zero }, | |
1757 | [CSR_HPMCOUNTER7H] = { "hpmcounter7h", ctr32, read_zero }, | |
1758 | [CSR_HPMCOUNTER8H] = { "hpmcounter8h", ctr32, read_zero }, | |
1759 | [CSR_HPMCOUNTER9H] = { "hpmcounter9h", ctr32, read_zero }, | |
1760 | [CSR_HPMCOUNTER10H] = { "hpmcounter10h", ctr32, read_zero }, | |
1761 | [CSR_HPMCOUNTER11H] = { "hpmcounter11h", ctr32, read_zero }, | |
1762 | [CSR_HPMCOUNTER12H] = { "hpmcounter12h", ctr32, read_zero }, | |
1763 | [CSR_HPMCOUNTER13H] = { "hpmcounter13h", ctr32, read_zero }, | |
1764 | [CSR_HPMCOUNTER14H] = { "hpmcounter14h", ctr32, read_zero }, | |
1765 | [CSR_HPMCOUNTER15H] = { "hpmcounter15h", ctr32, read_zero }, | |
1766 | [CSR_HPMCOUNTER16H] = { "hpmcounter16h", ctr32, read_zero }, | |
1767 | [CSR_HPMCOUNTER17H] = { "hpmcounter17h", ctr32, read_zero }, | |
1768 | [CSR_HPMCOUNTER18H] = { "hpmcounter18h", ctr32, read_zero }, | |
1769 | [CSR_HPMCOUNTER19H] = { "hpmcounter19h", ctr32, read_zero }, | |
1770 | [CSR_HPMCOUNTER20H] = { "hpmcounter20h", ctr32, read_zero }, | |
1771 | [CSR_HPMCOUNTER21H] = { "hpmcounter21h", ctr32, read_zero }, | |
1772 | [CSR_HPMCOUNTER22H] = { "hpmcounter22h", ctr32, read_zero }, | |
1773 | [CSR_HPMCOUNTER23H] = { "hpmcounter23h", ctr32, read_zero }, | |
1774 | [CSR_HPMCOUNTER24H] = { "hpmcounter24h", ctr32, read_zero }, | |
1775 | [CSR_HPMCOUNTER25H] = { "hpmcounter25h", ctr32, read_zero }, | |
1776 | [CSR_HPMCOUNTER26H] = { "hpmcounter26h", ctr32, read_zero }, | |
1777 | [CSR_HPMCOUNTER27H] = { "hpmcounter27h", ctr32, read_zero }, | |
1778 | [CSR_HPMCOUNTER28H] = { "hpmcounter28h", ctr32, read_zero }, | |
1779 | [CSR_HPMCOUNTER29H] = { "hpmcounter29h", ctr32, read_zero }, | |
1780 | [CSR_HPMCOUNTER30H] = { "hpmcounter30h", ctr32, read_zero }, | |
1781 | [CSR_HPMCOUNTER31H] = { "hpmcounter31h", ctr32, read_zero }, | |
1782 | ||
1783 | [CSR_MHPMCOUNTER3H] = { "mhpmcounter3h", any32, read_zero }, | |
1784 | [CSR_MHPMCOUNTER4H] = { "mhpmcounter4h", any32, read_zero }, | |
1785 | [CSR_MHPMCOUNTER5H] = { "mhpmcounter5h", any32, read_zero }, | |
1786 | [CSR_MHPMCOUNTER6H] = { "mhpmcounter6h", any32, read_zero }, | |
1787 | [CSR_MHPMCOUNTER7H] = { "mhpmcounter7h", any32, read_zero }, | |
1788 | [CSR_MHPMCOUNTER8H] = { "mhpmcounter8h", any32, read_zero }, | |
1789 | [CSR_MHPMCOUNTER9H] = { "mhpmcounter9h", any32, read_zero }, | |
1790 | [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", any32, read_zero }, | |
1791 | [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", any32, read_zero }, | |
1792 | [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", any32, read_zero }, | |
1793 | [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", any32, read_zero }, | |
1794 | [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", any32, read_zero }, | |
1795 | [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", any32, read_zero }, | |
1796 | [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", any32, read_zero }, | |
1797 | [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", any32, read_zero }, | |
1798 | [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", any32, read_zero }, | |
1799 | [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", any32, read_zero }, | |
1800 | [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", any32, read_zero }, | |
1801 | [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", any32, read_zero }, | |
1802 | [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", any32, read_zero }, | |
1803 | [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", any32, read_zero }, | |
1804 | [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", any32, read_zero }, | |
1805 | [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", any32, read_zero }, | |
1806 | [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", any32, read_zero }, | |
1807 | [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", any32, read_zero }, | |
1808 | [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", any32, read_zero }, | |
1809 | [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32, read_zero }, | |
1810 | [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32, read_zero }, | |
1811 | [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32, read_zero }, | |
c7b95171 MC |
1812 | #endif /* !CONFIG_USER_ONLY */ |
1813 | }; |