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c7b95171 MC |
1 | /* |
2 | * RISC-V Control and Status Registers. | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017-2018 SiFive, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2 or later, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
21 | #include "qemu/log.h" | |
22 | #include "cpu.h" | |
23 | #include "qemu/main-loop.h" | |
24 | #include "exec/exec-all.h" | |
25 | ||
c7b95171 MC |
26 | /* CSR function table public API */ |
27 | void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) | |
28 | { | |
29 | *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)]; | |
30 | } | |
31 | ||
32 | void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) | |
33 | { | |
34 | csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops; | |
35 | } | |
36 | ||
a88365c1 | 37 | /* Predicates */ |
0e62f92e | 38 | static RISCVException fs(CPURISCVState *env, int csrno) |
a88365c1 MC |
39 | { |
40 | #if !defined(CONFIG_USER_ONLY) | |
b345b480 | 41 | if (!env->debugger && !riscv_cpu_fp_enabled(env)) { |
0e62f92e | 42 | return RISCV_EXCP_ILLEGAL_INST; |
a88365c1 MC |
43 | } |
44 | #endif | |
0e62f92e | 45 | return RISCV_EXCP_NONE; |
a88365c1 MC |
46 | } |
47 | ||
0e62f92e | 48 | static RISCVException vs(CPURISCVState *env, int csrno) |
8e3a1f18 | 49 | { |
e91a7227 | 50 | if (env->misa_ext & RVV) { |
0e62f92e | 51 | return RISCV_EXCP_NONE; |
8e3a1f18 | 52 | } |
0e62f92e | 53 | return RISCV_EXCP_ILLEGAL_INST; |
8e3a1f18 LZ |
54 | } |
55 | ||
0e62f92e | 56 | static RISCVException ctr(CPURISCVState *env, int csrno) |
a88365c1 MC |
57 | { |
58 | #if !defined(CONFIG_USER_ONLY) | |
0a13a5b8 AF |
59 | CPUState *cs = env_cpu(env); |
60 | RISCVCPU *cpu = RISCV_CPU(cs); | |
0a13a5b8 AF |
61 | |
62 | if (!cpu->cfg.ext_counters) { | |
63 | /* The Counters extensions is not enabled */ | |
0e62f92e | 64 | return RISCV_EXCP_ILLEGAL_INST; |
0a13a5b8 | 65 | } |
e39a8320 AF |
66 | |
67 | if (riscv_cpu_virt_enabled(env)) { | |
68 | switch (csrno) { | |
69 | case CSR_CYCLE: | |
db70794e BM |
70 | if (!get_field(env->hcounteren, COUNTEREN_CY) && |
71 | get_field(env->mcounteren, COUNTEREN_CY)) { | |
0e62f92e | 72 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
e39a8320 AF |
73 | } |
74 | break; | |
75 | case CSR_TIME: | |
db70794e BM |
76 | if (!get_field(env->hcounteren, COUNTEREN_TM) && |
77 | get_field(env->mcounteren, COUNTEREN_TM)) { | |
0e62f92e | 78 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
e39a8320 AF |
79 | } |
80 | break; | |
81 | case CSR_INSTRET: | |
db70794e BM |
82 | if (!get_field(env->hcounteren, COUNTEREN_IR) && |
83 | get_field(env->mcounteren, COUNTEREN_IR)) { | |
0e62f92e | 84 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
e39a8320 AF |
85 | } |
86 | break; | |
87 | case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: | |
88 | if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) && | |
89 | get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) { | |
0e62f92e | 90 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
e39a8320 AF |
91 | } |
92 | break; | |
8987cdc4 | 93 | } |
db23e5d9 | 94 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
8987cdc4 AF |
95 | switch (csrno) { |
96 | case CSR_CYCLEH: | |
db70794e BM |
97 | if (!get_field(env->hcounteren, COUNTEREN_CY) && |
98 | get_field(env->mcounteren, COUNTEREN_CY)) { | |
0e62f92e | 99 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
8987cdc4 AF |
100 | } |
101 | break; | |
102 | case CSR_TIMEH: | |
db70794e BM |
103 | if (!get_field(env->hcounteren, COUNTEREN_TM) && |
104 | get_field(env->mcounteren, COUNTEREN_TM)) { | |
0e62f92e | 105 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
8987cdc4 AF |
106 | } |
107 | break; | |
108 | case CSR_INSTRETH: | |
db70794e BM |
109 | if (!get_field(env->hcounteren, COUNTEREN_IR) && |
110 | get_field(env->mcounteren, COUNTEREN_IR)) { | |
0e62f92e | 111 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
8987cdc4 AF |
112 | } |
113 | break; | |
114 | case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: | |
115 | if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) && | |
116 | get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) { | |
0e62f92e | 117 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
8987cdc4 AF |
118 | } |
119 | break; | |
e39a8320 | 120 | } |
e39a8320 AF |
121 | } |
122 | } | |
a88365c1 | 123 | #endif |
0e62f92e | 124 | return RISCV_EXCP_NONE; |
a88365c1 MC |
125 | } |
126 | ||
0e62f92e | 127 | static RISCVException ctr32(CPURISCVState *env, int csrno) |
8987cdc4 | 128 | { |
db23e5d9 | 129 | if (riscv_cpu_mxl(env) != MXL_RV32) { |
0e62f92e | 130 | return RISCV_EXCP_ILLEGAL_INST; |
8987cdc4 AF |
131 | } |
132 | ||
133 | return ctr(env, csrno); | |
134 | } | |
135 | ||
a88365c1 | 136 | #if !defined(CONFIG_USER_ONLY) |
0e62f92e | 137 | static RISCVException any(CPURISCVState *env, int csrno) |
a88365c1 | 138 | { |
0e62f92e | 139 | return RISCV_EXCP_NONE; |
a88365c1 MC |
140 | } |
141 | ||
0e62f92e | 142 | static RISCVException any32(CPURISCVState *env, int csrno) |
8987cdc4 | 143 | { |
db23e5d9 | 144 | if (riscv_cpu_mxl(env) != MXL_RV32) { |
0e62f92e | 145 | return RISCV_EXCP_ILLEGAL_INST; |
8987cdc4 AF |
146 | } |
147 | ||
148 | return any(env, csrno); | |
149 | ||
150 | } | |
151 | ||
0e62f92e | 152 | static RISCVException smode(CPURISCVState *env, int csrno) |
a88365c1 | 153 | { |
0e62f92e AF |
154 | if (riscv_has_ext(env, RVS)) { |
155 | return RISCV_EXCP_NONE; | |
156 | } | |
157 | ||
158 | return RISCV_EXCP_ILLEGAL_INST; | |
a88365c1 MC |
159 | } |
160 | ||
0e62f92e | 161 | static RISCVException hmode(CPURISCVState *env, int csrno) |
ff2cc129 AF |
162 | { |
163 | if (riscv_has_ext(env, RVS) && | |
164 | riscv_has_ext(env, RVH)) { | |
165 | /* Hypervisor extension is supported */ | |
166 | if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || | |
167 | env->priv == PRV_M) { | |
0e62f92e | 168 | return RISCV_EXCP_NONE; |
e39a8320 | 169 | } else { |
0e62f92e | 170 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
ff2cc129 AF |
171 | } |
172 | } | |
173 | ||
0e62f92e | 174 | return RISCV_EXCP_ILLEGAL_INST; |
ff2cc129 AF |
175 | } |
176 | ||
0e62f92e | 177 | static RISCVException hmode32(CPURISCVState *env, int csrno) |
8987cdc4 | 178 | { |
db23e5d9 | 179 | if (riscv_cpu_mxl(env) != MXL_RV32) { |
d6f20dac AF |
180 | if (riscv_cpu_virt_enabled(env)) { |
181 | return RISCV_EXCP_ILLEGAL_INST; | |
182 | } else { | |
183 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; | |
184 | } | |
8987cdc4 AF |
185 | } |
186 | ||
187 | return hmode(env, csrno); | |
188 | ||
189 | } | |
190 | ||
4bbe8033 AB |
191 | /* Checks if PointerMasking registers could be accessed */ |
192 | static RISCVException pointer_masking(CPURISCVState *env, int csrno) | |
193 | { | |
194 | /* Check if j-ext is present */ | |
195 | if (riscv_has_ext(env, RVJ)) { | |
196 | return RISCV_EXCP_NONE; | |
197 | } | |
198 | return RISCV_EXCP_ILLEGAL_INST; | |
199 | } | |
200 | ||
0e62f92e | 201 | static RISCVException pmp(CPURISCVState *env, int csrno) |
a88365c1 | 202 | { |
0e62f92e AF |
203 | if (riscv_feature(env, RISCV_FEATURE_PMP)) { |
204 | return RISCV_EXCP_NONE; | |
205 | } | |
206 | ||
207 | return RISCV_EXCP_ILLEGAL_INST; | |
a88365c1 | 208 | } |
2582a95c HW |
209 | |
210 | static RISCVException epmp(CPURISCVState *env, int csrno) | |
211 | { | |
212 | if (env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) { | |
213 | return RISCV_EXCP_NONE; | |
214 | } | |
215 | ||
216 | return RISCV_EXCP_ILLEGAL_INST; | |
217 | } | |
a88365c1 MC |
218 | #endif |
219 | ||
c7b95171 | 220 | /* User Floating-Point CSRs */ |
605def6e AF |
221 | static RISCVException read_fflags(CPURISCVState *env, int csrno, |
222 | target_ulong *val) | |
c7b95171 | 223 | { |
fb738839 | 224 | *val = riscv_cpu_get_fflags(env); |
605def6e | 225 | return RISCV_EXCP_NONE; |
c7b95171 MC |
226 | } |
227 | ||
605def6e AF |
228 | static RISCVException write_fflags(CPURISCVState *env, int csrno, |
229 | target_ulong val) | |
c7b95171 MC |
230 | { |
231 | #if !defined(CONFIG_USER_ONLY) | |
c7b95171 MC |
232 | env->mstatus |= MSTATUS_FS; |
233 | #endif | |
fb738839 | 234 | riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT)); |
605def6e | 235 | return RISCV_EXCP_NONE; |
c7b95171 MC |
236 | } |
237 | ||
605def6e AF |
238 | static RISCVException read_frm(CPURISCVState *env, int csrno, |
239 | target_ulong *val) | |
c7b95171 | 240 | { |
c7b95171 | 241 | *val = env->frm; |
605def6e | 242 | return RISCV_EXCP_NONE; |
c7b95171 MC |
243 | } |
244 | ||
605def6e AF |
245 | static RISCVException write_frm(CPURISCVState *env, int csrno, |
246 | target_ulong val) | |
c7b95171 MC |
247 | { |
248 | #if !defined(CONFIG_USER_ONLY) | |
c7b95171 MC |
249 | env->mstatus |= MSTATUS_FS; |
250 | #endif | |
251 | env->frm = val & (FSR_RD >> FSR_RD_SHIFT); | |
605def6e | 252 | return RISCV_EXCP_NONE; |
c7b95171 MC |
253 | } |
254 | ||
605def6e AF |
255 | static RISCVException read_fcsr(CPURISCVState *env, int csrno, |
256 | target_ulong *val) | |
c7b95171 | 257 | { |
fb738839 | 258 | *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) |
c7b95171 | 259 | | (env->frm << FSR_RD_SHIFT); |
605def6e | 260 | return RISCV_EXCP_NONE; |
c7b95171 MC |
261 | } |
262 | ||
605def6e AF |
263 | static RISCVException write_fcsr(CPURISCVState *env, int csrno, |
264 | target_ulong val) | |
c7b95171 MC |
265 | { |
266 | #if !defined(CONFIG_USER_ONLY) | |
c7b95171 MC |
267 | env->mstatus |= MSTATUS_FS; |
268 | #endif | |
269 | env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; | |
fb738839 | 270 | riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT); |
605def6e | 271 | return RISCV_EXCP_NONE; |
c7b95171 MC |
272 | } |
273 | ||
605def6e AF |
274 | static RISCVException read_vtype(CPURISCVState *env, int csrno, |
275 | target_ulong *val) | |
8e3a1f18 LZ |
276 | { |
277 | *val = env->vtype; | |
605def6e | 278 | return RISCV_EXCP_NONE; |
8e3a1f18 LZ |
279 | } |
280 | ||
605def6e AF |
281 | static RISCVException read_vl(CPURISCVState *env, int csrno, |
282 | target_ulong *val) | |
8e3a1f18 LZ |
283 | { |
284 | *val = env->vl; | |
605def6e | 285 | return RISCV_EXCP_NONE; |
8e3a1f18 LZ |
286 | } |
287 | ||
2e565054 GH |
288 | static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val) |
289 | { | |
290 | *val = env_archcpu(env)->cfg.vlen >> 3; | |
291 | return RISCV_EXCP_NONE; | |
292 | } | |
293 | ||
605def6e AF |
294 | static RISCVException read_vxrm(CPURISCVState *env, int csrno, |
295 | target_ulong *val) | |
8e3a1f18 LZ |
296 | { |
297 | *val = env->vxrm; | |
605def6e | 298 | return RISCV_EXCP_NONE; |
8e3a1f18 LZ |
299 | } |
300 | ||
605def6e AF |
301 | static RISCVException write_vxrm(CPURISCVState *env, int csrno, |
302 | target_ulong val) | |
8e3a1f18 | 303 | { |
61b4b69d LZ |
304 | #if !defined(CONFIG_USER_ONLY) |
305 | env->mstatus |= MSTATUS_VS; | |
306 | #endif | |
8e3a1f18 | 307 | env->vxrm = val; |
605def6e | 308 | return RISCV_EXCP_NONE; |
8e3a1f18 LZ |
309 | } |
310 | ||
605def6e AF |
311 | static RISCVException read_vxsat(CPURISCVState *env, int csrno, |
312 | target_ulong *val) | |
8e3a1f18 LZ |
313 | { |
314 | *val = env->vxsat; | |
605def6e | 315 | return RISCV_EXCP_NONE; |
8e3a1f18 LZ |
316 | } |
317 | ||
605def6e AF |
318 | static RISCVException write_vxsat(CPURISCVState *env, int csrno, |
319 | target_ulong val) | |
8e3a1f18 | 320 | { |
61b4b69d LZ |
321 | #if !defined(CONFIG_USER_ONLY) |
322 | env->mstatus |= MSTATUS_VS; | |
323 | #endif | |
8e3a1f18 | 324 | env->vxsat = val; |
605def6e | 325 | return RISCV_EXCP_NONE; |
8e3a1f18 LZ |
326 | } |
327 | ||
605def6e AF |
328 | static RISCVException read_vstart(CPURISCVState *env, int csrno, |
329 | target_ulong *val) | |
8e3a1f18 LZ |
330 | { |
331 | *val = env->vstart; | |
605def6e | 332 | return RISCV_EXCP_NONE; |
8e3a1f18 LZ |
333 | } |
334 | ||
605def6e AF |
335 | static RISCVException write_vstart(CPURISCVState *env, int csrno, |
336 | target_ulong val) | |
8e3a1f18 | 337 | { |
61b4b69d LZ |
338 | #if !defined(CONFIG_USER_ONLY) |
339 | env->mstatus |= MSTATUS_VS; | |
340 | #endif | |
8e3a1f18 | 341 | env->vstart = val; |
605def6e | 342 | return RISCV_EXCP_NONE; |
8e3a1f18 LZ |
343 | } |
344 | ||
4594fa5a LZ |
345 | static int read_vcsr(CPURISCVState *env, int csrno, target_ulong *val) |
346 | { | |
347 | *val = (env->vxrm << VCSR_VXRM_SHIFT) | (env->vxsat << VCSR_VXSAT_SHIFT); | |
348 | return RISCV_EXCP_NONE; | |
349 | } | |
350 | ||
351 | static int write_vcsr(CPURISCVState *env, int csrno, target_ulong val) | |
352 | { | |
353 | #if !defined(CONFIG_USER_ONLY) | |
354 | env->mstatus |= MSTATUS_VS; | |
355 | #endif | |
356 | env->vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT; | |
357 | env->vxsat = (val & VCSR_VXSAT) >> VCSR_VXSAT_SHIFT; | |
358 | return RISCV_EXCP_NONE; | |
359 | } | |
360 | ||
c7b95171 | 361 | /* User Timers and Counters */ |
605def6e AF |
362 | static RISCVException read_instret(CPURISCVState *env, int csrno, |
363 | target_ulong *val) | |
c7b95171 | 364 | { |
c7b95171 | 365 | #if !defined(CONFIG_USER_ONLY) |
740b1759 | 366 | if (icount_enabled()) { |
8191d368 | 367 | *val = icount_get(); |
c7b95171 MC |
368 | } else { |
369 | *val = cpu_get_host_ticks(); | |
370 | } | |
371 | #else | |
372 | *val = cpu_get_host_ticks(); | |
373 | #endif | |
605def6e | 374 | return RISCV_EXCP_NONE; |
c7b95171 MC |
375 | } |
376 | ||
605def6e AF |
377 | static RISCVException read_instreth(CPURISCVState *env, int csrno, |
378 | target_ulong *val) | |
c7b95171 | 379 | { |
c7b95171 | 380 | #if !defined(CONFIG_USER_ONLY) |
740b1759 | 381 | if (icount_enabled()) { |
8191d368 | 382 | *val = icount_get() >> 32; |
c7b95171 MC |
383 | } else { |
384 | *val = cpu_get_host_ticks() >> 32; | |
385 | } | |
386 | #else | |
387 | *val = cpu_get_host_ticks() >> 32; | |
388 | #endif | |
605def6e | 389 | return RISCV_EXCP_NONE; |
c7b95171 | 390 | } |
c7b95171 MC |
391 | |
392 | #if defined(CONFIG_USER_ONLY) | |
605def6e AF |
393 | static RISCVException read_time(CPURISCVState *env, int csrno, |
394 | target_ulong *val) | |
c7b95171 MC |
395 | { |
396 | *val = cpu_get_host_ticks(); | |
605def6e | 397 | return RISCV_EXCP_NONE; |
c7b95171 MC |
398 | } |
399 | ||
605def6e AF |
400 | static RISCVException read_timeh(CPURISCVState *env, int csrno, |
401 | target_ulong *val) | |
c7b95171 MC |
402 | { |
403 | *val = cpu_get_host_ticks() >> 32; | |
605def6e | 404 | return RISCV_EXCP_NONE; |
c7b95171 | 405 | } |
c7b95171 MC |
406 | |
407 | #else /* CONFIG_USER_ONLY */ | |
408 | ||
605def6e AF |
409 | static RISCVException read_time(CPURISCVState *env, int csrno, |
410 | target_ulong *val) | |
c6957248 AP |
411 | { |
412 | uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; | |
413 | ||
414 | if (!env->rdtime_fn) { | |
605def6e | 415 | return RISCV_EXCP_ILLEGAL_INST; |
c6957248 AP |
416 | } |
417 | ||
a47ef6e9 | 418 | *val = env->rdtime_fn(env->rdtime_fn_arg) + delta; |
605def6e | 419 | return RISCV_EXCP_NONE; |
c6957248 AP |
420 | } |
421 | ||
605def6e AF |
422 | static RISCVException read_timeh(CPURISCVState *env, int csrno, |
423 | target_ulong *val) | |
c6957248 AP |
424 | { |
425 | uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; | |
426 | ||
427 | if (!env->rdtime_fn) { | |
605def6e | 428 | return RISCV_EXCP_ILLEGAL_INST; |
c6957248 AP |
429 | } |
430 | ||
a47ef6e9 | 431 | *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32; |
605def6e | 432 | return RISCV_EXCP_NONE; |
c6957248 | 433 | } |
c6957248 | 434 | |
c7b95171 MC |
435 | /* Machine constants */ |
436 | ||
ff2cc129 AF |
437 | #define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP) |
438 | #define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP) | |
439 | #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) | |
c7b95171 | 440 | |
d0e53ce3 AF |
441 | static const target_ulong delegable_ints = S_MODE_INTERRUPTS | |
442 | VS_MODE_INTERRUPTS; | |
bc083a51 | 443 | static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS; |
d0e53ce3 AF |
444 | static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | |
445 | VS_MODE_INTERRUPTS; | |
bc083a51 JM |
446 | #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \ |
447 | (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \ | |
448 | (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \ | |
449 | (1ULL << (RISCV_EXCP_BREAKPOINT)) | \ | |
450 | (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | \ | |
451 | (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | \ | |
452 | (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | \ | |
453 | (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | \ | |
454 | (1ULL << (RISCV_EXCP_U_ECALL)) | \ | |
455 | (1ULL << (RISCV_EXCP_S_ECALL)) | \ | |
456 | (1ULL << (RISCV_EXCP_VS_ECALL)) | \ | |
457 | (1ULL << (RISCV_EXCP_M_ECALL)) | \ | |
458 | (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | \ | |
459 | (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | \ | |
460 | (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | \ | |
461 | (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | \ | |
462 | (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | \ | |
463 | (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | \ | |
464 | (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))) | |
465 | static const target_ulong vs_delegable_excps = DELEGABLE_EXCPS & | |
466 | ~((1ULL << (RISCV_EXCP_S_ECALL)) | | |
467 | (1ULL << (RISCV_EXCP_VS_ECALL)) | | |
468 | (1ULL << (RISCV_EXCP_M_ECALL)) | | |
469 | (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | | |
470 | (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | | |
471 | (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | | |
472 | (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))); | |
c7b95171 MC |
473 | static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | |
474 | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | | |
89a81e37 | 475 | SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS; |
087b051a | 476 | static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP; |
e89b631c GK |
477 | static const target_ulong hip_writable_mask = MIP_VSSIP; |
478 | static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; | |
8747c9ee | 479 | static const target_ulong vsip_writable_mask = MIP_VSSIP; |
c7b95171 | 480 | |
8987cdc4 | 481 | static const char valid_vm_1_10_32[16] = { |
c7b95171 MC |
482 | [VM_1_10_MBARE] = 1, |
483 | [VM_1_10_SV32] = 1 | |
484 | }; | |
8987cdc4 AF |
485 | |
486 | static const char valid_vm_1_10_64[16] = { | |
c7b95171 MC |
487 | [VM_1_10_MBARE] = 1, |
488 | [VM_1_10_SV39] = 1, | |
489 | [VM_1_10_SV48] = 1, | |
490 | [VM_1_10_SV57] = 1 | |
491 | }; | |
c7b95171 MC |
492 | |
493 | /* Machine Information Registers */ | |
605def6e AF |
494 | static RISCVException read_zero(CPURISCVState *env, int csrno, |
495 | target_ulong *val) | |
c7b95171 | 496 | { |
605def6e AF |
497 | *val = 0; |
498 | return RISCV_EXCP_NONE; | |
c7b95171 MC |
499 | } |
500 | ||
605def6e AF |
501 | static RISCVException read_mhartid(CPURISCVState *env, int csrno, |
502 | target_ulong *val) | |
c7b95171 MC |
503 | { |
504 | *val = env->mhartid; | |
605def6e | 505 | return RISCV_EXCP_NONE; |
c7b95171 MC |
506 | } |
507 | ||
508 | /* Machine Trap Setup */ | |
b550f894 RH |
509 | |
510 | /* We do not store SD explicitly, only compute it on demand. */ | |
511 | static uint64_t add_status_sd(RISCVMXL xl, uint64_t status) | |
512 | { | |
513 | if ((status & MSTATUS_FS) == MSTATUS_FS || | |
c36b2f1a | 514 | (status & MSTATUS_VS) == MSTATUS_VS || |
b550f894 RH |
515 | (status & MSTATUS_XS) == MSTATUS_XS) { |
516 | switch (xl) { | |
517 | case MXL_RV32: | |
518 | return status | MSTATUS32_SD; | |
519 | case MXL_RV64: | |
520 | return status | MSTATUS64_SD; | |
521 | default: | |
522 | g_assert_not_reached(); | |
523 | } | |
524 | } | |
525 | return status; | |
526 | } | |
527 | ||
605def6e AF |
528 | static RISCVException read_mstatus(CPURISCVState *env, int csrno, |
529 | target_ulong *val) | |
c7b95171 | 530 | { |
b550f894 | 531 | *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus); |
605def6e | 532 | return RISCV_EXCP_NONE; |
c7b95171 MC |
533 | } |
534 | ||
535 | static int validate_vm(CPURISCVState *env, target_ulong vm) | |
536 | { | |
db23e5d9 | 537 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
8987cdc4 AF |
538 | return valid_vm_1_10_32[vm & 0xf]; |
539 | } else { | |
540 | return valid_vm_1_10_64[vm & 0xf]; | |
541 | } | |
c7b95171 MC |
542 | } |
543 | ||
605def6e AF |
544 | static RISCVException write_mstatus(CPURISCVState *env, int csrno, |
545 | target_ulong val) | |
c7b95171 | 546 | { |
284d697c YJ |
547 | uint64_t mstatus = env->mstatus; |
548 | uint64_t mask = 0; | |
c7b95171 MC |
549 | |
550 | /* flush tlb on mstatus fields that affect VM */ | |
1a9540d1 AF |
551 | if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | |
552 | MSTATUS_MPRV | MSTATUS_SUM)) { | |
553 | tlb_flush(env_cpu(env)); | |
c7b95171 | 554 | } |
1a9540d1 AF |
555 | mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | |
556 | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | | |
557 | MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | | |
61b4b69d | 558 | MSTATUS_TW | MSTATUS_VS; |
8987cdc4 | 559 | |
db23e5d9 | 560 | if (riscv_cpu_mxl(env) != MXL_RV32) { |
8987cdc4 AF |
561 | /* |
562 | * RV32: MPV and GVA are not in mstatus. The current plan is to | |
563 | * add them to mstatush. For now, we just don't support it. | |
564 | */ | |
565 | mask |= MSTATUS_MPV | MSTATUS_GVA; | |
566 | } | |
c7b95171 MC |
567 | |
568 | mstatus = (mstatus & ~mask) | (val & mask); | |
569 | ||
b550f894 | 570 | if (riscv_cpu_mxl(env) == MXL_RV64) { |
92371bd9 RH |
571 | /* SXL and UXL fields are for now read only */ |
572 | mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64); | |
573 | mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64); | |
4fd7455b | 574 | } |
c7b95171 MC |
575 | env->mstatus = mstatus; |
576 | ||
605def6e | 577 | return RISCV_EXCP_NONE; |
c7b95171 MC |
578 | } |
579 | ||
605def6e AF |
580 | static RISCVException read_mstatush(CPURISCVState *env, int csrno, |
581 | target_ulong *val) | |
551fa7e8 | 582 | { |
284d697c | 583 | *val = env->mstatus >> 32; |
605def6e | 584 | return RISCV_EXCP_NONE; |
551fa7e8 AF |
585 | } |
586 | ||
605def6e AF |
587 | static RISCVException write_mstatush(CPURISCVState *env, int csrno, |
588 | target_ulong val) | |
551fa7e8 | 589 | { |
284d697c YJ |
590 | uint64_t valh = (uint64_t)val << 32; |
591 | uint64_t mask = MSTATUS_MPV | MSTATUS_GVA; | |
592 | ||
593 | if ((valh ^ env->mstatus) & (MSTATUS_MPV)) { | |
551fa7e8 AF |
594 | tlb_flush(env_cpu(env)); |
595 | } | |
596 | ||
284d697c | 597 | env->mstatus = (env->mstatus & ~mask) | (valh & mask); |
551fa7e8 | 598 | |
605def6e | 599 | return RISCV_EXCP_NONE; |
551fa7e8 | 600 | } |
551fa7e8 | 601 | |
605def6e AF |
602 | static RISCVException read_misa(CPURISCVState *env, int csrno, |
603 | target_ulong *val) | |
c7b95171 | 604 | { |
e91a7227 RH |
605 | target_ulong misa; |
606 | ||
607 | switch (env->misa_mxl) { | |
608 | case MXL_RV32: | |
609 | misa = (target_ulong)MXL_RV32 << 30; | |
610 | break; | |
611 | #ifdef TARGET_RISCV64 | |
612 | case MXL_RV64: | |
613 | misa = (target_ulong)MXL_RV64 << 62; | |
614 | break; | |
615 | #endif | |
616 | default: | |
617 | g_assert_not_reached(); | |
618 | } | |
619 | ||
620 | *val = misa | env->misa_ext; | |
605def6e | 621 | return RISCV_EXCP_NONE; |
c7b95171 MC |
622 | } |
623 | ||
605def6e AF |
624 | static RISCVException write_misa(CPURISCVState *env, int csrno, |
625 | target_ulong val) | |
f18637cd MC |
626 | { |
627 | if (!riscv_feature(env, RISCV_FEATURE_MISA)) { | |
628 | /* drop write to misa */ | |
605def6e | 629 | return RISCV_EXCP_NONE; |
f18637cd MC |
630 | } |
631 | ||
632 | /* 'I' or 'E' must be present */ | |
633 | if (!(val & (RVI | RVE))) { | |
634 | /* It is not, drop write to misa */ | |
605def6e | 635 | return RISCV_EXCP_NONE; |
f18637cd MC |
636 | } |
637 | ||
638 | /* 'E' excludes all other extensions */ | |
639 | if (val & RVE) { | |
640 | /* when we support 'E' we can do "val = RVE;" however | |
641 | * for now we just drop writes if 'E' is present. | |
642 | */ | |
605def6e | 643 | return RISCV_EXCP_NONE; |
f18637cd MC |
644 | } |
645 | ||
e91a7227 RH |
646 | /* |
647 | * misa.MXL writes are not supported by QEMU. | |
648 | * Drop writes to those bits. | |
649 | */ | |
650 | ||
f18637cd | 651 | /* Mask extensions that are not supported by this hart */ |
e91a7227 | 652 | val &= env->misa_ext_mask; |
f18637cd MC |
653 | |
654 | /* Mask extensions that are not supported by QEMU */ | |
7b07a37c | 655 | val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU | RVV); |
f18637cd MC |
656 | |
657 | /* 'D' depends on 'F', so clear 'D' if 'F' is not present */ | |
658 | if ((val & RVD) && !(val & RVF)) { | |
659 | val &= ~RVD; | |
660 | } | |
661 | ||
662 | /* Suppress 'C' if next instruction is not aligned | |
663 | * TODO: this should check next_pc | |
664 | */ | |
665 | if ((val & RVC) && (GETPC() & ~3) != 0) { | |
666 | val &= ~RVC; | |
667 | } | |
668 | ||
e91a7227 RH |
669 | /* If nothing changed, do nothing. */ |
670 | if (val == env->misa_ext) { | |
671 | return RISCV_EXCP_NONE; | |
4fd7455b | 672 | } |
f18637cd MC |
673 | |
674 | /* flush translation cache */ | |
e91a7227 RH |
675 | tb_flush(env_cpu(env)); |
676 | env->misa_ext = val; | |
605def6e | 677 | return RISCV_EXCP_NONE; |
f18637cd MC |
678 | } |
679 | ||
605def6e AF |
680 | static RISCVException read_medeleg(CPURISCVState *env, int csrno, |
681 | target_ulong *val) | |
c7b95171 MC |
682 | { |
683 | *val = env->medeleg; | |
605def6e | 684 | return RISCV_EXCP_NONE; |
c7b95171 MC |
685 | } |
686 | ||
605def6e AF |
687 | static RISCVException write_medeleg(CPURISCVState *env, int csrno, |
688 | target_ulong val) | |
c7b95171 | 689 | { |
bc083a51 | 690 | env->medeleg = (env->medeleg & ~DELEGABLE_EXCPS) | (val & DELEGABLE_EXCPS); |
605def6e | 691 | return RISCV_EXCP_NONE; |
c7b95171 MC |
692 | } |
693 | ||
605def6e AF |
694 | static RISCVException read_mideleg(CPURISCVState *env, int csrno, |
695 | target_ulong *val) | |
c7b95171 MC |
696 | { |
697 | *val = env->mideleg; | |
605def6e | 698 | return RISCV_EXCP_NONE; |
c7b95171 MC |
699 | } |
700 | ||
605def6e AF |
701 | static RISCVException write_mideleg(CPURISCVState *env, int csrno, |
702 | target_ulong val) | |
c7b95171 MC |
703 | { |
704 | env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints); | |
713d8363 AF |
705 | if (riscv_has_ext(env, RVH)) { |
706 | env->mideleg |= VS_MODE_INTERRUPTS; | |
707 | } | |
605def6e | 708 | return RISCV_EXCP_NONE; |
c7b95171 MC |
709 | } |
710 | ||
605def6e AF |
711 | static RISCVException read_mie(CPURISCVState *env, int csrno, |
712 | target_ulong *val) | |
c7b95171 MC |
713 | { |
714 | *val = env->mie; | |
605def6e | 715 | return RISCV_EXCP_NONE; |
c7b95171 MC |
716 | } |
717 | ||
605def6e AF |
718 | static RISCVException write_mie(CPURISCVState *env, int csrno, |
719 | target_ulong val) | |
c7b95171 MC |
720 | { |
721 | env->mie = (env->mie & ~all_ints) | (val & all_ints); | |
605def6e | 722 | return RISCV_EXCP_NONE; |
c7b95171 MC |
723 | } |
724 | ||
605def6e AF |
725 | static RISCVException read_mtvec(CPURISCVState *env, int csrno, |
726 | target_ulong *val) | |
c7b95171 MC |
727 | { |
728 | *val = env->mtvec; | |
605def6e | 729 | return RISCV_EXCP_NONE; |
c7b95171 MC |
730 | } |
731 | ||
605def6e AF |
732 | static RISCVException write_mtvec(CPURISCVState *env, int csrno, |
733 | target_ulong val) | |
c7b95171 MC |
734 | { |
735 | /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ | |
acbbb94e MC |
736 | if ((val & 3) < 2) { |
737 | env->mtvec = val; | |
c7b95171 | 738 | } else { |
acbbb94e | 739 | qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n"); |
c7b95171 | 740 | } |
605def6e | 741 | return RISCV_EXCP_NONE; |
c7b95171 MC |
742 | } |
743 | ||
605def6e AF |
744 | static RISCVException read_mcounteren(CPURISCVState *env, int csrno, |
745 | target_ulong *val) | |
c7b95171 | 746 | { |
c7b95171 | 747 | *val = env->mcounteren; |
605def6e | 748 | return RISCV_EXCP_NONE; |
c7b95171 MC |
749 | } |
750 | ||
605def6e AF |
751 | static RISCVException write_mcounteren(CPURISCVState *env, int csrno, |
752 | target_ulong val) | |
c7b95171 | 753 | { |
c7b95171 | 754 | env->mcounteren = val; |
605def6e | 755 | return RISCV_EXCP_NONE; |
c7b95171 MC |
756 | } |
757 | ||
c7b95171 | 758 | /* Machine Trap Handling */ |
605def6e AF |
759 | static RISCVException read_mscratch(CPURISCVState *env, int csrno, |
760 | target_ulong *val) | |
c7b95171 MC |
761 | { |
762 | *val = env->mscratch; | |
605def6e | 763 | return RISCV_EXCP_NONE; |
c7b95171 MC |
764 | } |
765 | ||
605def6e AF |
766 | static RISCVException write_mscratch(CPURISCVState *env, int csrno, |
767 | target_ulong val) | |
c7b95171 MC |
768 | { |
769 | env->mscratch = val; | |
605def6e | 770 | return RISCV_EXCP_NONE; |
c7b95171 MC |
771 | } |
772 | ||
605def6e AF |
773 | static RISCVException read_mepc(CPURISCVState *env, int csrno, |
774 | target_ulong *val) | |
c7b95171 MC |
775 | { |
776 | *val = env->mepc; | |
605def6e | 777 | return RISCV_EXCP_NONE; |
c7b95171 MC |
778 | } |
779 | ||
605def6e AF |
780 | static RISCVException write_mepc(CPURISCVState *env, int csrno, |
781 | target_ulong val) | |
c7b95171 MC |
782 | { |
783 | env->mepc = val; | |
605def6e | 784 | return RISCV_EXCP_NONE; |
c7b95171 MC |
785 | } |
786 | ||
605def6e AF |
787 | static RISCVException read_mcause(CPURISCVState *env, int csrno, |
788 | target_ulong *val) | |
c7b95171 MC |
789 | { |
790 | *val = env->mcause; | |
605def6e | 791 | return RISCV_EXCP_NONE; |
c7b95171 MC |
792 | } |
793 | ||
605def6e AF |
794 | static RISCVException write_mcause(CPURISCVState *env, int csrno, |
795 | target_ulong val) | |
c7b95171 MC |
796 | { |
797 | env->mcause = val; | |
605def6e | 798 | return RISCV_EXCP_NONE; |
c7b95171 MC |
799 | } |
800 | ||
605def6e AF |
801 | static RISCVException read_mtval(CPURISCVState *env, int csrno, |
802 | target_ulong *val) | |
c7b95171 | 803 | { |
ac12b601 | 804 | *val = env->mtval; |
605def6e | 805 | return RISCV_EXCP_NONE; |
c7b95171 MC |
806 | } |
807 | ||
605def6e AF |
808 | static RISCVException write_mtval(CPURISCVState *env, int csrno, |
809 | target_ulong val) | |
c7b95171 | 810 | { |
ac12b601 | 811 | env->mtval = val; |
605def6e | 812 | return RISCV_EXCP_NONE; |
c7b95171 MC |
813 | } |
814 | ||
605def6e AF |
815 | static RISCVException rmw_mip(CPURISCVState *env, int csrno, |
816 | target_ulong *ret_value, | |
817 | target_ulong new_value, target_ulong write_mask) | |
c7b95171 | 818 | { |
3109cd98 | 819 | RISCVCPU *cpu = env_archcpu(env); |
e3e7039c MC |
820 | /* Allow software control of delegable interrupts not claimed by hardware */ |
821 | target_ulong mask = write_mask & delegable_ints & ~env->miclaim; | |
71877e29 MC |
822 | uint32_t old_mip; |
823 | ||
71877e29 | 824 | if (mask) { |
71877e29 | 825 | old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask)); |
71877e29 | 826 | } else { |
7ec5d303 | 827 | old_mip = env->mip; |
71877e29 | 828 | } |
c7b95171 | 829 | |
71877e29 MC |
830 | if (ret_value) { |
831 | *ret_value = old_mip; | |
832 | } | |
c7b95171 | 833 | |
605def6e | 834 | return RISCV_EXCP_NONE; |
c7b95171 MC |
835 | } |
836 | ||
837 | /* Supervisor Trap Setup */ | |
605def6e AF |
838 | static RISCVException read_sstatus(CPURISCVState *env, int csrno, |
839 | target_ulong *val) | |
c7b95171 | 840 | { |
1a9540d1 | 841 | target_ulong mask = (sstatus_v1_10_mask); |
5f10e6d8 | 842 | |
b550f894 RH |
843 | /* TODO: Use SXL not MXL. */ |
844 | *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask); | |
605def6e | 845 | return RISCV_EXCP_NONE; |
c7b95171 MC |
846 | } |
847 | ||
605def6e AF |
848 | static RISCVException write_sstatus(CPURISCVState *env, int csrno, |
849 | target_ulong val) | |
c7b95171 | 850 | { |
1a9540d1 | 851 | target_ulong mask = (sstatus_v1_10_mask); |
c7b95171 MC |
852 | target_ulong newval = (env->mstatus & ~mask) | (val & mask); |
853 | return write_mstatus(env, CSR_MSTATUS, newval); | |
854 | } | |
855 | ||
605def6e AF |
856 | static RISCVException read_vsie(CPURISCVState *env, int csrno, |
857 | target_ulong *val) | |
9d5451e0 GK |
858 | { |
859 | /* Shift the VS bits to their S bit location in vsie */ | |
860 | *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1; | |
605def6e | 861 | return RISCV_EXCP_NONE; |
9d5451e0 GK |
862 | } |
863 | ||
605def6e AF |
864 | static RISCVException read_sie(CPURISCVState *env, int csrno, |
865 | target_ulong *val) | |
c7b95171 | 866 | { |
d0e53ce3 | 867 | if (riscv_cpu_virt_enabled(env)) { |
9d5451e0 | 868 | read_vsie(env, CSR_VSIE, val); |
d0e53ce3 AF |
869 | } else { |
870 | *val = env->mie & env->mideleg; | |
871 | } | |
605def6e | 872 | return RISCV_EXCP_NONE; |
c7b95171 MC |
873 | } |
874 | ||
605def6e AF |
875 | static RISCVException write_vsie(CPURISCVState *env, int csrno, |
876 | target_ulong val) | |
c7b95171 | 877 | { |
9d5451e0 GK |
878 | /* Shift the S bits to their VS bit location in mie */ |
879 | target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | | |
880 | ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS); | |
881 | return write_mie(env, CSR_MIE, newval); | |
882 | } | |
d0e53ce3 | 883 | |
9d5451e0 GK |
884 | static int write_sie(CPURISCVState *env, int csrno, target_ulong val) |
885 | { | |
d0e53ce3 | 886 | if (riscv_cpu_virt_enabled(env)) { |
9d5451e0 | 887 | write_vsie(env, CSR_VSIE, val); |
d0e53ce3 | 888 | } else { |
9d5451e0 GK |
889 | target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) | |
890 | (val & S_MODE_INTERRUPTS); | |
891 | write_mie(env, CSR_MIE, newval); | |
d0e53ce3 AF |
892 | } |
893 | ||
605def6e | 894 | return RISCV_EXCP_NONE; |
c7b95171 MC |
895 | } |
896 | ||
605def6e AF |
897 | static RISCVException read_stvec(CPURISCVState *env, int csrno, |
898 | target_ulong *val) | |
c7b95171 MC |
899 | { |
900 | *val = env->stvec; | |
605def6e | 901 | return RISCV_EXCP_NONE; |
c7b95171 MC |
902 | } |
903 | ||
605def6e AF |
904 | static RISCVException write_stvec(CPURISCVState *env, int csrno, |
905 | target_ulong val) | |
c7b95171 MC |
906 | { |
907 | /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ | |
acbbb94e MC |
908 | if ((val & 3) < 2) { |
909 | env->stvec = val; | |
c7b95171 | 910 | } else { |
acbbb94e | 911 | qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n"); |
c7b95171 | 912 | } |
605def6e | 913 | return RISCV_EXCP_NONE; |
c7b95171 MC |
914 | } |
915 | ||
605def6e AF |
916 | static RISCVException read_scounteren(CPURISCVState *env, int csrno, |
917 | target_ulong *val) | |
c7b95171 | 918 | { |
c7b95171 | 919 | *val = env->scounteren; |
605def6e | 920 | return RISCV_EXCP_NONE; |
c7b95171 MC |
921 | } |
922 | ||
605def6e AF |
923 | static RISCVException write_scounteren(CPURISCVState *env, int csrno, |
924 | target_ulong val) | |
c7b95171 | 925 | { |
c7b95171 | 926 | env->scounteren = val; |
605def6e | 927 | return RISCV_EXCP_NONE; |
c7b95171 MC |
928 | } |
929 | ||
930 | /* Supervisor Trap Handling */ | |
605def6e AF |
931 | static RISCVException read_sscratch(CPURISCVState *env, int csrno, |
932 | target_ulong *val) | |
c7b95171 MC |
933 | { |
934 | *val = env->sscratch; | |
605def6e | 935 | return RISCV_EXCP_NONE; |
c7b95171 MC |
936 | } |
937 | ||
605def6e AF |
938 | static RISCVException write_sscratch(CPURISCVState *env, int csrno, |
939 | target_ulong val) | |
c7b95171 MC |
940 | { |
941 | env->sscratch = val; | |
605def6e | 942 | return RISCV_EXCP_NONE; |
c7b95171 MC |
943 | } |
944 | ||
605def6e AF |
945 | static RISCVException read_sepc(CPURISCVState *env, int csrno, |
946 | target_ulong *val) | |
c7b95171 MC |
947 | { |
948 | *val = env->sepc; | |
605def6e | 949 | return RISCV_EXCP_NONE; |
c7b95171 MC |
950 | } |
951 | ||
605def6e AF |
952 | static RISCVException write_sepc(CPURISCVState *env, int csrno, |
953 | target_ulong val) | |
c7b95171 MC |
954 | { |
955 | env->sepc = val; | |
605def6e | 956 | return RISCV_EXCP_NONE; |
c7b95171 MC |
957 | } |
958 | ||
605def6e AF |
959 | static RISCVException read_scause(CPURISCVState *env, int csrno, |
960 | target_ulong *val) | |
c7b95171 MC |
961 | { |
962 | *val = env->scause; | |
605def6e | 963 | return RISCV_EXCP_NONE; |
c7b95171 MC |
964 | } |
965 | ||
605def6e AF |
966 | static RISCVException write_scause(CPURISCVState *env, int csrno, |
967 | target_ulong val) | |
c7b95171 MC |
968 | { |
969 | env->scause = val; | |
605def6e | 970 | return RISCV_EXCP_NONE; |
c7b95171 MC |
971 | } |
972 | ||
605def6e AF |
973 | static RISCVException read_stval(CPURISCVState *env, int csrno, |
974 | target_ulong *val) | |
c7b95171 | 975 | { |
ac12b601 | 976 | *val = env->stval; |
605def6e | 977 | return RISCV_EXCP_NONE; |
c7b95171 MC |
978 | } |
979 | ||
605def6e AF |
980 | static RISCVException write_stval(CPURISCVState *env, int csrno, |
981 | target_ulong val) | |
c7b95171 | 982 | { |
ac12b601 | 983 | env->stval = val; |
605def6e | 984 | return RISCV_EXCP_NONE; |
c7b95171 MC |
985 | } |
986 | ||
605def6e AF |
987 | static RISCVException rmw_vsip(CPURISCVState *env, int csrno, |
988 | target_ulong *ret_value, | |
989 | target_ulong new_value, target_ulong write_mask) | |
9d5451e0 GK |
990 | { |
991 | /* Shift the S bits to their VS bit location in mip */ | |
992 | int ret = rmw_mip(env, 0, ret_value, new_value << 1, | |
993 | (write_mask << 1) & vsip_writable_mask & env->hideleg); | |
33979526 RH |
994 | |
995 | if (ret_value) { | |
996 | *ret_value &= VS_MODE_INTERRUPTS; | |
997 | /* Shift the VS bits to their S bit location in vsip */ | |
998 | *ret_value >>= 1; | |
999 | } | |
9d5451e0 GK |
1000 | return ret; |
1001 | } | |
1002 | ||
605def6e AF |
1003 | static RISCVException rmw_sip(CPURISCVState *env, int csrno, |
1004 | target_ulong *ret_value, | |
1005 | target_ulong new_value, target_ulong write_mask) | |
c7b95171 | 1006 | { |
a2e9f57d AF |
1007 | int ret; |
1008 | ||
1009 | if (riscv_cpu_virt_enabled(env)) { | |
9d5451e0 | 1010 | ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask); |
a2e9f57d AF |
1011 | } else { |
1012 | ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value, | |
087b051a | 1013 | write_mask & env->mideleg & sip_writable_mask); |
a2e9f57d AF |
1014 | } |
1015 | ||
33979526 RH |
1016 | if (ret_value) { |
1017 | *ret_value &= env->mideleg; | |
1018 | } | |
087b051a | 1019 | return ret; |
c7b95171 MC |
1020 | } |
1021 | ||
1022 | /* Supervisor Protection and Translation */ | |
605def6e AF |
1023 | static RISCVException read_satp(CPURISCVState *env, int csrno, |
1024 | target_ulong *val) | |
c7b95171 MC |
1025 | { |
1026 | if (!riscv_feature(env, RISCV_FEATURE_MMU)) { | |
1027 | *val = 0; | |
605def6e | 1028 | return RISCV_EXCP_NONE; |
1a9540d1 AF |
1029 | } |
1030 | ||
1031 | if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { | |
605def6e | 1032 | return RISCV_EXCP_ILLEGAL_INST; |
c7b95171 | 1033 | } else { |
1a9540d1 | 1034 | *val = env->satp; |
c7b95171 | 1035 | } |
1a9540d1 | 1036 | |
605def6e | 1037 | return RISCV_EXCP_NONE; |
c7b95171 MC |
1038 | } |
1039 | ||
605def6e AF |
1040 | static RISCVException write_satp(CPURISCVState *env, int csrno, |
1041 | target_ulong val) | |
c7b95171 | 1042 | { |
15732b8e | 1043 | target_ulong vm, mask, asid; |
419ddf00 | 1044 | |
c7b95171 | 1045 | if (!riscv_feature(env, RISCV_FEATURE_MMU)) { |
605def6e | 1046 | return RISCV_EXCP_NONE; |
c7b95171 | 1047 | } |
419ddf00 | 1048 | |
db23e5d9 | 1049 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
419ddf00 AF |
1050 | vm = validate_vm(env, get_field(val, SATP32_MODE)); |
1051 | mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN); | |
1052 | asid = (val ^ env->satp) & SATP32_ASID; | |
1053 | } else { | |
1054 | vm = validate_vm(env, get_field(val, SATP64_MODE)); | |
1055 | mask = (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN); | |
1056 | asid = (val ^ env->satp) & SATP64_ASID; | |
1057 | } | |
1058 | ||
1059 | if (vm && mask) { | |
7f2b5ff1 | 1060 | if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { |
605def6e | 1061 | return RISCV_EXCP_ILLEGAL_INST; |
7f2b5ff1 | 1062 | } else { |
419ddf00 | 1063 | if (asid) { |
3109cd98 | 1064 | tlb_flush(env_cpu(env)); |
1e0d985f | 1065 | } |
7f2b5ff1 MC |
1066 | env->satp = val; |
1067 | } | |
c7b95171 | 1068 | } |
605def6e | 1069 | return RISCV_EXCP_NONE; |
c7b95171 MC |
1070 | } |
1071 | ||
ff2cc129 | 1072 | /* Hypervisor Extensions */ |
605def6e AF |
1073 | static RISCVException read_hstatus(CPURISCVState *env, int csrno, |
1074 | target_ulong *val) | |
ff2cc129 AF |
1075 | { |
1076 | *val = env->hstatus; | |
db23e5d9 | 1077 | if (riscv_cpu_mxl(env) != MXL_RV32) { |
8987cdc4 AF |
1078 | /* We only support 64-bit VSXL */ |
1079 | *val = set_field(*val, HSTATUS_VSXL, 2); | |
1080 | } | |
30f663b1 AF |
1081 | /* We only support little endian */ |
1082 | *val = set_field(*val, HSTATUS_VSBE, 0); | |
605def6e | 1083 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1084 | } |
1085 | ||
605def6e AF |
1086 | static RISCVException write_hstatus(CPURISCVState *env, int csrno, |
1087 | target_ulong val) | |
ff2cc129 AF |
1088 | { |
1089 | env->hstatus = val; | |
db23e5d9 | 1090 | if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) { |
f8dc878e AF |
1091 | qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options."); |
1092 | } | |
30f663b1 AF |
1093 | if (get_field(val, HSTATUS_VSBE) != 0) { |
1094 | qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests."); | |
1095 | } | |
605def6e | 1096 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1097 | } |
1098 | ||
605def6e AF |
1099 | static RISCVException read_hedeleg(CPURISCVState *env, int csrno, |
1100 | target_ulong *val) | |
ff2cc129 AF |
1101 | { |
1102 | *val = env->hedeleg; | |
605def6e | 1103 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1104 | } |
1105 | ||
605def6e AF |
1106 | static RISCVException write_hedeleg(CPURISCVState *env, int csrno, |
1107 | target_ulong val) | |
ff2cc129 | 1108 | { |
bc083a51 | 1109 | env->hedeleg = val & vs_delegable_excps; |
605def6e | 1110 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1111 | } |
1112 | ||
605def6e AF |
1113 | static RISCVException read_hideleg(CPURISCVState *env, int csrno, |
1114 | target_ulong *val) | |
ff2cc129 AF |
1115 | { |
1116 | *val = env->hideleg; | |
605def6e | 1117 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1118 | } |
1119 | ||
605def6e AF |
1120 | static RISCVException write_hideleg(CPURISCVState *env, int csrno, |
1121 | target_ulong val) | |
ff2cc129 | 1122 | { |
bc083a51 | 1123 | env->hideleg = val & vs_delegable_ints; |
605def6e | 1124 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1125 | } |
1126 | ||
605def6e AF |
1127 | static RISCVException rmw_hvip(CPURISCVState *env, int csrno, |
1128 | target_ulong *ret_value, | |
1129 | target_ulong new_value, target_ulong write_mask) | |
83028098 AF |
1130 | { |
1131 | int ret = rmw_mip(env, 0, ret_value, new_value, | |
e89b631c | 1132 | write_mask & hvip_writable_mask); |
83028098 | 1133 | |
33979526 RH |
1134 | if (ret_value) { |
1135 | *ret_value &= hvip_writable_mask; | |
1136 | } | |
83028098 AF |
1137 | return ret; |
1138 | } | |
1139 | ||
605def6e AF |
1140 | static RISCVException rmw_hip(CPURISCVState *env, int csrno, |
1141 | target_ulong *ret_value, | |
1142 | target_ulong new_value, target_ulong write_mask) | |
ff2cc129 AF |
1143 | { |
1144 | int ret = rmw_mip(env, 0, ret_value, new_value, | |
1145 | write_mask & hip_writable_mask); | |
1146 | ||
33979526 RH |
1147 | if (ret_value) { |
1148 | *ret_value &= hip_writable_mask; | |
1149 | } | |
ff2cc129 AF |
1150 | return ret; |
1151 | } | |
1152 | ||
605def6e AF |
1153 | static RISCVException read_hie(CPURISCVState *env, int csrno, |
1154 | target_ulong *val) | |
ff2cc129 AF |
1155 | { |
1156 | *val = env->mie & VS_MODE_INTERRUPTS; | |
605def6e | 1157 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1158 | } |
1159 | ||
605def6e AF |
1160 | static RISCVException write_hie(CPURISCVState *env, int csrno, |
1161 | target_ulong val) | |
ff2cc129 AF |
1162 | { |
1163 | target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS); | |
1164 | return write_mie(env, CSR_MIE, newval); | |
1165 | } | |
1166 | ||
605def6e AF |
1167 | static RISCVException read_hcounteren(CPURISCVState *env, int csrno, |
1168 | target_ulong *val) | |
ff2cc129 AF |
1169 | { |
1170 | *val = env->hcounteren; | |
605def6e | 1171 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1172 | } |
1173 | ||
605def6e AF |
1174 | static RISCVException write_hcounteren(CPURISCVState *env, int csrno, |
1175 | target_ulong val) | |
ff2cc129 AF |
1176 | { |
1177 | env->hcounteren = val; | |
605def6e | 1178 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1179 | } |
1180 | ||
605def6e AF |
1181 | static RISCVException write_hgeie(CPURISCVState *env, int csrno, |
1182 | target_ulong val) | |
83028098 | 1183 | { |
377cbb4b RH |
1184 | if (val) { |
1185 | qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); | |
1186 | } | |
605def6e | 1187 | return RISCV_EXCP_NONE; |
83028098 AF |
1188 | } |
1189 | ||
605def6e AF |
1190 | static RISCVException read_htval(CPURISCVState *env, int csrno, |
1191 | target_ulong *val) | |
ff2cc129 AF |
1192 | { |
1193 | *val = env->htval; | |
605def6e | 1194 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1195 | } |
1196 | ||
605def6e AF |
1197 | static RISCVException write_htval(CPURISCVState *env, int csrno, |
1198 | target_ulong val) | |
ff2cc129 AF |
1199 | { |
1200 | env->htval = val; | |
605def6e | 1201 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1202 | } |
1203 | ||
605def6e AF |
1204 | static RISCVException read_htinst(CPURISCVState *env, int csrno, |
1205 | target_ulong *val) | |
ff2cc129 AF |
1206 | { |
1207 | *val = env->htinst; | |
605def6e | 1208 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1209 | } |
1210 | ||
605def6e AF |
1211 | static RISCVException write_htinst(CPURISCVState *env, int csrno, |
1212 | target_ulong val) | |
ff2cc129 | 1213 | { |
605def6e | 1214 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1215 | } |
1216 | ||
605def6e AF |
1217 | static RISCVException write_hgeip(CPURISCVState *env, int csrno, |
1218 | target_ulong val) | |
83028098 | 1219 | { |
377cbb4b RH |
1220 | if (val) { |
1221 | qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); | |
1222 | } | |
605def6e | 1223 | return RISCV_EXCP_NONE; |
83028098 AF |
1224 | } |
1225 | ||
605def6e AF |
1226 | static RISCVException read_hgatp(CPURISCVState *env, int csrno, |
1227 | target_ulong *val) | |
ff2cc129 AF |
1228 | { |
1229 | *val = env->hgatp; | |
605def6e | 1230 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1231 | } |
1232 | ||
605def6e AF |
1233 | static RISCVException write_hgatp(CPURISCVState *env, int csrno, |
1234 | target_ulong val) | |
ff2cc129 AF |
1235 | { |
1236 | env->hgatp = val; | |
605def6e | 1237 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1238 | } |
1239 | ||
605def6e AF |
1240 | static RISCVException read_htimedelta(CPURISCVState *env, int csrno, |
1241 | target_ulong *val) | |
c6957248 AP |
1242 | { |
1243 | if (!env->rdtime_fn) { | |
605def6e | 1244 | return RISCV_EXCP_ILLEGAL_INST; |
c6957248 AP |
1245 | } |
1246 | ||
c6957248 | 1247 | *val = env->htimedelta; |
605def6e | 1248 | return RISCV_EXCP_NONE; |
c6957248 AP |
1249 | } |
1250 | ||
605def6e AF |
1251 | static RISCVException write_htimedelta(CPURISCVState *env, int csrno, |
1252 | target_ulong val) | |
c6957248 AP |
1253 | { |
1254 | if (!env->rdtime_fn) { | |
605def6e | 1255 | return RISCV_EXCP_ILLEGAL_INST; |
c6957248 AP |
1256 | } |
1257 | ||
db23e5d9 | 1258 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
8987cdc4 AF |
1259 | env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val); |
1260 | } else { | |
1261 | env->htimedelta = val; | |
1262 | } | |
605def6e | 1263 | return RISCV_EXCP_NONE; |
c6957248 AP |
1264 | } |
1265 | ||
605def6e AF |
1266 | static RISCVException read_htimedeltah(CPURISCVState *env, int csrno, |
1267 | target_ulong *val) | |
c6957248 AP |
1268 | { |
1269 | if (!env->rdtime_fn) { | |
605def6e | 1270 | return RISCV_EXCP_ILLEGAL_INST; |
c6957248 AP |
1271 | } |
1272 | ||
1273 | *val = env->htimedelta >> 32; | |
605def6e | 1274 | return RISCV_EXCP_NONE; |
c6957248 AP |
1275 | } |
1276 | ||
605def6e AF |
1277 | static RISCVException write_htimedeltah(CPURISCVState *env, int csrno, |
1278 | target_ulong val) | |
c6957248 AP |
1279 | { |
1280 | if (!env->rdtime_fn) { | |
605def6e | 1281 | return RISCV_EXCP_ILLEGAL_INST; |
c6957248 AP |
1282 | } |
1283 | ||
1284 | env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val); | |
605def6e | 1285 | return RISCV_EXCP_NONE; |
c6957248 | 1286 | } |
c6957248 | 1287 | |
8747c9ee | 1288 | /* Virtual CSR Registers */ |
605def6e AF |
1289 | static RISCVException read_vsstatus(CPURISCVState *env, int csrno, |
1290 | target_ulong *val) | |
8747c9ee AF |
1291 | { |
1292 | *val = env->vsstatus; | |
605def6e | 1293 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1294 | } |
1295 | ||
605def6e AF |
1296 | static RISCVException write_vsstatus(CPURISCVState *env, int csrno, |
1297 | target_ulong val) | |
8747c9ee | 1298 | { |
284d697c YJ |
1299 | uint64_t mask = (target_ulong)-1; |
1300 | env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val; | |
605def6e | 1301 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1302 | } |
1303 | ||
8747c9ee AF |
1304 | static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val) |
1305 | { | |
1306 | *val = env->vstvec; | |
605def6e | 1307 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1308 | } |
1309 | ||
605def6e AF |
1310 | static RISCVException write_vstvec(CPURISCVState *env, int csrno, |
1311 | target_ulong val) | |
8747c9ee AF |
1312 | { |
1313 | env->vstvec = val; | |
605def6e | 1314 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1315 | } |
1316 | ||
605def6e AF |
1317 | static RISCVException read_vsscratch(CPURISCVState *env, int csrno, |
1318 | target_ulong *val) | |
8747c9ee AF |
1319 | { |
1320 | *val = env->vsscratch; | |
605def6e | 1321 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1322 | } |
1323 | ||
605def6e AF |
1324 | static RISCVException write_vsscratch(CPURISCVState *env, int csrno, |
1325 | target_ulong val) | |
8747c9ee AF |
1326 | { |
1327 | env->vsscratch = val; | |
605def6e | 1328 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1329 | } |
1330 | ||
605def6e AF |
1331 | static RISCVException read_vsepc(CPURISCVState *env, int csrno, |
1332 | target_ulong *val) | |
8747c9ee AF |
1333 | { |
1334 | *val = env->vsepc; | |
605def6e | 1335 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1336 | } |
1337 | ||
605def6e AF |
1338 | static RISCVException write_vsepc(CPURISCVState *env, int csrno, |
1339 | target_ulong val) | |
8747c9ee AF |
1340 | { |
1341 | env->vsepc = val; | |
605def6e | 1342 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1343 | } |
1344 | ||
605def6e AF |
1345 | static RISCVException read_vscause(CPURISCVState *env, int csrno, |
1346 | target_ulong *val) | |
8747c9ee AF |
1347 | { |
1348 | *val = env->vscause; | |
605def6e | 1349 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1350 | } |
1351 | ||
605def6e AF |
1352 | static RISCVException write_vscause(CPURISCVState *env, int csrno, |
1353 | target_ulong val) | |
8747c9ee AF |
1354 | { |
1355 | env->vscause = val; | |
605def6e | 1356 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1357 | } |
1358 | ||
605def6e AF |
1359 | static RISCVException read_vstval(CPURISCVState *env, int csrno, |
1360 | target_ulong *val) | |
8747c9ee AF |
1361 | { |
1362 | *val = env->vstval; | |
605def6e | 1363 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1364 | } |
1365 | ||
605def6e AF |
1366 | static RISCVException write_vstval(CPURISCVState *env, int csrno, |
1367 | target_ulong val) | |
8747c9ee AF |
1368 | { |
1369 | env->vstval = val; | |
605def6e | 1370 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1371 | } |
1372 | ||
605def6e AF |
1373 | static RISCVException read_vsatp(CPURISCVState *env, int csrno, |
1374 | target_ulong *val) | |
8747c9ee AF |
1375 | { |
1376 | *val = env->vsatp; | |
605def6e | 1377 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1378 | } |
1379 | ||
605def6e AF |
1380 | static RISCVException write_vsatp(CPURISCVState *env, int csrno, |
1381 | target_ulong val) | |
8747c9ee AF |
1382 | { |
1383 | env->vsatp = val; | |
605def6e | 1384 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1385 | } |
1386 | ||
605def6e AF |
1387 | static RISCVException read_mtval2(CPURISCVState *env, int csrno, |
1388 | target_ulong *val) | |
34cfb5f6 AF |
1389 | { |
1390 | *val = env->mtval2; | |
605def6e | 1391 | return RISCV_EXCP_NONE; |
34cfb5f6 AF |
1392 | } |
1393 | ||
605def6e AF |
1394 | static RISCVException write_mtval2(CPURISCVState *env, int csrno, |
1395 | target_ulong val) | |
34cfb5f6 AF |
1396 | { |
1397 | env->mtval2 = val; | |
605def6e | 1398 | return RISCV_EXCP_NONE; |
34cfb5f6 AF |
1399 | } |
1400 | ||
605def6e AF |
1401 | static RISCVException read_mtinst(CPURISCVState *env, int csrno, |
1402 | target_ulong *val) | |
34cfb5f6 AF |
1403 | { |
1404 | *val = env->mtinst; | |
605def6e | 1405 | return RISCV_EXCP_NONE; |
34cfb5f6 AF |
1406 | } |
1407 | ||
605def6e AF |
1408 | static RISCVException write_mtinst(CPURISCVState *env, int csrno, |
1409 | target_ulong val) | |
34cfb5f6 AF |
1410 | { |
1411 | env->mtinst = val; | |
605def6e | 1412 | return RISCV_EXCP_NONE; |
34cfb5f6 AF |
1413 | } |
1414 | ||
c7b95171 | 1415 | /* Physical Memory Protection */ |
2582a95c HW |
1416 | static RISCVException read_mseccfg(CPURISCVState *env, int csrno, |
1417 | target_ulong *val) | |
1418 | { | |
1419 | *val = mseccfg_csr_read(env); | |
1420 | return RISCV_EXCP_NONE; | |
1421 | } | |
1422 | ||
1423 | static RISCVException write_mseccfg(CPURISCVState *env, int csrno, | |
1424 | target_ulong val) | |
1425 | { | |
1426 | mseccfg_csr_write(env, val); | |
1427 | return RISCV_EXCP_NONE; | |
1428 | } | |
1429 | ||
605def6e AF |
1430 | static RISCVException read_pmpcfg(CPURISCVState *env, int csrno, |
1431 | target_ulong *val) | |
c7b95171 MC |
1432 | { |
1433 | *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0); | |
605def6e | 1434 | return RISCV_EXCP_NONE; |
c7b95171 MC |
1435 | } |
1436 | ||
605def6e AF |
1437 | static RISCVException write_pmpcfg(CPURISCVState *env, int csrno, |
1438 | target_ulong val) | |
c7b95171 MC |
1439 | { |
1440 | pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val); | |
605def6e | 1441 | return RISCV_EXCP_NONE; |
c7b95171 MC |
1442 | } |
1443 | ||
605def6e AF |
1444 | static RISCVException read_pmpaddr(CPURISCVState *env, int csrno, |
1445 | target_ulong *val) | |
c7b95171 MC |
1446 | { |
1447 | *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0); | |
605def6e | 1448 | return RISCV_EXCP_NONE; |
c7b95171 MC |
1449 | } |
1450 | ||
605def6e AF |
1451 | static RISCVException write_pmpaddr(CPURISCVState *env, int csrno, |
1452 | target_ulong val) | |
c7b95171 MC |
1453 | { |
1454 | pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val); | |
605def6e | 1455 | return RISCV_EXCP_NONE; |
c7b95171 MC |
1456 | } |
1457 | ||
4bbe8033 AB |
1458 | /* |
1459 | * Functions to access Pointer Masking feature registers | |
1460 | * We have to check if current priv lvl could modify | |
1461 | * csr in given mode | |
1462 | */ | |
1463 | static bool check_pm_current_disabled(CPURISCVState *env, int csrno) | |
1464 | { | |
1465 | int csr_priv = get_field(csrno, 0x300); | |
1466 | int pm_current; | |
1467 | ||
1468 | /* | |
1469 | * If priv lvls differ that means we're accessing csr from higher priv lvl, | |
1470 | * so allow the access | |
1471 | */ | |
1472 | if (env->priv != csr_priv) { | |
1473 | return false; | |
1474 | } | |
1475 | switch (env->priv) { | |
1476 | case PRV_M: | |
1477 | pm_current = get_field(env->mmte, M_PM_CURRENT); | |
1478 | break; | |
1479 | case PRV_S: | |
1480 | pm_current = get_field(env->mmte, S_PM_CURRENT); | |
1481 | break; | |
1482 | case PRV_U: | |
1483 | pm_current = get_field(env->mmte, U_PM_CURRENT); | |
1484 | break; | |
1485 | default: | |
1486 | g_assert_not_reached(); | |
1487 | } | |
1488 | /* It's same priv lvl, so we allow to modify csr only if pm.current==1 */ | |
1489 | return !pm_current; | |
1490 | } | |
1491 | ||
1492 | static RISCVException read_mmte(CPURISCVState *env, int csrno, | |
1493 | target_ulong *val) | |
1494 | { | |
1495 | *val = env->mmte & MMTE_MASK; | |
1496 | return RISCV_EXCP_NONE; | |
1497 | } | |
1498 | ||
1499 | static RISCVException write_mmte(CPURISCVState *env, int csrno, | |
1500 | target_ulong val) | |
1501 | { | |
1502 | uint64_t mstatus; | |
1503 | target_ulong wpri_val = val & MMTE_MASK; | |
1504 | ||
1505 | if (val != wpri_val) { | |
1506 | qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n", | |
1507 | "MMTE: WPRI violation written 0x", val, | |
1508 | "vs expected 0x", wpri_val); | |
1509 | } | |
1510 | /* for machine mode pm.current is hardwired to 1 */ | |
1511 | wpri_val |= MMTE_M_PM_CURRENT; | |
1512 | ||
1513 | /* hardwiring pm.instruction bit to 0, since it's not supported yet */ | |
1514 | wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN); | |
1515 | env->mmte = wpri_val | PM_EXT_DIRTY; | |
1516 | ||
1517 | /* Set XS and SD bits, since PM CSRs are dirty */ | |
1518 | mstatus = env->mstatus | MSTATUS_XS; | |
1519 | write_mstatus(env, csrno, mstatus); | |
1520 | return RISCV_EXCP_NONE; | |
1521 | } | |
1522 | ||
1523 | static RISCVException read_smte(CPURISCVState *env, int csrno, | |
1524 | target_ulong *val) | |
1525 | { | |
1526 | *val = env->mmte & SMTE_MASK; | |
1527 | return RISCV_EXCP_NONE; | |
1528 | } | |
1529 | ||
1530 | static RISCVException write_smte(CPURISCVState *env, int csrno, | |
1531 | target_ulong val) | |
1532 | { | |
1533 | target_ulong wpri_val = val & SMTE_MASK; | |
1534 | ||
1535 | if (val != wpri_val) { | |
1536 | qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n", | |
1537 | "SMTE: WPRI violation written 0x", val, | |
1538 | "vs expected 0x", wpri_val); | |
1539 | } | |
1540 | ||
1541 | /* if pm.current==0 we can't modify current PM CSRs */ | |
1542 | if (check_pm_current_disabled(env, csrno)) { | |
1543 | return RISCV_EXCP_NONE; | |
1544 | } | |
1545 | ||
1546 | wpri_val |= (env->mmte & ~SMTE_MASK); | |
1547 | write_mmte(env, csrno, wpri_val); | |
1548 | return RISCV_EXCP_NONE; | |
1549 | } | |
1550 | ||
1551 | static RISCVException read_umte(CPURISCVState *env, int csrno, | |
1552 | target_ulong *val) | |
1553 | { | |
1554 | *val = env->mmte & UMTE_MASK; | |
1555 | return RISCV_EXCP_NONE; | |
1556 | } | |
1557 | ||
1558 | static RISCVException write_umte(CPURISCVState *env, int csrno, | |
1559 | target_ulong val) | |
1560 | { | |
1561 | target_ulong wpri_val = val & UMTE_MASK; | |
1562 | ||
1563 | if (val != wpri_val) { | |
1564 | qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n", | |
1565 | "UMTE: WPRI violation written 0x", val, | |
1566 | "vs expected 0x", wpri_val); | |
1567 | } | |
1568 | ||
1569 | if (check_pm_current_disabled(env, csrno)) { | |
1570 | return RISCV_EXCP_NONE; | |
1571 | } | |
1572 | ||
1573 | wpri_val |= (env->mmte & ~UMTE_MASK); | |
1574 | write_mmte(env, csrno, wpri_val); | |
1575 | return RISCV_EXCP_NONE; | |
1576 | } | |
1577 | ||
1578 | static RISCVException read_mpmmask(CPURISCVState *env, int csrno, | |
1579 | target_ulong *val) | |
1580 | { | |
1581 | *val = env->mpmmask; | |
1582 | return RISCV_EXCP_NONE; | |
1583 | } | |
1584 | ||
1585 | static RISCVException write_mpmmask(CPURISCVState *env, int csrno, | |
1586 | target_ulong val) | |
1587 | { | |
1588 | uint64_t mstatus; | |
1589 | ||
1590 | env->mpmmask = val; | |
1591 | env->mmte |= PM_EXT_DIRTY; | |
1592 | ||
1593 | /* Set XS and SD bits, since PM CSRs are dirty */ | |
1594 | mstatus = env->mstatus | MSTATUS_XS; | |
1595 | write_mstatus(env, csrno, mstatus); | |
1596 | return RISCV_EXCP_NONE; | |
1597 | } | |
1598 | ||
1599 | static RISCVException read_spmmask(CPURISCVState *env, int csrno, | |
1600 | target_ulong *val) | |
1601 | { | |
1602 | *val = env->spmmask; | |
1603 | return RISCV_EXCP_NONE; | |
1604 | } | |
1605 | ||
1606 | static RISCVException write_spmmask(CPURISCVState *env, int csrno, | |
1607 | target_ulong val) | |
1608 | { | |
1609 | uint64_t mstatus; | |
1610 | ||
1611 | /* if pm.current==0 we can't modify current PM CSRs */ | |
1612 | if (check_pm_current_disabled(env, csrno)) { | |
1613 | return RISCV_EXCP_NONE; | |
1614 | } | |
1615 | env->spmmask = val; | |
1616 | env->mmte |= PM_EXT_DIRTY; | |
1617 | ||
1618 | /* Set XS and SD bits, since PM CSRs are dirty */ | |
1619 | mstatus = env->mstatus | MSTATUS_XS; | |
1620 | write_mstatus(env, csrno, mstatus); | |
1621 | return RISCV_EXCP_NONE; | |
1622 | } | |
1623 | ||
1624 | static RISCVException read_upmmask(CPURISCVState *env, int csrno, | |
1625 | target_ulong *val) | |
1626 | { | |
1627 | *val = env->upmmask; | |
1628 | return RISCV_EXCP_NONE; | |
1629 | } | |
1630 | ||
1631 | static RISCVException write_upmmask(CPURISCVState *env, int csrno, | |
1632 | target_ulong val) | |
1633 | { | |
1634 | uint64_t mstatus; | |
1635 | ||
1636 | /* if pm.current==0 we can't modify current PM CSRs */ | |
1637 | if (check_pm_current_disabled(env, csrno)) { | |
1638 | return RISCV_EXCP_NONE; | |
1639 | } | |
1640 | env->upmmask = val; | |
1641 | env->mmte |= PM_EXT_DIRTY; | |
1642 | ||
1643 | /* Set XS and SD bits, since PM CSRs are dirty */ | |
1644 | mstatus = env->mstatus | MSTATUS_XS; | |
1645 | write_mstatus(env, csrno, mstatus); | |
1646 | return RISCV_EXCP_NONE; | |
1647 | } | |
1648 | ||
1649 | static RISCVException read_mpmbase(CPURISCVState *env, int csrno, | |
1650 | target_ulong *val) | |
1651 | { | |
1652 | *val = env->mpmbase; | |
1653 | return RISCV_EXCP_NONE; | |
1654 | } | |
1655 | ||
1656 | static RISCVException write_mpmbase(CPURISCVState *env, int csrno, | |
1657 | target_ulong val) | |
1658 | { | |
1659 | uint64_t mstatus; | |
1660 | ||
1661 | env->mpmbase = val; | |
1662 | env->mmte |= PM_EXT_DIRTY; | |
1663 | ||
1664 | /* Set XS and SD bits, since PM CSRs are dirty */ | |
1665 | mstatus = env->mstatus | MSTATUS_XS; | |
1666 | write_mstatus(env, csrno, mstatus); | |
1667 | return RISCV_EXCP_NONE; | |
1668 | } | |
1669 | ||
1670 | static RISCVException read_spmbase(CPURISCVState *env, int csrno, | |
1671 | target_ulong *val) | |
1672 | { | |
1673 | *val = env->spmbase; | |
1674 | return RISCV_EXCP_NONE; | |
1675 | } | |
1676 | ||
1677 | static RISCVException write_spmbase(CPURISCVState *env, int csrno, | |
1678 | target_ulong val) | |
1679 | { | |
1680 | uint64_t mstatus; | |
1681 | ||
1682 | /* if pm.current==0 we can't modify current PM CSRs */ | |
1683 | if (check_pm_current_disabled(env, csrno)) { | |
1684 | return RISCV_EXCP_NONE; | |
1685 | } | |
1686 | env->spmbase = val; | |
1687 | env->mmte |= PM_EXT_DIRTY; | |
1688 | ||
1689 | /* Set XS and SD bits, since PM CSRs are dirty */ | |
1690 | mstatus = env->mstatus | MSTATUS_XS; | |
1691 | write_mstatus(env, csrno, mstatus); | |
1692 | return RISCV_EXCP_NONE; | |
1693 | } | |
1694 | ||
1695 | static RISCVException read_upmbase(CPURISCVState *env, int csrno, | |
1696 | target_ulong *val) | |
1697 | { | |
1698 | *val = env->upmbase; | |
1699 | return RISCV_EXCP_NONE; | |
1700 | } | |
1701 | ||
1702 | static RISCVException write_upmbase(CPURISCVState *env, int csrno, | |
1703 | target_ulong val) | |
1704 | { | |
1705 | uint64_t mstatus; | |
1706 | ||
1707 | /* if pm.current==0 we can't modify current PM CSRs */ | |
1708 | if (check_pm_current_disabled(env, csrno)) { | |
1709 | return RISCV_EXCP_NONE; | |
1710 | } | |
1711 | env->upmbase = val; | |
1712 | env->mmte |= PM_EXT_DIRTY; | |
1713 | ||
1714 | /* Set XS and SD bits, since PM CSRs are dirty */ | |
1715 | mstatus = env->mstatus | MSTATUS_XS; | |
1716 | write_mstatus(env, csrno, mstatus); | |
1717 | return RISCV_EXCP_NONE; | |
1718 | } | |
1719 | ||
c7b95171 MC |
1720 | #endif |
1721 | ||
1722 | /* | |
1723 | * riscv_csrrw - read and/or update control and status register | |
1724 | * | |
1725 | * csrr <-> riscv_csrrw(env, csrno, ret_value, 0, 0); | |
1726 | * csrrw <-> riscv_csrrw(env, csrno, ret_value, value, -1); | |
1727 | * csrrs <-> riscv_csrrw(env, csrno, ret_value, -1, value); | |
1728 | * csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value); | |
1729 | */ | |
1730 | ||
533c91e8 AF |
1731 | RISCVException riscv_csrrw(CPURISCVState *env, int csrno, |
1732 | target_ulong *ret_value, | |
1733 | target_ulong new_value, target_ulong write_mask) | |
c7b95171 | 1734 | { |
533c91e8 | 1735 | RISCVException ret; |
c7b95171 | 1736 | target_ulong old_value; |
591bddea | 1737 | RISCVCPU *cpu = env_archcpu(env); |
42109837 | 1738 | int read_only = get_field(csrno, 0xC00) == 3; |
c7b95171 | 1739 | |
65e728a2 | 1740 | /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */ |
c7b95171 | 1741 | #if !defined(CONFIG_USER_ONLY) |
0a42f4c4 | 1742 | int effective_priv = env->priv; |
0a42f4c4 AF |
1743 | |
1744 | if (riscv_has_ext(env, RVH) && | |
1745 | env->priv == PRV_S && | |
1746 | !riscv_cpu_virt_enabled(env)) { | |
1747 | /* | |
1748 | * We are in S mode without virtualisation, therefore we are in HS Mode. | |
1749 | * Add 1 to the effective privledge level to allow us to access the | |
1750 | * Hypervisor CSRs. | |
1751 | */ | |
1752 | effective_priv++; | |
e6e03dcf | 1753 | } |
0a42f4c4 | 1754 | |
42109837 | 1755 | if (!env->debugger && (effective_priv < get_field(csrno, 0x300))) { |
533c91e8 | 1756 | return RISCV_EXCP_ILLEGAL_INST; |
c7b95171 MC |
1757 | } |
1758 | #endif | |
42109837 LZ |
1759 | if (write_mask && read_only) { |
1760 | return RISCV_EXCP_ILLEGAL_INST; | |
1761 | } | |
c7b95171 | 1762 | |
591bddea PD |
1763 | /* ensure the CSR extension is enabled. */ |
1764 | if (!cpu->cfg.ext_icsr) { | |
533c91e8 | 1765 | return RISCV_EXCP_ILLEGAL_INST; |
591bddea PD |
1766 | } |
1767 | ||
a88365c1 | 1768 | /* check predicate */ |
e39a8320 | 1769 | if (!csr_ops[csrno].predicate) { |
533c91e8 | 1770 | return RISCV_EXCP_ILLEGAL_INST; |
a88365c1 | 1771 | } |
e39a8320 | 1772 | ret = csr_ops[csrno].predicate(env, csrno); |
0e62f92e | 1773 | if (ret != RISCV_EXCP_NONE) { |
533c91e8 | 1774 | return ret; |
e39a8320 | 1775 | } |
a88365c1 | 1776 | |
c7b95171 MC |
1777 | /* execute combined read/write operation if it exists */ |
1778 | if (csr_ops[csrno].op) { | |
533c91e8 | 1779 | return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask); |
c7b95171 MC |
1780 | } |
1781 | ||
1782 | /* if no accessor exists then return failure */ | |
1783 | if (!csr_ops[csrno].read) { | |
533c91e8 | 1784 | return RISCV_EXCP_ILLEGAL_INST; |
c7b95171 | 1785 | } |
c7b95171 MC |
1786 | /* read old value */ |
1787 | ret = csr_ops[csrno].read(env, csrno, &old_value); | |
605def6e | 1788 | if (ret != RISCV_EXCP_NONE) { |
533c91e8 | 1789 | return ret; |
c7b95171 MC |
1790 | } |
1791 | ||
1792 | /* write value if writable and write mask set, otherwise drop writes */ | |
1793 | if (write_mask) { | |
1794 | new_value = (old_value & ~write_mask) | (new_value & write_mask); | |
1795 | if (csr_ops[csrno].write) { | |
1796 | ret = csr_ops[csrno].write(env, csrno, new_value); | |
605def6e | 1797 | if (ret != RISCV_EXCP_NONE) { |
533c91e8 | 1798 | return ret; |
c7b95171 MC |
1799 | } |
1800 | } | |
1801 | } | |
1802 | ||
1803 | /* return old value */ | |
1804 | if (ret_value) { | |
1805 | *ret_value = old_value; | |
1806 | } | |
1807 | ||
533c91e8 | 1808 | return RISCV_EXCP_NONE; |
c7b95171 MC |
1809 | } |
1810 | ||
753e3fe2 JW |
1811 | /* |
1812 | * Debugger support. If not in user mode, set env->debugger before the | |
1813 | * riscv_csrrw call and clear it after the call. | |
1814 | */ | |
533c91e8 AF |
1815 | RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, |
1816 | target_ulong *ret_value, | |
1817 | target_ulong new_value, | |
1818 | target_ulong write_mask) | |
753e3fe2 | 1819 | { |
533c91e8 | 1820 | RISCVException ret; |
753e3fe2 JW |
1821 | #if !defined(CONFIG_USER_ONLY) |
1822 | env->debugger = true; | |
1823 | #endif | |
1824 | ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask); | |
1825 | #if !defined(CONFIG_USER_ONLY) | |
1826 | env->debugger = false; | |
1827 | #endif | |
1828 | return ret; | |
1829 | } | |
1830 | ||
c7b95171 | 1831 | /* Control and Status Register function table */ |
56118ee8 | 1832 | riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { |
c7b95171 | 1833 | /* User Floating-Point CSRs */ |
8ceac5dc BM |
1834 | [CSR_FFLAGS] = { "fflags", fs, read_fflags, write_fflags }, |
1835 | [CSR_FRM] = { "frm", fs, read_frm, write_frm }, | |
1836 | [CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr }, | |
8e3a1f18 | 1837 | /* Vector CSRs */ |
8ceac5dc BM |
1838 | [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart }, |
1839 | [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat }, | |
1840 | [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm }, | |
4594fa5a | 1841 | [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr }, |
8ceac5dc BM |
1842 | [CSR_VL] = { "vl", vs, read_vl }, |
1843 | [CSR_VTYPE] = { "vtype", vs, read_vtype }, | |
2e565054 | 1844 | [CSR_VLENB] = { "vlenb", vs, read_vlenb }, |
c7b95171 | 1845 | /* User Timers and Counters */ |
8ceac5dc BM |
1846 | [CSR_CYCLE] = { "cycle", ctr, read_instret }, |
1847 | [CSR_INSTRET] = { "instret", ctr, read_instret }, | |
1848 | [CSR_CYCLEH] = { "cycleh", ctr32, read_instreth }, | |
1849 | [CSR_INSTRETH] = { "instreth", ctr32, read_instreth }, | |
1850 | ||
1851 | /* | |
1852 | * In privileged mode, the monitor will have to emulate TIME CSRs only if | |
1853 | * rdtime callback is not provided by machine/platform emulation. | |
1854 | */ | |
1855 | [CSR_TIME] = { "time", ctr, read_time }, | |
1856 | [CSR_TIMEH] = { "timeh", ctr32, read_timeh }, | |
c7b95171 MC |
1857 | |
1858 | #if !defined(CONFIG_USER_ONLY) | |
1859 | /* Machine Timers and Counters */ | |
8ceac5dc BM |
1860 | [CSR_MCYCLE] = { "mcycle", any, read_instret }, |
1861 | [CSR_MINSTRET] = { "minstret", any, read_instret }, | |
1862 | [CSR_MCYCLEH] = { "mcycleh", any32, read_instreth }, | |
1863 | [CSR_MINSTRETH] = { "minstreth", any32, read_instreth }, | |
c7b95171 MC |
1864 | |
1865 | /* Machine Information Registers */ | |
8ceac5dc BM |
1866 | [CSR_MVENDORID] = { "mvendorid", any, read_zero }, |
1867 | [CSR_MARCHID] = { "marchid", any, read_zero }, | |
1868 | [CSR_MIMPID] = { "mimpid", any, read_zero }, | |
1869 | [CSR_MHARTID] = { "mhartid", any, read_mhartid }, | |
c7b95171 MC |
1870 | |
1871 | /* Machine Trap Setup */ | |
8ceac5dc BM |
1872 | [CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus }, |
1873 | [CSR_MISA] = { "misa", any, read_misa, write_misa }, | |
1874 | [CSR_MIDELEG] = { "mideleg", any, read_mideleg, write_mideleg }, | |
1875 | [CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg }, | |
1876 | [CSR_MIE] = { "mie", any, read_mie, write_mie }, | |
1877 | [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec }, | |
1878 | [CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, write_mcounteren }, | |
c7b95171 | 1879 | |
8ceac5dc | 1880 | [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush }, |
551fa7e8 | 1881 | |
c7b95171 | 1882 | /* Machine Trap Handling */ |
8ceac5dc BM |
1883 | [CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch }, |
1884 | [CSR_MEPC] = { "mepc", any, read_mepc, write_mepc }, | |
1885 | [CSR_MCAUSE] = { "mcause", any, read_mcause, write_mcause }, | |
ac12b601 | 1886 | [CSR_MTVAL] = { "mtval", any, read_mtval, write_mtval }, |
8ceac5dc | 1887 | [CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip }, |
c7b95171 MC |
1888 | |
1889 | /* Supervisor Trap Setup */ | |
8ceac5dc BM |
1890 | [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus }, |
1891 | [CSR_SIE] = { "sie", smode, read_sie, write_sie }, | |
1892 | [CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec }, | |
1893 | [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren }, | |
c7b95171 MC |
1894 | |
1895 | /* Supervisor Trap Handling */ | |
8ceac5dc BM |
1896 | [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch }, |
1897 | [CSR_SEPC] = { "sepc", smode, read_sepc, write_sepc }, | |
1898 | [CSR_SCAUSE] = { "scause", smode, read_scause, write_scause }, | |
ac12b601 | 1899 | [CSR_STVAL] = { "stval", smode, read_stval, write_stval }, |
8ceac5dc | 1900 | [CSR_SIP] = { "sip", smode, NULL, NULL, rmw_sip }, |
c7b95171 MC |
1901 | |
1902 | /* Supervisor Protection and Translation */ | |
8ceac5dc BM |
1903 | [CSR_SATP] = { "satp", smode, read_satp, write_satp }, |
1904 | ||
1905 | [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus }, | |
1906 | [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg }, | |
1907 | [CSR_HIDELEG] = { "hideleg", hmode, read_hideleg, write_hideleg }, | |
1908 | [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip }, | |
1909 | [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip }, | |
1910 | [CSR_HIE] = { "hie", hmode, read_hie, write_hie }, | |
1911 | [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren }, | |
377cbb4b | 1912 | [CSR_HGEIE] = { "hgeie", hmode, read_zero, write_hgeie }, |
8ceac5dc BM |
1913 | [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval }, |
1914 | [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst }, | |
377cbb4b | 1915 | [CSR_HGEIP] = { "hgeip", hmode, read_zero, write_hgeip }, |
8ceac5dc BM |
1916 | [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp }, |
1917 | [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta }, | |
1918 | [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah }, | |
1919 | ||
1920 | [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus }, | |
1921 | [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip }, | |
1922 | [CSR_VSIE] = { "vsie", hmode, read_vsie, write_vsie }, | |
1923 | [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec }, | |
1924 | [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch }, | |
1925 | [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc }, | |
1926 | [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause }, | |
1927 | [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval }, | |
1928 | [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp }, | |
1929 | ||
1930 | [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2 }, | |
1931 | [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst }, | |
34cfb5f6 | 1932 | |
c7b95171 | 1933 | /* Physical Memory Protection */ |
2582a95c | 1934 | [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg }, |
8ceac5dc BM |
1935 | [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg }, |
1936 | [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, | |
1937 | [CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg }, | |
1938 | [CSR_PMPCFG3] = { "pmpcfg3", pmp, read_pmpcfg, write_pmpcfg }, | |
1939 | [CSR_PMPADDR0] = { "pmpaddr0", pmp, read_pmpaddr, write_pmpaddr }, | |
1940 | [CSR_PMPADDR1] = { "pmpaddr1", pmp, read_pmpaddr, write_pmpaddr }, | |
1941 | [CSR_PMPADDR2] = { "pmpaddr2", pmp, read_pmpaddr, write_pmpaddr }, | |
1942 | [CSR_PMPADDR3] = { "pmpaddr3", pmp, read_pmpaddr, write_pmpaddr }, | |
1943 | [CSR_PMPADDR4] = { "pmpaddr4", pmp, read_pmpaddr, write_pmpaddr }, | |
1944 | [CSR_PMPADDR5] = { "pmpaddr5", pmp, read_pmpaddr, write_pmpaddr }, | |
1945 | [CSR_PMPADDR6] = { "pmpaddr6", pmp, read_pmpaddr, write_pmpaddr }, | |
1946 | [CSR_PMPADDR7] = { "pmpaddr7", pmp, read_pmpaddr, write_pmpaddr }, | |
1947 | [CSR_PMPADDR8] = { "pmpaddr8", pmp, read_pmpaddr, write_pmpaddr }, | |
1948 | [CSR_PMPADDR9] = { "pmpaddr9", pmp, read_pmpaddr, write_pmpaddr }, | |
1949 | [CSR_PMPADDR10] = { "pmpaddr10", pmp, read_pmpaddr, write_pmpaddr }, | |
1950 | [CSR_PMPADDR11] = { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr }, | |
1951 | [CSR_PMPADDR12] = { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr }, | |
1952 | [CSR_PMPADDR13] = { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr }, | |
1953 | [CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr }, | |
1954 | [CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr }, | |
c7b95171 | 1955 | |
4bbe8033 AB |
1956 | /* User Pointer Masking */ |
1957 | [CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte }, | |
1958 | [CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask, write_upmmask }, | |
1959 | [CSR_UPMBASE] = { "upmbase", pointer_masking, read_upmbase, write_upmbase }, | |
1960 | /* Machine Pointer Masking */ | |
1961 | [CSR_MMTE] = { "mmte", pointer_masking, read_mmte, write_mmte }, | |
1962 | [CSR_MPMMASK] = { "mpmmask", pointer_masking, read_mpmmask, write_mpmmask }, | |
1963 | [CSR_MPMBASE] = { "mpmbase", pointer_masking, read_mpmbase, write_mpmbase }, | |
1964 | /* Supervisor Pointer Masking */ | |
1965 | [CSR_SMTE] = { "smte", pointer_masking, read_smte, write_smte }, | |
1966 | [CSR_SPMMASK] = { "spmmask", pointer_masking, read_spmmask, write_spmmask }, | |
1967 | [CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase, write_spmbase }, | |
1968 | ||
c7b95171 | 1969 | /* Performance Counters */ |
8ceac5dc BM |
1970 | [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_zero }, |
1971 | [CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_zero }, | |
1972 | [CSR_HPMCOUNTER5] = { "hpmcounter5", ctr, read_zero }, | |
1973 | [CSR_HPMCOUNTER6] = { "hpmcounter6", ctr, read_zero }, | |
1974 | [CSR_HPMCOUNTER7] = { "hpmcounter7", ctr, read_zero }, | |
1975 | [CSR_HPMCOUNTER8] = { "hpmcounter8", ctr, read_zero }, | |
1976 | [CSR_HPMCOUNTER9] = { "hpmcounter9", ctr, read_zero }, | |
1977 | [CSR_HPMCOUNTER10] = { "hpmcounter10", ctr, read_zero }, | |
1978 | [CSR_HPMCOUNTER11] = { "hpmcounter11", ctr, read_zero }, | |
1979 | [CSR_HPMCOUNTER12] = { "hpmcounter12", ctr, read_zero }, | |
1980 | [CSR_HPMCOUNTER13] = { "hpmcounter13", ctr, read_zero }, | |
1981 | [CSR_HPMCOUNTER14] = { "hpmcounter14", ctr, read_zero }, | |
1982 | [CSR_HPMCOUNTER15] = { "hpmcounter15", ctr, read_zero }, | |
1983 | [CSR_HPMCOUNTER16] = { "hpmcounter16", ctr, read_zero }, | |
1984 | [CSR_HPMCOUNTER17] = { "hpmcounter17", ctr, read_zero }, | |
1985 | [CSR_HPMCOUNTER18] = { "hpmcounter18", ctr, read_zero }, | |
1986 | [CSR_HPMCOUNTER19] = { "hpmcounter19", ctr, read_zero }, | |
1987 | [CSR_HPMCOUNTER20] = { "hpmcounter20", ctr, read_zero }, | |
1988 | [CSR_HPMCOUNTER21] = { "hpmcounter21", ctr, read_zero }, | |
1989 | [CSR_HPMCOUNTER22] = { "hpmcounter22", ctr, read_zero }, | |
1990 | [CSR_HPMCOUNTER23] = { "hpmcounter23", ctr, read_zero }, | |
1991 | [CSR_HPMCOUNTER24] = { "hpmcounter24", ctr, read_zero }, | |
1992 | [CSR_HPMCOUNTER25] = { "hpmcounter25", ctr, read_zero }, | |
1993 | [CSR_HPMCOUNTER26] = { "hpmcounter26", ctr, read_zero }, | |
1994 | [CSR_HPMCOUNTER27] = { "hpmcounter27", ctr, read_zero }, | |
1995 | [CSR_HPMCOUNTER28] = { "hpmcounter28", ctr, read_zero }, | |
1996 | [CSR_HPMCOUNTER29] = { "hpmcounter29", ctr, read_zero }, | |
1997 | [CSR_HPMCOUNTER30] = { "hpmcounter30", ctr, read_zero }, | |
1998 | [CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_zero }, | |
1999 | ||
2000 | [CSR_MHPMCOUNTER3] = { "mhpmcounter3", any, read_zero }, | |
2001 | [CSR_MHPMCOUNTER4] = { "mhpmcounter4", any, read_zero }, | |
2002 | [CSR_MHPMCOUNTER5] = { "mhpmcounter5", any, read_zero }, | |
2003 | [CSR_MHPMCOUNTER6] = { "mhpmcounter6", any, read_zero }, | |
2004 | [CSR_MHPMCOUNTER7] = { "mhpmcounter7", any, read_zero }, | |
2005 | [CSR_MHPMCOUNTER8] = { "mhpmcounter8", any, read_zero }, | |
2006 | [CSR_MHPMCOUNTER9] = { "mhpmcounter9", any, read_zero }, | |
2007 | [CSR_MHPMCOUNTER10] = { "mhpmcounter10", any, read_zero }, | |
2008 | [CSR_MHPMCOUNTER11] = { "mhpmcounter11", any, read_zero }, | |
2009 | [CSR_MHPMCOUNTER12] = { "mhpmcounter12", any, read_zero }, | |
2010 | [CSR_MHPMCOUNTER13] = { "mhpmcounter13", any, read_zero }, | |
2011 | [CSR_MHPMCOUNTER14] = { "mhpmcounter14", any, read_zero }, | |
2012 | [CSR_MHPMCOUNTER15] = { "mhpmcounter15", any, read_zero }, | |
2013 | [CSR_MHPMCOUNTER16] = { "mhpmcounter16", any, read_zero }, | |
2014 | [CSR_MHPMCOUNTER17] = { "mhpmcounter17", any, read_zero }, | |
2015 | [CSR_MHPMCOUNTER18] = { "mhpmcounter18", any, read_zero }, | |
2016 | [CSR_MHPMCOUNTER19] = { "mhpmcounter19", any, read_zero }, | |
2017 | [CSR_MHPMCOUNTER20] = { "mhpmcounter20", any, read_zero }, | |
2018 | [CSR_MHPMCOUNTER21] = { "mhpmcounter21", any, read_zero }, | |
2019 | [CSR_MHPMCOUNTER22] = { "mhpmcounter22", any, read_zero }, | |
2020 | [CSR_MHPMCOUNTER23] = { "mhpmcounter23", any, read_zero }, | |
2021 | [CSR_MHPMCOUNTER24] = { "mhpmcounter24", any, read_zero }, | |
2022 | [CSR_MHPMCOUNTER25] = { "mhpmcounter25", any, read_zero }, | |
2023 | [CSR_MHPMCOUNTER26] = { "mhpmcounter26", any, read_zero }, | |
2024 | [CSR_MHPMCOUNTER27] = { "mhpmcounter27", any, read_zero }, | |
2025 | [CSR_MHPMCOUNTER28] = { "mhpmcounter28", any, read_zero }, | |
2026 | [CSR_MHPMCOUNTER29] = { "mhpmcounter29", any, read_zero }, | |
2027 | [CSR_MHPMCOUNTER30] = { "mhpmcounter30", any, read_zero }, | |
2028 | [CSR_MHPMCOUNTER31] = { "mhpmcounter31", any, read_zero }, | |
2029 | ||
2030 | [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_zero }, | |
2031 | [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_zero }, | |
2032 | [CSR_MHPMEVENT5] = { "mhpmevent5", any, read_zero }, | |
2033 | [CSR_MHPMEVENT6] = { "mhpmevent6", any, read_zero }, | |
2034 | [CSR_MHPMEVENT7] = { "mhpmevent7", any, read_zero }, | |
2035 | [CSR_MHPMEVENT8] = { "mhpmevent8", any, read_zero }, | |
2036 | [CSR_MHPMEVENT9] = { "mhpmevent9", any, read_zero }, | |
2037 | [CSR_MHPMEVENT10] = { "mhpmevent10", any, read_zero }, | |
2038 | [CSR_MHPMEVENT11] = { "mhpmevent11", any, read_zero }, | |
2039 | [CSR_MHPMEVENT12] = { "mhpmevent12", any, read_zero }, | |
2040 | [CSR_MHPMEVENT13] = { "mhpmevent13", any, read_zero }, | |
2041 | [CSR_MHPMEVENT14] = { "mhpmevent14", any, read_zero }, | |
2042 | [CSR_MHPMEVENT15] = { "mhpmevent15", any, read_zero }, | |
2043 | [CSR_MHPMEVENT16] = { "mhpmevent16", any, read_zero }, | |
2044 | [CSR_MHPMEVENT17] = { "mhpmevent17", any, read_zero }, | |
2045 | [CSR_MHPMEVENT18] = { "mhpmevent18", any, read_zero }, | |
2046 | [CSR_MHPMEVENT19] = { "mhpmevent19", any, read_zero }, | |
2047 | [CSR_MHPMEVENT20] = { "mhpmevent20", any, read_zero }, | |
2048 | [CSR_MHPMEVENT21] = { "mhpmevent21", any, read_zero }, | |
2049 | [CSR_MHPMEVENT22] = { "mhpmevent22", any, read_zero }, | |
2050 | [CSR_MHPMEVENT23] = { "mhpmevent23", any, read_zero }, | |
2051 | [CSR_MHPMEVENT24] = { "mhpmevent24", any, read_zero }, | |
2052 | [CSR_MHPMEVENT25] = { "mhpmevent25", any, read_zero }, | |
2053 | [CSR_MHPMEVENT26] = { "mhpmevent26", any, read_zero }, | |
2054 | [CSR_MHPMEVENT27] = { "mhpmevent27", any, read_zero }, | |
2055 | [CSR_MHPMEVENT28] = { "mhpmevent28", any, read_zero }, | |
2056 | [CSR_MHPMEVENT29] = { "mhpmevent29", any, read_zero }, | |
2057 | [CSR_MHPMEVENT30] = { "mhpmevent30", any, read_zero }, | |
2058 | [CSR_MHPMEVENT31] = { "mhpmevent31", any, read_zero }, | |
2059 | ||
2060 | [CSR_HPMCOUNTER3H] = { "hpmcounter3h", ctr32, read_zero }, | |
2061 | [CSR_HPMCOUNTER4H] = { "hpmcounter4h", ctr32, read_zero }, | |
2062 | [CSR_HPMCOUNTER5H] = { "hpmcounter5h", ctr32, read_zero }, | |
2063 | [CSR_HPMCOUNTER6H] = { "hpmcounter6h", ctr32, read_zero }, | |
2064 | [CSR_HPMCOUNTER7H] = { "hpmcounter7h", ctr32, read_zero }, | |
2065 | [CSR_HPMCOUNTER8H] = { "hpmcounter8h", ctr32, read_zero }, | |
2066 | [CSR_HPMCOUNTER9H] = { "hpmcounter9h", ctr32, read_zero }, | |
2067 | [CSR_HPMCOUNTER10H] = { "hpmcounter10h", ctr32, read_zero }, | |
2068 | [CSR_HPMCOUNTER11H] = { "hpmcounter11h", ctr32, read_zero }, | |
2069 | [CSR_HPMCOUNTER12H] = { "hpmcounter12h", ctr32, read_zero }, | |
2070 | [CSR_HPMCOUNTER13H] = { "hpmcounter13h", ctr32, read_zero }, | |
2071 | [CSR_HPMCOUNTER14H] = { "hpmcounter14h", ctr32, read_zero }, | |
2072 | [CSR_HPMCOUNTER15H] = { "hpmcounter15h", ctr32, read_zero }, | |
2073 | [CSR_HPMCOUNTER16H] = { "hpmcounter16h", ctr32, read_zero }, | |
2074 | [CSR_HPMCOUNTER17H] = { "hpmcounter17h", ctr32, read_zero }, | |
2075 | [CSR_HPMCOUNTER18H] = { "hpmcounter18h", ctr32, read_zero }, | |
2076 | [CSR_HPMCOUNTER19H] = { "hpmcounter19h", ctr32, read_zero }, | |
2077 | [CSR_HPMCOUNTER20H] = { "hpmcounter20h", ctr32, read_zero }, | |
2078 | [CSR_HPMCOUNTER21H] = { "hpmcounter21h", ctr32, read_zero }, | |
2079 | [CSR_HPMCOUNTER22H] = { "hpmcounter22h", ctr32, read_zero }, | |
2080 | [CSR_HPMCOUNTER23H] = { "hpmcounter23h", ctr32, read_zero }, | |
2081 | [CSR_HPMCOUNTER24H] = { "hpmcounter24h", ctr32, read_zero }, | |
2082 | [CSR_HPMCOUNTER25H] = { "hpmcounter25h", ctr32, read_zero }, | |
2083 | [CSR_HPMCOUNTER26H] = { "hpmcounter26h", ctr32, read_zero }, | |
2084 | [CSR_HPMCOUNTER27H] = { "hpmcounter27h", ctr32, read_zero }, | |
2085 | [CSR_HPMCOUNTER28H] = { "hpmcounter28h", ctr32, read_zero }, | |
2086 | [CSR_HPMCOUNTER29H] = { "hpmcounter29h", ctr32, read_zero }, | |
2087 | [CSR_HPMCOUNTER30H] = { "hpmcounter30h", ctr32, read_zero }, | |
2088 | [CSR_HPMCOUNTER31H] = { "hpmcounter31h", ctr32, read_zero }, | |
2089 | ||
2090 | [CSR_MHPMCOUNTER3H] = { "mhpmcounter3h", any32, read_zero }, | |
2091 | [CSR_MHPMCOUNTER4H] = { "mhpmcounter4h", any32, read_zero }, | |
2092 | [CSR_MHPMCOUNTER5H] = { "mhpmcounter5h", any32, read_zero }, | |
2093 | [CSR_MHPMCOUNTER6H] = { "mhpmcounter6h", any32, read_zero }, | |
2094 | [CSR_MHPMCOUNTER7H] = { "mhpmcounter7h", any32, read_zero }, | |
2095 | [CSR_MHPMCOUNTER8H] = { "mhpmcounter8h", any32, read_zero }, | |
2096 | [CSR_MHPMCOUNTER9H] = { "mhpmcounter9h", any32, read_zero }, | |
2097 | [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", any32, read_zero }, | |
2098 | [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", any32, read_zero }, | |
2099 | [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", any32, read_zero }, | |
2100 | [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", any32, read_zero }, | |
2101 | [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", any32, read_zero }, | |
2102 | [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", any32, read_zero }, | |
2103 | [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", any32, read_zero }, | |
2104 | [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", any32, read_zero }, | |
2105 | [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", any32, read_zero }, | |
2106 | [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", any32, read_zero }, | |
2107 | [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", any32, read_zero }, | |
2108 | [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", any32, read_zero }, | |
2109 | [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", any32, read_zero }, | |
2110 | [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", any32, read_zero }, | |
2111 | [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", any32, read_zero }, | |
2112 | [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", any32, read_zero }, | |
2113 | [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", any32, read_zero }, | |
2114 | [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", any32, read_zero }, | |
2115 | [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", any32, read_zero }, | |
2116 | [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32, read_zero }, | |
2117 | [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32, read_zero }, | |
2118 | [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32, read_zero }, | |
c7b95171 MC |
2119 | #endif /* !CONFIG_USER_ONLY */ |
2120 | }; |