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c7b95171 MC |
1 | /* |
2 | * RISC-V Control and Status Registers. | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017-2018 SiFive, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2 or later, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
21 | #include "qemu/log.h" | |
22 | #include "cpu.h" | |
23 | #include "qemu/main-loop.h" | |
24 | #include "exec/exec-all.h" | |
25 | ||
c7b95171 MC |
26 | /* CSR function table public API */ |
27 | void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) | |
28 | { | |
29 | *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)]; | |
30 | } | |
31 | ||
32 | void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) | |
33 | { | |
34 | csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops; | |
35 | } | |
36 | ||
a88365c1 | 37 | /* Predicates */ |
0e62f92e | 38 | static RISCVException fs(CPURISCVState *env, int csrno) |
a88365c1 MC |
39 | { |
40 | #if !defined(CONFIG_USER_ONLY) | |
8e3a1f18 LZ |
41 | /* loose check condition for fcsr in vector extension */ |
42 | if ((csrno == CSR_FCSR) && (env->misa & RVV)) { | |
0e62f92e | 43 | return RISCV_EXCP_NONE; |
8e3a1f18 | 44 | } |
b345b480 | 45 | if (!env->debugger && !riscv_cpu_fp_enabled(env)) { |
0e62f92e | 46 | return RISCV_EXCP_ILLEGAL_INST; |
a88365c1 MC |
47 | } |
48 | #endif | |
0e62f92e | 49 | return RISCV_EXCP_NONE; |
a88365c1 MC |
50 | } |
51 | ||
0e62f92e | 52 | static RISCVException vs(CPURISCVState *env, int csrno) |
8e3a1f18 LZ |
53 | { |
54 | if (env->misa & RVV) { | |
0e62f92e | 55 | return RISCV_EXCP_NONE; |
8e3a1f18 | 56 | } |
0e62f92e | 57 | return RISCV_EXCP_ILLEGAL_INST; |
8e3a1f18 LZ |
58 | } |
59 | ||
0e62f92e | 60 | static RISCVException ctr(CPURISCVState *env, int csrno) |
a88365c1 MC |
61 | { |
62 | #if !defined(CONFIG_USER_ONLY) | |
0a13a5b8 AF |
63 | CPUState *cs = env_cpu(env); |
64 | RISCVCPU *cpu = RISCV_CPU(cs); | |
0a13a5b8 AF |
65 | |
66 | if (!cpu->cfg.ext_counters) { | |
67 | /* The Counters extensions is not enabled */ | |
0e62f92e | 68 | return RISCV_EXCP_ILLEGAL_INST; |
0a13a5b8 | 69 | } |
e39a8320 AF |
70 | |
71 | if (riscv_cpu_virt_enabled(env)) { | |
72 | switch (csrno) { | |
73 | case CSR_CYCLE: | |
74 | if (!get_field(env->hcounteren, HCOUNTEREN_CY) && | |
75 | get_field(env->mcounteren, HCOUNTEREN_CY)) { | |
0e62f92e | 76 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
e39a8320 AF |
77 | } |
78 | break; | |
79 | case CSR_TIME: | |
80 | if (!get_field(env->hcounteren, HCOUNTEREN_TM) && | |
81 | get_field(env->mcounteren, HCOUNTEREN_TM)) { | |
0e62f92e | 82 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
e39a8320 AF |
83 | } |
84 | break; | |
85 | case CSR_INSTRET: | |
86 | if (!get_field(env->hcounteren, HCOUNTEREN_IR) && | |
87 | get_field(env->mcounteren, HCOUNTEREN_IR)) { | |
0e62f92e | 88 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
e39a8320 AF |
89 | } |
90 | break; | |
91 | case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: | |
92 | if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) && | |
93 | get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) { | |
0e62f92e | 94 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
e39a8320 AF |
95 | } |
96 | break; | |
8987cdc4 AF |
97 | } |
98 | if (riscv_cpu_is_32bit(env)) { | |
99 | switch (csrno) { | |
100 | case CSR_CYCLEH: | |
101 | if (!get_field(env->hcounteren, HCOUNTEREN_CY) && | |
102 | get_field(env->mcounteren, HCOUNTEREN_CY)) { | |
0e62f92e | 103 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
8987cdc4 AF |
104 | } |
105 | break; | |
106 | case CSR_TIMEH: | |
107 | if (!get_field(env->hcounteren, HCOUNTEREN_TM) && | |
108 | get_field(env->mcounteren, HCOUNTEREN_TM)) { | |
0e62f92e | 109 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
8987cdc4 AF |
110 | } |
111 | break; | |
112 | case CSR_INSTRETH: | |
113 | if (!get_field(env->hcounteren, HCOUNTEREN_IR) && | |
114 | get_field(env->mcounteren, HCOUNTEREN_IR)) { | |
0e62f92e | 115 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
8987cdc4 AF |
116 | } |
117 | break; | |
118 | case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: | |
119 | if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) && | |
120 | get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) { | |
0e62f92e | 121 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
8987cdc4 AF |
122 | } |
123 | break; | |
e39a8320 | 124 | } |
e39a8320 AF |
125 | } |
126 | } | |
a88365c1 | 127 | #endif |
0e62f92e | 128 | return RISCV_EXCP_NONE; |
a88365c1 MC |
129 | } |
130 | ||
0e62f92e | 131 | static RISCVException ctr32(CPURISCVState *env, int csrno) |
8987cdc4 AF |
132 | { |
133 | if (!riscv_cpu_is_32bit(env)) { | |
0e62f92e | 134 | return RISCV_EXCP_ILLEGAL_INST; |
8987cdc4 AF |
135 | } |
136 | ||
137 | return ctr(env, csrno); | |
138 | } | |
139 | ||
a88365c1 | 140 | #if !defined(CONFIG_USER_ONLY) |
0e62f92e | 141 | static RISCVException any(CPURISCVState *env, int csrno) |
a88365c1 | 142 | { |
0e62f92e | 143 | return RISCV_EXCP_NONE; |
a88365c1 MC |
144 | } |
145 | ||
0e62f92e | 146 | static RISCVException any32(CPURISCVState *env, int csrno) |
8987cdc4 AF |
147 | { |
148 | if (!riscv_cpu_is_32bit(env)) { | |
0e62f92e | 149 | return RISCV_EXCP_ILLEGAL_INST; |
8987cdc4 AF |
150 | } |
151 | ||
152 | return any(env, csrno); | |
153 | ||
154 | } | |
155 | ||
0e62f92e | 156 | static RISCVException smode(CPURISCVState *env, int csrno) |
a88365c1 | 157 | { |
0e62f92e AF |
158 | if (riscv_has_ext(env, RVS)) { |
159 | return RISCV_EXCP_NONE; | |
160 | } | |
161 | ||
162 | return RISCV_EXCP_ILLEGAL_INST; | |
a88365c1 MC |
163 | } |
164 | ||
0e62f92e | 165 | static RISCVException hmode(CPURISCVState *env, int csrno) |
ff2cc129 AF |
166 | { |
167 | if (riscv_has_ext(env, RVS) && | |
168 | riscv_has_ext(env, RVH)) { | |
169 | /* Hypervisor extension is supported */ | |
170 | if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || | |
171 | env->priv == PRV_M) { | |
0e62f92e | 172 | return RISCV_EXCP_NONE; |
e39a8320 | 173 | } else { |
0e62f92e | 174 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
ff2cc129 AF |
175 | } |
176 | } | |
177 | ||
0e62f92e | 178 | return RISCV_EXCP_ILLEGAL_INST; |
ff2cc129 AF |
179 | } |
180 | ||
0e62f92e | 181 | static RISCVException hmode32(CPURISCVState *env, int csrno) |
8987cdc4 AF |
182 | { |
183 | if (!riscv_cpu_is_32bit(env)) { | |
d6f20dac AF |
184 | if (riscv_cpu_virt_enabled(env)) { |
185 | return RISCV_EXCP_ILLEGAL_INST; | |
186 | } else { | |
187 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; | |
188 | } | |
8987cdc4 AF |
189 | } |
190 | ||
191 | return hmode(env, csrno); | |
192 | ||
193 | } | |
194 | ||
0e62f92e | 195 | static RISCVException pmp(CPURISCVState *env, int csrno) |
a88365c1 | 196 | { |
0e62f92e AF |
197 | if (riscv_feature(env, RISCV_FEATURE_PMP)) { |
198 | return RISCV_EXCP_NONE; | |
199 | } | |
200 | ||
201 | return RISCV_EXCP_ILLEGAL_INST; | |
a88365c1 MC |
202 | } |
203 | #endif | |
204 | ||
c7b95171 | 205 | /* User Floating-Point CSRs */ |
605def6e AF |
206 | static RISCVException read_fflags(CPURISCVState *env, int csrno, |
207 | target_ulong *val) | |
c7b95171 MC |
208 | { |
209 | #if !defined(CONFIG_USER_ONLY) | |
b345b480 | 210 | if (!env->debugger && !riscv_cpu_fp_enabled(env)) { |
605def6e | 211 | return RISCV_EXCP_ILLEGAL_INST; |
c7b95171 MC |
212 | } |
213 | #endif | |
fb738839 | 214 | *val = riscv_cpu_get_fflags(env); |
605def6e | 215 | return RISCV_EXCP_NONE; |
c7b95171 MC |
216 | } |
217 | ||
605def6e AF |
218 | static RISCVException write_fflags(CPURISCVState *env, int csrno, |
219 | target_ulong val) | |
c7b95171 MC |
220 | { |
221 | #if !defined(CONFIG_USER_ONLY) | |
b345b480 | 222 | if (!env->debugger && !riscv_cpu_fp_enabled(env)) { |
605def6e | 223 | return RISCV_EXCP_ILLEGAL_INST; |
c7b95171 MC |
224 | } |
225 | env->mstatus |= MSTATUS_FS; | |
226 | #endif | |
fb738839 | 227 | riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT)); |
605def6e | 228 | return RISCV_EXCP_NONE; |
c7b95171 MC |
229 | } |
230 | ||
605def6e AF |
231 | static RISCVException read_frm(CPURISCVState *env, int csrno, |
232 | target_ulong *val) | |
c7b95171 MC |
233 | { |
234 | #if !defined(CONFIG_USER_ONLY) | |
b345b480 | 235 | if (!env->debugger && !riscv_cpu_fp_enabled(env)) { |
605def6e | 236 | return RISCV_EXCP_ILLEGAL_INST; |
c7b95171 MC |
237 | } |
238 | #endif | |
239 | *val = env->frm; | |
605def6e | 240 | return RISCV_EXCP_NONE; |
c7b95171 MC |
241 | } |
242 | ||
605def6e AF |
243 | static RISCVException write_frm(CPURISCVState *env, int csrno, |
244 | target_ulong val) | |
c7b95171 MC |
245 | { |
246 | #if !defined(CONFIG_USER_ONLY) | |
b345b480 | 247 | if (!env->debugger && !riscv_cpu_fp_enabled(env)) { |
605def6e | 248 | return RISCV_EXCP_ILLEGAL_INST; |
c7b95171 MC |
249 | } |
250 | env->mstatus |= MSTATUS_FS; | |
251 | #endif | |
252 | env->frm = val & (FSR_RD >> FSR_RD_SHIFT); | |
605def6e | 253 | return RISCV_EXCP_NONE; |
c7b95171 MC |
254 | } |
255 | ||
605def6e AF |
256 | static RISCVException read_fcsr(CPURISCVState *env, int csrno, |
257 | target_ulong *val) | |
c7b95171 MC |
258 | { |
259 | #if !defined(CONFIG_USER_ONLY) | |
b345b480 | 260 | if (!env->debugger && !riscv_cpu_fp_enabled(env)) { |
605def6e | 261 | return RISCV_EXCP_ILLEGAL_INST; |
c7b95171 MC |
262 | } |
263 | #endif | |
fb738839 | 264 | *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) |
c7b95171 | 265 | | (env->frm << FSR_RD_SHIFT); |
8e3a1f18 LZ |
266 | if (vs(env, csrno) >= 0) { |
267 | *val |= (env->vxrm << FSR_VXRM_SHIFT) | |
268 | | (env->vxsat << FSR_VXSAT_SHIFT); | |
269 | } | |
605def6e | 270 | return RISCV_EXCP_NONE; |
c7b95171 MC |
271 | } |
272 | ||
605def6e AF |
273 | static RISCVException write_fcsr(CPURISCVState *env, int csrno, |
274 | target_ulong val) | |
c7b95171 MC |
275 | { |
276 | #if !defined(CONFIG_USER_ONLY) | |
b345b480 | 277 | if (!env->debugger && !riscv_cpu_fp_enabled(env)) { |
605def6e | 278 | return RISCV_EXCP_ILLEGAL_INST; |
c7b95171 MC |
279 | } |
280 | env->mstatus |= MSTATUS_FS; | |
281 | #endif | |
282 | env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; | |
8e3a1f18 LZ |
283 | if (vs(env, csrno) >= 0) { |
284 | env->vxrm = (val & FSR_VXRM) >> FSR_VXRM_SHIFT; | |
285 | env->vxsat = (val & FSR_VXSAT) >> FSR_VXSAT_SHIFT; | |
286 | } | |
fb738839 | 287 | riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT); |
605def6e | 288 | return RISCV_EXCP_NONE; |
c7b95171 MC |
289 | } |
290 | ||
605def6e AF |
291 | static RISCVException read_vtype(CPURISCVState *env, int csrno, |
292 | target_ulong *val) | |
8e3a1f18 LZ |
293 | { |
294 | *val = env->vtype; | |
605def6e | 295 | return RISCV_EXCP_NONE; |
8e3a1f18 LZ |
296 | } |
297 | ||
605def6e AF |
298 | static RISCVException read_vl(CPURISCVState *env, int csrno, |
299 | target_ulong *val) | |
8e3a1f18 LZ |
300 | { |
301 | *val = env->vl; | |
605def6e | 302 | return RISCV_EXCP_NONE; |
8e3a1f18 LZ |
303 | } |
304 | ||
605def6e AF |
305 | static RISCVException read_vxrm(CPURISCVState *env, int csrno, |
306 | target_ulong *val) | |
8e3a1f18 LZ |
307 | { |
308 | *val = env->vxrm; | |
605def6e | 309 | return RISCV_EXCP_NONE; |
8e3a1f18 LZ |
310 | } |
311 | ||
605def6e AF |
312 | static RISCVException write_vxrm(CPURISCVState *env, int csrno, |
313 | target_ulong val) | |
8e3a1f18 LZ |
314 | { |
315 | env->vxrm = val; | |
605def6e | 316 | return RISCV_EXCP_NONE; |
8e3a1f18 LZ |
317 | } |
318 | ||
605def6e AF |
319 | static RISCVException read_vxsat(CPURISCVState *env, int csrno, |
320 | target_ulong *val) | |
8e3a1f18 LZ |
321 | { |
322 | *val = env->vxsat; | |
605def6e | 323 | return RISCV_EXCP_NONE; |
8e3a1f18 LZ |
324 | } |
325 | ||
605def6e AF |
326 | static RISCVException write_vxsat(CPURISCVState *env, int csrno, |
327 | target_ulong val) | |
8e3a1f18 LZ |
328 | { |
329 | env->vxsat = val; | |
605def6e | 330 | return RISCV_EXCP_NONE; |
8e3a1f18 LZ |
331 | } |
332 | ||
605def6e AF |
333 | static RISCVException read_vstart(CPURISCVState *env, int csrno, |
334 | target_ulong *val) | |
8e3a1f18 LZ |
335 | { |
336 | *val = env->vstart; | |
605def6e | 337 | return RISCV_EXCP_NONE; |
8e3a1f18 LZ |
338 | } |
339 | ||
605def6e AF |
340 | static RISCVException write_vstart(CPURISCVState *env, int csrno, |
341 | target_ulong val) | |
8e3a1f18 LZ |
342 | { |
343 | env->vstart = val; | |
605def6e | 344 | return RISCV_EXCP_NONE; |
8e3a1f18 LZ |
345 | } |
346 | ||
c7b95171 | 347 | /* User Timers and Counters */ |
605def6e AF |
348 | static RISCVException read_instret(CPURISCVState *env, int csrno, |
349 | target_ulong *val) | |
c7b95171 | 350 | { |
c7b95171 | 351 | #if !defined(CONFIG_USER_ONLY) |
740b1759 | 352 | if (icount_enabled()) { |
8191d368 | 353 | *val = icount_get(); |
c7b95171 MC |
354 | } else { |
355 | *val = cpu_get_host_ticks(); | |
356 | } | |
357 | #else | |
358 | *val = cpu_get_host_ticks(); | |
359 | #endif | |
605def6e | 360 | return RISCV_EXCP_NONE; |
c7b95171 MC |
361 | } |
362 | ||
605def6e AF |
363 | static RISCVException read_instreth(CPURISCVState *env, int csrno, |
364 | target_ulong *val) | |
c7b95171 | 365 | { |
c7b95171 | 366 | #if !defined(CONFIG_USER_ONLY) |
740b1759 | 367 | if (icount_enabled()) { |
8191d368 | 368 | *val = icount_get() >> 32; |
c7b95171 MC |
369 | } else { |
370 | *val = cpu_get_host_ticks() >> 32; | |
371 | } | |
372 | #else | |
373 | *val = cpu_get_host_ticks() >> 32; | |
374 | #endif | |
605def6e | 375 | return RISCV_EXCP_NONE; |
c7b95171 | 376 | } |
c7b95171 MC |
377 | |
378 | #if defined(CONFIG_USER_ONLY) | |
605def6e AF |
379 | static RISCVException read_time(CPURISCVState *env, int csrno, |
380 | target_ulong *val) | |
c7b95171 MC |
381 | { |
382 | *val = cpu_get_host_ticks(); | |
605def6e | 383 | return RISCV_EXCP_NONE; |
c7b95171 MC |
384 | } |
385 | ||
605def6e AF |
386 | static RISCVException read_timeh(CPURISCVState *env, int csrno, |
387 | target_ulong *val) | |
c7b95171 MC |
388 | { |
389 | *val = cpu_get_host_ticks() >> 32; | |
605def6e | 390 | return RISCV_EXCP_NONE; |
c7b95171 | 391 | } |
c7b95171 MC |
392 | |
393 | #else /* CONFIG_USER_ONLY */ | |
394 | ||
605def6e AF |
395 | static RISCVException read_time(CPURISCVState *env, int csrno, |
396 | target_ulong *val) | |
c6957248 AP |
397 | { |
398 | uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; | |
399 | ||
400 | if (!env->rdtime_fn) { | |
605def6e | 401 | return RISCV_EXCP_ILLEGAL_INST; |
c6957248 AP |
402 | } |
403 | ||
a47ef6e9 | 404 | *val = env->rdtime_fn(env->rdtime_fn_arg) + delta; |
605def6e | 405 | return RISCV_EXCP_NONE; |
c6957248 AP |
406 | } |
407 | ||
605def6e AF |
408 | static RISCVException read_timeh(CPURISCVState *env, int csrno, |
409 | target_ulong *val) | |
c6957248 AP |
410 | { |
411 | uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; | |
412 | ||
413 | if (!env->rdtime_fn) { | |
605def6e | 414 | return RISCV_EXCP_ILLEGAL_INST; |
c6957248 AP |
415 | } |
416 | ||
a47ef6e9 | 417 | *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32; |
605def6e | 418 | return RISCV_EXCP_NONE; |
c6957248 | 419 | } |
c6957248 | 420 | |
c7b95171 MC |
421 | /* Machine constants */ |
422 | ||
ff2cc129 AF |
423 | #define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP) |
424 | #define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP) | |
425 | #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) | |
c7b95171 | 426 | |
d0e53ce3 AF |
427 | static const target_ulong delegable_ints = S_MODE_INTERRUPTS | |
428 | VS_MODE_INTERRUPTS; | |
429 | static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | | |
430 | VS_MODE_INTERRUPTS; | |
c7b95171 MC |
431 | static const target_ulong delegable_excps = |
432 | (1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | | |
433 | (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | | |
434 | (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | | |
435 | (1ULL << (RISCV_EXCP_BREAKPOINT)) | | |
436 | (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | | |
437 | (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | | |
438 | (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | | |
439 | (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | | |
440 | (1ULL << (RISCV_EXCP_U_ECALL)) | | |
441 | (1ULL << (RISCV_EXCP_S_ECALL)) | | |
ab67a1d0 | 442 | (1ULL << (RISCV_EXCP_VS_ECALL)) | |
c7b95171 MC |
443 | (1ULL << (RISCV_EXCP_M_ECALL)) | |
444 | (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | | |
445 | (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | | |
ab67a1d0 AF |
446 | (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | |
447 | (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | | |
448 | (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | | |
e39a8320 | 449 | (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | |
ab67a1d0 | 450 | (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)); |
c7b95171 MC |
451 | static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | |
452 | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | | |
453 | SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD; | |
087b051a | 454 | static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP; |
e89b631c GK |
455 | static const target_ulong hip_writable_mask = MIP_VSSIP; |
456 | static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; | |
8747c9ee | 457 | static const target_ulong vsip_writable_mask = MIP_VSSIP; |
c7b95171 | 458 | |
8987cdc4 | 459 | static const char valid_vm_1_10_32[16] = { |
c7b95171 MC |
460 | [VM_1_10_MBARE] = 1, |
461 | [VM_1_10_SV32] = 1 | |
462 | }; | |
8987cdc4 AF |
463 | |
464 | static const char valid_vm_1_10_64[16] = { | |
c7b95171 MC |
465 | [VM_1_10_MBARE] = 1, |
466 | [VM_1_10_SV39] = 1, | |
467 | [VM_1_10_SV48] = 1, | |
468 | [VM_1_10_SV57] = 1 | |
469 | }; | |
c7b95171 MC |
470 | |
471 | /* Machine Information Registers */ | |
605def6e AF |
472 | static RISCVException read_zero(CPURISCVState *env, int csrno, |
473 | target_ulong *val) | |
c7b95171 | 474 | { |
605def6e AF |
475 | *val = 0; |
476 | return RISCV_EXCP_NONE; | |
c7b95171 MC |
477 | } |
478 | ||
605def6e AF |
479 | static RISCVException read_mhartid(CPURISCVState *env, int csrno, |
480 | target_ulong *val) | |
c7b95171 MC |
481 | { |
482 | *val = env->mhartid; | |
605def6e | 483 | return RISCV_EXCP_NONE; |
c7b95171 MC |
484 | } |
485 | ||
486 | /* Machine Trap Setup */ | |
605def6e AF |
487 | static RISCVException read_mstatus(CPURISCVState *env, int csrno, |
488 | target_ulong *val) | |
c7b95171 MC |
489 | { |
490 | *val = env->mstatus; | |
605def6e | 491 | return RISCV_EXCP_NONE; |
c7b95171 MC |
492 | } |
493 | ||
494 | static int validate_vm(CPURISCVState *env, target_ulong vm) | |
495 | { | |
8987cdc4 AF |
496 | if (riscv_cpu_is_32bit(env)) { |
497 | return valid_vm_1_10_32[vm & 0xf]; | |
498 | } else { | |
499 | return valid_vm_1_10_64[vm & 0xf]; | |
500 | } | |
c7b95171 MC |
501 | } |
502 | ||
605def6e AF |
503 | static RISCVException write_mstatus(CPURISCVState *env, int csrno, |
504 | target_ulong val) | |
c7b95171 | 505 | { |
284d697c YJ |
506 | uint64_t mstatus = env->mstatus; |
507 | uint64_t mask = 0; | |
b345b480 | 508 | int dirty; |
c7b95171 MC |
509 | |
510 | /* flush tlb on mstatus fields that affect VM */ | |
1a9540d1 AF |
511 | if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | |
512 | MSTATUS_MPRV | MSTATUS_SUM)) { | |
513 | tlb_flush(env_cpu(env)); | |
c7b95171 | 514 | } |
1a9540d1 AF |
515 | mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | |
516 | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | | |
517 | MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | | |
518 | MSTATUS_TW; | |
8987cdc4 AF |
519 | |
520 | if (!riscv_cpu_is_32bit(env)) { | |
521 | /* | |
522 | * RV32: MPV and GVA are not in mstatus. The current plan is to | |
523 | * add them to mstatush. For now, we just don't support it. | |
524 | */ | |
525 | mask |= MSTATUS_MPV | MSTATUS_GVA; | |
526 | } | |
c7b95171 MC |
527 | |
528 | mstatus = (mstatus & ~mask) | (val & mask); | |
529 | ||
82f01467 | 530 | dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) | |
b345b480 | 531 | ((mstatus & MSTATUS_XS) == MSTATUS_XS); |
c7b95171 MC |
532 | mstatus = set_field(mstatus, MSTATUS_SD, dirty); |
533 | env->mstatus = mstatus; | |
534 | ||
605def6e | 535 | return RISCV_EXCP_NONE; |
c7b95171 MC |
536 | } |
537 | ||
605def6e AF |
538 | static RISCVException read_mstatush(CPURISCVState *env, int csrno, |
539 | target_ulong *val) | |
551fa7e8 | 540 | { |
284d697c | 541 | *val = env->mstatus >> 32; |
605def6e | 542 | return RISCV_EXCP_NONE; |
551fa7e8 AF |
543 | } |
544 | ||
605def6e AF |
545 | static RISCVException write_mstatush(CPURISCVState *env, int csrno, |
546 | target_ulong val) | |
551fa7e8 | 547 | { |
284d697c YJ |
548 | uint64_t valh = (uint64_t)val << 32; |
549 | uint64_t mask = MSTATUS_MPV | MSTATUS_GVA; | |
550 | ||
551 | if ((valh ^ env->mstatus) & (MSTATUS_MPV)) { | |
551fa7e8 AF |
552 | tlb_flush(env_cpu(env)); |
553 | } | |
554 | ||
284d697c | 555 | env->mstatus = (env->mstatus & ~mask) | (valh & mask); |
551fa7e8 | 556 | |
605def6e | 557 | return RISCV_EXCP_NONE; |
551fa7e8 | 558 | } |
551fa7e8 | 559 | |
605def6e AF |
560 | static RISCVException read_misa(CPURISCVState *env, int csrno, |
561 | target_ulong *val) | |
c7b95171 MC |
562 | { |
563 | *val = env->misa; | |
605def6e | 564 | return RISCV_EXCP_NONE; |
c7b95171 MC |
565 | } |
566 | ||
605def6e AF |
567 | static RISCVException write_misa(CPURISCVState *env, int csrno, |
568 | target_ulong val) | |
f18637cd MC |
569 | { |
570 | if (!riscv_feature(env, RISCV_FEATURE_MISA)) { | |
571 | /* drop write to misa */ | |
605def6e | 572 | return RISCV_EXCP_NONE; |
f18637cd MC |
573 | } |
574 | ||
575 | /* 'I' or 'E' must be present */ | |
576 | if (!(val & (RVI | RVE))) { | |
577 | /* It is not, drop write to misa */ | |
605def6e | 578 | return RISCV_EXCP_NONE; |
f18637cd MC |
579 | } |
580 | ||
581 | /* 'E' excludes all other extensions */ | |
582 | if (val & RVE) { | |
583 | /* when we support 'E' we can do "val = RVE;" however | |
584 | * for now we just drop writes if 'E' is present. | |
585 | */ | |
605def6e | 586 | return RISCV_EXCP_NONE; |
f18637cd MC |
587 | } |
588 | ||
589 | /* Mask extensions that are not supported by this hart */ | |
590 | val &= env->misa_mask; | |
591 | ||
592 | /* Mask extensions that are not supported by QEMU */ | |
593 | val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU); | |
594 | ||
595 | /* 'D' depends on 'F', so clear 'D' if 'F' is not present */ | |
596 | if ((val & RVD) && !(val & RVF)) { | |
597 | val &= ~RVD; | |
598 | } | |
599 | ||
600 | /* Suppress 'C' if next instruction is not aligned | |
601 | * TODO: this should check next_pc | |
602 | */ | |
603 | if ((val & RVC) && (GETPC() & ~3) != 0) { | |
604 | val &= ~RVC; | |
605 | } | |
606 | ||
607 | /* misa.MXL writes are not supported by QEMU */ | |
608 | val = (env->misa & MISA_MXL) | (val & ~MISA_MXL); | |
609 | ||
610 | /* flush translation cache */ | |
611 | if (val != env->misa) { | |
3109cd98 | 612 | tb_flush(env_cpu(env)); |
f18637cd MC |
613 | } |
614 | ||
615 | env->misa = val; | |
616 | ||
605def6e | 617 | return RISCV_EXCP_NONE; |
f18637cd MC |
618 | } |
619 | ||
605def6e AF |
620 | static RISCVException read_medeleg(CPURISCVState *env, int csrno, |
621 | target_ulong *val) | |
c7b95171 MC |
622 | { |
623 | *val = env->medeleg; | |
605def6e | 624 | return RISCV_EXCP_NONE; |
c7b95171 MC |
625 | } |
626 | ||
605def6e AF |
627 | static RISCVException write_medeleg(CPURISCVState *env, int csrno, |
628 | target_ulong val) | |
c7b95171 MC |
629 | { |
630 | env->medeleg = (env->medeleg & ~delegable_excps) | (val & delegable_excps); | |
605def6e | 631 | return RISCV_EXCP_NONE; |
c7b95171 MC |
632 | } |
633 | ||
605def6e AF |
634 | static RISCVException read_mideleg(CPURISCVState *env, int csrno, |
635 | target_ulong *val) | |
c7b95171 MC |
636 | { |
637 | *val = env->mideleg; | |
605def6e | 638 | return RISCV_EXCP_NONE; |
c7b95171 MC |
639 | } |
640 | ||
605def6e AF |
641 | static RISCVException write_mideleg(CPURISCVState *env, int csrno, |
642 | target_ulong val) | |
c7b95171 MC |
643 | { |
644 | env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints); | |
713d8363 AF |
645 | if (riscv_has_ext(env, RVH)) { |
646 | env->mideleg |= VS_MODE_INTERRUPTS; | |
647 | } | |
605def6e | 648 | return RISCV_EXCP_NONE; |
c7b95171 MC |
649 | } |
650 | ||
605def6e AF |
651 | static RISCVException read_mie(CPURISCVState *env, int csrno, |
652 | target_ulong *val) | |
c7b95171 MC |
653 | { |
654 | *val = env->mie; | |
605def6e | 655 | return RISCV_EXCP_NONE; |
c7b95171 MC |
656 | } |
657 | ||
605def6e AF |
658 | static RISCVException write_mie(CPURISCVState *env, int csrno, |
659 | target_ulong val) | |
c7b95171 MC |
660 | { |
661 | env->mie = (env->mie & ~all_ints) | (val & all_ints); | |
605def6e | 662 | return RISCV_EXCP_NONE; |
c7b95171 MC |
663 | } |
664 | ||
605def6e AF |
665 | static RISCVException read_mtvec(CPURISCVState *env, int csrno, |
666 | target_ulong *val) | |
c7b95171 MC |
667 | { |
668 | *val = env->mtvec; | |
605def6e | 669 | return RISCV_EXCP_NONE; |
c7b95171 MC |
670 | } |
671 | ||
605def6e AF |
672 | static RISCVException write_mtvec(CPURISCVState *env, int csrno, |
673 | target_ulong val) | |
c7b95171 MC |
674 | { |
675 | /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ | |
acbbb94e MC |
676 | if ((val & 3) < 2) { |
677 | env->mtvec = val; | |
c7b95171 | 678 | } else { |
acbbb94e | 679 | qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n"); |
c7b95171 | 680 | } |
605def6e | 681 | return RISCV_EXCP_NONE; |
c7b95171 MC |
682 | } |
683 | ||
605def6e AF |
684 | static RISCVException read_mcounteren(CPURISCVState *env, int csrno, |
685 | target_ulong *val) | |
c7b95171 | 686 | { |
c7b95171 | 687 | *val = env->mcounteren; |
605def6e | 688 | return RISCV_EXCP_NONE; |
c7b95171 MC |
689 | } |
690 | ||
605def6e AF |
691 | static RISCVException write_mcounteren(CPURISCVState *env, int csrno, |
692 | target_ulong val) | |
c7b95171 | 693 | { |
c7b95171 | 694 | env->mcounteren = val; |
605def6e | 695 | return RISCV_EXCP_NONE; |
c7b95171 MC |
696 | } |
697 | ||
c7b95171 | 698 | /* Machine Trap Handling */ |
605def6e AF |
699 | static RISCVException read_mscratch(CPURISCVState *env, int csrno, |
700 | target_ulong *val) | |
c7b95171 MC |
701 | { |
702 | *val = env->mscratch; | |
605def6e | 703 | return RISCV_EXCP_NONE; |
c7b95171 MC |
704 | } |
705 | ||
605def6e AF |
706 | static RISCVException write_mscratch(CPURISCVState *env, int csrno, |
707 | target_ulong val) | |
c7b95171 MC |
708 | { |
709 | env->mscratch = val; | |
605def6e | 710 | return RISCV_EXCP_NONE; |
c7b95171 MC |
711 | } |
712 | ||
605def6e AF |
713 | static RISCVException read_mepc(CPURISCVState *env, int csrno, |
714 | target_ulong *val) | |
c7b95171 MC |
715 | { |
716 | *val = env->mepc; | |
605def6e | 717 | return RISCV_EXCP_NONE; |
c7b95171 MC |
718 | } |
719 | ||
605def6e AF |
720 | static RISCVException write_mepc(CPURISCVState *env, int csrno, |
721 | target_ulong val) | |
c7b95171 MC |
722 | { |
723 | env->mepc = val; | |
605def6e | 724 | return RISCV_EXCP_NONE; |
c7b95171 MC |
725 | } |
726 | ||
605def6e AF |
727 | static RISCVException read_mcause(CPURISCVState *env, int csrno, |
728 | target_ulong *val) | |
c7b95171 MC |
729 | { |
730 | *val = env->mcause; | |
605def6e | 731 | return RISCV_EXCP_NONE; |
c7b95171 MC |
732 | } |
733 | ||
605def6e AF |
734 | static RISCVException write_mcause(CPURISCVState *env, int csrno, |
735 | target_ulong val) | |
c7b95171 MC |
736 | { |
737 | env->mcause = val; | |
605def6e | 738 | return RISCV_EXCP_NONE; |
c7b95171 MC |
739 | } |
740 | ||
605def6e AF |
741 | static RISCVException read_mtval(CPURISCVState *env, int csrno, |
742 | target_ulong *val) | |
c7b95171 | 743 | { |
ac12b601 | 744 | *val = env->mtval; |
605def6e | 745 | return RISCV_EXCP_NONE; |
c7b95171 MC |
746 | } |
747 | ||
605def6e AF |
748 | static RISCVException write_mtval(CPURISCVState *env, int csrno, |
749 | target_ulong val) | |
c7b95171 | 750 | { |
ac12b601 | 751 | env->mtval = val; |
605def6e | 752 | return RISCV_EXCP_NONE; |
c7b95171 MC |
753 | } |
754 | ||
605def6e AF |
755 | static RISCVException rmw_mip(CPURISCVState *env, int csrno, |
756 | target_ulong *ret_value, | |
757 | target_ulong new_value, target_ulong write_mask) | |
c7b95171 | 758 | { |
3109cd98 | 759 | RISCVCPU *cpu = env_archcpu(env); |
e3e7039c MC |
760 | /* Allow software control of delegable interrupts not claimed by hardware */ |
761 | target_ulong mask = write_mask & delegable_ints & ~env->miclaim; | |
71877e29 MC |
762 | uint32_t old_mip; |
763 | ||
71877e29 | 764 | if (mask) { |
71877e29 | 765 | old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask)); |
71877e29 | 766 | } else { |
7ec5d303 | 767 | old_mip = env->mip; |
71877e29 | 768 | } |
c7b95171 | 769 | |
71877e29 MC |
770 | if (ret_value) { |
771 | *ret_value = old_mip; | |
772 | } | |
c7b95171 | 773 | |
605def6e | 774 | return RISCV_EXCP_NONE; |
c7b95171 MC |
775 | } |
776 | ||
777 | /* Supervisor Trap Setup */ | |
605def6e AF |
778 | static RISCVException read_sstatus(CPURISCVState *env, int csrno, |
779 | target_ulong *val) | |
c7b95171 | 780 | { |
1a9540d1 | 781 | target_ulong mask = (sstatus_v1_10_mask); |
c7b95171 | 782 | *val = env->mstatus & mask; |
605def6e | 783 | return RISCV_EXCP_NONE; |
c7b95171 MC |
784 | } |
785 | ||
605def6e AF |
786 | static RISCVException write_sstatus(CPURISCVState *env, int csrno, |
787 | target_ulong val) | |
c7b95171 | 788 | { |
1a9540d1 | 789 | target_ulong mask = (sstatus_v1_10_mask); |
c7b95171 MC |
790 | target_ulong newval = (env->mstatus & ~mask) | (val & mask); |
791 | return write_mstatus(env, CSR_MSTATUS, newval); | |
792 | } | |
793 | ||
605def6e AF |
794 | static RISCVException read_vsie(CPURISCVState *env, int csrno, |
795 | target_ulong *val) | |
9d5451e0 GK |
796 | { |
797 | /* Shift the VS bits to their S bit location in vsie */ | |
798 | *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1; | |
605def6e | 799 | return RISCV_EXCP_NONE; |
9d5451e0 GK |
800 | } |
801 | ||
605def6e AF |
802 | static RISCVException read_sie(CPURISCVState *env, int csrno, |
803 | target_ulong *val) | |
c7b95171 | 804 | { |
d0e53ce3 | 805 | if (riscv_cpu_virt_enabled(env)) { |
9d5451e0 | 806 | read_vsie(env, CSR_VSIE, val); |
d0e53ce3 AF |
807 | } else { |
808 | *val = env->mie & env->mideleg; | |
809 | } | |
605def6e | 810 | return RISCV_EXCP_NONE; |
c7b95171 MC |
811 | } |
812 | ||
605def6e AF |
813 | static RISCVException write_vsie(CPURISCVState *env, int csrno, |
814 | target_ulong val) | |
c7b95171 | 815 | { |
9d5451e0 GK |
816 | /* Shift the S bits to their VS bit location in mie */ |
817 | target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | | |
818 | ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS); | |
819 | return write_mie(env, CSR_MIE, newval); | |
820 | } | |
d0e53ce3 | 821 | |
9d5451e0 GK |
822 | static int write_sie(CPURISCVState *env, int csrno, target_ulong val) |
823 | { | |
d0e53ce3 | 824 | if (riscv_cpu_virt_enabled(env)) { |
9d5451e0 | 825 | write_vsie(env, CSR_VSIE, val); |
d0e53ce3 | 826 | } else { |
9d5451e0 GK |
827 | target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) | |
828 | (val & S_MODE_INTERRUPTS); | |
829 | write_mie(env, CSR_MIE, newval); | |
d0e53ce3 AF |
830 | } |
831 | ||
605def6e | 832 | return RISCV_EXCP_NONE; |
c7b95171 MC |
833 | } |
834 | ||
605def6e AF |
835 | static RISCVException read_stvec(CPURISCVState *env, int csrno, |
836 | target_ulong *val) | |
c7b95171 MC |
837 | { |
838 | *val = env->stvec; | |
605def6e | 839 | return RISCV_EXCP_NONE; |
c7b95171 MC |
840 | } |
841 | ||
605def6e AF |
842 | static RISCVException write_stvec(CPURISCVState *env, int csrno, |
843 | target_ulong val) | |
c7b95171 MC |
844 | { |
845 | /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ | |
acbbb94e MC |
846 | if ((val & 3) < 2) { |
847 | env->stvec = val; | |
c7b95171 | 848 | } else { |
acbbb94e | 849 | qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n"); |
c7b95171 | 850 | } |
605def6e | 851 | return RISCV_EXCP_NONE; |
c7b95171 MC |
852 | } |
853 | ||
605def6e AF |
854 | static RISCVException read_scounteren(CPURISCVState *env, int csrno, |
855 | target_ulong *val) | |
c7b95171 | 856 | { |
c7b95171 | 857 | *val = env->scounteren; |
605def6e | 858 | return RISCV_EXCP_NONE; |
c7b95171 MC |
859 | } |
860 | ||
605def6e AF |
861 | static RISCVException write_scounteren(CPURISCVState *env, int csrno, |
862 | target_ulong val) | |
c7b95171 | 863 | { |
c7b95171 | 864 | env->scounteren = val; |
605def6e | 865 | return RISCV_EXCP_NONE; |
c7b95171 MC |
866 | } |
867 | ||
868 | /* Supervisor Trap Handling */ | |
605def6e AF |
869 | static RISCVException read_sscratch(CPURISCVState *env, int csrno, |
870 | target_ulong *val) | |
c7b95171 MC |
871 | { |
872 | *val = env->sscratch; | |
605def6e | 873 | return RISCV_EXCP_NONE; |
c7b95171 MC |
874 | } |
875 | ||
605def6e AF |
876 | static RISCVException write_sscratch(CPURISCVState *env, int csrno, |
877 | target_ulong val) | |
c7b95171 MC |
878 | { |
879 | env->sscratch = val; | |
605def6e | 880 | return RISCV_EXCP_NONE; |
c7b95171 MC |
881 | } |
882 | ||
605def6e AF |
883 | static RISCVException read_sepc(CPURISCVState *env, int csrno, |
884 | target_ulong *val) | |
c7b95171 MC |
885 | { |
886 | *val = env->sepc; | |
605def6e | 887 | return RISCV_EXCP_NONE; |
c7b95171 MC |
888 | } |
889 | ||
605def6e AF |
890 | static RISCVException write_sepc(CPURISCVState *env, int csrno, |
891 | target_ulong val) | |
c7b95171 MC |
892 | { |
893 | env->sepc = val; | |
605def6e | 894 | return RISCV_EXCP_NONE; |
c7b95171 MC |
895 | } |
896 | ||
605def6e AF |
897 | static RISCVException read_scause(CPURISCVState *env, int csrno, |
898 | target_ulong *val) | |
c7b95171 MC |
899 | { |
900 | *val = env->scause; | |
605def6e | 901 | return RISCV_EXCP_NONE; |
c7b95171 MC |
902 | } |
903 | ||
605def6e AF |
904 | static RISCVException write_scause(CPURISCVState *env, int csrno, |
905 | target_ulong val) | |
c7b95171 MC |
906 | { |
907 | env->scause = val; | |
605def6e | 908 | return RISCV_EXCP_NONE; |
c7b95171 MC |
909 | } |
910 | ||
605def6e AF |
911 | static RISCVException read_stval(CPURISCVState *env, int csrno, |
912 | target_ulong *val) | |
c7b95171 | 913 | { |
ac12b601 | 914 | *val = env->stval; |
605def6e | 915 | return RISCV_EXCP_NONE; |
c7b95171 MC |
916 | } |
917 | ||
605def6e AF |
918 | static RISCVException write_stval(CPURISCVState *env, int csrno, |
919 | target_ulong val) | |
c7b95171 | 920 | { |
ac12b601 | 921 | env->stval = val; |
605def6e | 922 | return RISCV_EXCP_NONE; |
c7b95171 MC |
923 | } |
924 | ||
605def6e AF |
925 | static RISCVException rmw_vsip(CPURISCVState *env, int csrno, |
926 | target_ulong *ret_value, | |
927 | target_ulong new_value, target_ulong write_mask) | |
9d5451e0 GK |
928 | { |
929 | /* Shift the S bits to their VS bit location in mip */ | |
930 | int ret = rmw_mip(env, 0, ret_value, new_value << 1, | |
931 | (write_mask << 1) & vsip_writable_mask & env->hideleg); | |
932 | *ret_value &= VS_MODE_INTERRUPTS; | |
933 | /* Shift the VS bits to their S bit location in vsip */ | |
934 | *ret_value >>= 1; | |
935 | return ret; | |
936 | } | |
937 | ||
605def6e AF |
938 | static RISCVException rmw_sip(CPURISCVState *env, int csrno, |
939 | target_ulong *ret_value, | |
940 | target_ulong new_value, target_ulong write_mask) | |
c7b95171 | 941 | { |
a2e9f57d AF |
942 | int ret; |
943 | ||
944 | if (riscv_cpu_virt_enabled(env)) { | |
9d5451e0 | 945 | ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask); |
a2e9f57d AF |
946 | } else { |
947 | ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value, | |
087b051a | 948 | write_mask & env->mideleg & sip_writable_mask); |
a2e9f57d AF |
949 | } |
950 | ||
087b051a JB |
951 | *ret_value &= env->mideleg; |
952 | return ret; | |
c7b95171 MC |
953 | } |
954 | ||
955 | /* Supervisor Protection and Translation */ | |
605def6e AF |
956 | static RISCVException read_satp(CPURISCVState *env, int csrno, |
957 | target_ulong *val) | |
c7b95171 MC |
958 | { |
959 | if (!riscv_feature(env, RISCV_FEATURE_MMU)) { | |
960 | *val = 0; | |
605def6e | 961 | return RISCV_EXCP_NONE; |
1a9540d1 AF |
962 | } |
963 | ||
964 | if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { | |
605def6e | 965 | return RISCV_EXCP_ILLEGAL_INST; |
c7b95171 | 966 | } else { |
1a9540d1 | 967 | *val = env->satp; |
c7b95171 | 968 | } |
1a9540d1 | 969 | |
605def6e | 970 | return RISCV_EXCP_NONE; |
c7b95171 MC |
971 | } |
972 | ||
605def6e AF |
973 | static RISCVException write_satp(CPURISCVState *env, int csrno, |
974 | target_ulong val) | |
c7b95171 MC |
975 | { |
976 | if (!riscv_feature(env, RISCV_FEATURE_MMU)) { | |
605def6e | 977 | return RISCV_EXCP_NONE; |
c7b95171 | 978 | } |
1a9540d1 | 979 | if (validate_vm(env, get_field(val, SATP_MODE)) && |
c7b95171 MC |
980 | ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN))) |
981 | { | |
7f2b5ff1 | 982 | if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { |
605def6e | 983 | return RISCV_EXCP_ILLEGAL_INST; |
7f2b5ff1 | 984 | } else { |
42281977 | 985 | if ((val ^ env->satp) & SATP_ASID) { |
3109cd98 | 986 | tlb_flush(env_cpu(env)); |
1e0d985f | 987 | } |
7f2b5ff1 MC |
988 | env->satp = val; |
989 | } | |
c7b95171 | 990 | } |
605def6e | 991 | return RISCV_EXCP_NONE; |
c7b95171 MC |
992 | } |
993 | ||
ff2cc129 | 994 | /* Hypervisor Extensions */ |
605def6e AF |
995 | static RISCVException read_hstatus(CPURISCVState *env, int csrno, |
996 | target_ulong *val) | |
ff2cc129 AF |
997 | { |
998 | *val = env->hstatus; | |
8987cdc4 AF |
999 | if (!riscv_cpu_is_32bit(env)) { |
1000 | /* We only support 64-bit VSXL */ | |
1001 | *val = set_field(*val, HSTATUS_VSXL, 2); | |
1002 | } | |
30f663b1 AF |
1003 | /* We only support little endian */ |
1004 | *val = set_field(*val, HSTATUS_VSBE, 0); | |
605def6e | 1005 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1006 | } |
1007 | ||
605def6e AF |
1008 | static RISCVException write_hstatus(CPURISCVState *env, int csrno, |
1009 | target_ulong val) | |
ff2cc129 AF |
1010 | { |
1011 | env->hstatus = val; | |
8987cdc4 | 1012 | if (!riscv_cpu_is_32bit(env) && get_field(val, HSTATUS_VSXL) != 2) { |
f8dc878e AF |
1013 | qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options."); |
1014 | } | |
30f663b1 AF |
1015 | if (get_field(val, HSTATUS_VSBE) != 0) { |
1016 | qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests."); | |
1017 | } | |
605def6e | 1018 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1019 | } |
1020 | ||
605def6e AF |
1021 | static RISCVException read_hedeleg(CPURISCVState *env, int csrno, |
1022 | target_ulong *val) | |
ff2cc129 AF |
1023 | { |
1024 | *val = env->hedeleg; | |
605def6e | 1025 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1026 | } |
1027 | ||
605def6e AF |
1028 | static RISCVException write_hedeleg(CPURISCVState *env, int csrno, |
1029 | target_ulong val) | |
ff2cc129 AF |
1030 | { |
1031 | env->hedeleg = val; | |
605def6e | 1032 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1033 | } |
1034 | ||
605def6e AF |
1035 | static RISCVException read_hideleg(CPURISCVState *env, int csrno, |
1036 | target_ulong *val) | |
ff2cc129 AF |
1037 | { |
1038 | *val = env->hideleg; | |
605def6e | 1039 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1040 | } |
1041 | ||
605def6e AF |
1042 | static RISCVException write_hideleg(CPURISCVState *env, int csrno, |
1043 | target_ulong val) | |
ff2cc129 AF |
1044 | { |
1045 | env->hideleg = val; | |
605def6e | 1046 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1047 | } |
1048 | ||
605def6e AF |
1049 | static RISCVException rmw_hvip(CPURISCVState *env, int csrno, |
1050 | target_ulong *ret_value, | |
1051 | target_ulong new_value, target_ulong write_mask) | |
83028098 AF |
1052 | { |
1053 | int ret = rmw_mip(env, 0, ret_value, new_value, | |
e89b631c | 1054 | write_mask & hvip_writable_mask); |
83028098 | 1055 | |
e89b631c | 1056 | *ret_value &= hvip_writable_mask; |
83028098 AF |
1057 | |
1058 | return ret; | |
1059 | } | |
1060 | ||
605def6e AF |
1061 | static RISCVException rmw_hip(CPURISCVState *env, int csrno, |
1062 | target_ulong *ret_value, | |
1063 | target_ulong new_value, target_ulong write_mask) | |
ff2cc129 AF |
1064 | { |
1065 | int ret = rmw_mip(env, 0, ret_value, new_value, | |
1066 | write_mask & hip_writable_mask); | |
1067 | ||
83028098 AF |
1068 | *ret_value &= hip_writable_mask; |
1069 | ||
ff2cc129 AF |
1070 | return ret; |
1071 | } | |
1072 | ||
605def6e AF |
1073 | static RISCVException read_hie(CPURISCVState *env, int csrno, |
1074 | target_ulong *val) | |
ff2cc129 AF |
1075 | { |
1076 | *val = env->mie & VS_MODE_INTERRUPTS; | |
605def6e | 1077 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1078 | } |
1079 | ||
605def6e AF |
1080 | static RISCVException write_hie(CPURISCVState *env, int csrno, |
1081 | target_ulong val) | |
ff2cc129 AF |
1082 | { |
1083 | target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS); | |
1084 | return write_mie(env, CSR_MIE, newval); | |
1085 | } | |
1086 | ||
605def6e AF |
1087 | static RISCVException read_hcounteren(CPURISCVState *env, int csrno, |
1088 | target_ulong *val) | |
ff2cc129 AF |
1089 | { |
1090 | *val = env->hcounteren; | |
605def6e | 1091 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1092 | } |
1093 | ||
605def6e AF |
1094 | static RISCVException write_hcounteren(CPURISCVState *env, int csrno, |
1095 | target_ulong val) | |
ff2cc129 AF |
1096 | { |
1097 | env->hcounteren = val; | |
605def6e | 1098 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1099 | } |
1100 | ||
605def6e AF |
1101 | static RISCVException read_hgeie(CPURISCVState *env, int csrno, |
1102 | target_ulong *val) | |
83028098 AF |
1103 | { |
1104 | qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); | |
605def6e | 1105 | return RISCV_EXCP_NONE; |
83028098 AF |
1106 | } |
1107 | ||
605def6e AF |
1108 | static RISCVException write_hgeie(CPURISCVState *env, int csrno, |
1109 | target_ulong val) | |
83028098 AF |
1110 | { |
1111 | qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); | |
605def6e | 1112 | return RISCV_EXCP_NONE; |
83028098 AF |
1113 | } |
1114 | ||
605def6e AF |
1115 | static RISCVException read_htval(CPURISCVState *env, int csrno, |
1116 | target_ulong *val) | |
ff2cc129 AF |
1117 | { |
1118 | *val = env->htval; | |
605def6e | 1119 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1120 | } |
1121 | ||
605def6e AF |
1122 | static RISCVException write_htval(CPURISCVState *env, int csrno, |
1123 | target_ulong val) | |
ff2cc129 AF |
1124 | { |
1125 | env->htval = val; | |
605def6e | 1126 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1127 | } |
1128 | ||
605def6e AF |
1129 | static RISCVException read_htinst(CPURISCVState *env, int csrno, |
1130 | target_ulong *val) | |
ff2cc129 AF |
1131 | { |
1132 | *val = env->htinst; | |
605def6e | 1133 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1134 | } |
1135 | ||
605def6e AF |
1136 | static RISCVException write_htinst(CPURISCVState *env, int csrno, |
1137 | target_ulong val) | |
ff2cc129 | 1138 | { |
605def6e | 1139 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1140 | } |
1141 | ||
605def6e AF |
1142 | static RISCVException read_hgeip(CPURISCVState *env, int csrno, |
1143 | target_ulong *val) | |
83028098 AF |
1144 | { |
1145 | qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); | |
605def6e | 1146 | return RISCV_EXCP_NONE; |
83028098 AF |
1147 | } |
1148 | ||
605def6e AF |
1149 | static RISCVException write_hgeip(CPURISCVState *env, int csrno, |
1150 | target_ulong val) | |
83028098 AF |
1151 | { |
1152 | qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); | |
605def6e | 1153 | return RISCV_EXCP_NONE; |
83028098 AF |
1154 | } |
1155 | ||
605def6e AF |
1156 | static RISCVException read_hgatp(CPURISCVState *env, int csrno, |
1157 | target_ulong *val) | |
ff2cc129 AF |
1158 | { |
1159 | *val = env->hgatp; | |
605def6e | 1160 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1161 | } |
1162 | ||
605def6e AF |
1163 | static RISCVException write_hgatp(CPURISCVState *env, int csrno, |
1164 | target_ulong val) | |
ff2cc129 AF |
1165 | { |
1166 | env->hgatp = val; | |
605def6e | 1167 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1168 | } |
1169 | ||
605def6e AF |
1170 | static RISCVException read_htimedelta(CPURISCVState *env, int csrno, |
1171 | target_ulong *val) | |
c6957248 AP |
1172 | { |
1173 | if (!env->rdtime_fn) { | |
605def6e | 1174 | return RISCV_EXCP_ILLEGAL_INST; |
c6957248 AP |
1175 | } |
1176 | ||
c6957248 | 1177 | *val = env->htimedelta; |
605def6e | 1178 | return RISCV_EXCP_NONE; |
c6957248 AP |
1179 | } |
1180 | ||
605def6e AF |
1181 | static RISCVException write_htimedelta(CPURISCVState *env, int csrno, |
1182 | target_ulong val) | |
c6957248 AP |
1183 | { |
1184 | if (!env->rdtime_fn) { | |
605def6e | 1185 | return RISCV_EXCP_ILLEGAL_INST; |
c6957248 AP |
1186 | } |
1187 | ||
8987cdc4 AF |
1188 | if (riscv_cpu_is_32bit(env)) { |
1189 | env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val); | |
1190 | } else { | |
1191 | env->htimedelta = val; | |
1192 | } | |
605def6e | 1193 | return RISCV_EXCP_NONE; |
c6957248 AP |
1194 | } |
1195 | ||
605def6e AF |
1196 | static RISCVException read_htimedeltah(CPURISCVState *env, int csrno, |
1197 | target_ulong *val) | |
c6957248 AP |
1198 | { |
1199 | if (!env->rdtime_fn) { | |
605def6e | 1200 | return RISCV_EXCP_ILLEGAL_INST; |
c6957248 AP |
1201 | } |
1202 | ||
1203 | *val = env->htimedelta >> 32; | |
605def6e | 1204 | return RISCV_EXCP_NONE; |
c6957248 AP |
1205 | } |
1206 | ||
605def6e AF |
1207 | static RISCVException write_htimedeltah(CPURISCVState *env, int csrno, |
1208 | target_ulong val) | |
c6957248 AP |
1209 | { |
1210 | if (!env->rdtime_fn) { | |
605def6e | 1211 | return RISCV_EXCP_ILLEGAL_INST; |
c6957248 AP |
1212 | } |
1213 | ||
1214 | env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val); | |
605def6e | 1215 | return RISCV_EXCP_NONE; |
c6957248 | 1216 | } |
c6957248 | 1217 | |
8747c9ee | 1218 | /* Virtual CSR Registers */ |
605def6e AF |
1219 | static RISCVException read_vsstatus(CPURISCVState *env, int csrno, |
1220 | target_ulong *val) | |
8747c9ee AF |
1221 | { |
1222 | *val = env->vsstatus; | |
605def6e | 1223 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1224 | } |
1225 | ||
605def6e AF |
1226 | static RISCVException write_vsstatus(CPURISCVState *env, int csrno, |
1227 | target_ulong val) | |
8747c9ee | 1228 | { |
284d697c YJ |
1229 | uint64_t mask = (target_ulong)-1; |
1230 | env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val; | |
605def6e | 1231 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1232 | } |
1233 | ||
8747c9ee AF |
1234 | static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val) |
1235 | { | |
1236 | *val = env->vstvec; | |
605def6e | 1237 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1238 | } |
1239 | ||
605def6e AF |
1240 | static RISCVException write_vstvec(CPURISCVState *env, int csrno, |
1241 | target_ulong val) | |
8747c9ee AF |
1242 | { |
1243 | env->vstvec = val; | |
605def6e | 1244 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1245 | } |
1246 | ||
605def6e AF |
1247 | static RISCVException read_vsscratch(CPURISCVState *env, int csrno, |
1248 | target_ulong *val) | |
8747c9ee AF |
1249 | { |
1250 | *val = env->vsscratch; | |
605def6e | 1251 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1252 | } |
1253 | ||
605def6e AF |
1254 | static RISCVException write_vsscratch(CPURISCVState *env, int csrno, |
1255 | target_ulong val) | |
8747c9ee AF |
1256 | { |
1257 | env->vsscratch = val; | |
605def6e | 1258 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1259 | } |
1260 | ||
605def6e AF |
1261 | static RISCVException read_vsepc(CPURISCVState *env, int csrno, |
1262 | target_ulong *val) | |
8747c9ee AF |
1263 | { |
1264 | *val = env->vsepc; | |
605def6e | 1265 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1266 | } |
1267 | ||
605def6e AF |
1268 | static RISCVException write_vsepc(CPURISCVState *env, int csrno, |
1269 | target_ulong val) | |
8747c9ee AF |
1270 | { |
1271 | env->vsepc = val; | |
605def6e | 1272 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1273 | } |
1274 | ||
605def6e AF |
1275 | static RISCVException read_vscause(CPURISCVState *env, int csrno, |
1276 | target_ulong *val) | |
8747c9ee AF |
1277 | { |
1278 | *val = env->vscause; | |
605def6e | 1279 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1280 | } |
1281 | ||
605def6e AF |
1282 | static RISCVException write_vscause(CPURISCVState *env, int csrno, |
1283 | target_ulong val) | |
8747c9ee AF |
1284 | { |
1285 | env->vscause = val; | |
605def6e | 1286 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1287 | } |
1288 | ||
605def6e AF |
1289 | static RISCVException read_vstval(CPURISCVState *env, int csrno, |
1290 | target_ulong *val) | |
8747c9ee AF |
1291 | { |
1292 | *val = env->vstval; | |
605def6e | 1293 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1294 | } |
1295 | ||
605def6e AF |
1296 | static RISCVException write_vstval(CPURISCVState *env, int csrno, |
1297 | target_ulong val) | |
8747c9ee AF |
1298 | { |
1299 | env->vstval = val; | |
605def6e | 1300 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1301 | } |
1302 | ||
605def6e AF |
1303 | static RISCVException read_vsatp(CPURISCVState *env, int csrno, |
1304 | target_ulong *val) | |
8747c9ee AF |
1305 | { |
1306 | *val = env->vsatp; | |
605def6e | 1307 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1308 | } |
1309 | ||
605def6e AF |
1310 | static RISCVException write_vsatp(CPURISCVState *env, int csrno, |
1311 | target_ulong val) | |
8747c9ee AF |
1312 | { |
1313 | env->vsatp = val; | |
605def6e | 1314 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1315 | } |
1316 | ||
605def6e AF |
1317 | static RISCVException read_mtval2(CPURISCVState *env, int csrno, |
1318 | target_ulong *val) | |
34cfb5f6 AF |
1319 | { |
1320 | *val = env->mtval2; | |
605def6e | 1321 | return RISCV_EXCP_NONE; |
34cfb5f6 AF |
1322 | } |
1323 | ||
605def6e AF |
1324 | static RISCVException write_mtval2(CPURISCVState *env, int csrno, |
1325 | target_ulong val) | |
34cfb5f6 AF |
1326 | { |
1327 | env->mtval2 = val; | |
605def6e | 1328 | return RISCV_EXCP_NONE; |
34cfb5f6 AF |
1329 | } |
1330 | ||
605def6e AF |
1331 | static RISCVException read_mtinst(CPURISCVState *env, int csrno, |
1332 | target_ulong *val) | |
34cfb5f6 AF |
1333 | { |
1334 | *val = env->mtinst; | |
605def6e | 1335 | return RISCV_EXCP_NONE; |
34cfb5f6 AF |
1336 | } |
1337 | ||
605def6e AF |
1338 | static RISCVException write_mtinst(CPURISCVState *env, int csrno, |
1339 | target_ulong val) | |
34cfb5f6 AF |
1340 | { |
1341 | env->mtinst = val; | |
605def6e | 1342 | return RISCV_EXCP_NONE; |
34cfb5f6 AF |
1343 | } |
1344 | ||
c7b95171 | 1345 | /* Physical Memory Protection */ |
605def6e AF |
1346 | static RISCVException read_pmpcfg(CPURISCVState *env, int csrno, |
1347 | target_ulong *val) | |
c7b95171 MC |
1348 | { |
1349 | *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0); | |
605def6e | 1350 | return RISCV_EXCP_NONE; |
c7b95171 MC |
1351 | } |
1352 | ||
605def6e AF |
1353 | static RISCVException write_pmpcfg(CPURISCVState *env, int csrno, |
1354 | target_ulong val) | |
c7b95171 MC |
1355 | { |
1356 | pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val); | |
605def6e | 1357 | return RISCV_EXCP_NONE; |
c7b95171 MC |
1358 | } |
1359 | ||
605def6e AF |
1360 | static RISCVException read_pmpaddr(CPURISCVState *env, int csrno, |
1361 | target_ulong *val) | |
c7b95171 MC |
1362 | { |
1363 | *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0); | |
605def6e | 1364 | return RISCV_EXCP_NONE; |
c7b95171 MC |
1365 | } |
1366 | ||
605def6e AF |
1367 | static RISCVException write_pmpaddr(CPURISCVState *env, int csrno, |
1368 | target_ulong val) | |
c7b95171 MC |
1369 | { |
1370 | pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val); | |
605def6e | 1371 | return RISCV_EXCP_NONE; |
c7b95171 MC |
1372 | } |
1373 | ||
1374 | #endif | |
1375 | ||
1376 | /* | |
1377 | * riscv_csrrw - read and/or update control and status register | |
1378 | * | |
1379 | * csrr <-> riscv_csrrw(env, csrno, ret_value, 0, 0); | |
1380 | * csrrw <-> riscv_csrrw(env, csrno, ret_value, value, -1); | |
1381 | * csrrs <-> riscv_csrrw(env, csrno, ret_value, -1, value); | |
1382 | * csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value); | |
1383 | */ | |
1384 | ||
1385 | int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, | |
1386 | target_ulong new_value, target_ulong write_mask) | |
1387 | { | |
1388 | int ret; | |
1389 | target_ulong old_value; | |
591bddea | 1390 | RISCVCPU *cpu = env_archcpu(env); |
c7b95171 MC |
1391 | |
1392 | /* check privileges and return -1 if check fails */ | |
1393 | #if !defined(CONFIG_USER_ONLY) | |
0a42f4c4 | 1394 | int effective_priv = env->priv; |
c7b95171 | 1395 | int read_only = get_field(csrno, 0xC00) == 3; |
0a42f4c4 AF |
1396 | |
1397 | if (riscv_has_ext(env, RVH) && | |
1398 | env->priv == PRV_S && | |
1399 | !riscv_cpu_virt_enabled(env)) { | |
1400 | /* | |
1401 | * We are in S mode without virtualisation, therefore we are in HS Mode. | |
1402 | * Add 1 to the effective privledge level to allow us to access the | |
1403 | * Hypervisor CSRs. | |
1404 | */ | |
1405 | effective_priv++; | |
e6e03dcf | 1406 | } |
0a42f4c4 AF |
1407 | |
1408 | if ((write_mask && read_only) || | |
1409 | (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) { | |
57cb2083 | 1410 | return -RISCV_EXCP_ILLEGAL_INST; |
c7b95171 MC |
1411 | } |
1412 | #endif | |
1413 | ||
591bddea PD |
1414 | /* ensure the CSR extension is enabled. */ |
1415 | if (!cpu->cfg.ext_icsr) { | |
57cb2083 | 1416 | return -RISCV_EXCP_ILLEGAL_INST; |
591bddea PD |
1417 | } |
1418 | ||
a88365c1 | 1419 | /* check predicate */ |
e39a8320 | 1420 | if (!csr_ops[csrno].predicate) { |
57cb2083 | 1421 | return -RISCV_EXCP_ILLEGAL_INST; |
a88365c1 | 1422 | } |
e39a8320 | 1423 | ret = csr_ops[csrno].predicate(env, csrno); |
0e62f92e AF |
1424 | if (ret != RISCV_EXCP_NONE) { |
1425 | return -ret; | |
e39a8320 | 1426 | } |
a88365c1 | 1427 | |
c7b95171 MC |
1428 | /* execute combined read/write operation if it exists */ |
1429 | if (csr_ops[csrno].op) { | |
605def6e AF |
1430 | ret = csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask); |
1431 | if (ret != RISCV_EXCP_NONE) { | |
1432 | return -ret; | |
1433 | } | |
1434 | return 0; | |
c7b95171 MC |
1435 | } |
1436 | ||
1437 | /* if no accessor exists then return failure */ | |
1438 | if (!csr_ops[csrno].read) { | |
57cb2083 | 1439 | return -RISCV_EXCP_ILLEGAL_INST; |
c7b95171 | 1440 | } |
c7b95171 MC |
1441 | /* read old value */ |
1442 | ret = csr_ops[csrno].read(env, csrno, &old_value); | |
605def6e AF |
1443 | if (ret != RISCV_EXCP_NONE) { |
1444 | return -ret; | |
c7b95171 MC |
1445 | } |
1446 | ||
1447 | /* write value if writable and write mask set, otherwise drop writes */ | |
1448 | if (write_mask) { | |
1449 | new_value = (old_value & ~write_mask) | (new_value & write_mask); | |
1450 | if (csr_ops[csrno].write) { | |
1451 | ret = csr_ops[csrno].write(env, csrno, new_value); | |
605def6e AF |
1452 | if (ret != RISCV_EXCP_NONE) { |
1453 | return -ret; | |
c7b95171 MC |
1454 | } |
1455 | } | |
1456 | } | |
1457 | ||
1458 | /* return old value */ | |
1459 | if (ret_value) { | |
1460 | *ret_value = old_value; | |
1461 | } | |
1462 | ||
1463 | return 0; | |
1464 | } | |
1465 | ||
753e3fe2 JW |
1466 | /* |
1467 | * Debugger support. If not in user mode, set env->debugger before the | |
1468 | * riscv_csrrw call and clear it after the call. | |
1469 | */ | |
1470 | int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value, | |
1471 | target_ulong new_value, target_ulong write_mask) | |
1472 | { | |
1473 | int ret; | |
1474 | #if !defined(CONFIG_USER_ONLY) | |
1475 | env->debugger = true; | |
1476 | #endif | |
1477 | ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask); | |
1478 | #if !defined(CONFIG_USER_ONLY) | |
1479 | env->debugger = false; | |
1480 | #endif | |
1481 | return ret; | |
1482 | } | |
1483 | ||
c7b95171 | 1484 | /* Control and Status Register function table */ |
56118ee8 | 1485 | riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { |
c7b95171 | 1486 | /* User Floating-Point CSRs */ |
8ceac5dc BM |
1487 | [CSR_FFLAGS] = { "fflags", fs, read_fflags, write_fflags }, |
1488 | [CSR_FRM] = { "frm", fs, read_frm, write_frm }, | |
1489 | [CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr }, | |
8e3a1f18 | 1490 | /* Vector CSRs */ |
8ceac5dc BM |
1491 | [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart }, |
1492 | [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat }, | |
1493 | [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm }, | |
1494 | [CSR_VL] = { "vl", vs, read_vl }, | |
1495 | [CSR_VTYPE] = { "vtype", vs, read_vtype }, | |
c7b95171 | 1496 | /* User Timers and Counters */ |
8ceac5dc BM |
1497 | [CSR_CYCLE] = { "cycle", ctr, read_instret }, |
1498 | [CSR_INSTRET] = { "instret", ctr, read_instret }, | |
1499 | [CSR_CYCLEH] = { "cycleh", ctr32, read_instreth }, | |
1500 | [CSR_INSTRETH] = { "instreth", ctr32, read_instreth }, | |
1501 | ||
1502 | /* | |
1503 | * In privileged mode, the monitor will have to emulate TIME CSRs only if | |
1504 | * rdtime callback is not provided by machine/platform emulation. | |
1505 | */ | |
1506 | [CSR_TIME] = { "time", ctr, read_time }, | |
1507 | [CSR_TIMEH] = { "timeh", ctr32, read_timeh }, | |
c7b95171 MC |
1508 | |
1509 | #if !defined(CONFIG_USER_ONLY) | |
1510 | /* Machine Timers and Counters */ | |
8ceac5dc BM |
1511 | [CSR_MCYCLE] = { "mcycle", any, read_instret }, |
1512 | [CSR_MINSTRET] = { "minstret", any, read_instret }, | |
1513 | [CSR_MCYCLEH] = { "mcycleh", any32, read_instreth }, | |
1514 | [CSR_MINSTRETH] = { "minstreth", any32, read_instreth }, | |
c7b95171 MC |
1515 | |
1516 | /* Machine Information Registers */ | |
8ceac5dc BM |
1517 | [CSR_MVENDORID] = { "mvendorid", any, read_zero }, |
1518 | [CSR_MARCHID] = { "marchid", any, read_zero }, | |
1519 | [CSR_MIMPID] = { "mimpid", any, read_zero }, | |
1520 | [CSR_MHARTID] = { "mhartid", any, read_mhartid }, | |
c7b95171 MC |
1521 | |
1522 | /* Machine Trap Setup */ | |
8ceac5dc BM |
1523 | [CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus }, |
1524 | [CSR_MISA] = { "misa", any, read_misa, write_misa }, | |
1525 | [CSR_MIDELEG] = { "mideleg", any, read_mideleg, write_mideleg }, | |
1526 | [CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg }, | |
1527 | [CSR_MIE] = { "mie", any, read_mie, write_mie }, | |
1528 | [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec }, | |
1529 | [CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, write_mcounteren }, | |
c7b95171 | 1530 | |
8ceac5dc | 1531 | [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush }, |
551fa7e8 | 1532 | |
c7b95171 | 1533 | /* Machine Trap Handling */ |
8ceac5dc BM |
1534 | [CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch }, |
1535 | [CSR_MEPC] = { "mepc", any, read_mepc, write_mepc }, | |
1536 | [CSR_MCAUSE] = { "mcause", any, read_mcause, write_mcause }, | |
ac12b601 | 1537 | [CSR_MTVAL] = { "mtval", any, read_mtval, write_mtval }, |
8ceac5dc | 1538 | [CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip }, |
c7b95171 MC |
1539 | |
1540 | /* Supervisor Trap Setup */ | |
8ceac5dc BM |
1541 | [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus }, |
1542 | [CSR_SIE] = { "sie", smode, read_sie, write_sie }, | |
1543 | [CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec }, | |
1544 | [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren }, | |
c7b95171 MC |
1545 | |
1546 | /* Supervisor Trap Handling */ | |
8ceac5dc BM |
1547 | [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch }, |
1548 | [CSR_SEPC] = { "sepc", smode, read_sepc, write_sepc }, | |
1549 | [CSR_SCAUSE] = { "scause", smode, read_scause, write_scause }, | |
ac12b601 | 1550 | [CSR_STVAL] = { "stval", smode, read_stval, write_stval }, |
8ceac5dc | 1551 | [CSR_SIP] = { "sip", smode, NULL, NULL, rmw_sip }, |
c7b95171 MC |
1552 | |
1553 | /* Supervisor Protection and Translation */ | |
8ceac5dc BM |
1554 | [CSR_SATP] = { "satp", smode, read_satp, write_satp }, |
1555 | ||
1556 | [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus }, | |
1557 | [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg }, | |
1558 | [CSR_HIDELEG] = { "hideleg", hmode, read_hideleg, write_hideleg }, | |
1559 | [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip }, | |
1560 | [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip }, | |
1561 | [CSR_HIE] = { "hie", hmode, read_hie, write_hie }, | |
1562 | [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren }, | |
1563 | [CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie }, | |
1564 | [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval }, | |
1565 | [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst }, | |
1566 | [CSR_HGEIP] = { "hgeip", hmode, read_hgeip, write_hgeip }, | |
1567 | [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp }, | |
1568 | [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta }, | |
1569 | [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah }, | |
1570 | ||
1571 | [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus }, | |
1572 | [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip }, | |
1573 | [CSR_VSIE] = { "vsie", hmode, read_vsie, write_vsie }, | |
1574 | [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec }, | |
1575 | [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch }, | |
1576 | [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc }, | |
1577 | [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause }, | |
1578 | [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval }, | |
1579 | [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp }, | |
1580 | ||
1581 | [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2 }, | |
1582 | [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst }, | |
34cfb5f6 | 1583 | |
c7b95171 | 1584 | /* Physical Memory Protection */ |
8ceac5dc BM |
1585 | [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg }, |
1586 | [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, | |
1587 | [CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg }, | |
1588 | [CSR_PMPCFG3] = { "pmpcfg3", pmp, read_pmpcfg, write_pmpcfg }, | |
1589 | [CSR_PMPADDR0] = { "pmpaddr0", pmp, read_pmpaddr, write_pmpaddr }, | |
1590 | [CSR_PMPADDR1] = { "pmpaddr1", pmp, read_pmpaddr, write_pmpaddr }, | |
1591 | [CSR_PMPADDR2] = { "pmpaddr2", pmp, read_pmpaddr, write_pmpaddr }, | |
1592 | [CSR_PMPADDR3] = { "pmpaddr3", pmp, read_pmpaddr, write_pmpaddr }, | |
1593 | [CSR_PMPADDR4] = { "pmpaddr4", pmp, read_pmpaddr, write_pmpaddr }, | |
1594 | [CSR_PMPADDR5] = { "pmpaddr5", pmp, read_pmpaddr, write_pmpaddr }, | |
1595 | [CSR_PMPADDR6] = { "pmpaddr6", pmp, read_pmpaddr, write_pmpaddr }, | |
1596 | [CSR_PMPADDR7] = { "pmpaddr7", pmp, read_pmpaddr, write_pmpaddr }, | |
1597 | [CSR_PMPADDR8] = { "pmpaddr8", pmp, read_pmpaddr, write_pmpaddr }, | |
1598 | [CSR_PMPADDR9] = { "pmpaddr9", pmp, read_pmpaddr, write_pmpaddr }, | |
1599 | [CSR_PMPADDR10] = { "pmpaddr10", pmp, read_pmpaddr, write_pmpaddr }, | |
1600 | [CSR_PMPADDR11] = { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr }, | |
1601 | [CSR_PMPADDR12] = { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr }, | |
1602 | [CSR_PMPADDR13] = { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr }, | |
1603 | [CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr }, | |
1604 | [CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr }, | |
c7b95171 MC |
1605 | |
1606 | /* Performance Counters */ | |
8ceac5dc BM |
1607 | [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_zero }, |
1608 | [CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_zero }, | |
1609 | [CSR_HPMCOUNTER5] = { "hpmcounter5", ctr, read_zero }, | |
1610 | [CSR_HPMCOUNTER6] = { "hpmcounter6", ctr, read_zero }, | |
1611 | [CSR_HPMCOUNTER7] = { "hpmcounter7", ctr, read_zero }, | |
1612 | [CSR_HPMCOUNTER8] = { "hpmcounter8", ctr, read_zero }, | |
1613 | [CSR_HPMCOUNTER9] = { "hpmcounter9", ctr, read_zero }, | |
1614 | [CSR_HPMCOUNTER10] = { "hpmcounter10", ctr, read_zero }, | |
1615 | [CSR_HPMCOUNTER11] = { "hpmcounter11", ctr, read_zero }, | |
1616 | [CSR_HPMCOUNTER12] = { "hpmcounter12", ctr, read_zero }, | |
1617 | [CSR_HPMCOUNTER13] = { "hpmcounter13", ctr, read_zero }, | |
1618 | [CSR_HPMCOUNTER14] = { "hpmcounter14", ctr, read_zero }, | |
1619 | [CSR_HPMCOUNTER15] = { "hpmcounter15", ctr, read_zero }, | |
1620 | [CSR_HPMCOUNTER16] = { "hpmcounter16", ctr, read_zero }, | |
1621 | [CSR_HPMCOUNTER17] = { "hpmcounter17", ctr, read_zero }, | |
1622 | [CSR_HPMCOUNTER18] = { "hpmcounter18", ctr, read_zero }, | |
1623 | [CSR_HPMCOUNTER19] = { "hpmcounter19", ctr, read_zero }, | |
1624 | [CSR_HPMCOUNTER20] = { "hpmcounter20", ctr, read_zero }, | |
1625 | [CSR_HPMCOUNTER21] = { "hpmcounter21", ctr, read_zero }, | |
1626 | [CSR_HPMCOUNTER22] = { "hpmcounter22", ctr, read_zero }, | |
1627 | [CSR_HPMCOUNTER23] = { "hpmcounter23", ctr, read_zero }, | |
1628 | [CSR_HPMCOUNTER24] = { "hpmcounter24", ctr, read_zero }, | |
1629 | [CSR_HPMCOUNTER25] = { "hpmcounter25", ctr, read_zero }, | |
1630 | [CSR_HPMCOUNTER26] = { "hpmcounter26", ctr, read_zero }, | |
1631 | [CSR_HPMCOUNTER27] = { "hpmcounter27", ctr, read_zero }, | |
1632 | [CSR_HPMCOUNTER28] = { "hpmcounter28", ctr, read_zero }, | |
1633 | [CSR_HPMCOUNTER29] = { "hpmcounter29", ctr, read_zero }, | |
1634 | [CSR_HPMCOUNTER30] = { "hpmcounter30", ctr, read_zero }, | |
1635 | [CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_zero }, | |
1636 | ||
1637 | [CSR_MHPMCOUNTER3] = { "mhpmcounter3", any, read_zero }, | |
1638 | [CSR_MHPMCOUNTER4] = { "mhpmcounter4", any, read_zero }, | |
1639 | [CSR_MHPMCOUNTER5] = { "mhpmcounter5", any, read_zero }, | |
1640 | [CSR_MHPMCOUNTER6] = { "mhpmcounter6", any, read_zero }, | |
1641 | [CSR_MHPMCOUNTER7] = { "mhpmcounter7", any, read_zero }, | |
1642 | [CSR_MHPMCOUNTER8] = { "mhpmcounter8", any, read_zero }, | |
1643 | [CSR_MHPMCOUNTER9] = { "mhpmcounter9", any, read_zero }, | |
1644 | [CSR_MHPMCOUNTER10] = { "mhpmcounter10", any, read_zero }, | |
1645 | [CSR_MHPMCOUNTER11] = { "mhpmcounter11", any, read_zero }, | |
1646 | [CSR_MHPMCOUNTER12] = { "mhpmcounter12", any, read_zero }, | |
1647 | [CSR_MHPMCOUNTER13] = { "mhpmcounter13", any, read_zero }, | |
1648 | [CSR_MHPMCOUNTER14] = { "mhpmcounter14", any, read_zero }, | |
1649 | [CSR_MHPMCOUNTER15] = { "mhpmcounter15", any, read_zero }, | |
1650 | [CSR_MHPMCOUNTER16] = { "mhpmcounter16", any, read_zero }, | |
1651 | [CSR_MHPMCOUNTER17] = { "mhpmcounter17", any, read_zero }, | |
1652 | [CSR_MHPMCOUNTER18] = { "mhpmcounter18", any, read_zero }, | |
1653 | [CSR_MHPMCOUNTER19] = { "mhpmcounter19", any, read_zero }, | |
1654 | [CSR_MHPMCOUNTER20] = { "mhpmcounter20", any, read_zero }, | |
1655 | [CSR_MHPMCOUNTER21] = { "mhpmcounter21", any, read_zero }, | |
1656 | [CSR_MHPMCOUNTER22] = { "mhpmcounter22", any, read_zero }, | |
1657 | [CSR_MHPMCOUNTER23] = { "mhpmcounter23", any, read_zero }, | |
1658 | [CSR_MHPMCOUNTER24] = { "mhpmcounter24", any, read_zero }, | |
1659 | [CSR_MHPMCOUNTER25] = { "mhpmcounter25", any, read_zero }, | |
1660 | [CSR_MHPMCOUNTER26] = { "mhpmcounter26", any, read_zero }, | |
1661 | [CSR_MHPMCOUNTER27] = { "mhpmcounter27", any, read_zero }, | |
1662 | [CSR_MHPMCOUNTER28] = { "mhpmcounter28", any, read_zero }, | |
1663 | [CSR_MHPMCOUNTER29] = { "mhpmcounter29", any, read_zero }, | |
1664 | [CSR_MHPMCOUNTER30] = { "mhpmcounter30", any, read_zero }, | |
1665 | [CSR_MHPMCOUNTER31] = { "mhpmcounter31", any, read_zero }, | |
1666 | ||
1667 | [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_zero }, | |
1668 | [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_zero }, | |
1669 | [CSR_MHPMEVENT5] = { "mhpmevent5", any, read_zero }, | |
1670 | [CSR_MHPMEVENT6] = { "mhpmevent6", any, read_zero }, | |
1671 | [CSR_MHPMEVENT7] = { "mhpmevent7", any, read_zero }, | |
1672 | [CSR_MHPMEVENT8] = { "mhpmevent8", any, read_zero }, | |
1673 | [CSR_MHPMEVENT9] = { "mhpmevent9", any, read_zero }, | |
1674 | [CSR_MHPMEVENT10] = { "mhpmevent10", any, read_zero }, | |
1675 | [CSR_MHPMEVENT11] = { "mhpmevent11", any, read_zero }, | |
1676 | [CSR_MHPMEVENT12] = { "mhpmevent12", any, read_zero }, | |
1677 | [CSR_MHPMEVENT13] = { "mhpmevent13", any, read_zero }, | |
1678 | [CSR_MHPMEVENT14] = { "mhpmevent14", any, read_zero }, | |
1679 | [CSR_MHPMEVENT15] = { "mhpmevent15", any, read_zero }, | |
1680 | [CSR_MHPMEVENT16] = { "mhpmevent16", any, read_zero }, | |
1681 | [CSR_MHPMEVENT17] = { "mhpmevent17", any, read_zero }, | |
1682 | [CSR_MHPMEVENT18] = { "mhpmevent18", any, read_zero }, | |
1683 | [CSR_MHPMEVENT19] = { "mhpmevent19", any, read_zero }, | |
1684 | [CSR_MHPMEVENT20] = { "mhpmevent20", any, read_zero }, | |
1685 | [CSR_MHPMEVENT21] = { "mhpmevent21", any, read_zero }, | |
1686 | [CSR_MHPMEVENT22] = { "mhpmevent22", any, read_zero }, | |
1687 | [CSR_MHPMEVENT23] = { "mhpmevent23", any, read_zero }, | |
1688 | [CSR_MHPMEVENT24] = { "mhpmevent24", any, read_zero }, | |
1689 | [CSR_MHPMEVENT25] = { "mhpmevent25", any, read_zero }, | |
1690 | [CSR_MHPMEVENT26] = { "mhpmevent26", any, read_zero }, | |
1691 | [CSR_MHPMEVENT27] = { "mhpmevent27", any, read_zero }, | |
1692 | [CSR_MHPMEVENT28] = { "mhpmevent28", any, read_zero }, | |
1693 | [CSR_MHPMEVENT29] = { "mhpmevent29", any, read_zero }, | |
1694 | [CSR_MHPMEVENT30] = { "mhpmevent30", any, read_zero }, | |
1695 | [CSR_MHPMEVENT31] = { "mhpmevent31", any, read_zero }, | |
1696 | ||
1697 | [CSR_HPMCOUNTER3H] = { "hpmcounter3h", ctr32, read_zero }, | |
1698 | [CSR_HPMCOUNTER4H] = { "hpmcounter4h", ctr32, read_zero }, | |
1699 | [CSR_HPMCOUNTER5H] = { "hpmcounter5h", ctr32, read_zero }, | |
1700 | [CSR_HPMCOUNTER6H] = { "hpmcounter6h", ctr32, read_zero }, | |
1701 | [CSR_HPMCOUNTER7H] = { "hpmcounter7h", ctr32, read_zero }, | |
1702 | [CSR_HPMCOUNTER8H] = { "hpmcounter8h", ctr32, read_zero }, | |
1703 | [CSR_HPMCOUNTER9H] = { "hpmcounter9h", ctr32, read_zero }, | |
1704 | [CSR_HPMCOUNTER10H] = { "hpmcounter10h", ctr32, read_zero }, | |
1705 | [CSR_HPMCOUNTER11H] = { "hpmcounter11h", ctr32, read_zero }, | |
1706 | [CSR_HPMCOUNTER12H] = { "hpmcounter12h", ctr32, read_zero }, | |
1707 | [CSR_HPMCOUNTER13H] = { "hpmcounter13h", ctr32, read_zero }, | |
1708 | [CSR_HPMCOUNTER14H] = { "hpmcounter14h", ctr32, read_zero }, | |
1709 | [CSR_HPMCOUNTER15H] = { "hpmcounter15h", ctr32, read_zero }, | |
1710 | [CSR_HPMCOUNTER16H] = { "hpmcounter16h", ctr32, read_zero }, | |
1711 | [CSR_HPMCOUNTER17H] = { "hpmcounter17h", ctr32, read_zero }, | |
1712 | [CSR_HPMCOUNTER18H] = { "hpmcounter18h", ctr32, read_zero }, | |
1713 | [CSR_HPMCOUNTER19H] = { "hpmcounter19h", ctr32, read_zero }, | |
1714 | [CSR_HPMCOUNTER20H] = { "hpmcounter20h", ctr32, read_zero }, | |
1715 | [CSR_HPMCOUNTER21H] = { "hpmcounter21h", ctr32, read_zero }, | |
1716 | [CSR_HPMCOUNTER22H] = { "hpmcounter22h", ctr32, read_zero }, | |
1717 | [CSR_HPMCOUNTER23H] = { "hpmcounter23h", ctr32, read_zero }, | |
1718 | [CSR_HPMCOUNTER24H] = { "hpmcounter24h", ctr32, read_zero }, | |
1719 | [CSR_HPMCOUNTER25H] = { "hpmcounter25h", ctr32, read_zero }, | |
1720 | [CSR_HPMCOUNTER26H] = { "hpmcounter26h", ctr32, read_zero }, | |
1721 | [CSR_HPMCOUNTER27H] = { "hpmcounter27h", ctr32, read_zero }, | |
1722 | [CSR_HPMCOUNTER28H] = { "hpmcounter28h", ctr32, read_zero }, | |
1723 | [CSR_HPMCOUNTER29H] = { "hpmcounter29h", ctr32, read_zero }, | |
1724 | [CSR_HPMCOUNTER30H] = { "hpmcounter30h", ctr32, read_zero }, | |
1725 | [CSR_HPMCOUNTER31H] = { "hpmcounter31h", ctr32, read_zero }, | |
1726 | ||
1727 | [CSR_MHPMCOUNTER3H] = { "mhpmcounter3h", any32, read_zero }, | |
1728 | [CSR_MHPMCOUNTER4H] = { "mhpmcounter4h", any32, read_zero }, | |
1729 | [CSR_MHPMCOUNTER5H] = { "mhpmcounter5h", any32, read_zero }, | |
1730 | [CSR_MHPMCOUNTER6H] = { "mhpmcounter6h", any32, read_zero }, | |
1731 | [CSR_MHPMCOUNTER7H] = { "mhpmcounter7h", any32, read_zero }, | |
1732 | [CSR_MHPMCOUNTER8H] = { "mhpmcounter8h", any32, read_zero }, | |
1733 | [CSR_MHPMCOUNTER9H] = { "mhpmcounter9h", any32, read_zero }, | |
1734 | [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", any32, read_zero }, | |
1735 | [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", any32, read_zero }, | |
1736 | [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", any32, read_zero }, | |
1737 | [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", any32, read_zero }, | |
1738 | [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", any32, read_zero }, | |
1739 | [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", any32, read_zero }, | |
1740 | [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", any32, read_zero }, | |
1741 | [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", any32, read_zero }, | |
1742 | [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", any32, read_zero }, | |
1743 | [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", any32, read_zero }, | |
1744 | [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", any32, read_zero }, | |
1745 | [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", any32, read_zero }, | |
1746 | [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", any32, read_zero }, | |
1747 | [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", any32, read_zero }, | |
1748 | [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", any32, read_zero }, | |
1749 | [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", any32, read_zero }, | |
1750 | [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", any32, read_zero }, | |
1751 | [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", any32, read_zero }, | |
1752 | [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", any32, read_zero }, | |
1753 | [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32, read_zero }, | |
1754 | [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32, read_zero }, | |
1755 | [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32, read_zero }, | |
c7b95171 MC |
1756 | #endif /* !CONFIG_USER_ONLY */ |
1757 | }; |