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c7b95171 MC |
1 | /* |
2 | * RISC-V Control and Status Registers. | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017-2018 SiFive, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2 or later, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
21 | #include "qemu/log.h" | |
22 | #include "cpu.h" | |
23 | #include "qemu/main-loop.h" | |
24 | #include "exec/exec-all.h" | |
25 | ||
26 | /* CSR function table */ | |
27 | static riscv_csr_operations csr_ops[]; | |
28 | ||
29 | /* CSR function table constants */ | |
30 | enum { | |
31 | CSR_TABLE_SIZE = 0x1000 | |
32 | }; | |
33 | ||
34 | /* CSR function table public API */ | |
35 | void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) | |
36 | { | |
37 | *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)]; | |
38 | } | |
39 | ||
40 | void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) | |
41 | { | |
42 | csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops; | |
43 | } | |
44 | ||
a88365c1 MC |
45 | /* Predicates */ |
46 | static int fs(CPURISCVState *env, int csrno) | |
47 | { | |
48 | #if !defined(CONFIG_USER_ONLY) | |
b345b480 | 49 | if (!env->debugger && !riscv_cpu_fp_enabled(env)) { |
a88365c1 MC |
50 | return -1; |
51 | } | |
52 | #endif | |
53 | return 0; | |
54 | } | |
55 | ||
56 | static int ctr(CPURISCVState *env, int csrno) | |
57 | { | |
58 | #if !defined(CONFIG_USER_ONLY) | |
0a13a5b8 AF |
59 | CPUState *cs = env_cpu(env); |
60 | RISCVCPU *cpu = RISCV_CPU(cs); | |
61 | uint32_t ctr_en = ~0u; | |
62 | ||
63 | if (!cpu->cfg.ext_counters) { | |
64 | /* The Counters extensions is not enabled */ | |
65 | return -1; | |
66 | } | |
67 | ||
747a43e8 | 68 | /* |
0a13a5b8 AF |
69 | * The counters are always enabled at run time on newer priv specs, as the |
70 | * CSR has changed from controlling that the counters can be read to | |
71 | * controlling that the counters increment. | |
747a43e8 AF |
72 | */ |
73 | if (env->priv_ver > PRIV_VERSION_1_09_1) { | |
74 | return 0; | |
75 | } | |
76 | ||
ff9f31d9 XW |
77 | if (env->priv < PRV_M) { |
78 | ctr_en &= env->mcounteren; | |
79 | } | |
80 | if (env->priv < PRV_S) { | |
81 | ctr_en &= env->scounteren; | |
82 | } | |
83 | if (!(ctr_en & (1u << (csrno & 31)))) { | |
a88365c1 MC |
84 | return -1; |
85 | } | |
86 | #endif | |
87 | return 0; | |
88 | } | |
89 | ||
90 | #if !defined(CONFIG_USER_ONLY) | |
91 | static int any(CPURISCVState *env, int csrno) | |
92 | { | |
93 | return 0; | |
94 | } | |
95 | ||
96 | static int smode(CPURISCVState *env, int csrno) | |
97 | { | |
98 | return -!riscv_has_ext(env, RVS); | |
99 | } | |
100 | ||
ff2cc129 AF |
101 | static int hmode(CPURISCVState *env, int csrno) |
102 | { | |
103 | if (riscv_has_ext(env, RVS) && | |
104 | riscv_has_ext(env, RVH)) { | |
105 | /* Hypervisor extension is supported */ | |
106 | if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || | |
107 | env->priv == PRV_M) { | |
108 | return 0; | |
109 | } | |
110 | } | |
111 | ||
112 | return -1; | |
113 | } | |
114 | ||
a88365c1 MC |
115 | static int pmp(CPURISCVState *env, int csrno) |
116 | { | |
117 | return -!riscv_feature(env, RISCV_FEATURE_PMP); | |
118 | } | |
119 | #endif | |
120 | ||
c7b95171 MC |
121 | /* User Floating-Point CSRs */ |
122 | static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val) | |
123 | { | |
124 | #if !defined(CONFIG_USER_ONLY) | |
b345b480 | 125 | if (!env->debugger && !riscv_cpu_fp_enabled(env)) { |
c7b95171 MC |
126 | return -1; |
127 | } | |
128 | #endif | |
fb738839 | 129 | *val = riscv_cpu_get_fflags(env); |
c7b95171 MC |
130 | return 0; |
131 | } | |
132 | ||
133 | static int write_fflags(CPURISCVState *env, int csrno, target_ulong val) | |
134 | { | |
135 | #if !defined(CONFIG_USER_ONLY) | |
b345b480 | 136 | if (!env->debugger && !riscv_cpu_fp_enabled(env)) { |
c7b95171 MC |
137 | return -1; |
138 | } | |
139 | env->mstatus |= MSTATUS_FS; | |
140 | #endif | |
fb738839 | 141 | riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT)); |
c7b95171 MC |
142 | return 0; |
143 | } | |
144 | ||
145 | static int read_frm(CPURISCVState *env, int csrno, target_ulong *val) | |
146 | { | |
147 | #if !defined(CONFIG_USER_ONLY) | |
b345b480 | 148 | if (!env->debugger && !riscv_cpu_fp_enabled(env)) { |
c7b95171 MC |
149 | return -1; |
150 | } | |
151 | #endif | |
152 | *val = env->frm; | |
153 | return 0; | |
154 | } | |
155 | ||
156 | static int write_frm(CPURISCVState *env, int csrno, target_ulong val) | |
157 | { | |
158 | #if !defined(CONFIG_USER_ONLY) | |
b345b480 | 159 | if (!env->debugger && !riscv_cpu_fp_enabled(env)) { |
c7b95171 MC |
160 | return -1; |
161 | } | |
162 | env->mstatus |= MSTATUS_FS; | |
163 | #endif | |
164 | env->frm = val & (FSR_RD >> FSR_RD_SHIFT); | |
165 | return 0; | |
166 | } | |
167 | ||
168 | static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val) | |
169 | { | |
170 | #if !defined(CONFIG_USER_ONLY) | |
b345b480 | 171 | if (!env->debugger && !riscv_cpu_fp_enabled(env)) { |
c7b95171 MC |
172 | return -1; |
173 | } | |
174 | #endif | |
fb738839 | 175 | *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) |
c7b95171 MC |
176 | | (env->frm << FSR_RD_SHIFT); |
177 | return 0; | |
178 | } | |
179 | ||
180 | static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val) | |
181 | { | |
182 | #if !defined(CONFIG_USER_ONLY) | |
b345b480 | 183 | if (!env->debugger && !riscv_cpu_fp_enabled(env)) { |
c7b95171 MC |
184 | return -1; |
185 | } | |
186 | env->mstatus |= MSTATUS_FS; | |
187 | #endif | |
188 | env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; | |
fb738839 | 189 | riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT); |
c7b95171 MC |
190 | return 0; |
191 | } | |
192 | ||
193 | /* User Timers and Counters */ | |
c7b95171 MC |
194 | static int read_instret(CPURISCVState *env, int csrno, target_ulong *val) |
195 | { | |
c7b95171 MC |
196 | #if !defined(CONFIG_USER_ONLY) |
197 | if (use_icount) { | |
198 | *val = cpu_get_icount(); | |
199 | } else { | |
200 | *val = cpu_get_host_ticks(); | |
201 | } | |
202 | #else | |
203 | *val = cpu_get_host_ticks(); | |
204 | #endif | |
205 | return 0; | |
206 | } | |
207 | ||
208 | #if defined(TARGET_RISCV32) | |
209 | static int read_instreth(CPURISCVState *env, int csrno, target_ulong *val) | |
210 | { | |
c7b95171 MC |
211 | #if !defined(CONFIG_USER_ONLY) |
212 | if (use_icount) { | |
213 | *val = cpu_get_icount() >> 32; | |
214 | } else { | |
215 | *val = cpu_get_host_ticks() >> 32; | |
216 | } | |
217 | #else | |
218 | *val = cpu_get_host_ticks() >> 32; | |
219 | #endif | |
220 | return 0; | |
221 | } | |
222 | #endif /* TARGET_RISCV32 */ | |
223 | ||
224 | #if defined(CONFIG_USER_ONLY) | |
225 | static int read_time(CPURISCVState *env, int csrno, target_ulong *val) | |
226 | { | |
227 | *val = cpu_get_host_ticks(); | |
228 | return 0; | |
229 | } | |
230 | ||
231 | #if defined(TARGET_RISCV32) | |
232 | static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val) | |
233 | { | |
234 | *val = cpu_get_host_ticks() >> 32; | |
235 | return 0; | |
236 | } | |
237 | #endif | |
238 | ||
239 | #else /* CONFIG_USER_ONLY */ | |
240 | ||
241 | /* Machine constants */ | |
242 | ||
ff2cc129 AF |
243 | #define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP) |
244 | #define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP) | |
245 | #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) | |
c7b95171 MC |
246 | |
247 | static const target_ulong delegable_ints = S_MODE_INTERRUPTS; | |
248 | static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS; | |
249 | static const target_ulong delegable_excps = | |
250 | (1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | | |
251 | (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | | |
252 | (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | | |
253 | (1ULL << (RISCV_EXCP_BREAKPOINT)) | | |
254 | (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | | |
255 | (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | | |
256 | (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | | |
257 | (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | | |
258 | (1ULL << (RISCV_EXCP_U_ECALL)) | | |
259 | (1ULL << (RISCV_EXCP_S_ECALL)) | | |
ab67a1d0 | 260 | (1ULL << (RISCV_EXCP_VS_ECALL)) | |
c7b95171 MC |
261 | (1ULL << (RISCV_EXCP_M_ECALL)) | |
262 | (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | | |
263 | (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | | |
ab67a1d0 AF |
264 | (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | |
265 | (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | | |
266 | (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | | |
267 | (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)); | |
c7b95171 MC |
268 | static const target_ulong sstatus_v1_9_mask = SSTATUS_SIE | SSTATUS_SPIE | |
269 | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | | |
270 | SSTATUS_SUM | SSTATUS_SD; | |
271 | static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | | |
272 | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | | |
273 | SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD; | |
087b051a | 274 | static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP; |
ff2cc129 | 275 | static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; |
8747c9ee | 276 | static const target_ulong vsip_writable_mask = MIP_VSSIP; |
c7b95171 MC |
277 | |
278 | #if defined(TARGET_RISCV32) | |
279 | static const char valid_vm_1_09[16] = { | |
280 | [VM_1_09_MBARE] = 1, | |
281 | [VM_1_09_SV32] = 1, | |
282 | }; | |
283 | static const char valid_vm_1_10[16] = { | |
284 | [VM_1_10_MBARE] = 1, | |
285 | [VM_1_10_SV32] = 1 | |
286 | }; | |
287 | #elif defined(TARGET_RISCV64) | |
288 | static const char valid_vm_1_09[16] = { | |
289 | [VM_1_09_MBARE] = 1, | |
290 | [VM_1_09_SV39] = 1, | |
291 | [VM_1_09_SV48] = 1, | |
292 | }; | |
293 | static const char valid_vm_1_10[16] = { | |
294 | [VM_1_10_MBARE] = 1, | |
295 | [VM_1_10_SV39] = 1, | |
296 | [VM_1_10_SV48] = 1, | |
297 | [VM_1_10_SV57] = 1 | |
298 | }; | |
299 | #endif /* CONFIG_USER_ONLY */ | |
300 | ||
301 | /* Machine Information Registers */ | |
302 | static int read_zero(CPURISCVState *env, int csrno, target_ulong *val) | |
303 | { | |
304 | return *val = 0; | |
305 | } | |
306 | ||
307 | static int read_mhartid(CPURISCVState *env, int csrno, target_ulong *val) | |
308 | { | |
309 | *val = env->mhartid; | |
310 | return 0; | |
311 | } | |
312 | ||
313 | /* Machine Trap Setup */ | |
314 | static int read_mstatus(CPURISCVState *env, int csrno, target_ulong *val) | |
315 | { | |
316 | *val = env->mstatus; | |
317 | return 0; | |
318 | } | |
319 | ||
320 | static int validate_vm(CPURISCVState *env, target_ulong vm) | |
321 | { | |
322 | return (env->priv_ver >= PRIV_VERSION_1_10_0) ? | |
323 | valid_vm_1_10[vm & 0xf] : valid_vm_1_09[vm & 0xf]; | |
324 | } | |
325 | ||
326 | static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) | |
327 | { | |
328 | target_ulong mstatus = env->mstatus; | |
329 | target_ulong mask = 0; | |
b345b480 | 330 | int dirty; |
c7b95171 MC |
331 | |
332 | /* flush tlb on mstatus fields that affect VM */ | |
333 | if (env->priv_ver <= PRIV_VERSION_1_09_1) { | |
334 | if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | | |
335 | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_VM)) { | |
3109cd98 | 336 | tlb_flush(env_cpu(env)); |
c7b95171 MC |
337 | } |
338 | mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | | |
339 | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | | |
340 | MSTATUS_MPP | MSTATUS_MXR | | |
341 | (validate_vm(env, get_field(val, MSTATUS_VM)) ? | |
342 | MSTATUS_VM : 0); | |
343 | } | |
344 | if (env->priv_ver >= PRIV_VERSION_1_10_0) { | |
1f0419cb | 345 | if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | |
c7b95171 | 346 | MSTATUS_MPRV | MSTATUS_SUM)) { |
3109cd98 | 347 | tlb_flush(env_cpu(env)); |
c7b95171 MC |
348 | } |
349 | mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | | |
350 | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | | |
7f2b5ff1 MC |
351 | MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | |
352 | MSTATUS_TW; | |
1f0419cb AF |
353 | #if defined(TARGET_RISCV64) |
354 | /* | |
355 | * RV32: MPV and MTL are not in mstatus. The current plan is to | |
356 | * add them to mstatush. For now, we just don't support it. | |
357 | */ | |
14115b91 | 358 | mask |= MSTATUS_MTL | MSTATUS_MPV; |
1f0419cb | 359 | #endif |
c7b95171 MC |
360 | } |
361 | ||
362 | mstatus = (mstatus & ~mask) | (val & mask); | |
363 | ||
82f01467 | 364 | dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) | |
b345b480 | 365 | ((mstatus & MSTATUS_XS) == MSTATUS_XS); |
c7b95171 MC |
366 | mstatus = set_field(mstatus, MSTATUS_SD, dirty); |
367 | env->mstatus = mstatus; | |
368 | ||
369 | return 0; | |
370 | } | |
371 | ||
372 | static int read_misa(CPURISCVState *env, int csrno, target_ulong *val) | |
373 | { | |
374 | *val = env->misa; | |
375 | return 0; | |
376 | } | |
377 | ||
f18637cd MC |
378 | static int write_misa(CPURISCVState *env, int csrno, target_ulong val) |
379 | { | |
380 | if (!riscv_feature(env, RISCV_FEATURE_MISA)) { | |
381 | /* drop write to misa */ | |
382 | return 0; | |
383 | } | |
384 | ||
385 | /* 'I' or 'E' must be present */ | |
386 | if (!(val & (RVI | RVE))) { | |
387 | /* It is not, drop write to misa */ | |
388 | return 0; | |
389 | } | |
390 | ||
391 | /* 'E' excludes all other extensions */ | |
392 | if (val & RVE) { | |
393 | /* when we support 'E' we can do "val = RVE;" however | |
394 | * for now we just drop writes if 'E' is present. | |
395 | */ | |
396 | return 0; | |
397 | } | |
398 | ||
399 | /* Mask extensions that are not supported by this hart */ | |
400 | val &= env->misa_mask; | |
401 | ||
402 | /* Mask extensions that are not supported by QEMU */ | |
403 | val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU); | |
404 | ||
405 | /* 'D' depends on 'F', so clear 'D' if 'F' is not present */ | |
406 | if ((val & RVD) && !(val & RVF)) { | |
407 | val &= ~RVD; | |
408 | } | |
409 | ||
410 | /* Suppress 'C' if next instruction is not aligned | |
411 | * TODO: this should check next_pc | |
412 | */ | |
413 | if ((val & RVC) && (GETPC() & ~3) != 0) { | |
414 | val &= ~RVC; | |
415 | } | |
416 | ||
417 | /* misa.MXL writes are not supported by QEMU */ | |
418 | val = (env->misa & MISA_MXL) | (val & ~MISA_MXL); | |
419 | ||
420 | /* flush translation cache */ | |
421 | if (val != env->misa) { | |
3109cd98 | 422 | tb_flush(env_cpu(env)); |
f18637cd MC |
423 | } |
424 | ||
425 | env->misa = val; | |
426 | ||
427 | return 0; | |
428 | } | |
429 | ||
c7b95171 MC |
430 | static int read_medeleg(CPURISCVState *env, int csrno, target_ulong *val) |
431 | { | |
432 | *val = env->medeleg; | |
433 | return 0; | |
434 | } | |
435 | ||
436 | static int write_medeleg(CPURISCVState *env, int csrno, target_ulong val) | |
437 | { | |
438 | env->medeleg = (env->medeleg & ~delegable_excps) | (val & delegable_excps); | |
439 | return 0; | |
440 | } | |
441 | ||
442 | static int read_mideleg(CPURISCVState *env, int csrno, target_ulong *val) | |
443 | { | |
444 | *val = env->mideleg; | |
445 | return 0; | |
446 | } | |
447 | ||
448 | static int write_mideleg(CPURISCVState *env, int csrno, target_ulong val) | |
449 | { | |
450 | env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints); | |
451 | return 0; | |
452 | } | |
453 | ||
454 | static int read_mie(CPURISCVState *env, int csrno, target_ulong *val) | |
455 | { | |
456 | *val = env->mie; | |
457 | return 0; | |
458 | } | |
459 | ||
460 | static int write_mie(CPURISCVState *env, int csrno, target_ulong val) | |
461 | { | |
462 | env->mie = (env->mie & ~all_ints) | (val & all_ints); | |
463 | return 0; | |
464 | } | |
465 | ||
466 | static int read_mtvec(CPURISCVState *env, int csrno, target_ulong *val) | |
467 | { | |
468 | *val = env->mtvec; | |
469 | return 0; | |
470 | } | |
471 | ||
472 | static int write_mtvec(CPURISCVState *env, int csrno, target_ulong val) | |
473 | { | |
474 | /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ | |
acbbb94e MC |
475 | if ((val & 3) < 2) { |
476 | env->mtvec = val; | |
c7b95171 | 477 | } else { |
acbbb94e | 478 | qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n"); |
c7b95171 MC |
479 | } |
480 | return 0; | |
481 | } | |
482 | ||
483 | static int read_mcounteren(CPURISCVState *env, int csrno, target_ulong *val) | |
484 | { | |
485 | if (env->priv_ver < PRIV_VERSION_1_10_0) { | |
486 | return -1; | |
487 | } | |
488 | *val = env->mcounteren; | |
489 | return 0; | |
490 | } | |
491 | ||
492 | static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val) | |
493 | { | |
494 | if (env->priv_ver < PRIV_VERSION_1_10_0) { | |
495 | return -1; | |
496 | } | |
497 | env->mcounteren = val; | |
498 | return 0; | |
499 | } | |
500 | ||
747a43e8 | 501 | /* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ |
c7b95171 MC |
502 | static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val) |
503 | { | |
747a43e8 AF |
504 | if (env->priv_ver > PRIV_VERSION_1_09_1 |
505 | && env->priv_ver < PRIV_VERSION_1_11_0) { | |
c7b95171 MC |
506 | return -1; |
507 | } | |
508 | *val = env->mcounteren; | |
509 | return 0; | |
510 | } | |
511 | ||
747a43e8 | 512 | /* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ |
c7b95171 MC |
513 | static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val) |
514 | { | |
747a43e8 AF |
515 | if (env->priv_ver > PRIV_VERSION_1_09_1 |
516 | && env->priv_ver < PRIV_VERSION_1_11_0) { | |
c7b95171 MC |
517 | return -1; |
518 | } | |
519 | env->mcounteren = val; | |
520 | return 0; | |
521 | } | |
522 | ||
523 | static int read_mucounteren(CPURISCVState *env, int csrno, target_ulong *val) | |
524 | { | |
525 | if (env->priv_ver > PRIV_VERSION_1_09_1) { | |
526 | return -1; | |
527 | } | |
528 | *val = env->scounteren; | |
529 | return 0; | |
530 | } | |
531 | ||
532 | static int write_mucounteren(CPURISCVState *env, int csrno, target_ulong val) | |
533 | { | |
534 | if (env->priv_ver > PRIV_VERSION_1_09_1) { | |
535 | return -1; | |
536 | } | |
537 | env->scounteren = val; | |
538 | return 0; | |
539 | } | |
540 | ||
541 | /* Machine Trap Handling */ | |
542 | static int read_mscratch(CPURISCVState *env, int csrno, target_ulong *val) | |
543 | { | |
544 | *val = env->mscratch; | |
545 | return 0; | |
546 | } | |
547 | ||
548 | static int write_mscratch(CPURISCVState *env, int csrno, target_ulong val) | |
549 | { | |
550 | env->mscratch = val; | |
551 | return 0; | |
552 | } | |
553 | ||
554 | static int read_mepc(CPURISCVState *env, int csrno, target_ulong *val) | |
555 | { | |
556 | *val = env->mepc; | |
557 | return 0; | |
558 | } | |
559 | ||
560 | static int write_mepc(CPURISCVState *env, int csrno, target_ulong val) | |
561 | { | |
562 | env->mepc = val; | |
563 | return 0; | |
564 | } | |
565 | ||
566 | static int read_mcause(CPURISCVState *env, int csrno, target_ulong *val) | |
567 | { | |
568 | *val = env->mcause; | |
569 | return 0; | |
570 | } | |
571 | ||
572 | static int write_mcause(CPURISCVState *env, int csrno, target_ulong val) | |
573 | { | |
574 | env->mcause = val; | |
575 | return 0; | |
576 | } | |
577 | ||
578 | static int read_mbadaddr(CPURISCVState *env, int csrno, target_ulong *val) | |
579 | { | |
580 | *val = env->mbadaddr; | |
581 | return 0; | |
582 | } | |
583 | ||
584 | static int write_mbadaddr(CPURISCVState *env, int csrno, target_ulong val) | |
585 | { | |
586 | env->mbadaddr = val; | |
587 | return 0; | |
588 | } | |
589 | ||
71877e29 MC |
590 | static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value, |
591 | target_ulong new_value, target_ulong write_mask) | |
c7b95171 | 592 | { |
3109cd98 | 593 | RISCVCPU *cpu = env_archcpu(env); |
e3e7039c MC |
594 | /* Allow software control of delegable interrupts not claimed by hardware */ |
595 | target_ulong mask = write_mask & delegable_ints & ~env->miclaim; | |
71877e29 MC |
596 | uint32_t old_mip; |
597 | ||
71877e29 | 598 | if (mask) { |
71877e29 | 599 | old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask)); |
71877e29 | 600 | } else { |
7ec5d303 | 601 | old_mip = env->mip; |
71877e29 | 602 | } |
c7b95171 | 603 | |
71877e29 MC |
604 | if (ret_value) { |
605 | *ret_value = old_mip; | |
606 | } | |
c7b95171 MC |
607 | |
608 | return 0; | |
609 | } | |
610 | ||
611 | /* Supervisor Trap Setup */ | |
612 | static int read_sstatus(CPURISCVState *env, int csrno, target_ulong *val) | |
613 | { | |
614 | target_ulong mask = ((env->priv_ver >= PRIV_VERSION_1_10_0) ? | |
615 | sstatus_v1_10_mask : sstatus_v1_9_mask); | |
616 | *val = env->mstatus & mask; | |
617 | return 0; | |
618 | } | |
619 | ||
620 | static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val) | |
621 | { | |
622 | target_ulong mask = ((env->priv_ver >= PRIV_VERSION_1_10_0) ? | |
623 | sstatus_v1_10_mask : sstatus_v1_9_mask); | |
624 | target_ulong newval = (env->mstatus & ~mask) | (val & mask); | |
625 | return write_mstatus(env, CSR_MSTATUS, newval); | |
626 | } | |
627 | ||
628 | static int read_sie(CPURISCVState *env, int csrno, target_ulong *val) | |
629 | { | |
630 | *val = env->mie & env->mideleg; | |
631 | return 0; | |
632 | } | |
633 | ||
634 | static int write_sie(CPURISCVState *env, int csrno, target_ulong val) | |
635 | { | |
636 | target_ulong newval = (env->mie & ~env->mideleg) | (val & env->mideleg); | |
637 | return write_mie(env, CSR_MIE, newval); | |
638 | } | |
639 | ||
640 | static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val) | |
641 | { | |
642 | *val = env->stvec; | |
643 | return 0; | |
644 | } | |
645 | ||
646 | static int write_stvec(CPURISCVState *env, int csrno, target_ulong val) | |
647 | { | |
648 | /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ | |
acbbb94e MC |
649 | if ((val & 3) < 2) { |
650 | env->stvec = val; | |
c7b95171 | 651 | } else { |
acbbb94e | 652 | qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n"); |
c7b95171 MC |
653 | } |
654 | return 0; | |
655 | } | |
656 | ||
657 | static int read_scounteren(CPURISCVState *env, int csrno, target_ulong *val) | |
658 | { | |
659 | if (env->priv_ver < PRIV_VERSION_1_10_0) { | |
660 | return -1; | |
661 | } | |
662 | *val = env->scounteren; | |
663 | return 0; | |
664 | } | |
665 | ||
666 | static int write_scounteren(CPURISCVState *env, int csrno, target_ulong val) | |
667 | { | |
668 | if (env->priv_ver < PRIV_VERSION_1_10_0) { | |
669 | return -1; | |
670 | } | |
671 | env->scounteren = val; | |
672 | return 0; | |
673 | } | |
674 | ||
675 | /* Supervisor Trap Handling */ | |
676 | static int read_sscratch(CPURISCVState *env, int csrno, target_ulong *val) | |
677 | { | |
678 | *val = env->sscratch; | |
679 | return 0; | |
680 | } | |
681 | ||
682 | static int write_sscratch(CPURISCVState *env, int csrno, target_ulong val) | |
683 | { | |
684 | env->sscratch = val; | |
685 | return 0; | |
686 | } | |
687 | ||
688 | static int read_sepc(CPURISCVState *env, int csrno, target_ulong *val) | |
689 | { | |
690 | *val = env->sepc; | |
691 | return 0; | |
692 | } | |
693 | ||
694 | static int write_sepc(CPURISCVState *env, int csrno, target_ulong val) | |
695 | { | |
696 | env->sepc = val; | |
697 | return 0; | |
698 | } | |
699 | ||
700 | static int read_scause(CPURISCVState *env, int csrno, target_ulong *val) | |
701 | { | |
702 | *val = env->scause; | |
703 | return 0; | |
704 | } | |
705 | ||
706 | static int write_scause(CPURISCVState *env, int csrno, target_ulong val) | |
707 | { | |
708 | env->scause = val; | |
709 | return 0; | |
710 | } | |
711 | ||
712 | static int read_sbadaddr(CPURISCVState *env, int csrno, target_ulong *val) | |
713 | { | |
714 | *val = env->sbadaddr; | |
715 | return 0; | |
716 | } | |
717 | ||
718 | static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val) | |
719 | { | |
720 | env->sbadaddr = val; | |
721 | return 0; | |
722 | } | |
723 | ||
71877e29 MC |
724 | static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value, |
725 | target_ulong new_value, target_ulong write_mask) | |
c7b95171 | 726 | { |
087b051a JB |
727 | int ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value, |
728 | write_mask & env->mideleg & sip_writable_mask); | |
729 | *ret_value &= env->mideleg; | |
730 | return ret; | |
c7b95171 MC |
731 | } |
732 | ||
733 | /* Supervisor Protection and Translation */ | |
734 | static int read_satp(CPURISCVState *env, int csrno, target_ulong *val) | |
735 | { | |
736 | if (!riscv_feature(env, RISCV_FEATURE_MMU)) { | |
737 | *val = 0; | |
738 | } else if (env->priv_ver >= PRIV_VERSION_1_10_0) { | |
7f2b5ff1 MC |
739 | if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { |
740 | return -1; | |
741 | } else { | |
742 | *val = env->satp; | |
743 | } | |
c7b95171 MC |
744 | } else { |
745 | *val = env->sptbr; | |
746 | } | |
747 | return 0; | |
748 | } | |
749 | ||
750 | static int write_satp(CPURISCVState *env, int csrno, target_ulong val) | |
751 | { | |
752 | if (!riscv_feature(env, RISCV_FEATURE_MMU)) { | |
753 | return 0; | |
754 | } | |
755 | if (env->priv_ver <= PRIV_VERSION_1_09_1 && (val ^ env->sptbr)) { | |
3109cd98 | 756 | tlb_flush(env_cpu(env)); |
c7b95171 MC |
757 | env->sptbr = val & (((target_ulong) |
758 | 1 << (TARGET_PHYS_ADDR_SPACE_BITS - PGSHIFT)) - 1); | |
759 | } | |
760 | if (env->priv_ver >= PRIV_VERSION_1_10_0 && | |
761 | validate_vm(env, get_field(val, SATP_MODE)) && | |
762 | ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN))) | |
763 | { | |
7f2b5ff1 MC |
764 | if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { |
765 | return -1; | |
766 | } else { | |
1e0d985f | 767 | if((val ^ env->satp) & SATP_ASID) { |
3109cd98 | 768 | tlb_flush(env_cpu(env)); |
1e0d985f | 769 | } |
7f2b5ff1 MC |
770 | env->satp = val; |
771 | } | |
c7b95171 MC |
772 | } |
773 | return 0; | |
774 | } | |
775 | ||
ff2cc129 AF |
776 | /* Hypervisor Extensions */ |
777 | static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val) | |
778 | { | |
779 | *val = env->hstatus; | |
780 | return 0; | |
781 | } | |
782 | ||
783 | static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val) | |
784 | { | |
785 | env->hstatus = val; | |
786 | return 0; | |
787 | } | |
788 | ||
789 | static int read_hedeleg(CPURISCVState *env, int csrno, target_ulong *val) | |
790 | { | |
791 | *val = env->hedeleg; | |
792 | return 0; | |
793 | } | |
794 | ||
795 | static int write_hedeleg(CPURISCVState *env, int csrno, target_ulong val) | |
796 | { | |
797 | env->hedeleg = val; | |
798 | return 0; | |
799 | } | |
800 | ||
801 | static int read_hideleg(CPURISCVState *env, int csrno, target_ulong *val) | |
802 | { | |
803 | *val = env->hideleg; | |
804 | return 0; | |
805 | } | |
806 | ||
807 | static int write_hideleg(CPURISCVState *env, int csrno, target_ulong val) | |
808 | { | |
809 | env->hideleg = val; | |
810 | return 0; | |
811 | } | |
812 | ||
813 | static int rmw_hip(CPURISCVState *env, int csrno, target_ulong *ret_value, | |
814 | target_ulong new_value, target_ulong write_mask) | |
815 | { | |
816 | int ret = rmw_mip(env, 0, ret_value, new_value, | |
817 | write_mask & hip_writable_mask); | |
818 | ||
819 | return ret; | |
820 | } | |
821 | ||
822 | static int read_hie(CPURISCVState *env, int csrno, target_ulong *val) | |
823 | { | |
824 | *val = env->mie & VS_MODE_INTERRUPTS; | |
825 | return 0; | |
826 | } | |
827 | ||
828 | static int write_hie(CPURISCVState *env, int csrno, target_ulong val) | |
829 | { | |
830 | target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS); | |
831 | return write_mie(env, CSR_MIE, newval); | |
832 | } | |
833 | ||
834 | static int read_hcounteren(CPURISCVState *env, int csrno, target_ulong *val) | |
835 | { | |
836 | *val = env->hcounteren; | |
837 | return 0; | |
838 | } | |
839 | ||
840 | static int write_hcounteren(CPURISCVState *env, int csrno, target_ulong val) | |
841 | { | |
842 | env->hcounteren = val; | |
843 | return 0; | |
844 | } | |
845 | ||
846 | static int read_htval(CPURISCVState *env, int csrno, target_ulong *val) | |
847 | { | |
848 | *val = env->htval; | |
849 | return 0; | |
850 | } | |
851 | ||
852 | static int write_htval(CPURISCVState *env, int csrno, target_ulong val) | |
853 | { | |
854 | env->htval = val; | |
855 | return 0; | |
856 | } | |
857 | ||
858 | static int read_htinst(CPURISCVState *env, int csrno, target_ulong *val) | |
859 | { | |
860 | *val = env->htinst; | |
861 | return 0; | |
862 | } | |
863 | ||
864 | static int write_htinst(CPURISCVState *env, int csrno, target_ulong val) | |
865 | { | |
866 | env->htinst = val; | |
867 | return 0; | |
868 | } | |
869 | ||
870 | static int read_hgatp(CPURISCVState *env, int csrno, target_ulong *val) | |
871 | { | |
872 | *val = env->hgatp; | |
873 | return 0; | |
874 | } | |
875 | ||
876 | static int write_hgatp(CPURISCVState *env, int csrno, target_ulong val) | |
877 | { | |
878 | env->hgatp = val; | |
879 | return 0; | |
880 | } | |
881 | ||
8747c9ee AF |
882 | /* Virtual CSR Registers */ |
883 | static int read_vsstatus(CPURISCVState *env, int csrno, target_ulong *val) | |
884 | { | |
885 | *val = env->vsstatus; | |
886 | return 0; | |
887 | } | |
888 | ||
889 | static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val) | |
890 | { | |
891 | env->vsstatus = val; | |
892 | return 0; | |
893 | } | |
894 | ||
895 | static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value, | |
896 | target_ulong new_value, target_ulong write_mask) | |
897 | { | |
898 | int ret = rmw_mip(env, 0, ret_value, new_value, | |
899 | write_mask & env->mideleg & vsip_writable_mask); | |
900 | return ret; | |
901 | } | |
902 | ||
903 | static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val) | |
904 | { | |
905 | *val = env->mie & env->mideleg & VS_MODE_INTERRUPTS; | |
906 | return 0; | |
907 | } | |
908 | ||
909 | static int write_vsie(CPURISCVState *env, int csrno, target_ulong val) | |
910 | { | |
911 | target_ulong newval = (env->mie & ~env->mideleg) | (val & env->mideleg & MIP_VSSIP); | |
912 | return write_mie(env, CSR_MIE, newval); | |
913 | } | |
914 | ||
915 | static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val) | |
916 | { | |
917 | *val = env->vstvec; | |
918 | return 0; | |
919 | } | |
920 | ||
921 | static int write_vstvec(CPURISCVState *env, int csrno, target_ulong val) | |
922 | { | |
923 | env->vstvec = val; | |
924 | return 0; | |
925 | } | |
926 | ||
927 | static int read_vsscratch(CPURISCVState *env, int csrno, target_ulong *val) | |
928 | { | |
929 | *val = env->vsscratch; | |
930 | return 0; | |
931 | } | |
932 | ||
933 | static int write_vsscratch(CPURISCVState *env, int csrno, target_ulong val) | |
934 | { | |
935 | env->vsscratch = val; | |
936 | return 0; | |
937 | } | |
938 | ||
939 | static int read_vsepc(CPURISCVState *env, int csrno, target_ulong *val) | |
940 | { | |
941 | *val = env->vsepc; | |
942 | return 0; | |
943 | } | |
944 | ||
945 | static int write_vsepc(CPURISCVState *env, int csrno, target_ulong val) | |
946 | { | |
947 | env->vsepc = val; | |
948 | return 0; | |
949 | } | |
950 | ||
951 | static int read_vscause(CPURISCVState *env, int csrno, target_ulong *val) | |
952 | { | |
953 | *val = env->vscause; | |
954 | return 0; | |
955 | } | |
956 | ||
957 | static int write_vscause(CPURISCVState *env, int csrno, target_ulong val) | |
958 | { | |
959 | env->vscause = val; | |
960 | return 0; | |
961 | } | |
962 | ||
963 | static int read_vstval(CPURISCVState *env, int csrno, target_ulong *val) | |
964 | { | |
965 | *val = env->vstval; | |
966 | return 0; | |
967 | } | |
968 | ||
969 | static int write_vstval(CPURISCVState *env, int csrno, target_ulong val) | |
970 | { | |
971 | env->vstval = val; | |
972 | return 0; | |
973 | } | |
974 | ||
975 | static int read_vsatp(CPURISCVState *env, int csrno, target_ulong *val) | |
976 | { | |
977 | *val = env->vsatp; | |
978 | return 0; | |
979 | } | |
980 | ||
981 | static int write_vsatp(CPURISCVState *env, int csrno, target_ulong val) | |
982 | { | |
983 | env->vsatp = val; | |
984 | return 0; | |
985 | } | |
986 | ||
34cfb5f6 AF |
987 | static int read_mtval2(CPURISCVState *env, int csrno, target_ulong *val) |
988 | { | |
989 | *val = env->mtval2; | |
990 | return 0; | |
991 | } | |
992 | ||
993 | static int write_mtval2(CPURISCVState *env, int csrno, target_ulong val) | |
994 | { | |
995 | env->mtval2 = val; | |
996 | return 0; | |
997 | } | |
998 | ||
999 | static int read_mtinst(CPURISCVState *env, int csrno, target_ulong *val) | |
1000 | { | |
1001 | *val = env->mtinst; | |
1002 | return 0; | |
1003 | } | |
1004 | ||
1005 | static int write_mtinst(CPURISCVState *env, int csrno, target_ulong val) | |
1006 | { | |
1007 | env->mtinst = val; | |
1008 | return 0; | |
1009 | } | |
1010 | ||
c7b95171 MC |
1011 | /* Physical Memory Protection */ |
1012 | static int read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val) | |
1013 | { | |
1014 | *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0); | |
1015 | return 0; | |
1016 | } | |
1017 | ||
1018 | static int write_pmpcfg(CPURISCVState *env, int csrno, target_ulong val) | |
1019 | { | |
1020 | pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val); | |
1021 | return 0; | |
1022 | } | |
1023 | ||
1024 | static int read_pmpaddr(CPURISCVState *env, int csrno, target_ulong *val) | |
1025 | { | |
1026 | *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0); | |
1027 | return 0; | |
1028 | } | |
1029 | ||
1030 | static int write_pmpaddr(CPURISCVState *env, int csrno, target_ulong val) | |
1031 | { | |
1032 | pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val); | |
1033 | return 0; | |
1034 | } | |
1035 | ||
1036 | #endif | |
1037 | ||
1038 | /* | |
1039 | * riscv_csrrw - read and/or update control and status register | |
1040 | * | |
1041 | * csrr <-> riscv_csrrw(env, csrno, ret_value, 0, 0); | |
1042 | * csrrw <-> riscv_csrrw(env, csrno, ret_value, value, -1); | |
1043 | * csrrs <-> riscv_csrrw(env, csrno, ret_value, -1, value); | |
1044 | * csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value); | |
1045 | */ | |
1046 | ||
1047 | int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, | |
1048 | target_ulong new_value, target_ulong write_mask) | |
1049 | { | |
1050 | int ret; | |
1051 | target_ulong old_value; | |
591bddea | 1052 | RISCVCPU *cpu = env_archcpu(env); |
c7b95171 MC |
1053 | |
1054 | /* check privileges and return -1 if check fails */ | |
1055 | #if !defined(CONFIG_USER_ONLY) | |
0a42f4c4 | 1056 | int effective_priv = env->priv; |
c7b95171 | 1057 | int read_only = get_field(csrno, 0xC00) == 3; |
0a42f4c4 AF |
1058 | |
1059 | if (riscv_has_ext(env, RVH) && | |
1060 | env->priv == PRV_S && | |
1061 | !riscv_cpu_virt_enabled(env)) { | |
1062 | /* | |
1063 | * We are in S mode without virtualisation, therefore we are in HS Mode. | |
1064 | * Add 1 to the effective privledge level to allow us to access the | |
1065 | * Hypervisor CSRs. | |
1066 | */ | |
1067 | effective_priv++; | |
e6e03dcf | 1068 | } |
0a42f4c4 AF |
1069 | |
1070 | if ((write_mask && read_only) || | |
1071 | (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) { | |
c7b95171 MC |
1072 | return -1; |
1073 | } | |
1074 | #endif | |
1075 | ||
591bddea PD |
1076 | /* ensure the CSR extension is enabled. */ |
1077 | if (!cpu->cfg.ext_icsr) { | |
1078 | return -1; | |
1079 | } | |
1080 | ||
a88365c1 MC |
1081 | /* check predicate */ |
1082 | if (!csr_ops[csrno].predicate || csr_ops[csrno].predicate(env, csrno) < 0) { | |
1083 | return -1; | |
1084 | } | |
1085 | ||
c7b95171 MC |
1086 | /* execute combined read/write operation if it exists */ |
1087 | if (csr_ops[csrno].op) { | |
1088 | return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask); | |
1089 | } | |
1090 | ||
1091 | /* if no accessor exists then return failure */ | |
1092 | if (!csr_ops[csrno].read) { | |
1093 | return -1; | |
1094 | } | |
1095 | ||
1096 | /* read old value */ | |
1097 | ret = csr_ops[csrno].read(env, csrno, &old_value); | |
1098 | if (ret < 0) { | |
1099 | return ret; | |
1100 | } | |
1101 | ||
1102 | /* write value if writable and write mask set, otherwise drop writes */ | |
1103 | if (write_mask) { | |
1104 | new_value = (old_value & ~write_mask) | (new_value & write_mask); | |
1105 | if (csr_ops[csrno].write) { | |
1106 | ret = csr_ops[csrno].write(env, csrno, new_value); | |
1107 | if (ret < 0) { | |
1108 | return ret; | |
1109 | } | |
1110 | } | |
1111 | } | |
1112 | ||
1113 | /* return old value */ | |
1114 | if (ret_value) { | |
1115 | *ret_value = old_value; | |
1116 | } | |
1117 | ||
1118 | return 0; | |
1119 | } | |
1120 | ||
753e3fe2 JW |
1121 | /* |
1122 | * Debugger support. If not in user mode, set env->debugger before the | |
1123 | * riscv_csrrw call and clear it after the call. | |
1124 | */ | |
1125 | int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value, | |
1126 | target_ulong new_value, target_ulong write_mask) | |
1127 | { | |
1128 | int ret; | |
1129 | #if !defined(CONFIG_USER_ONLY) | |
1130 | env->debugger = true; | |
1131 | #endif | |
1132 | ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask); | |
1133 | #if !defined(CONFIG_USER_ONLY) | |
1134 | env->debugger = false; | |
1135 | #endif | |
1136 | return ret; | |
1137 | } | |
1138 | ||
c7b95171 MC |
1139 | /* Control and Status Register function table */ |
1140 | static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { | |
1141 | /* User Floating-Point CSRs */ | |
a88365c1 MC |
1142 | [CSR_FFLAGS] = { fs, read_fflags, write_fflags }, |
1143 | [CSR_FRM] = { fs, read_frm, write_frm }, | |
1144 | [CSR_FCSR] = { fs, read_fcsr, write_fcsr }, | |
c7b95171 MC |
1145 | |
1146 | /* User Timers and Counters */ | |
a88365c1 MC |
1147 | [CSR_CYCLE] = { ctr, read_instret }, |
1148 | [CSR_INSTRET] = { ctr, read_instret }, | |
c7b95171 | 1149 | #if defined(TARGET_RISCV32) |
a88365c1 MC |
1150 | [CSR_CYCLEH] = { ctr, read_instreth }, |
1151 | [CSR_INSTRETH] = { ctr, read_instreth }, | |
c7b95171 MC |
1152 | #endif |
1153 | ||
1154 | /* User-level time CSRs are only available in linux-user | |
1155 | * In privileged mode, the monitor emulates these CSRs */ | |
1156 | #if defined(CONFIG_USER_ONLY) | |
a88365c1 | 1157 | [CSR_TIME] = { ctr, read_time }, |
c7b95171 | 1158 | #if defined(TARGET_RISCV32) |
a88365c1 | 1159 | [CSR_TIMEH] = { ctr, read_timeh }, |
c7b95171 MC |
1160 | #endif |
1161 | #endif | |
1162 | ||
1163 | #if !defined(CONFIG_USER_ONLY) | |
1164 | /* Machine Timers and Counters */ | |
a88365c1 MC |
1165 | [CSR_MCYCLE] = { any, read_instret }, |
1166 | [CSR_MINSTRET] = { any, read_instret }, | |
c7b95171 | 1167 | #if defined(TARGET_RISCV32) |
a88365c1 MC |
1168 | [CSR_MCYCLEH] = { any, read_instreth }, |
1169 | [CSR_MINSTRETH] = { any, read_instreth }, | |
c7b95171 MC |
1170 | #endif |
1171 | ||
1172 | /* Machine Information Registers */ | |
a88365c1 MC |
1173 | [CSR_MVENDORID] = { any, read_zero }, |
1174 | [CSR_MARCHID] = { any, read_zero }, | |
1175 | [CSR_MIMPID] = { any, read_zero }, | |
1176 | [CSR_MHARTID] = { any, read_mhartid }, | |
c7b95171 MC |
1177 | |
1178 | /* Machine Trap Setup */ | |
a88365c1 | 1179 | [CSR_MSTATUS] = { any, read_mstatus, write_mstatus }, |
f18637cd | 1180 | [CSR_MISA] = { any, read_misa, write_misa }, |
a88365c1 MC |
1181 | [CSR_MIDELEG] = { any, read_mideleg, write_mideleg }, |
1182 | [CSR_MEDELEG] = { any, read_medeleg, write_medeleg }, | |
1183 | [CSR_MIE] = { any, read_mie, write_mie }, | |
1184 | [CSR_MTVEC] = { any, read_mtvec, write_mtvec }, | |
1185 | [CSR_MCOUNTEREN] = { any, read_mcounteren, write_mcounteren }, | |
c7b95171 MC |
1186 | |
1187 | /* Legacy Counter Setup (priv v1.9.1) */ | |
a88365c1 MC |
1188 | [CSR_MUCOUNTEREN] = { any, read_mucounteren, write_mucounteren }, |
1189 | [CSR_MSCOUNTEREN] = { any, read_mscounteren, write_mscounteren }, | |
c7b95171 MC |
1190 | |
1191 | /* Machine Trap Handling */ | |
a88365c1 MC |
1192 | [CSR_MSCRATCH] = { any, read_mscratch, write_mscratch }, |
1193 | [CSR_MEPC] = { any, read_mepc, write_mepc }, | |
1194 | [CSR_MCAUSE] = { any, read_mcause, write_mcause }, | |
1195 | [CSR_MBADADDR] = { any, read_mbadaddr, write_mbadaddr }, | |
1196 | [CSR_MIP] = { any, NULL, NULL, rmw_mip }, | |
c7b95171 MC |
1197 | |
1198 | /* Supervisor Trap Setup */ | |
a88365c1 MC |
1199 | [CSR_SSTATUS] = { smode, read_sstatus, write_sstatus }, |
1200 | [CSR_SIE] = { smode, read_sie, write_sie }, | |
1201 | [CSR_STVEC] = { smode, read_stvec, write_stvec }, | |
1202 | [CSR_SCOUNTEREN] = { smode, read_scounteren, write_scounteren }, | |
c7b95171 MC |
1203 | |
1204 | /* Supervisor Trap Handling */ | |
a88365c1 MC |
1205 | [CSR_SSCRATCH] = { smode, read_sscratch, write_sscratch }, |
1206 | [CSR_SEPC] = { smode, read_sepc, write_sepc }, | |
1207 | [CSR_SCAUSE] = { smode, read_scause, write_scause }, | |
1208 | [CSR_SBADADDR] = { smode, read_sbadaddr, write_sbadaddr }, | |
1209 | [CSR_SIP] = { smode, NULL, NULL, rmw_sip }, | |
c7b95171 MC |
1210 | |
1211 | /* Supervisor Protection and Translation */ | |
a88365c1 | 1212 | [CSR_SATP] = { smode, read_satp, write_satp }, |
c7b95171 | 1213 | |
ff2cc129 AF |
1214 | [CSR_HSTATUS] = { hmode, read_hstatus, write_hstatus }, |
1215 | [CSR_HEDELEG] = { hmode, read_hedeleg, write_hedeleg }, | |
1216 | [CSR_HIDELEG] = { hmode, read_hideleg, write_hideleg }, | |
1217 | [CSR_HIP] = { hmode, NULL, NULL, rmw_hip }, | |
1218 | [CSR_HIE] = { hmode, read_hie, write_hie }, | |
1219 | [CSR_HCOUNTEREN] = { hmode, read_hcounteren, write_hcounteren }, | |
1220 | [CSR_HTVAL] = { hmode, read_htval, write_htval }, | |
1221 | [CSR_HTINST] = { hmode, read_htinst, write_htinst }, | |
1222 | [CSR_HGATP] = { hmode, read_hgatp, write_hgatp }, | |
1223 | ||
8747c9ee AF |
1224 | [CSR_VSSTATUS] = { hmode, read_vsstatus, write_vsstatus }, |
1225 | [CSR_VSIP] = { hmode, NULL, NULL, rmw_vsip }, | |
1226 | [CSR_VSIE] = { hmode, read_vsie, write_vsie }, | |
1227 | [CSR_VSTVEC] = { hmode, read_vstvec, write_vstvec }, | |
1228 | [CSR_VSSCRATCH] = { hmode, read_vsscratch, write_vsscratch }, | |
1229 | [CSR_VSEPC] = { hmode, read_vsepc, write_vsepc }, | |
1230 | [CSR_VSCAUSE] = { hmode, read_vscause, write_vscause }, | |
1231 | [CSR_VSTVAL] = { hmode, read_vstval, write_vstval }, | |
1232 | [CSR_VSATP] = { hmode, read_vsatp, write_vsatp }, | |
1233 | ||
34cfb5f6 AF |
1234 | [CSR_MTVAL2] = { hmode, read_mtval2, write_mtval2 }, |
1235 | [CSR_MTINST] = { hmode, read_mtinst, write_mtinst }, | |
1236 | ||
c7b95171 | 1237 | /* Physical Memory Protection */ |
a88365c1 MC |
1238 | [CSR_PMPCFG0 ... CSR_PMPADDR9] = { pmp, read_pmpcfg, write_pmpcfg }, |
1239 | [CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr }, | |
c7b95171 MC |
1240 | |
1241 | /* Performance Counters */ | |
a88365c1 MC |
1242 | [CSR_HPMCOUNTER3 ... CSR_HPMCOUNTER31] = { ctr, read_zero }, |
1243 | [CSR_MHPMCOUNTER3 ... CSR_MHPMCOUNTER31] = { any, read_zero }, | |
1244 | [CSR_MHPMEVENT3 ... CSR_MHPMEVENT31] = { any, read_zero }, | |
c7b95171 | 1245 | #if defined(TARGET_RISCV32) |
a88365c1 MC |
1246 | [CSR_HPMCOUNTER3H ... CSR_HPMCOUNTER31H] = { ctr, read_zero }, |
1247 | [CSR_MHPMCOUNTER3H ... CSR_MHPMCOUNTER31H] = { any, read_zero }, | |
c7b95171 MC |
1248 | #endif |
1249 | #endif /* !CONFIG_USER_ONLY */ | |
1250 | }; |