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c7b95171 MC |
1 | /* |
2 | * RISC-V Control and Status Registers. | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017-2018 SiFive, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2 or later, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
21 | #include "qemu/log.h" | |
22 | #include "cpu.h" | |
23 | #include "qemu/main-loop.h" | |
24 | #include "exec/exec-all.h" | |
25 | ||
c7b95171 MC |
26 | /* CSR function table public API */ |
27 | void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) | |
28 | { | |
29 | *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)]; | |
30 | } | |
31 | ||
32 | void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) | |
33 | { | |
34 | csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops; | |
35 | } | |
36 | ||
a88365c1 | 37 | /* Predicates */ |
0e62f92e | 38 | static RISCVException fs(CPURISCVState *env, int csrno) |
a88365c1 MC |
39 | { |
40 | #if !defined(CONFIG_USER_ONLY) | |
b345b480 | 41 | if (!env->debugger && !riscv_cpu_fp_enabled(env)) { |
0e62f92e | 42 | return RISCV_EXCP_ILLEGAL_INST; |
a88365c1 MC |
43 | } |
44 | #endif | |
0e62f92e | 45 | return RISCV_EXCP_NONE; |
a88365c1 MC |
46 | } |
47 | ||
0e62f92e | 48 | static RISCVException vs(CPURISCVState *env, int csrno) |
8e3a1f18 | 49 | { |
b4a99d40 FC |
50 | CPUState *cs = env_cpu(env); |
51 | RISCVCPU *cpu = RISCV_CPU(cs); | |
52 | ||
53 | if (env->misa_ext & RVV || | |
32e579b8 | 54 | cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) { |
6bc3dfa9 FC |
55 | #if !defined(CONFIG_USER_ONLY) |
56 | if (!env->debugger && !riscv_cpu_vector_enabled(env)) { | |
57 | return RISCV_EXCP_ILLEGAL_INST; | |
58 | } | |
59 | #endif | |
0e62f92e | 60 | return RISCV_EXCP_NONE; |
8e3a1f18 | 61 | } |
0e62f92e | 62 | return RISCV_EXCP_ILLEGAL_INST; |
8e3a1f18 LZ |
63 | } |
64 | ||
0e62f92e | 65 | static RISCVException ctr(CPURISCVState *env, int csrno) |
a88365c1 MC |
66 | { |
67 | #if !defined(CONFIG_USER_ONLY) | |
0a13a5b8 AF |
68 | CPUState *cs = env_cpu(env); |
69 | RISCVCPU *cpu = RISCV_CPU(cs); | |
0a13a5b8 AF |
70 | |
71 | if (!cpu->cfg.ext_counters) { | |
72 | /* The Counters extensions is not enabled */ | |
0e62f92e | 73 | return RISCV_EXCP_ILLEGAL_INST; |
0a13a5b8 | 74 | } |
e39a8320 AF |
75 | |
76 | if (riscv_cpu_virt_enabled(env)) { | |
77 | switch (csrno) { | |
78 | case CSR_CYCLE: | |
db70794e BM |
79 | if (!get_field(env->hcounteren, COUNTEREN_CY) && |
80 | get_field(env->mcounteren, COUNTEREN_CY)) { | |
0e62f92e | 81 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
e39a8320 AF |
82 | } |
83 | break; | |
84 | case CSR_TIME: | |
db70794e BM |
85 | if (!get_field(env->hcounteren, COUNTEREN_TM) && |
86 | get_field(env->mcounteren, COUNTEREN_TM)) { | |
0e62f92e | 87 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
e39a8320 AF |
88 | } |
89 | break; | |
90 | case CSR_INSTRET: | |
db70794e BM |
91 | if (!get_field(env->hcounteren, COUNTEREN_IR) && |
92 | get_field(env->mcounteren, COUNTEREN_IR)) { | |
0e62f92e | 93 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
e39a8320 AF |
94 | } |
95 | break; | |
96 | case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: | |
97 | if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) && | |
98 | get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) { | |
0e62f92e | 99 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
e39a8320 AF |
100 | } |
101 | break; | |
8987cdc4 | 102 | } |
db23e5d9 | 103 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
8987cdc4 AF |
104 | switch (csrno) { |
105 | case CSR_CYCLEH: | |
db70794e BM |
106 | if (!get_field(env->hcounteren, COUNTEREN_CY) && |
107 | get_field(env->mcounteren, COUNTEREN_CY)) { | |
0e62f92e | 108 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
8987cdc4 AF |
109 | } |
110 | break; | |
111 | case CSR_TIMEH: | |
db70794e BM |
112 | if (!get_field(env->hcounteren, COUNTEREN_TM) && |
113 | get_field(env->mcounteren, COUNTEREN_TM)) { | |
0e62f92e | 114 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
8987cdc4 AF |
115 | } |
116 | break; | |
117 | case CSR_INSTRETH: | |
db70794e BM |
118 | if (!get_field(env->hcounteren, COUNTEREN_IR) && |
119 | get_field(env->mcounteren, COUNTEREN_IR)) { | |
0e62f92e | 120 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
8987cdc4 AF |
121 | } |
122 | break; | |
123 | case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: | |
124 | if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) && | |
125 | get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) { | |
0e62f92e | 126 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
8987cdc4 AF |
127 | } |
128 | break; | |
e39a8320 | 129 | } |
e39a8320 AF |
130 | } |
131 | } | |
a88365c1 | 132 | #endif |
0e62f92e | 133 | return RISCV_EXCP_NONE; |
a88365c1 MC |
134 | } |
135 | ||
0e62f92e | 136 | static RISCVException ctr32(CPURISCVState *env, int csrno) |
8987cdc4 | 137 | { |
db23e5d9 | 138 | if (riscv_cpu_mxl(env) != MXL_RV32) { |
0e62f92e | 139 | return RISCV_EXCP_ILLEGAL_INST; |
8987cdc4 AF |
140 | } |
141 | ||
142 | return ctr(env, csrno); | |
143 | } | |
144 | ||
a88365c1 | 145 | #if !defined(CONFIG_USER_ONLY) |
0e62f92e | 146 | static RISCVException any(CPURISCVState *env, int csrno) |
a88365c1 | 147 | { |
0e62f92e | 148 | return RISCV_EXCP_NONE; |
a88365c1 MC |
149 | } |
150 | ||
0e62f92e | 151 | static RISCVException any32(CPURISCVState *env, int csrno) |
8987cdc4 | 152 | { |
db23e5d9 | 153 | if (riscv_cpu_mxl(env) != MXL_RV32) { |
0e62f92e | 154 | return RISCV_EXCP_ILLEGAL_INST; |
8987cdc4 AF |
155 | } |
156 | ||
157 | return any(env, csrno); | |
158 | ||
159 | } | |
160 | ||
0e62f92e | 161 | static RISCVException smode(CPURISCVState *env, int csrno) |
a88365c1 | 162 | { |
0e62f92e AF |
163 | if (riscv_has_ext(env, RVS)) { |
164 | return RISCV_EXCP_NONE; | |
165 | } | |
166 | ||
167 | return RISCV_EXCP_ILLEGAL_INST; | |
a88365c1 MC |
168 | } |
169 | ||
0e62f92e | 170 | static RISCVException hmode(CPURISCVState *env, int csrno) |
ff2cc129 AF |
171 | { |
172 | if (riscv_has_ext(env, RVS) && | |
173 | riscv_has_ext(env, RVH)) { | |
174 | /* Hypervisor extension is supported */ | |
175 | if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || | |
176 | env->priv == PRV_M) { | |
0e62f92e | 177 | return RISCV_EXCP_NONE; |
e39a8320 | 178 | } else { |
0e62f92e | 179 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |
ff2cc129 AF |
180 | } |
181 | } | |
182 | ||
0e62f92e | 183 | return RISCV_EXCP_ILLEGAL_INST; |
ff2cc129 AF |
184 | } |
185 | ||
0e62f92e | 186 | static RISCVException hmode32(CPURISCVState *env, int csrno) |
8987cdc4 | 187 | { |
db23e5d9 | 188 | if (riscv_cpu_mxl(env) != MXL_RV32) { |
d6f20dac AF |
189 | if (riscv_cpu_virt_enabled(env)) { |
190 | return RISCV_EXCP_ILLEGAL_INST; | |
191 | } else { | |
192 | return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; | |
193 | } | |
8987cdc4 AF |
194 | } |
195 | ||
196 | return hmode(env, csrno); | |
197 | ||
198 | } | |
199 | ||
4bbe8033 AB |
200 | /* Checks if PointerMasking registers could be accessed */ |
201 | static RISCVException pointer_masking(CPURISCVState *env, int csrno) | |
202 | { | |
203 | /* Check if j-ext is present */ | |
204 | if (riscv_has_ext(env, RVJ)) { | |
205 | return RISCV_EXCP_NONE; | |
206 | } | |
207 | return RISCV_EXCP_ILLEGAL_INST; | |
208 | } | |
209 | ||
0e62f92e | 210 | static RISCVException pmp(CPURISCVState *env, int csrno) |
a88365c1 | 211 | { |
0e62f92e AF |
212 | if (riscv_feature(env, RISCV_FEATURE_PMP)) { |
213 | return RISCV_EXCP_NONE; | |
214 | } | |
215 | ||
216 | return RISCV_EXCP_ILLEGAL_INST; | |
a88365c1 | 217 | } |
2582a95c HW |
218 | |
219 | static RISCVException epmp(CPURISCVState *env, int csrno) | |
220 | { | |
221 | if (env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) { | |
222 | return RISCV_EXCP_NONE; | |
223 | } | |
224 | ||
225 | return RISCV_EXCP_ILLEGAL_INST; | |
226 | } | |
a88365c1 MC |
227 | #endif |
228 | ||
c7b95171 | 229 | /* User Floating-Point CSRs */ |
605def6e AF |
230 | static RISCVException read_fflags(CPURISCVState *env, int csrno, |
231 | target_ulong *val) | |
c7b95171 | 232 | { |
fb738839 | 233 | *val = riscv_cpu_get_fflags(env); |
605def6e | 234 | return RISCV_EXCP_NONE; |
c7b95171 MC |
235 | } |
236 | ||
605def6e AF |
237 | static RISCVException write_fflags(CPURISCVState *env, int csrno, |
238 | target_ulong val) | |
c7b95171 MC |
239 | { |
240 | #if !defined(CONFIG_USER_ONLY) | |
c7b95171 MC |
241 | env->mstatus |= MSTATUS_FS; |
242 | #endif | |
fb738839 | 243 | riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT)); |
605def6e | 244 | return RISCV_EXCP_NONE; |
c7b95171 MC |
245 | } |
246 | ||
605def6e AF |
247 | static RISCVException read_frm(CPURISCVState *env, int csrno, |
248 | target_ulong *val) | |
c7b95171 | 249 | { |
c7b95171 | 250 | *val = env->frm; |
605def6e | 251 | return RISCV_EXCP_NONE; |
c7b95171 MC |
252 | } |
253 | ||
605def6e AF |
254 | static RISCVException write_frm(CPURISCVState *env, int csrno, |
255 | target_ulong val) | |
c7b95171 MC |
256 | { |
257 | #if !defined(CONFIG_USER_ONLY) | |
c7b95171 MC |
258 | env->mstatus |= MSTATUS_FS; |
259 | #endif | |
260 | env->frm = val & (FSR_RD >> FSR_RD_SHIFT); | |
605def6e | 261 | return RISCV_EXCP_NONE; |
c7b95171 MC |
262 | } |
263 | ||
605def6e AF |
264 | static RISCVException read_fcsr(CPURISCVState *env, int csrno, |
265 | target_ulong *val) | |
c7b95171 | 266 | { |
fb738839 | 267 | *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) |
c7b95171 | 268 | | (env->frm << FSR_RD_SHIFT); |
605def6e | 269 | return RISCV_EXCP_NONE; |
c7b95171 MC |
270 | } |
271 | ||
605def6e AF |
272 | static RISCVException write_fcsr(CPURISCVState *env, int csrno, |
273 | target_ulong val) | |
c7b95171 MC |
274 | { |
275 | #if !defined(CONFIG_USER_ONLY) | |
c7b95171 MC |
276 | env->mstatus |= MSTATUS_FS; |
277 | #endif | |
278 | env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; | |
fb738839 | 279 | riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT); |
605def6e | 280 | return RISCV_EXCP_NONE; |
c7b95171 MC |
281 | } |
282 | ||
605def6e AF |
283 | static RISCVException read_vtype(CPURISCVState *env, int csrno, |
284 | target_ulong *val) | |
8e3a1f18 LZ |
285 | { |
286 | *val = env->vtype; | |
605def6e | 287 | return RISCV_EXCP_NONE; |
8e3a1f18 LZ |
288 | } |
289 | ||
605def6e AF |
290 | static RISCVException read_vl(CPURISCVState *env, int csrno, |
291 | target_ulong *val) | |
8e3a1f18 LZ |
292 | { |
293 | *val = env->vl; | |
605def6e | 294 | return RISCV_EXCP_NONE; |
8e3a1f18 LZ |
295 | } |
296 | ||
2e565054 GH |
297 | static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val) |
298 | { | |
299 | *val = env_archcpu(env)->cfg.vlen >> 3; | |
300 | return RISCV_EXCP_NONE; | |
301 | } | |
302 | ||
605def6e AF |
303 | static RISCVException read_vxrm(CPURISCVState *env, int csrno, |
304 | target_ulong *val) | |
8e3a1f18 LZ |
305 | { |
306 | *val = env->vxrm; | |
605def6e | 307 | return RISCV_EXCP_NONE; |
8e3a1f18 LZ |
308 | } |
309 | ||
605def6e AF |
310 | static RISCVException write_vxrm(CPURISCVState *env, int csrno, |
311 | target_ulong val) | |
8e3a1f18 | 312 | { |
61b4b69d LZ |
313 | #if !defined(CONFIG_USER_ONLY) |
314 | env->mstatus |= MSTATUS_VS; | |
315 | #endif | |
8e3a1f18 | 316 | env->vxrm = val; |
605def6e | 317 | return RISCV_EXCP_NONE; |
8e3a1f18 LZ |
318 | } |
319 | ||
605def6e AF |
320 | static RISCVException read_vxsat(CPURISCVState *env, int csrno, |
321 | target_ulong *val) | |
8e3a1f18 LZ |
322 | { |
323 | *val = env->vxsat; | |
605def6e | 324 | return RISCV_EXCP_NONE; |
8e3a1f18 LZ |
325 | } |
326 | ||
605def6e AF |
327 | static RISCVException write_vxsat(CPURISCVState *env, int csrno, |
328 | target_ulong val) | |
8e3a1f18 | 329 | { |
61b4b69d LZ |
330 | #if !defined(CONFIG_USER_ONLY) |
331 | env->mstatus |= MSTATUS_VS; | |
332 | #endif | |
8e3a1f18 | 333 | env->vxsat = val; |
605def6e | 334 | return RISCV_EXCP_NONE; |
8e3a1f18 LZ |
335 | } |
336 | ||
605def6e AF |
337 | static RISCVException read_vstart(CPURISCVState *env, int csrno, |
338 | target_ulong *val) | |
8e3a1f18 LZ |
339 | { |
340 | *val = env->vstart; | |
605def6e | 341 | return RISCV_EXCP_NONE; |
8e3a1f18 LZ |
342 | } |
343 | ||
605def6e AF |
344 | static RISCVException write_vstart(CPURISCVState *env, int csrno, |
345 | target_ulong val) | |
8e3a1f18 | 346 | { |
61b4b69d LZ |
347 | #if !defined(CONFIG_USER_ONLY) |
348 | env->mstatus |= MSTATUS_VS; | |
349 | #endif | |
f714361e FC |
350 | /* |
351 | * The vstart CSR is defined to have only enough writable bits | |
352 | * to hold the largest element index, i.e. lg2(VLEN) bits. | |
353 | */ | |
354 | env->vstart = val & ~(~0ULL << ctzl(env_archcpu(env)->cfg.vlen)); | |
605def6e | 355 | return RISCV_EXCP_NONE; |
8e3a1f18 LZ |
356 | } |
357 | ||
4594fa5a LZ |
358 | static int read_vcsr(CPURISCVState *env, int csrno, target_ulong *val) |
359 | { | |
360 | *val = (env->vxrm << VCSR_VXRM_SHIFT) | (env->vxsat << VCSR_VXSAT_SHIFT); | |
361 | return RISCV_EXCP_NONE; | |
362 | } | |
363 | ||
364 | static int write_vcsr(CPURISCVState *env, int csrno, target_ulong val) | |
365 | { | |
366 | #if !defined(CONFIG_USER_ONLY) | |
367 | env->mstatus |= MSTATUS_VS; | |
368 | #endif | |
369 | env->vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT; | |
370 | env->vxsat = (val & VCSR_VXSAT) >> VCSR_VXSAT_SHIFT; | |
371 | return RISCV_EXCP_NONE; | |
372 | } | |
373 | ||
c7b95171 | 374 | /* User Timers and Counters */ |
605def6e AF |
375 | static RISCVException read_instret(CPURISCVState *env, int csrno, |
376 | target_ulong *val) | |
c7b95171 | 377 | { |
c7b95171 | 378 | #if !defined(CONFIG_USER_ONLY) |
740b1759 | 379 | if (icount_enabled()) { |
8191d368 | 380 | *val = icount_get(); |
c7b95171 MC |
381 | } else { |
382 | *val = cpu_get_host_ticks(); | |
383 | } | |
384 | #else | |
385 | *val = cpu_get_host_ticks(); | |
386 | #endif | |
605def6e | 387 | return RISCV_EXCP_NONE; |
c7b95171 MC |
388 | } |
389 | ||
605def6e AF |
390 | static RISCVException read_instreth(CPURISCVState *env, int csrno, |
391 | target_ulong *val) | |
c7b95171 | 392 | { |
c7b95171 | 393 | #if !defined(CONFIG_USER_ONLY) |
740b1759 | 394 | if (icount_enabled()) { |
8191d368 | 395 | *val = icount_get() >> 32; |
c7b95171 MC |
396 | } else { |
397 | *val = cpu_get_host_ticks() >> 32; | |
398 | } | |
399 | #else | |
400 | *val = cpu_get_host_ticks() >> 32; | |
401 | #endif | |
605def6e | 402 | return RISCV_EXCP_NONE; |
c7b95171 | 403 | } |
c7b95171 MC |
404 | |
405 | #if defined(CONFIG_USER_ONLY) | |
605def6e AF |
406 | static RISCVException read_time(CPURISCVState *env, int csrno, |
407 | target_ulong *val) | |
c7b95171 MC |
408 | { |
409 | *val = cpu_get_host_ticks(); | |
605def6e | 410 | return RISCV_EXCP_NONE; |
c7b95171 MC |
411 | } |
412 | ||
605def6e AF |
413 | static RISCVException read_timeh(CPURISCVState *env, int csrno, |
414 | target_ulong *val) | |
c7b95171 MC |
415 | { |
416 | *val = cpu_get_host_ticks() >> 32; | |
605def6e | 417 | return RISCV_EXCP_NONE; |
c7b95171 | 418 | } |
c7b95171 MC |
419 | |
420 | #else /* CONFIG_USER_ONLY */ | |
421 | ||
605def6e AF |
422 | static RISCVException read_time(CPURISCVState *env, int csrno, |
423 | target_ulong *val) | |
c6957248 AP |
424 | { |
425 | uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; | |
426 | ||
427 | if (!env->rdtime_fn) { | |
605def6e | 428 | return RISCV_EXCP_ILLEGAL_INST; |
c6957248 AP |
429 | } |
430 | ||
a47ef6e9 | 431 | *val = env->rdtime_fn(env->rdtime_fn_arg) + delta; |
605def6e | 432 | return RISCV_EXCP_NONE; |
c6957248 AP |
433 | } |
434 | ||
605def6e AF |
435 | static RISCVException read_timeh(CPURISCVState *env, int csrno, |
436 | target_ulong *val) | |
c6957248 AP |
437 | { |
438 | uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; | |
439 | ||
440 | if (!env->rdtime_fn) { | |
605def6e | 441 | return RISCV_EXCP_ILLEGAL_INST; |
c6957248 AP |
442 | } |
443 | ||
a47ef6e9 | 444 | *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32; |
605def6e | 445 | return RISCV_EXCP_NONE; |
c6957248 | 446 | } |
c6957248 | 447 | |
c7b95171 MC |
448 | /* Machine constants */ |
449 | ||
ff2cc129 AF |
450 | #define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP) |
451 | #define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP) | |
452 | #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) | |
c7b95171 | 453 | |
d0e53ce3 AF |
454 | static const target_ulong delegable_ints = S_MODE_INTERRUPTS | |
455 | VS_MODE_INTERRUPTS; | |
bc083a51 | 456 | static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS; |
d0e53ce3 AF |
457 | static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | |
458 | VS_MODE_INTERRUPTS; | |
bc083a51 JM |
459 | #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \ |
460 | (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \ | |
461 | (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \ | |
462 | (1ULL << (RISCV_EXCP_BREAKPOINT)) | \ | |
463 | (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | \ | |
464 | (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | \ | |
465 | (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | \ | |
466 | (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | \ | |
467 | (1ULL << (RISCV_EXCP_U_ECALL)) | \ | |
468 | (1ULL << (RISCV_EXCP_S_ECALL)) | \ | |
469 | (1ULL << (RISCV_EXCP_VS_ECALL)) | \ | |
470 | (1ULL << (RISCV_EXCP_M_ECALL)) | \ | |
471 | (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | \ | |
472 | (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | \ | |
473 | (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | \ | |
474 | (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | \ | |
475 | (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | \ | |
476 | (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | \ | |
477 | (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))) | |
478 | static const target_ulong vs_delegable_excps = DELEGABLE_EXCPS & | |
479 | ~((1ULL << (RISCV_EXCP_S_ECALL)) | | |
480 | (1ULL << (RISCV_EXCP_VS_ECALL)) | | |
481 | (1ULL << (RISCV_EXCP_M_ECALL)) | | |
482 | (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | | |
483 | (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | | |
484 | (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | | |
485 | (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))); | |
c7b95171 MC |
486 | static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | |
487 | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | | |
457c360f | 488 | SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS | (target_ulong)SSTATUS64_UXL; |
087b051a | 489 | static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP; |
e89b631c GK |
490 | static const target_ulong hip_writable_mask = MIP_VSSIP; |
491 | static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; | |
8747c9ee | 492 | static const target_ulong vsip_writable_mask = MIP_VSSIP; |
c7b95171 | 493 | |
8987cdc4 | 494 | static const char valid_vm_1_10_32[16] = { |
c7b95171 MC |
495 | [VM_1_10_MBARE] = 1, |
496 | [VM_1_10_SV32] = 1 | |
497 | }; | |
8987cdc4 AF |
498 | |
499 | static const char valid_vm_1_10_64[16] = { | |
c7b95171 MC |
500 | [VM_1_10_MBARE] = 1, |
501 | [VM_1_10_SV39] = 1, | |
502 | [VM_1_10_SV48] = 1, | |
503 | [VM_1_10_SV57] = 1 | |
504 | }; | |
c7b95171 MC |
505 | |
506 | /* Machine Information Registers */ | |
605def6e AF |
507 | static RISCVException read_zero(CPURISCVState *env, int csrno, |
508 | target_ulong *val) | |
c7b95171 | 509 | { |
605def6e AF |
510 | *val = 0; |
511 | return RISCV_EXCP_NONE; | |
c7b95171 MC |
512 | } |
513 | ||
605def6e AF |
514 | static RISCVException read_mhartid(CPURISCVState *env, int csrno, |
515 | target_ulong *val) | |
c7b95171 MC |
516 | { |
517 | *val = env->mhartid; | |
605def6e | 518 | return RISCV_EXCP_NONE; |
c7b95171 MC |
519 | } |
520 | ||
521 | /* Machine Trap Setup */ | |
b550f894 RH |
522 | |
523 | /* We do not store SD explicitly, only compute it on demand. */ | |
524 | static uint64_t add_status_sd(RISCVMXL xl, uint64_t status) | |
525 | { | |
526 | if ((status & MSTATUS_FS) == MSTATUS_FS || | |
c36b2f1a | 527 | (status & MSTATUS_VS) == MSTATUS_VS || |
b550f894 RH |
528 | (status & MSTATUS_XS) == MSTATUS_XS) { |
529 | switch (xl) { | |
530 | case MXL_RV32: | |
531 | return status | MSTATUS32_SD; | |
532 | case MXL_RV64: | |
533 | return status | MSTATUS64_SD; | |
457c360f FP |
534 | case MXL_RV128: |
535 | return MSTATUSH128_SD; | |
b550f894 RH |
536 | default: |
537 | g_assert_not_reached(); | |
538 | } | |
539 | } | |
540 | return status; | |
541 | } | |
542 | ||
605def6e AF |
543 | static RISCVException read_mstatus(CPURISCVState *env, int csrno, |
544 | target_ulong *val) | |
c7b95171 | 545 | { |
b550f894 | 546 | *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus); |
605def6e | 547 | return RISCV_EXCP_NONE; |
c7b95171 MC |
548 | } |
549 | ||
550 | static int validate_vm(CPURISCVState *env, target_ulong vm) | |
551 | { | |
db23e5d9 | 552 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
8987cdc4 AF |
553 | return valid_vm_1_10_32[vm & 0xf]; |
554 | } else { | |
555 | return valid_vm_1_10_64[vm & 0xf]; | |
556 | } | |
c7b95171 MC |
557 | } |
558 | ||
605def6e AF |
559 | static RISCVException write_mstatus(CPURISCVState *env, int csrno, |
560 | target_ulong val) | |
c7b95171 | 561 | { |
284d697c YJ |
562 | uint64_t mstatus = env->mstatus; |
563 | uint64_t mask = 0; | |
c7b95171 MC |
564 | |
565 | /* flush tlb on mstatus fields that affect VM */ | |
1a9540d1 AF |
566 | if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | |
567 | MSTATUS_MPRV | MSTATUS_SUM)) { | |
568 | tlb_flush(env_cpu(env)); | |
c7b95171 | 569 | } |
1a9540d1 AF |
570 | mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | |
571 | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | | |
572 | MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | | |
61b4b69d | 573 | MSTATUS_TW | MSTATUS_VS; |
8987cdc4 | 574 | |
db23e5d9 | 575 | if (riscv_cpu_mxl(env) != MXL_RV32) { |
8987cdc4 AF |
576 | /* |
577 | * RV32: MPV and GVA are not in mstatus. The current plan is to | |
578 | * add them to mstatush. For now, we just don't support it. | |
579 | */ | |
580 | mask |= MSTATUS_MPV | MSTATUS_GVA; | |
581 | } | |
c7b95171 MC |
582 | |
583 | mstatus = (mstatus & ~mask) | (val & mask); | |
584 | ||
457c360f FP |
585 | RISCVMXL xl = riscv_cpu_mxl(env); |
586 | if (xl > MXL_RV32) { | |
92371bd9 | 587 | /* SXL and UXL fields are for now read only */ |
457c360f FP |
588 | mstatus = set_field(mstatus, MSTATUS64_SXL, xl); |
589 | mstatus = set_field(mstatus, MSTATUS64_UXL, xl); | |
4fd7455b | 590 | } |
c7b95171 | 591 | env->mstatus = mstatus; |
440544e1 | 592 | env->xl = cpu_recompute_xl(env); |
c7b95171 | 593 | |
605def6e | 594 | return RISCV_EXCP_NONE; |
c7b95171 MC |
595 | } |
596 | ||
605def6e AF |
597 | static RISCVException read_mstatush(CPURISCVState *env, int csrno, |
598 | target_ulong *val) | |
551fa7e8 | 599 | { |
284d697c | 600 | *val = env->mstatus >> 32; |
605def6e | 601 | return RISCV_EXCP_NONE; |
551fa7e8 AF |
602 | } |
603 | ||
605def6e AF |
604 | static RISCVException write_mstatush(CPURISCVState *env, int csrno, |
605 | target_ulong val) | |
551fa7e8 | 606 | { |
284d697c YJ |
607 | uint64_t valh = (uint64_t)val << 32; |
608 | uint64_t mask = MSTATUS_MPV | MSTATUS_GVA; | |
609 | ||
610 | if ((valh ^ env->mstatus) & (MSTATUS_MPV)) { | |
551fa7e8 AF |
611 | tlb_flush(env_cpu(env)); |
612 | } | |
613 | ||
284d697c | 614 | env->mstatus = (env->mstatus & ~mask) | (valh & mask); |
551fa7e8 | 615 | |
605def6e | 616 | return RISCV_EXCP_NONE; |
551fa7e8 | 617 | } |
551fa7e8 | 618 | |
457c360f FP |
619 | static RISCVException read_mstatus_i128(CPURISCVState *env, int csrno, |
620 | Int128 *val) | |
621 | { | |
622 | *val = int128_make128(env->mstatus, add_status_sd(MXL_RV128, env->mstatus)); | |
623 | return RISCV_EXCP_NONE; | |
624 | } | |
625 | ||
626 | static RISCVException read_misa_i128(CPURISCVState *env, int csrno, | |
627 | Int128 *val) | |
628 | { | |
629 | *val = int128_make128(env->misa_ext, (uint64_t)MXL_RV128 << 62); | |
630 | return RISCV_EXCP_NONE; | |
631 | } | |
632 | ||
605def6e AF |
633 | static RISCVException read_misa(CPURISCVState *env, int csrno, |
634 | target_ulong *val) | |
c7b95171 | 635 | { |
e91a7227 RH |
636 | target_ulong misa; |
637 | ||
638 | switch (env->misa_mxl) { | |
639 | case MXL_RV32: | |
640 | misa = (target_ulong)MXL_RV32 << 30; | |
641 | break; | |
642 | #ifdef TARGET_RISCV64 | |
643 | case MXL_RV64: | |
644 | misa = (target_ulong)MXL_RV64 << 62; | |
645 | break; | |
646 | #endif | |
647 | default: | |
648 | g_assert_not_reached(); | |
649 | } | |
650 | ||
651 | *val = misa | env->misa_ext; | |
605def6e | 652 | return RISCV_EXCP_NONE; |
c7b95171 MC |
653 | } |
654 | ||
605def6e AF |
655 | static RISCVException write_misa(CPURISCVState *env, int csrno, |
656 | target_ulong val) | |
f18637cd MC |
657 | { |
658 | if (!riscv_feature(env, RISCV_FEATURE_MISA)) { | |
659 | /* drop write to misa */ | |
605def6e | 660 | return RISCV_EXCP_NONE; |
f18637cd MC |
661 | } |
662 | ||
663 | /* 'I' or 'E' must be present */ | |
664 | if (!(val & (RVI | RVE))) { | |
665 | /* It is not, drop write to misa */ | |
605def6e | 666 | return RISCV_EXCP_NONE; |
f18637cd MC |
667 | } |
668 | ||
669 | /* 'E' excludes all other extensions */ | |
670 | if (val & RVE) { | |
671 | /* when we support 'E' we can do "val = RVE;" however | |
672 | * for now we just drop writes if 'E' is present. | |
673 | */ | |
605def6e | 674 | return RISCV_EXCP_NONE; |
f18637cd MC |
675 | } |
676 | ||
e91a7227 RH |
677 | /* |
678 | * misa.MXL writes are not supported by QEMU. | |
679 | * Drop writes to those bits. | |
680 | */ | |
681 | ||
f18637cd | 682 | /* Mask extensions that are not supported by this hart */ |
e91a7227 | 683 | val &= env->misa_ext_mask; |
f18637cd MC |
684 | |
685 | /* Mask extensions that are not supported by QEMU */ | |
7b07a37c | 686 | val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU | RVV); |
f18637cd MC |
687 | |
688 | /* 'D' depends on 'F', so clear 'D' if 'F' is not present */ | |
689 | if ((val & RVD) && !(val & RVF)) { | |
690 | val &= ~RVD; | |
691 | } | |
692 | ||
693 | /* Suppress 'C' if next instruction is not aligned | |
694 | * TODO: this should check next_pc | |
695 | */ | |
696 | if ((val & RVC) && (GETPC() & ~3) != 0) { | |
697 | val &= ~RVC; | |
698 | } | |
699 | ||
e91a7227 RH |
700 | /* If nothing changed, do nothing. */ |
701 | if (val == env->misa_ext) { | |
702 | return RISCV_EXCP_NONE; | |
4fd7455b | 703 | } |
f18637cd MC |
704 | |
705 | /* flush translation cache */ | |
e91a7227 RH |
706 | tb_flush(env_cpu(env)); |
707 | env->misa_ext = val; | |
440544e1 | 708 | env->xl = riscv_cpu_mxl(env); |
605def6e | 709 | return RISCV_EXCP_NONE; |
f18637cd MC |
710 | } |
711 | ||
605def6e AF |
712 | static RISCVException read_medeleg(CPURISCVState *env, int csrno, |
713 | target_ulong *val) | |
c7b95171 MC |
714 | { |
715 | *val = env->medeleg; | |
605def6e | 716 | return RISCV_EXCP_NONE; |
c7b95171 MC |
717 | } |
718 | ||
605def6e AF |
719 | static RISCVException write_medeleg(CPURISCVState *env, int csrno, |
720 | target_ulong val) | |
c7b95171 | 721 | { |
bc083a51 | 722 | env->medeleg = (env->medeleg & ~DELEGABLE_EXCPS) | (val & DELEGABLE_EXCPS); |
605def6e | 723 | return RISCV_EXCP_NONE; |
c7b95171 MC |
724 | } |
725 | ||
605def6e AF |
726 | static RISCVException read_mideleg(CPURISCVState *env, int csrno, |
727 | target_ulong *val) | |
c7b95171 MC |
728 | { |
729 | *val = env->mideleg; | |
605def6e | 730 | return RISCV_EXCP_NONE; |
c7b95171 MC |
731 | } |
732 | ||
605def6e AF |
733 | static RISCVException write_mideleg(CPURISCVState *env, int csrno, |
734 | target_ulong val) | |
c7b95171 MC |
735 | { |
736 | env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints); | |
713d8363 AF |
737 | if (riscv_has_ext(env, RVH)) { |
738 | env->mideleg |= VS_MODE_INTERRUPTS; | |
739 | } | |
605def6e | 740 | return RISCV_EXCP_NONE; |
c7b95171 MC |
741 | } |
742 | ||
605def6e AF |
743 | static RISCVException read_mie(CPURISCVState *env, int csrno, |
744 | target_ulong *val) | |
c7b95171 MC |
745 | { |
746 | *val = env->mie; | |
605def6e | 747 | return RISCV_EXCP_NONE; |
c7b95171 MC |
748 | } |
749 | ||
605def6e AF |
750 | static RISCVException write_mie(CPURISCVState *env, int csrno, |
751 | target_ulong val) | |
c7b95171 MC |
752 | { |
753 | env->mie = (env->mie & ~all_ints) | (val & all_ints); | |
605def6e | 754 | return RISCV_EXCP_NONE; |
c7b95171 MC |
755 | } |
756 | ||
605def6e AF |
757 | static RISCVException read_mtvec(CPURISCVState *env, int csrno, |
758 | target_ulong *val) | |
c7b95171 MC |
759 | { |
760 | *val = env->mtvec; | |
605def6e | 761 | return RISCV_EXCP_NONE; |
c7b95171 MC |
762 | } |
763 | ||
605def6e AF |
764 | static RISCVException write_mtvec(CPURISCVState *env, int csrno, |
765 | target_ulong val) | |
c7b95171 MC |
766 | { |
767 | /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ | |
acbbb94e MC |
768 | if ((val & 3) < 2) { |
769 | env->mtvec = val; | |
c7b95171 | 770 | } else { |
acbbb94e | 771 | qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n"); |
c7b95171 | 772 | } |
605def6e | 773 | return RISCV_EXCP_NONE; |
c7b95171 MC |
774 | } |
775 | ||
605def6e AF |
776 | static RISCVException read_mcounteren(CPURISCVState *env, int csrno, |
777 | target_ulong *val) | |
c7b95171 | 778 | { |
c7b95171 | 779 | *val = env->mcounteren; |
605def6e | 780 | return RISCV_EXCP_NONE; |
c7b95171 MC |
781 | } |
782 | ||
605def6e AF |
783 | static RISCVException write_mcounteren(CPURISCVState *env, int csrno, |
784 | target_ulong val) | |
c7b95171 | 785 | { |
c7b95171 | 786 | env->mcounteren = val; |
605def6e | 787 | return RISCV_EXCP_NONE; |
c7b95171 MC |
788 | } |
789 | ||
c7b95171 | 790 | /* Machine Trap Handling */ |
457c360f FP |
791 | static RISCVException read_mscratch_i128(CPURISCVState *env, int csrno, |
792 | Int128 *val) | |
793 | { | |
794 | *val = int128_make128(env->mscratch, env->mscratchh); | |
795 | return RISCV_EXCP_NONE; | |
796 | } | |
797 | ||
798 | static RISCVException write_mscratch_i128(CPURISCVState *env, int csrno, | |
799 | Int128 val) | |
800 | { | |
801 | env->mscratch = int128_getlo(val); | |
802 | env->mscratchh = int128_gethi(val); | |
803 | return RISCV_EXCP_NONE; | |
804 | } | |
805 | ||
605def6e AF |
806 | static RISCVException read_mscratch(CPURISCVState *env, int csrno, |
807 | target_ulong *val) | |
c7b95171 MC |
808 | { |
809 | *val = env->mscratch; | |
605def6e | 810 | return RISCV_EXCP_NONE; |
c7b95171 MC |
811 | } |
812 | ||
605def6e AF |
813 | static RISCVException write_mscratch(CPURISCVState *env, int csrno, |
814 | target_ulong val) | |
c7b95171 MC |
815 | { |
816 | env->mscratch = val; | |
605def6e | 817 | return RISCV_EXCP_NONE; |
c7b95171 MC |
818 | } |
819 | ||
605def6e AF |
820 | static RISCVException read_mepc(CPURISCVState *env, int csrno, |
821 | target_ulong *val) | |
c7b95171 MC |
822 | { |
823 | *val = env->mepc; | |
605def6e | 824 | return RISCV_EXCP_NONE; |
c7b95171 MC |
825 | } |
826 | ||
605def6e AF |
827 | static RISCVException write_mepc(CPURISCVState *env, int csrno, |
828 | target_ulong val) | |
c7b95171 MC |
829 | { |
830 | env->mepc = val; | |
605def6e | 831 | return RISCV_EXCP_NONE; |
c7b95171 MC |
832 | } |
833 | ||
605def6e AF |
834 | static RISCVException read_mcause(CPURISCVState *env, int csrno, |
835 | target_ulong *val) | |
c7b95171 MC |
836 | { |
837 | *val = env->mcause; | |
605def6e | 838 | return RISCV_EXCP_NONE; |
c7b95171 MC |
839 | } |
840 | ||
605def6e AF |
841 | static RISCVException write_mcause(CPURISCVState *env, int csrno, |
842 | target_ulong val) | |
c7b95171 MC |
843 | { |
844 | env->mcause = val; | |
605def6e | 845 | return RISCV_EXCP_NONE; |
c7b95171 MC |
846 | } |
847 | ||
605def6e AF |
848 | static RISCVException read_mtval(CPURISCVState *env, int csrno, |
849 | target_ulong *val) | |
c7b95171 | 850 | { |
ac12b601 | 851 | *val = env->mtval; |
605def6e | 852 | return RISCV_EXCP_NONE; |
c7b95171 MC |
853 | } |
854 | ||
605def6e AF |
855 | static RISCVException write_mtval(CPURISCVState *env, int csrno, |
856 | target_ulong val) | |
c7b95171 | 857 | { |
ac12b601 | 858 | env->mtval = val; |
605def6e | 859 | return RISCV_EXCP_NONE; |
c7b95171 MC |
860 | } |
861 | ||
605def6e AF |
862 | static RISCVException rmw_mip(CPURISCVState *env, int csrno, |
863 | target_ulong *ret_value, | |
864 | target_ulong new_value, target_ulong write_mask) | |
c7b95171 | 865 | { |
3109cd98 | 866 | RISCVCPU *cpu = env_archcpu(env); |
e3e7039c MC |
867 | /* Allow software control of delegable interrupts not claimed by hardware */ |
868 | target_ulong mask = write_mask & delegable_ints & ~env->miclaim; | |
71877e29 MC |
869 | uint32_t old_mip; |
870 | ||
71877e29 | 871 | if (mask) { |
71877e29 | 872 | old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask)); |
71877e29 | 873 | } else { |
7ec5d303 | 874 | old_mip = env->mip; |
71877e29 | 875 | } |
c7b95171 | 876 | |
71877e29 MC |
877 | if (ret_value) { |
878 | *ret_value = old_mip; | |
879 | } | |
c7b95171 | 880 | |
605def6e | 881 | return RISCV_EXCP_NONE; |
c7b95171 MC |
882 | } |
883 | ||
884 | /* Supervisor Trap Setup */ | |
457c360f FP |
885 | static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno, |
886 | Int128 *val) | |
887 | { | |
888 | uint64_t mask = sstatus_v1_10_mask; | |
889 | uint64_t sstatus = env->mstatus & mask; | |
890 | ||
891 | *val = int128_make128(sstatus, add_status_sd(MXL_RV128, sstatus)); | |
892 | return RISCV_EXCP_NONE; | |
893 | } | |
894 | ||
605def6e AF |
895 | static RISCVException read_sstatus(CPURISCVState *env, int csrno, |
896 | target_ulong *val) | |
c7b95171 | 897 | { |
1a9540d1 | 898 | target_ulong mask = (sstatus_v1_10_mask); |
5f10e6d8 | 899 | |
b550f894 RH |
900 | /* TODO: Use SXL not MXL. */ |
901 | *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask); | |
605def6e | 902 | return RISCV_EXCP_NONE; |
c7b95171 MC |
903 | } |
904 | ||
605def6e AF |
905 | static RISCVException write_sstatus(CPURISCVState *env, int csrno, |
906 | target_ulong val) | |
c7b95171 | 907 | { |
1a9540d1 | 908 | target_ulong mask = (sstatus_v1_10_mask); |
c7b95171 MC |
909 | target_ulong newval = (env->mstatus & ~mask) | (val & mask); |
910 | return write_mstatus(env, CSR_MSTATUS, newval); | |
911 | } | |
912 | ||
605def6e AF |
913 | static RISCVException read_vsie(CPURISCVState *env, int csrno, |
914 | target_ulong *val) | |
9d5451e0 GK |
915 | { |
916 | /* Shift the VS bits to their S bit location in vsie */ | |
917 | *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1; | |
605def6e | 918 | return RISCV_EXCP_NONE; |
9d5451e0 GK |
919 | } |
920 | ||
605def6e AF |
921 | static RISCVException read_sie(CPURISCVState *env, int csrno, |
922 | target_ulong *val) | |
c7b95171 | 923 | { |
d0e53ce3 | 924 | if (riscv_cpu_virt_enabled(env)) { |
9d5451e0 | 925 | read_vsie(env, CSR_VSIE, val); |
d0e53ce3 AF |
926 | } else { |
927 | *val = env->mie & env->mideleg; | |
928 | } | |
605def6e | 929 | return RISCV_EXCP_NONE; |
c7b95171 MC |
930 | } |
931 | ||
605def6e AF |
932 | static RISCVException write_vsie(CPURISCVState *env, int csrno, |
933 | target_ulong val) | |
c7b95171 | 934 | { |
9d5451e0 GK |
935 | /* Shift the S bits to their VS bit location in mie */ |
936 | target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | | |
937 | ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS); | |
938 | return write_mie(env, CSR_MIE, newval); | |
939 | } | |
d0e53ce3 | 940 | |
9d5451e0 GK |
941 | static int write_sie(CPURISCVState *env, int csrno, target_ulong val) |
942 | { | |
d0e53ce3 | 943 | if (riscv_cpu_virt_enabled(env)) { |
9d5451e0 | 944 | write_vsie(env, CSR_VSIE, val); |
d0e53ce3 | 945 | } else { |
9d5451e0 GK |
946 | target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) | |
947 | (val & S_MODE_INTERRUPTS); | |
948 | write_mie(env, CSR_MIE, newval); | |
d0e53ce3 AF |
949 | } |
950 | ||
605def6e | 951 | return RISCV_EXCP_NONE; |
c7b95171 MC |
952 | } |
953 | ||
605def6e AF |
954 | static RISCVException read_stvec(CPURISCVState *env, int csrno, |
955 | target_ulong *val) | |
c7b95171 MC |
956 | { |
957 | *val = env->stvec; | |
605def6e | 958 | return RISCV_EXCP_NONE; |
c7b95171 MC |
959 | } |
960 | ||
605def6e AF |
961 | static RISCVException write_stvec(CPURISCVState *env, int csrno, |
962 | target_ulong val) | |
c7b95171 MC |
963 | { |
964 | /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ | |
acbbb94e MC |
965 | if ((val & 3) < 2) { |
966 | env->stvec = val; | |
c7b95171 | 967 | } else { |
acbbb94e | 968 | qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n"); |
c7b95171 | 969 | } |
605def6e | 970 | return RISCV_EXCP_NONE; |
c7b95171 MC |
971 | } |
972 | ||
605def6e AF |
973 | static RISCVException read_scounteren(CPURISCVState *env, int csrno, |
974 | target_ulong *val) | |
c7b95171 | 975 | { |
c7b95171 | 976 | *val = env->scounteren; |
605def6e | 977 | return RISCV_EXCP_NONE; |
c7b95171 MC |
978 | } |
979 | ||
605def6e AF |
980 | static RISCVException write_scounteren(CPURISCVState *env, int csrno, |
981 | target_ulong val) | |
c7b95171 | 982 | { |
c7b95171 | 983 | env->scounteren = val; |
605def6e | 984 | return RISCV_EXCP_NONE; |
c7b95171 MC |
985 | } |
986 | ||
987 | /* Supervisor Trap Handling */ | |
457c360f FP |
988 | static RISCVException read_sscratch_i128(CPURISCVState *env, int csrno, |
989 | Int128 *val) | |
990 | { | |
991 | *val = int128_make128(env->sscratch, env->sscratchh); | |
992 | return RISCV_EXCP_NONE; | |
993 | } | |
994 | ||
995 | static RISCVException write_sscratch_i128(CPURISCVState *env, int csrno, | |
996 | Int128 val) | |
997 | { | |
998 | env->sscratch = int128_getlo(val); | |
999 | env->sscratchh = int128_gethi(val); | |
1000 | return RISCV_EXCP_NONE; | |
1001 | } | |
1002 | ||
605def6e AF |
1003 | static RISCVException read_sscratch(CPURISCVState *env, int csrno, |
1004 | target_ulong *val) | |
c7b95171 MC |
1005 | { |
1006 | *val = env->sscratch; | |
605def6e | 1007 | return RISCV_EXCP_NONE; |
c7b95171 MC |
1008 | } |
1009 | ||
605def6e AF |
1010 | static RISCVException write_sscratch(CPURISCVState *env, int csrno, |
1011 | target_ulong val) | |
c7b95171 MC |
1012 | { |
1013 | env->sscratch = val; | |
605def6e | 1014 | return RISCV_EXCP_NONE; |
c7b95171 MC |
1015 | } |
1016 | ||
605def6e AF |
1017 | static RISCVException read_sepc(CPURISCVState *env, int csrno, |
1018 | target_ulong *val) | |
c7b95171 MC |
1019 | { |
1020 | *val = env->sepc; | |
605def6e | 1021 | return RISCV_EXCP_NONE; |
c7b95171 MC |
1022 | } |
1023 | ||
605def6e AF |
1024 | static RISCVException write_sepc(CPURISCVState *env, int csrno, |
1025 | target_ulong val) | |
c7b95171 MC |
1026 | { |
1027 | env->sepc = val; | |
605def6e | 1028 | return RISCV_EXCP_NONE; |
c7b95171 MC |
1029 | } |
1030 | ||
605def6e AF |
1031 | static RISCVException read_scause(CPURISCVState *env, int csrno, |
1032 | target_ulong *val) | |
c7b95171 MC |
1033 | { |
1034 | *val = env->scause; | |
605def6e | 1035 | return RISCV_EXCP_NONE; |
c7b95171 MC |
1036 | } |
1037 | ||
605def6e AF |
1038 | static RISCVException write_scause(CPURISCVState *env, int csrno, |
1039 | target_ulong val) | |
c7b95171 MC |
1040 | { |
1041 | env->scause = val; | |
605def6e | 1042 | return RISCV_EXCP_NONE; |
c7b95171 MC |
1043 | } |
1044 | ||
605def6e AF |
1045 | static RISCVException read_stval(CPURISCVState *env, int csrno, |
1046 | target_ulong *val) | |
c7b95171 | 1047 | { |
ac12b601 | 1048 | *val = env->stval; |
605def6e | 1049 | return RISCV_EXCP_NONE; |
c7b95171 MC |
1050 | } |
1051 | ||
605def6e AF |
1052 | static RISCVException write_stval(CPURISCVState *env, int csrno, |
1053 | target_ulong val) | |
c7b95171 | 1054 | { |
ac12b601 | 1055 | env->stval = val; |
605def6e | 1056 | return RISCV_EXCP_NONE; |
c7b95171 MC |
1057 | } |
1058 | ||
605def6e AF |
1059 | static RISCVException rmw_vsip(CPURISCVState *env, int csrno, |
1060 | target_ulong *ret_value, | |
1061 | target_ulong new_value, target_ulong write_mask) | |
9d5451e0 GK |
1062 | { |
1063 | /* Shift the S bits to their VS bit location in mip */ | |
1064 | int ret = rmw_mip(env, 0, ret_value, new_value << 1, | |
1065 | (write_mask << 1) & vsip_writable_mask & env->hideleg); | |
33979526 RH |
1066 | |
1067 | if (ret_value) { | |
1068 | *ret_value &= VS_MODE_INTERRUPTS; | |
1069 | /* Shift the VS bits to their S bit location in vsip */ | |
1070 | *ret_value >>= 1; | |
1071 | } | |
9d5451e0 GK |
1072 | return ret; |
1073 | } | |
1074 | ||
605def6e AF |
1075 | static RISCVException rmw_sip(CPURISCVState *env, int csrno, |
1076 | target_ulong *ret_value, | |
1077 | target_ulong new_value, target_ulong write_mask) | |
c7b95171 | 1078 | { |
a2e9f57d AF |
1079 | int ret; |
1080 | ||
1081 | if (riscv_cpu_virt_enabled(env)) { | |
9d5451e0 | 1082 | ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask); |
a2e9f57d AF |
1083 | } else { |
1084 | ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value, | |
087b051a | 1085 | write_mask & env->mideleg & sip_writable_mask); |
a2e9f57d AF |
1086 | } |
1087 | ||
33979526 RH |
1088 | if (ret_value) { |
1089 | *ret_value &= env->mideleg; | |
1090 | } | |
087b051a | 1091 | return ret; |
c7b95171 MC |
1092 | } |
1093 | ||
1094 | /* Supervisor Protection and Translation */ | |
605def6e AF |
1095 | static RISCVException read_satp(CPURISCVState *env, int csrno, |
1096 | target_ulong *val) | |
c7b95171 MC |
1097 | { |
1098 | if (!riscv_feature(env, RISCV_FEATURE_MMU)) { | |
1099 | *val = 0; | |
605def6e | 1100 | return RISCV_EXCP_NONE; |
1a9540d1 AF |
1101 | } |
1102 | ||
1103 | if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { | |
605def6e | 1104 | return RISCV_EXCP_ILLEGAL_INST; |
c7b95171 | 1105 | } else { |
1a9540d1 | 1106 | *val = env->satp; |
c7b95171 | 1107 | } |
1a9540d1 | 1108 | |
605def6e | 1109 | return RISCV_EXCP_NONE; |
c7b95171 MC |
1110 | } |
1111 | ||
605def6e AF |
1112 | static RISCVException write_satp(CPURISCVState *env, int csrno, |
1113 | target_ulong val) | |
c7b95171 | 1114 | { |
15732b8e | 1115 | target_ulong vm, mask, asid; |
419ddf00 | 1116 | |
c7b95171 | 1117 | if (!riscv_feature(env, RISCV_FEATURE_MMU)) { |
605def6e | 1118 | return RISCV_EXCP_NONE; |
c7b95171 | 1119 | } |
419ddf00 | 1120 | |
db23e5d9 | 1121 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
419ddf00 AF |
1122 | vm = validate_vm(env, get_field(val, SATP32_MODE)); |
1123 | mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN); | |
1124 | asid = (val ^ env->satp) & SATP32_ASID; | |
1125 | } else { | |
1126 | vm = validate_vm(env, get_field(val, SATP64_MODE)); | |
1127 | mask = (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN); | |
1128 | asid = (val ^ env->satp) & SATP64_ASID; | |
1129 | } | |
1130 | ||
1131 | if (vm && mask) { | |
7f2b5ff1 | 1132 | if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { |
605def6e | 1133 | return RISCV_EXCP_ILLEGAL_INST; |
7f2b5ff1 | 1134 | } else { |
419ddf00 | 1135 | if (asid) { |
3109cd98 | 1136 | tlb_flush(env_cpu(env)); |
1e0d985f | 1137 | } |
7f2b5ff1 MC |
1138 | env->satp = val; |
1139 | } | |
c7b95171 | 1140 | } |
605def6e | 1141 | return RISCV_EXCP_NONE; |
c7b95171 MC |
1142 | } |
1143 | ||
ff2cc129 | 1144 | /* Hypervisor Extensions */ |
605def6e AF |
1145 | static RISCVException read_hstatus(CPURISCVState *env, int csrno, |
1146 | target_ulong *val) | |
ff2cc129 AF |
1147 | { |
1148 | *val = env->hstatus; | |
db23e5d9 | 1149 | if (riscv_cpu_mxl(env) != MXL_RV32) { |
8987cdc4 AF |
1150 | /* We only support 64-bit VSXL */ |
1151 | *val = set_field(*val, HSTATUS_VSXL, 2); | |
1152 | } | |
30f663b1 AF |
1153 | /* We only support little endian */ |
1154 | *val = set_field(*val, HSTATUS_VSBE, 0); | |
605def6e | 1155 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1156 | } |
1157 | ||
605def6e AF |
1158 | static RISCVException write_hstatus(CPURISCVState *env, int csrno, |
1159 | target_ulong val) | |
ff2cc129 AF |
1160 | { |
1161 | env->hstatus = val; | |
db23e5d9 | 1162 | if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) { |
f8dc878e AF |
1163 | qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options."); |
1164 | } | |
30f663b1 AF |
1165 | if (get_field(val, HSTATUS_VSBE) != 0) { |
1166 | qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests."); | |
1167 | } | |
605def6e | 1168 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1169 | } |
1170 | ||
605def6e AF |
1171 | static RISCVException read_hedeleg(CPURISCVState *env, int csrno, |
1172 | target_ulong *val) | |
ff2cc129 AF |
1173 | { |
1174 | *val = env->hedeleg; | |
605def6e | 1175 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1176 | } |
1177 | ||
605def6e AF |
1178 | static RISCVException write_hedeleg(CPURISCVState *env, int csrno, |
1179 | target_ulong val) | |
ff2cc129 | 1180 | { |
bc083a51 | 1181 | env->hedeleg = val & vs_delegable_excps; |
605def6e | 1182 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1183 | } |
1184 | ||
605def6e AF |
1185 | static RISCVException read_hideleg(CPURISCVState *env, int csrno, |
1186 | target_ulong *val) | |
ff2cc129 AF |
1187 | { |
1188 | *val = env->hideleg; | |
605def6e | 1189 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1190 | } |
1191 | ||
605def6e AF |
1192 | static RISCVException write_hideleg(CPURISCVState *env, int csrno, |
1193 | target_ulong val) | |
ff2cc129 | 1194 | { |
bc083a51 | 1195 | env->hideleg = val & vs_delegable_ints; |
605def6e | 1196 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1197 | } |
1198 | ||
605def6e AF |
1199 | static RISCVException rmw_hvip(CPURISCVState *env, int csrno, |
1200 | target_ulong *ret_value, | |
1201 | target_ulong new_value, target_ulong write_mask) | |
83028098 AF |
1202 | { |
1203 | int ret = rmw_mip(env, 0, ret_value, new_value, | |
e89b631c | 1204 | write_mask & hvip_writable_mask); |
83028098 | 1205 | |
33979526 RH |
1206 | if (ret_value) { |
1207 | *ret_value &= hvip_writable_mask; | |
1208 | } | |
83028098 AF |
1209 | return ret; |
1210 | } | |
1211 | ||
605def6e AF |
1212 | static RISCVException rmw_hip(CPURISCVState *env, int csrno, |
1213 | target_ulong *ret_value, | |
1214 | target_ulong new_value, target_ulong write_mask) | |
ff2cc129 AF |
1215 | { |
1216 | int ret = rmw_mip(env, 0, ret_value, new_value, | |
1217 | write_mask & hip_writable_mask); | |
1218 | ||
33979526 RH |
1219 | if (ret_value) { |
1220 | *ret_value &= hip_writable_mask; | |
1221 | } | |
ff2cc129 AF |
1222 | return ret; |
1223 | } | |
1224 | ||
605def6e AF |
1225 | static RISCVException read_hie(CPURISCVState *env, int csrno, |
1226 | target_ulong *val) | |
ff2cc129 AF |
1227 | { |
1228 | *val = env->mie & VS_MODE_INTERRUPTS; | |
605def6e | 1229 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1230 | } |
1231 | ||
605def6e AF |
1232 | static RISCVException write_hie(CPURISCVState *env, int csrno, |
1233 | target_ulong val) | |
ff2cc129 AF |
1234 | { |
1235 | target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS); | |
1236 | return write_mie(env, CSR_MIE, newval); | |
1237 | } | |
1238 | ||
605def6e AF |
1239 | static RISCVException read_hcounteren(CPURISCVState *env, int csrno, |
1240 | target_ulong *val) | |
ff2cc129 AF |
1241 | { |
1242 | *val = env->hcounteren; | |
605def6e | 1243 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1244 | } |
1245 | ||
605def6e AF |
1246 | static RISCVException write_hcounteren(CPURISCVState *env, int csrno, |
1247 | target_ulong val) | |
ff2cc129 AF |
1248 | { |
1249 | env->hcounteren = val; | |
605def6e | 1250 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1251 | } |
1252 | ||
605def6e AF |
1253 | static RISCVException write_hgeie(CPURISCVState *env, int csrno, |
1254 | target_ulong val) | |
83028098 | 1255 | { |
377cbb4b RH |
1256 | if (val) { |
1257 | qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); | |
1258 | } | |
605def6e | 1259 | return RISCV_EXCP_NONE; |
83028098 AF |
1260 | } |
1261 | ||
605def6e AF |
1262 | static RISCVException read_htval(CPURISCVState *env, int csrno, |
1263 | target_ulong *val) | |
ff2cc129 AF |
1264 | { |
1265 | *val = env->htval; | |
605def6e | 1266 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1267 | } |
1268 | ||
605def6e AF |
1269 | static RISCVException write_htval(CPURISCVState *env, int csrno, |
1270 | target_ulong val) | |
ff2cc129 AF |
1271 | { |
1272 | env->htval = val; | |
605def6e | 1273 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1274 | } |
1275 | ||
605def6e AF |
1276 | static RISCVException read_htinst(CPURISCVState *env, int csrno, |
1277 | target_ulong *val) | |
ff2cc129 AF |
1278 | { |
1279 | *val = env->htinst; | |
605def6e | 1280 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1281 | } |
1282 | ||
605def6e AF |
1283 | static RISCVException write_htinst(CPURISCVState *env, int csrno, |
1284 | target_ulong val) | |
ff2cc129 | 1285 | { |
605def6e | 1286 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1287 | } |
1288 | ||
605def6e AF |
1289 | static RISCVException write_hgeip(CPURISCVState *env, int csrno, |
1290 | target_ulong val) | |
83028098 | 1291 | { |
377cbb4b RH |
1292 | if (val) { |
1293 | qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); | |
1294 | } | |
605def6e | 1295 | return RISCV_EXCP_NONE; |
83028098 AF |
1296 | } |
1297 | ||
605def6e AF |
1298 | static RISCVException read_hgatp(CPURISCVState *env, int csrno, |
1299 | target_ulong *val) | |
ff2cc129 AF |
1300 | { |
1301 | *val = env->hgatp; | |
605def6e | 1302 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1303 | } |
1304 | ||
605def6e AF |
1305 | static RISCVException write_hgatp(CPURISCVState *env, int csrno, |
1306 | target_ulong val) | |
ff2cc129 AF |
1307 | { |
1308 | env->hgatp = val; | |
605def6e | 1309 | return RISCV_EXCP_NONE; |
ff2cc129 AF |
1310 | } |
1311 | ||
605def6e AF |
1312 | static RISCVException read_htimedelta(CPURISCVState *env, int csrno, |
1313 | target_ulong *val) | |
c6957248 AP |
1314 | { |
1315 | if (!env->rdtime_fn) { | |
605def6e | 1316 | return RISCV_EXCP_ILLEGAL_INST; |
c6957248 AP |
1317 | } |
1318 | ||
c6957248 | 1319 | *val = env->htimedelta; |
605def6e | 1320 | return RISCV_EXCP_NONE; |
c6957248 AP |
1321 | } |
1322 | ||
605def6e AF |
1323 | static RISCVException write_htimedelta(CPURISCVState *env, int csrno, |
1324 | target_ulong val) | |
c6957248 AP |
1325 | { |
1326 | if (!env->rdtime_fn) { | |
605def6e | 1327 | return RISCV_EXCP_ILLEGAL_INST; |
c6957248 AP |
1328 | } |
1329 | ||
db23e5d9 | 1330 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
8987cdc4 AF |
1331 | env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val); |
1332 | } else { | |
1333 | env->htimedelta = val; | |
1334 | } | |
605def6e | 1335 | return RISCV_EXCP_NONE; |
c6957248 AP |
1336 | } |
1337 | ||
605def6e AF |
1338 | static RISCVException read_htimedeltah(CPURISCVState *env, int csrno, |
1339 | target_ulong *val) | |
c6957248 AP |
1340 | { |
1341 | if (!env->rdtime_fn) { | |
605def6e | 1342 | return RISCV_EXCP_ILLEGAL_INST; |
c6957248 AP |
1343 | } |
1344 | ||
1345 | *val = env->htimedelta >> 32; | |
605def6e | 1346 | return RISCV_EXCP_NONE; |
c6957248 AP |
1347 | } |
1348 | ||
605def6e AF |
1349 | static RISCVException write_htimedeltah(CPURISCVState *env, int csrno, |
1350 | target_ulong val) | |
c6957248 AP |
1351 | { |
1352 | if (!env->rdtime_fn) { | |
605def6e | 1353 | return RISCV_EXCP_ILLEGAL_INST; |
c6957248 AP |
1354 | } |
1355 | ||
1356 | env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val); | |
605def6e | 1357 | return RISCV_EXCP_NONE; |
c6957248 | 1358 | } |
c6957248 | 1359 | |
8747c9ee | 1360 | /* Virtual CSR Registers */ |
605def6e AF |
1361 | static RISCVException read_vsstatus(CPURISCVState *env, int csrno, |
1362 | target_ulong *val) | |
8747c9ee AF |
1363 | { |
1364 | *val = env->vsstatus; | |
605def6e | 1365 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1366 | } |
1367 | ||
605def6e AF |
1368 | static RISCVException write_vsstatus(CPURISCVState *env, int csrno, |
1369 | target_ulong val) | |
8747c9ee | 1370 | { |
284d697c YJ |
1371 | uint64_t mask = (target_ulong)-1; |
1372 | env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val; | |
605def6e | 1373 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1374 | } |
1375 | ||
8747c9ee AF |
1376 | static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val) |
1377 | { | |
1378 | *val = env->vstvec; | |
605def6e | 1379 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1380 | } |
1381 | ||
605def6e AF |
1382 | static RISCVException write_vstvec(CPURISCVState *env, int csrno, |
1383 | target_ulong val) | |
8747c9ee AF |
1384 | { |
1385 | env->vstvec = val; | |
605def6e | 1386 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1387 | } |
1388 | ||
605def6e AF |
1389 | static RISCVException read_vsscratch(CPURISCVState *env, int csrno, |
1390 | target_ulong *val) | |
8747c9ee AF |
1391 | { |
1392 | *val = env->vsscratch; | |
605def6e | 1393 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1394 | } |
1395 | ||
605def6e AF |
1396 | static RISCVException write_vsscratch(CPURISCVState *env, int csrno, |
1397 | target_ulong val) | |
8747c9ee AF |
1398 | { |
1399 | env->vsscratch = val; | |
605def6e | 1400 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1401 | } |
1402 | ||
605def6e AF |
1403 | static RISCVException read_vsepc(CPURISCVState *env, int csrno, |
1404 | target_ulong *val) | |
8747c9ee AF |
1405 | { |
1406 | *val = env->vsepc; | |
605def6e | 1407 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1408 | } |
1409 | ||
605def6e AF |
1410 | static RISCVException write_vsepc(CPURISCVState *env, int csrno, |
1411 | target_ulong val) | |
8747c9ee AF |
1412 | { |
1413 | env->vsepc = val; | |
605def6e | 1414 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1415 | } |
1416 | ||
605def6e AF |
1417 | static RISCVException read_vscause(CPURISCVState *env, int csrno, |
1418 | target_ulong *val) | |
8747c9ee AF |
1419 | { |
1420 | *val = env->vscause; | |
605def6e | 1421 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1422 | } |
1423 | ||
605def6e AF |
1424 | static RISCVException write_vscause(CPURISCVState *env, int csrno, |
1425 | target_ulong val) | |
8747c9ee AF |
1426 | { |
1427 | env->vscause = val; | |
605def6e | 1428 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1429 | } |
1430 | ||
605def6e AF |
1431 | static RISCVException read_vstval(CPURISCVState *env, int csrno, |
1432 | target_ulong *val) | |
8747c9ee AF |
1433 | { |
1434 | *val = env->vstval; | |
605def6e | 1435 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1436 | } |
1437 | ||
605def6e AF |
1438 | static RISCVException write_vstval(CPURISCVState *env, int csrno, |
1439 | target_ulong val) | |
8747c9ee AF |
1440 | { |
1441 | env->vstval = val; | |
605def6e | 1442 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1443 | } |
1444 | ||
605def6e AF |
1445 | static RISCVException read_vsatp(CPURISCVState *env, int csrno, |
1446 | target_ulong *val) | |
8747c9ee AF |
1447 | { |
1448 | *val = env->vsatp; | |
605def6e | 1449 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1450 | } |
1451 | ||
605def6e AF |
1452 | static RISCVException write_vsatp(CPURISCVState *env, int csrno, |
1453 | target_ulong val) | |
8747c9ee AF |
1454 | { |
1455 | env->vsatp = val; | |
605def6e | 1456 | return RISCV_EXCP_NONE; |
8747c9ee AF |
1457 | } |
1458 | ||
605def6e AF |
1459 | static RISCVException read_mtval2(CPURISCVState *env, int csrno, |
1460 | target_ulong *val) | |
34cfb5f6 AF |
1461 | { |
1462 | *val = env->mtval2; | |
605def6e | 1463 | return RISCV_EXCP_NONE; |
34cfb5f6 AF |
1464 | } |
1465 | ||
605def6e AF |
1466 | static RISCVException write_mtval2(CPURISCVState *env, int csrno, |
1467 | target_ulong val) | |
34cfb5f6 AF |
1468 | { |
1469 | env->mtval2 = val; | |
605def6e | 1470 | return RISCV_EXCP_NONE; |
34cfb5f6 AF |
1471 | } |
1472 | ||
605def6e AF |
1473 | static RISCVException read_mtinst(CPURISCVState *env, int csrno, |
1474 | target_ulong *val) | |
34cfb5f6 AF |
1475 | { |
1476 | *val = env->mtinst; | |
605def6e | 1477 | return RISCV_EXCP_NONE; |
34cfb5f6 AF |
1478 | } |
1479 | ||
605def6e AF |
1480 | static RISCVException write_mtinst(CPURISCVState *env, int csrno, |
1481 | target_ulong val) | |
34cfb5f6 AF |
1482 | { |
1483 | env->mtinst = val; | |
605def6e | 1484 | return RISCV_EXCP_NONE; |
34cfb5f6 AF |
1485 | } |
1486 | ||
c7b95171 | 1487 | /* Physical Memory Protection */ |
2582a95c HW |
1488 | static RISCVException read_mseccfg(CPURISCVState *env, int csrno, |
1489 | target_ulong *val) | |
1490 | { | |
1491 | *val = mseccfg_csr_read(env); | |
1492 | return RISCV_EXCP_NONE; | |
1493 | } | |
1494 | ||
1495 | static RISCVException write_mseccfg(CPURISCVState *env, int csrno, | |
1496 | target_ulong val) | |
1497 | { | |
1498 | mseccfg_csr_write(env, val); | |
1499 | return RISCV_EXCP_NONE; | |
1500 | } | |
1501 | ||
79f26b3b LZ |
1502 | static bool check_pmp_reg_index(CPURISCVState *env, uint32_t reg_index) |
1503 | { | |
1504 | /* TODO: RV128 restriction check */ | |
1505 | if ((reg_index & 1) && (riscv_cpu_mxl(env) == MXL_RV64)) { | |
1506 | return false; | |
1507 | } | |
1508 | return true; | |
1509 | } | |
1510 | ||
605def6e AF |
1511 | static RISCVException read_pmpcfg(CPURISCVState *env, int csrno, |
1512 | target_ulong *val) | |
c7b95171 | 1513 | { |
79f26b3b LZ |
1514 | uint32_t reg_index = csrno - CSR_PMPCFG0; |
1515 | ||
1516 | if (!check_pmp_reg_index(env, reg_index)) { | |
1517 | return RISCV_EXCP_ILLEGAL_INST; | |
1518 | } | |
c7b95171 | 1519 | *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0); |
605def6e | 1520 | return RISCV_EXCP_NONE; |
c7b95171 MC |
1521 | } |
1522 | ||
605def6e AF |
1523 | static RISCVException write_pmpcfg(CPURISCVState *env, int csrno, |
1524 | target_ulong val) | |
c7b95171 | 1525 | { |
79f26b3b LZ |
1526 | uint32_t reg_index = csrno - CSR_PMPCFG0; |
1527 | ||
1528 | if (!check_pmp_reg_index(env, reg_index)) { | |
1529 | return RISCV_EXCP_ILLEGAL_INST; | |
1530 | } | |
c7b95171 | 1531 | pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val); |
605def6e | 1532 | return RISCV_EXCP_NONE; |
c7b95171 MC |
1533 | } |
1534 | ||
605def6e AF |
1535 | static RISCVException read_pmpaddr(CPURISCVState *env, int csrno, |
1536 | target_ulong *val) | |
c7b95171 MC |
1537 | { |
1538 | *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0); | |
605def6e | 1539 | return RISCV_EXCP_NONE; |
c7b95171 MC |
1540 | } |
1541 | ||
605def6e AF |
1542 | static RISCVException write_pmpaddr(CPURISCVState *env, int csrno, |
1543 | target_ulong val) | |
c7b95171 MC |
1544 | { |
1545 | pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val); | |
605def6e | 1546 | return RISCV_EXCP_NONE; |
c7b95171 MC |
1547 | } |
1548 | ||
4bbe8033 AB |
1549 | /* |
1550 | * Functions to access Pointer Masking feature registers | |
1551 | * We have to check if current priv lvl could modify | |
1552 | * csr in given mode | |
1553 | */ | |
1554 | static bool check_pm_current_disabled(CPURISCVState *env, int csrno) | |
1555 | { | |
1556 | int csr_priv = get_field(csrno, 0x300); | |
1557 | int pm_current; | |
1558 | ||
47bdec82 LZ |
1559 | if (env->debugger) { |
1560 | return false; | |
1561 | } | |
4bbe8033 AB |
1562 | /* |
1563 | * If priv lvls differ that means we're accessing csr from higher priv lvl, | |
1564 | * so allow the access | |
1565 | */ | |
1566 | if (env->priv != csr_priv) { | |
1567 | return false; | |
1568 | } | |
1569 | switch (env->priv) { | |
1570 | case PRV_M: | |
1571 | pm_current = get_field(env->mmte, M_PM_CURRENT); | |
1572 | break; | |
1573 | case PRV_S: | |
1574 | pm_current = get_field(env->mmte, S_PM_CURRENT); | |
1575 | break; | |
1576 | case PRV_U: | |
1577 | pm_current = get_field(env->mmte, U_PM_CURRENT); | |
1578 | break; | |
1579 | default: | |
1580 | g_assert_not_reached(); | |
1581 | } | |
1582 | /* It's same priv lvl, so we allow to modify csr only if pm.current==1 */ | |
1583 | return !pm_current; | |
1584 | } | |
1585 | ||
1586 | static RISCVException read_mmte(CPURISCVState *env, int csrno, | |
1587 | target_ulong *val) | |
1588 | { | |
1589 | *val = env->mmte & MMTE_MASK; | |
1590 | return RISCV_EXCP_NONE; | |
1591 | } | |
1592 | ||
1593 | static RISCVException write_mmte(CPURISCVState *env, int csrno, | |
1594 | target_ulong val) | |
1595 | { | |
1596 | uint64_t mstatus; | |
1597 | target_ulong wpri_val = val & MMTE_MASK; | |
1598 | ||
1599 | if (val != wpri_val) { | |
1600 | qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n", | |
1601 | "MMTE: WPRI violation written 0x", val, | |
1602 | "vs expected 0x", wpri_val); | |
1603 | } | |
1604 | /* for machine mode pm.current is hardwired to 1 */ | |
1605 | wpri_val |= MMTE_M_PM_CURRENT; | |
1606 | ||
1607 | /* hardwiring pm.instruction bit to 0, since it's not supported yet */ | |
1608 | wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN); | |
1609 | env->mmte = wpri_val | PM_EXT_DIRTY; | |
1610 | ||
1611 | /* Set XS and SD bits, since PM CSRs are dirty */ | |
1612 | mstatus = env->mstatus | MSTATUS_XS; | |
1613 | write_mstatus(env, csrno, mstatus); | |
1614 | return RISCV_EXCP_NONE; | |
1615 | } | |
1616 | ||
1617 | static RISCVException read_smte(CPURISCVState *env, int csrno, | |
1618 | target_ulong *val) | |
1619 | { | |
1620 | *val = env->mmte & SMTE_MASK; | |
1621 | return RISCV_EXCP_NONE; | |
1622 | } | |
1623 | ||
1624 | static RISCVException write_smte(CPURISCVState *env, int csrno, | |
1625 | target_ulong val) | |
1626 | { | |
1627 | target_ulong wpri_val = val & SMTE_MASK; | |
1628 | ||
1629 | if (val != wpri_val) { | |
1630 | qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n", | |
1631 | "SMTE: WPRI violation written 0x", val, | |
1632 | "vs expected 0x", wpri_val); | |
1633 | } | |
1634 | ||
1635 | /* if pm.current==0 we can't modify current PM CSRs */ | |
1636 | if (check_pm_current_disabled(env, csrno)) { | |
1637 | return RISCV_EXCP_NONE; | |
1638 | } | |
1639 | ||
1640 | wpri_val |= (env->mmte & ~SMTE_MASK); | |
1641 | write_mmte(env, csrno, wpri_val); | |
1642 | return RISCV_EXCP_NONE; | |
1643 | } | |
1644 | ||
1645 | static RISCVException read_umte(CPURISCVState *env, int csrno, | |
1646 | target_ulong *val) | |
1647 | { | |
1648 | *val = env->mmte & UMTE_MASK; | |
1649 | return RISCV_EXCP_NONE; | |
1650 | } | |
1651 | ||
1652 | static RISCVException write_umte(CPURISCVState *env, int csrno, | |
1653 | target_ulong val) | |
1654 | { | |
1655 | target_ulong wpri_val = val & UMTE_MASK; | |
1656 | ||
1657 | if (val != wpri_val) { | |
1658 | qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n", | |
1659 | "UMTE: WPRI violation written 0x", val, | |
1660 | "vs expected 0x", wpri_val); | |
1661 | } | |
1662 | ||
1663 | if (check_pm_current_disabled(env, csrno)) { | |
1664 | return RISCV_EXCP_NONE; | |
1665 | } | |
1666 | ||
1667 | wpri_val |= (env->mmte & ~UMTE_MASK); | |
1668 | write_mmte(env, csrno, wpri_val); | |
1669 | return RISCV_EXCP_NONE; | |
1670 | } | |
1671 | ||
1672 | static RISCVException read_mpmmask(CPURISCVState *env, int csrno, | |
1673 | target_ulong *val) | |
1674 | { | |
1675 | *val = env->mpmmask; | |
1676 | return RISCV_EXCP_NONE; | |
1677 | } | |
1678 | ||
1679 | static RISCVException write_mpmmask(CPURISCVState *env, int csrno, | |
1680 | target_ulong val) | |
1681 | { | |
1682 | uint64_t mstatus; | |
1683 | ||
1684 | env->mpmmask = val; | |
1685 | env->mmte |= PM_EXT_DIRTY; | |
1686 | ||
1687 | /* Set XS and SD bits, since PM CSRs are dirty */ | |
1688 | mstatus = env->mstatus | MSTATUS_XS; | |
1689 | write_mstatus(env, csrno, mstatus); | |
1690 | return RISCV_EXCP_NONE; | |
1691 | } | |
1692 | ||
1693 | static RISCVException read_spmmask(CPURISCVState *env, int csrno, | |
1694 | target_ulong *val) | |
1695 | { | |
1696 | *val = env->spmmask; | |
1697 | return RISCV_EXCP_NONE; | |
1698 | } | |
1699 | ||
1700 | static RISCVException write_spmmask(CPURISCVState *env, int csrno, | |
1701 | target_ulong val) | |
1702 | { | |
1703 | uint64_t mstatus; | |
1704 | ||
1705 | /* if pm.current==0 we can't modify current PM CSRs */ | |
1706 | if (check_pm_current_disabled(env, csrno)) { | |
1707 | return RISCV_EXCP_NONE; | |
1708 | } | |
1709 | env->spmmask = val; | |
1710 | env->mmte |= PM_EXT_DIRTY; | |
1711 | ||
1712 | /* Set XS and SD bits, since PM CSRs are dirty */ | |
1713 | mstatus = env->mstatus | MSTATUS_XS; | |
1714 | write_mstatus(env, csrno, mstatus); | |
1715 | return RISCV_EXCP_NONE; | |
1716 | } | |
1717 | ||
1718 | static RISCVException read_upmmask(CPURISCVState *env, int csrno, | |
1719 | target_ulong *val) | |
1720 | { | |
1721 | *val = env->upmmask; | |
1722 | return RISCV_EXCP_NONE; | |
1723 | } | |
1724 | ||
1725 | static RISCVException write_upmmask(CPURISCVState *env, int csrno, | |
1726 | target_ulong val) | |
1727 | { | |
1728 | uint64_t mstatus; | |
1729 | ||
1730 | /* if pm.current==0 we can't modify current PM CSRs */ | |
1731 | if (check_pm_current_disabled(env, csrno)) { | |
1732 | return RISCV_EXCP_NONE; | |
1733 | } | |
1734 | env->upmmask = val; | |
1735 | env->mmte |= PM_EXT_DIRTY; | |
1736 | ||
1737 | /* Set XS and SD bits, since PM CSRs are dirty */ | |
1738 | mstatus = env->mstatus | MSTATUS_XS; | |
1739 | write_mstatus(env, csrno, mstatus); | |
1740 | return RISCV_EXCP_NONE; | |
1741 | } | |
1742 | ||
1743 | static RISCVException read_mpmbase(CPURISCVState *env, int csrno, | |
1744 | target_ulong *val) | |
1745 | { | |
1746 | *val = env->mpmbase; | |
1747 | return RISCV_EXCP_NONE; | |
1748 | } | |
1749 | ||
1750 | static RISCVException write_mpmbase(CPURISCVState *env, int csrno, | |
1751 | target_ulong val) | |
1752 | { | |
1753 | uint64_t mstatus; | |
1754 | ||
1755 | env->mpmbase = val; | |
1756 | env->mmte |= PM_EXT_DIRTY; | |
1757 | ||
1758 | /* Set XS and SD bits, since PM CSRs are dirty */ | |
1759 | mstatus = env->mstatus | MSTATUS_XS; | |
1760 | write_mstatus(env, csrno, mstatus); | |
1761 | return RISCV_EXCP_NONE; | |
1762 | } | |
1763 | ||
1764 | static RISCVException read_spmbase(CPURISCVState *env, int csrno, | |
1765 | target_ulong *val) | |
1766 | { | |
1767 | *val = env->spmbase; | |
1768 | return RISCV_EXCP_NONE; | |
1769 | } | |
1770 | ||
1771 | static RISCVException write_spmbase(CPURISCVState *env, int csrno, | |
1772 | target_ulong val) | |
1773 | { | |
1774 | uint64_t mstatus; | |
1775 | ||
1776 | /* if pm.current==0 we can't modify current PM CSRs */ | |
1777 | if (check_pm_current_disabled(env, csrno)) { | |
1778 | return RISCV_EXCP_NONE; | |
1779 | } | |
1780 | env->spmbase = val; | |
1781 | env->mmte |= PM_EXT_DIRTY; | |
1782 | ||
1783 | /* Set XS and SD bits, since PM CSRs are dirty */ | |
1784 | mstatus = env->mstatus | MSTATUS_XS; | |
1785 | write_mstatus(env, csrno, mstatus); | |
1786 | return RISCV_EXCP_NONE; | |
1787 | } | |
1788 | ||
1789 | static RISCVException read_upmbase(CPURISCVState *env, int csrno, | |
1790 | target_ulong *val) | |
1791 | { | |
1792 | *val = env->upmbase; | |
1793 | return RISCV_EXCP_NONE; | |
1794 | } | |
1795 | ||
1796 | static RISCVException write_upmbase(CPURISCVState *env, int csrno, | |
1797 | target_ulong val) | |
1798 | { | |
1799 | uint64_t mstatus; | |
1800 | ||
1801 | /* if pm.current==0 we can't modify current PM CSRs */ | |
1802 | if (check_pm_current_disabled(env, csrno)) { | |
1803 | return RISCV_EXCP_NONE; | |
1804 | } | |
1805 | env->upmbase = val; | |
1806 | env->mmte |= PM_EXT_DIRTY; | |
1807 | ||
1808 | /* Set XS and SD bits, since PM CSRs are dirty */ | |
1809 | mstatus = env->mstatus | MSTATUS_XS; | |
1810 | write_mstatus(env, csrno, mstatus); | |
1811 | return RISCV_EXCP_NONE; | |
1812 | } | |
1813 | ||
c7b95171 MC |
1814 | #endif |
1815 | ||
1816 | /* | |
1817 | * riscv_csrrw - read and/or update control and status register | |
1818 | * | |
1819 | * csrr <-> riscv_csrrw(env, csrno, ret_value, 0, 0); | |
1820 | * csrrw <-> riscv_csrrw(env, csrno, ret_value, value, -1); | |
1821 | * csrrs <-> riscv_csrrw(env, csrno, ret_value, -1, value); | |
1822 | * csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value); | |
1823 | */ | |
1824 | ||
457c360f FP |
1825 | static inline RISCVException riscv_csrrw_check(CPURISCVState *env, |
1826 | int csrno, | |
1827 | bool write_mask, | |
1828 | RISCVCPU *cpu) | |
c7b95171 | 1829 | { |
65e728a2 | 1830 | /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */ |
457c360f | 1831 | int read_only = get_field(csrno, 0xC00) == 3; |
c7b95171 | 1832 | #if !defined(CONFIG_USER_ONLY) |
0a42f4c4 | 1833 | int effective_priv = env->priv; |
0a42f4c4 AF |
1834 | |
1835 | if (riscv_has_ext(env, RVH) && | |
1836 | env->priv == PRV_S && | |
1837 | !riscv_cpu_virt_enabled(env)) { | |
1838 | /* | |
1839 | * We are in S mode without virtualisation, therefore we are in HS Mode. | |
1840 | * Add 1 to the effective privledge level to allow us to access the | |
1841 | * Hypervisor CSRs. | |
1842 | */ | |
1843 | effective_priv++; | |
e6e03dcf | 1844 | } |
0a42f4c4 | 1845 | |
42109837 | 1846 | if (!env->debugger && (effective_priv < get_field(csrno, 0x300))) { |
533c91e8 | 1847 | return RISCV_EXCP_ILLEGAL_INST; |
c7b95171 MC |
1848 | } |
1849 | #endif | |
42109837 LZ |
1850 | if (write_mask && read_only) { |
1851 | return RISCV_EXCP_ILLEGAL_INST; | |
1852 | } | |
c7b95171 | 1853 | |
591bddea PD |
1854 | /* ensure the CSR extension is enabled. */ |
1855 | if (!cpu->cfg.ext_icsr) { | |
533c91e8 | 1856 | return RISCV_EXCP_ILLEGAL_INST; |
591bddea PD |
1857 | } |
1858 | ||
a88365c1 | 1859 | /* check predicate */ |
e39a8320 | 1860 | if (!csr_ops[csrno].predicate) { |
533c91e8 | 1861 | return RISCV_EXCP_ILLEGAL_INST; |
a88365c1 | 1862 | } |
457c360f FP |
1863 | |
1864 | return csr_ops[csrno].predicate(env, csrno); | |
1865 | } | |
1866 | ||
1867 | static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno, | |
1868 | target_ulong *ret_value, | |
1869 | target_ulong new_value, | |
1870 | target_ulong write_mask) | |
1871 | { | |
1872 | RISCVException ret; | |
1873 | target_ulong old_value; | |
a88365c1 | 1874 | |
c7b95171 MC |
1875 | /* execute combined read/write operation if it exists */ |
1876 | if (csr_ops[csrno].op) { | |
533c91e8 | 1877 | return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask); |
c7b95171 MC |
1878 | } |
1879 | ||
1880 | /* if no accessor exists then return failure */ | |
1881 | if (!csr_ops[csrno].read) { | |
533c91e8 | 1882 | return RISCV_EXCP_ILLEGAL_INST; |
c7b95171 | 1883 | } |
c7b95171 MC |
1884 | /* read old value */ |
1885 | ret = csr_ops[csrno].read(env, csrno, &old_value); | |
605def6e | 1886 | if (ret != RISCV_EXCP_NONE) { |
533c91e8 | 1887 | return ret; |
c7b95171 MC |
1888 | } |
1889 | ||
1890 | /* write value if writable and write mask set, otherwise drop writes */ | |
1891 | if (write_mask) { | |
1892 | new_value = (old_value & ~write_mask) | (new_value & write_mask); | |
1893 | if (csr_ops[csrno].write) { | |
1894 | ret = csr_ops[csrno].write(env, csrno, new_value); | |
605def6e | 1895 | if (ret != RISCV_EXCP_NONE) { |
533c91e8 | 1896 | return ret; |
c7b95171 MC |
1897 | } |
1898 | } | |
1899 | } | |
1900 | ||
1901 | /* return old value */ | |
1902 | if (ret_value) { | |
1903 | *ret_value = old_value; | |
1904 | } | |
1905 | ||
533c91e8 | 1906 | return RISCV_EXCP_NONE; |
c7b95171 MC |
1907 | } |
1908 | ||
457c360f FP |
1909 | RISCVException riscv_csrrw(CPURISCVState *env, int csrno, |
1910 | target_ulong *ret_value, | |
1911 | target_ulong new_value, target_ulong write_mask) | |
1912 | { | |
1913 | RISCVCPU *cpu = env_archcpu(env); | |
1914 | ||
1915 | RISCVException ret = riscv_csrrw_check(env, csrno, write_mask, cpu); | |
1916 | if (ret != RISCV_EXCP_NONE) { | |
1917 | return ret; | |
1918 | } | |
1919 | ||
1920 | return riscv_csrrw_do64(env, csrno, ret_value, new_value, write_mask); | |
1921 | } | |
1922 | ||
1923 | static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno, | |
1924 | Int128 *ret_value, | |
1925 | Int128 new_value, | |
1926 | Int128 write_mask) | |
961738ff | 1927 | { |
457c360f FP |
1928 | RISCVException ret; |
1929 | Int128 old_value; | |
1930 | ||
1931 | /* read old value */ | |
1932 | ret = csr_ops[csrno].read128(env, csrno, &old_value); | |
1933 | if (ret != RISCV_EXCP_NONE) { | |
1934 | return ret; | |
1935 | } | |
1936 | ||
1937 | /* write value if writable and write mask set, otherwise drop writes */ | |
1938 | if (int128_nz(write_mask)) { | |
1939 | new_value = int128_or(int128_and(old_value, int128_not(write_mask)), | |
1940 | int128_and(new_value, write_mask)); | |
1941 | if (csr_ops[csrno].write128) { | |
1942 | ret = csr_ops[csrno].write128(env, csrno, new_value); | |
1943 | if (ret != RISCV_EXCP_NONE) { | |
1944 | return ret; | |
1945 | } | |
1946 | } else if (csr_ops[csrno].write) { | |
1947 | /* avoids having to write wrappers for all registers */ | |
1948 | ret = csr_ops[csrno].write(env, csrno, int128_getlo(new_value)); | |
1949 | if (ret != RISCV_EXCP_NONE) { | |
1950 | return ret; | |
1951 | } | |
1952 | } | |
1953 | } | |
961738ff | 1954 | |
457c360f | 1955 | /* return old value */ |
961738ff | 1956 | if (ret_value) { |
457c360f FP |
1957 | *ret_value = old_value; |
1958 | } | |
1959 | ||
1960 | return RISCV_EXCP_NONE; | |
1961 | } | |
1962 | ||
1963 | RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, | |
1964 | Int128 *ret_value, | |
1965 | Int128 new_value, Int128 write_mask) | |
1966 | { | |
1967 | RISCVException ret; | |
1968 | RISCVCPU *cpu = env_archcpu(env); | |
1969 | ||
1970 | ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask), cpu); | |
1971 | if (ret != RISCV_EXCP_NONE) { | |
1972 | return ret; | |
961738ff FP |
1973 | } |
1974 | ||
457c360f FP |
1975 | if (csr_ops[csrno].read128) { |
1976 | return riscv_csrrw_do128(env, csrno, ret_value, new_value, write_mask); | |
1977 | } | |
1978 | ||
1979 | /* | |
1980 | * Fall back to 64-bit version for now, if the 128-bit alternative isn't | |
1981 | * at all defined. | |
1982 | * Note, some CSRs don't need to extend to MXLEN (64 upper bits non | |
1983 | * significant), for those, this fallback is correctly handling the accesses | |
1984 | */ | |
1985 | target_ulong old_value; | |
1986 | ret = riscv_csrrw_do64(env, csrno, &old_value, | |
1987 | int128_getlo(new_value), | |
1988 | int128_getlo(write_mask)); | |
1989 | if (ret == RISCV_EXCP_NONE && ret_value) { | |
1990 | *ret_value = int128_make64(old_value); | |
1991 | } | |
961738ff FP |
1992 | return ret; |
1993 | } | |
1994 | ||
753e3fe2 JW |
1995 | /* |
1996 | * Debugger support. If not in user mode, set env->debugger before the | |
1997 | * riscv_csrrw call and clear it after the call. | |
1998 | */ | |
533c91e8 AF |
1999 | RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, |
2000 | target_ulong *ret_value, | |
2001 | target_ulong new_value, | |
2002 | target_ulong write_mask) | |
753e3fe2 | 2003 | { |
533c91e8 | 2004 | RISCVException ret; |
753e3fe2 JW |
2005 | #if !defined(CONFIG_USER_ONLY) |
2006 | env->debugger = true; | |
2007 | #endif | |
2008 | ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask); | |
2009 | #if !defined(CONFIG_USER_ONLY) | |
2010 | env->debugger = false; | |
2011 | #endif | |
2012 | return ret; | |
2013 | } | |
2014 | ||
c7b95171 | 2015 | /* Control and Status Register function table */ |
56118ee8 | 2016 | riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { |
c7b95171 | 2017 | /* User Floating-Point CSRs */ |
8ceac5dc BM |
2018 | [CSR_FFLAGS] = { "fflags", fs, read_fflags, write_fflags }, |
2019 | [CSR_FRM] = { "frm", fs, read_frm, write_frm }, | |
2020 | [CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr }, | |
8e3a1f18 | 2021 | /* Vector CSRs */ |
8ceac5dc BM |
2022 | [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart }, |
2023 | [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat }, | |
2024 | [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm }, | |
4594fa5a | 2025 | [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr }, |
8ceac5dc BM |
2026 | [CSR_VL] = { "vl", vs, read_vl }, |
2027 | [CSR_VTYPE] = { "vtype", vs, read_vtype }, | |
2e565054 | 2028 | [CSR_VLENB] = { "vlenb", vs, read_vlenb }, |
c7b95171 | 2029 | /* User Timers and Counters */ |
8ceac5dc BM |
2030 | [CSR_CYCLE] = { "cycle", ctr, read_instret }, |
2031 | [CSR_INSTRET] = { "instret", ctr, read_instret }, | |
2032 | [CSR_CYCLEH] = { "cycleh", ctr32, read_instreth }, | |
2033 | [CSR_INSTRETH] = { "instreth", ctr32, read_instreth }, | |
2034 | ||
2035 | /* | |
2036 | * In privileged mode, the monitor will have to emulate TIME CSRs only if | |
2037 | * rdtime callback is not provided by machine/platform emulation. | |
2038 | */ | |
2039 | [CSR_TIME] = { "time", ctr, read_time }, | |
2040 | [CSR_TIMEH] = { "timeh", ctr32, read_timeh }, | |
c7b95171 MC |
2041 | |
2042 | #if !defined(CONFIG_USER_ONLY) | |
2043 | /* Machine Timers and Counters */ | |
8ceac5dc BM |
2044 | [CSR_MCYCLE] = { "mcycle", any, read_instret }, |
2045 | [CSR_MINSTRET] = { "minstret", any, read_instret }, | |
2046 | [CSR_MCYCLEH] = { "mcycleh", any32, read_instreth }, | |
2047 | [CSR_MINSTRETH] = { "minstreth", any32, read_instreth }, | |
c7b95171 MC |
2048 | |
2049 | /* Machine Information Registers */ | |
8ceac5dc BM |
2050 | [CSR_MVENDORID] = { "mvendorid", any, read_zero }, |
2051 | [CSR_MARCHID] = { "marchid", any, read_zero }, | |
2052 | [CSR_MIMPID] = { "mimpid", any, read_zero }, | |
2053 | [CSR_MHARTID] = { "mhartid", any, read_mhartid }, | |
c7b95171 MC |
2054 | |
2055 | /* Machine Trap Setup */ | |
457c360f FP |
2056 | [CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus, NULL, |
2057 | read_mstatus_i128 }, | |
2058 | [CSR_MISA] = { "misa", any, read_misa, write_misa, NULL, | |
2059 | read_misa_i128 }, | |
8ceac5dc BM |
2060 | [CSR_MIDELEG] = { "mideleg", any, read_mideleg, write_mideleg }, |
2061 | [CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg }, | |
2062 | [CSR_MIE] = { "mie", any, read_mie, write_mie }, | |
2063 | [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec }, | |
2064 | [CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, write_mcounteren }, | |
c7b95171 | 2065 | |
8ceac5dc | 2066 | [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush }, |
551fa7e8 | 2067 | |
c7b95171 | 2068 | /* Machine Trap Handling */ |
457c360f FP |
2069 | [CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch, NULL, |
2070 | read_mscratch_i128, write_mscratch_i128 }, | |
8ceac5dc BM |
2071 | [CSR_MEPC] = { "mepc", any, read_mepc, write_mepc }, |
2072 | [CSR_MCAUSE] = { "mcause", any, read_mcause, write_mcause }, | |
ac12b601 | 2073 | [CSR_MTVAL] = { "mtval", any, read_mtval, write_mtval }, |
8ceac5dc | 2074 | [CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip }, |
c7b95171 MC |
2075 | |
2076 | /* Supervisor Trap Setup */ | |
457c360f FP |
2077 | [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus, NULL, |
2078 | read_sstatus_i128 }, | |
8ceac5dc BM |
2079 | [CSR_SIE] = { "sie", smode, read_sie, write_sie }, |
2080 | [CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec }, | |
2081 | [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren }, | |
c7b95171 MC |
2082 | |
2083 | /* Supervisor Trap Handling */ | |
457c360f FP |
2084 | [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch, NULL, |
2085 | read_sscratch_i128, write_sscratch_i128 }, | |
8ceac5dc BM |
2086 | [CSR_SEPC] = { "sepc", smode, read_sepc, write_sepc }, |
2087 | [CSR_SCAUSE] = { "scause", smode, read_scause, write_scause }, | |
ac12b601 | 2088 | [CSR_STVAL] = { "stval", smode, read_stval, write_stval }, |
8ceac5dc | 2089 | [CSR_SIP] = { "sip", smode, NULL, NULL, rmw_sip }, |
c7b95171 MC |
2090 | |
2091 | /* Supervisor Protection and Translation */ | |
8ceac5dc BM |
2092 | [CSR_SATP] = { "satp", smode, read_satp, write_satp }, |
2093 | ||
2094 | [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus }, | |
2095 | [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg }, | |
2096 | [CSR_HIDELEG] = { "hideleg", hmode, read_hideleg, write_hideleg }, | |
2097 | [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip }, | |
2098 | [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip }, | |
2099 | [CSR_HIE] = { "hie", hmode, read_hie, write_hie }, | |
2100 | [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren }, | |
377cbb4b | 2101 | [CSR_HGEIE] = { "hgeie", hmode, read_zero, write_hgeie }, |
8ceac5dc BM |
2102 | [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval }, |
2103 | [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst }, | |
377cbb4b | 2104 | [CSR_HGEIP] = { "hgeip", hmode, read_zero, write_hgeip }, |
8ceac5dc BM |
2105 | [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp }, |
2106 | [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta }, | |
2107 | [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah }, | |
2108 | ||
2109 | [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus }, | |
2110 | [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip }, | |
2111 | [CSR_VSIE] = { "vsie", hmode, read_vsie, write_vsie }, | |
2112 | [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec }, | |
2113 | [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch }, | |
2114 | [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc }, | |
2115 | [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause }, | |
2116 | [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval }, | |
2117 | [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp }, | |
2118 | ||
2119 | [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2 }, | |
2120 | [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst }, | |
34cfb5f6 | 2121 | |
c7b95171 | 2122 | /* Physical Memory Protection */ |
2582a95c | 2123 | [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg }, |
8ceac5dc BM |
2124 | [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg }, |
2125 | [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, | |
2126 | [CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg }, | |
2127 | [CSR_PMPCFG3] = { "pmpcfg3", pmp, read_pmpcfg, write_pmpcfg }, | |
2128 | [CSR_PMPADDR0] = { "pmpaddr0", pmp, read_pmpaddr, write_pmpaddr }, | |
2129 | [CSR_PMPADDR1] = { "pmpaddr1", pmp, read_pmpaddr, write_pmpaddr }, | |
2130 | [CSR_PMPADDR2] = { "pmpaddr2", pmp, read_pmpaddr, write_pmpaddr }, | |
2131 | [CSR_PMPADDR3] = { "pmpaddr3", pmp, read_pmpaddr, write_pmpaddr }, | |
2132 | [CSR_PMPADDR4] = { "pmpaddr4", pmp, read_pmpaddr, write_pmpaddr }, | |
2133 | [CSR_PMPADDR5] = { "pmpaddr5", pmp, read_pmpaddr, write_pmpaddr }, | |
2134 | [CSR_PMPADDR6] = { "pmpaddr6", pmp, read_pmpaddr, write_pmpaddr }, | |
2135 | [CSR_PMPADDR7] = { "pmpaddr7", pmp, read_pmpaddr, write_pmpaddr }, | |
2136 | [CSR_PMPADDR8] = { "pmpaddr8", pmp, read_pmpaddr, write_pmpaddr }, | |
2137 | [CSR_PMPADDR9] = { "pmpaddr9", pmp, read_pmpaddr, write_pmpaddr }, | |
2138 | [CSR_PMPADDR10] = { "pmpaddr10", pmp, read_pmpaddr, write_pmpaddr }, | |
2139 | [CSR_PMPADDR11] = { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr }, | |
2140 | [CSR_PMPADDR12] = { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr }, | |
2141 | [CSR_PMPADDR13] = { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr }, | |
2142 | [CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr }, | |
2143 | [CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr }, | |
c7b95171 | 2144 | |
4bbe8033 AB |
2145 | /* User Pointer Masking */ |
2146 | [CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte }, | |
2147 | [CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask, write_upmmask }, | |
2148 | [CSR_UPMBASE] = { "upmbase", pointer_masking, read_upmbase, write_upmbase }, | |
2149 | /* Machine Pointer Masking */ | |
2150 | [CSR_MMTE] = { "mmte", pointer_masking, read_mmte, write_mmte }, | |
2151 | [CSR_MPMMASK] = { "mpmmask", pointer_masking, read_mpmmask, write_mpmmask }, | |
2152 | [CSR_MPMBASE] = { "mpmbase", pointer_masking, read_mpmbase, write_mpmbase }, | |
2153 | /* Supervisor Pointer Masking */ | |
2154 | [CSR_SMTE] = { "smte", pointer_masking, read_smte, write_smte }, | |
2155 | [CSR_SPMMASK] = { "spmmask", pointer_masking, read_spmmask, write_spmmask }, | |
2156 | [CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase, write_spmbase }, | |
2157 | ||
c7b95171 | 2158 | /* Performance Counters */ |
8ceac5dc BM |
2159 | [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_zero }, |
2160 | [CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_zero }, | |
2161 | [CSR_HPMCOUNTER5] = { "hpmcounter5", ctr, read_zero }, | |
2162 | [CSR_HPMCOUNTER6] = { "hpmcounter6", ctr, read_zero }, | |
2163 | [CSR_HPMCOUNTER7] = { "hpmcounter7", ctr, read_zero }, | |
2164 | [CSR_HPMCOUNTER8] = { "hpmcounter8", ctr, read_zero }, | |
2165 | [CSR_HPMCOUNTER9] = { "hpmcounter9", ctr, read_zero }, | |
2166 | [CSR_HPMCOUNTER10] = { "hpmcounter10", ctr, read_zero }, | |
2167 | [CSR_HPMCOUNTER11] = { "hpmcounter11", ctr, read_zero }, | |
2168 | [CSR_HPMCOUNTER12] = { "hpmcounter12", ctr, read_zero }, | |
2169 | [CSR_HPMCOUNTER13] = { "hpmcounter13", ctr, read_zero }, | |
2170 | [CSR_HPMCOUNTER14] = { "hpmcounter14", ctr, read_zero }, | |
2171 | [CSR_HPMCOUNTER15] = { "hpmcounter15", ctr, read_zero }, | |
2172 | [CSR_HPMCOUNTER16] = { "hpmcounter16", ctr, read_zero }, | |
2173 | [CSR_HPMCOUNTER17] = { "hpmcounter17", ctr, read_zero }, | |
2174 | [CSR_HPMCOUNTER18] = { "hpmcounter18", ctr, read_zero }, | |
2175 | [CSR_HPMCOUNTER19] = { "hpmcounter19", ctr, read_zero }, | |
2176 | [CSR_HPMCOUNTER20] = { "hpmcounter20", ctr, read_zero }, | |
2177 | [CSR_HPMCOUNTER21] = { "hpmcounter21", ctr, read_zero }, | |
2178 | [CSR_HPMCOUNTER22] = { "hpmcounter22", ctr, read_zero }, | |
2179 | [CSR_HPMCOUNTER23] = { "hpmcounter23", ctr, read_zero }, | |
2180 | [CSR_HPMCOUNTER24] = { "hpmcounter24", ctr, read_zero }, | |
2181 | [CSR_HPMCOUNTER25] = { "hpmcounter25", ctr, read_zero }, | |
2182 | [CSR_HPMCOUNTER26] = { "hpmcounter26", ctr, read_zero }, | |
2183 | [CSR_HPMCOUNTER27] = { "hpmcounter27", ctr, read_zero }, | |
2184 | [CSR_HPMCOUNTER28] = { "hpmcounter28", ctr, read_zero }, | |
2185 | [CSR_HPMCOUNTER29] = { "hpmcounter29", ctr, read_zero }, | |
2186 | [CSR_HPMCOUNTER30] = { "hpmcounter30", ctr, read_zero }, | |
2187 | [CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_zero }, | |
2188 | ||
2189 | [CSR_MHPMCOUNTER3] = { "mhpmcounter3", any, read_zero }, | |
2190 | [CSR_MHPMCOUNTER4] = { "mhpmcounter4", any, read_zero }, | |
2191 | [CSR_MHPMCOUNTER5] = { "mhpmcounter5", any, read_zero }, | |
2192 | [CSR_MHPMCOUNTER6] = { "mhpmcounter6", any, read_zero }, | |
2193 | [CSR_MHPMCOUNTER7] = { "mhpmcounter7", any, read_zero }, | |
2194 | [CSR_MHPMCOUNTER8] = { "mhpmcounter8", any, read_zero }, | |
2195 | [CSR_MHPMCOUNTER9] = { "mhpmcounter9", any, read_zero }, | |
2196 | [CSR_MHPMCOUNTER10] = { "mhpmcounter10", any, read_zero }, | |
2197 | [CSR_MHPMCOUNTER11] = { "mhpmcounter11", any, read_zero }, | |
2198 | [CSR_MHPMCOUNTER12] = { "mhpmcounter12", any, read_zero }, | |
2199 | [CSR_MHPMCOUNTER13] = { "mhpmcounter13", any, read_zero }, | |
2200 | [CSR_MHPMCOUNTER14] = { "mhpmcounter14", any, read_zero }, | |
2201 | [CSR_MHPMCOUNTER15] = { "mhpmcounter15", any, read_zero }, | |
2202 | [CSR_MHPMCOUNTER16] = { "mhpmcounter16", any, read_zero }, | |
2203 | [CSR_MHPMCOUNTER17] = { "mhpmcounter17", any, read_zero }, | |
2204 | [CSR_MHPMCOUNTER18] = { "mhpmcounter18", any, read_zero }, | |
2205 | [CSR_MHPMCOUNTER19] = { "mhpmcounter19", any, read_zero }, | |
2206 | [CSR_MHPMCOUNTER20] = { "mhpmcounter20", any, read_zero }, | |
2207 | [CSR_MHPMCOUNTER21] = { "mhpmcounter21", any, read_zero }, | |
2208 | [CSR_MHPMCOUNTER22] = { "mhpmcounter22", any, read_zero }, | |
2209 | [CSR_MHPMCOUNTER23] = { "mhpmcounter23", any, read_zero }, | |
2210 | [CSR_MHPMCOUNTER24] = { "mhpmcounter24", any, read_zero }, | |
2211 | [CSR_MHPMCOUNTER25] = { "mhpmcounter25", any, read_zero }, | |
2212 | [CSR_MHPMCOUNTER26] = { "mhpmcounter26", any, read_zero }, | |
2213 | [CSR_MHPMCOUNTER27] = { "mhpmcounter27", any, read_zero }, | |
2214 | [CSR_MHPMCOUNTER28] = { "mhpmcounter28", any, read_zero }, | |
2215 | [CSR_MHPMCOUNTER29] = { "mhpmcounter29", any, read_zero }, | |
2216 | [CSR_MHPMCOUNTER30] = { "mhpmcounter30", any, read_zero }, | |
2217 | [CSR_MHPMCOUNTER31] = { "mhpmcounter31", any, read_zero }, | |
2218 | ||
2219 | [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_zero }, | |
2220 | [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_zero }, | |
2221 | [CSR_MHPMEVENT5] = { "mhpmevent5", any, read_zero }, | |
2222 | [CSR_MHPMEVENT6] = { "mhpmevent6", any, read_zero }, | |
2223 | [CSR_MHPMEVENT7] = { "mhpmevent7", any, read_zero }, | |
2224 | [CSR_MHPMEVENT8] = { "mhpmevent8", any, read_zero }, | |
2225 | [CSR_MHPMEVENT9] = { "mhpmevent9", any, read_zero }, | |
2226 | [CSR_MHPMEVENT10] = { "mhpmevent10", any, read_zero }, | |
2227 | [CSR_MHPMEVENT11] = { "mhpmevent11", any, read_zero }, | |
2228 | [CSR_MHPMEVENT12] = { "mhpmevent12", any, read_zero }, | |
2229 | [CSR_MHPMEVENT13] = { "mhpmevent13", any, read_zero }, | |
2230 | [CSR_MHPMEVENT14] = { "mhpmevent14", any, read_zero }, | |
2231 | [CSR_MHPMEVENT15] = { "mhpmevent15", any, read_zero }, | |
2232 | [CSR_MHPMEVENT16] = { "mhpmevent16", any, read_zero }, | |
2233 | [CSR_MHPMEVENT17] = { "mhpmevent17", any, read_zero }, | |
2234 | [CSR_MHPMEVENT18] = { "mhpmevent18", any, read_zero }, | |
2235 | [CSR_MHPMEVENT19] = { "mhpmevent19", any, read_zero }, | |
2236 | [CSR_MHPMEVENT20] = { "mhpmevent20", any, read_zero }, | |
2237 | [CSR_MHPMEVENT21] = { "mhpmevent21", any, read_zero }, | |
2238 | [CSR_MHPMEVENT22] = { "mhpmevent22", any, read_zero }, | |
2239 | [CSR_MHPMEVENT23] = { "mhpmevent23", any, read_zero }, | |
2240 | [CSR_MHPMEVENT24] = { "mhpmevent24", any, read_zero }, | |
2241 | [CSR_MHPMEVENT25] = { "mhpmevent25", any, read_zero }, | |
2242 | [CSR_MHPMEVENT26] = { "mhpmevent26", any, read_zero }, | |
2243 | [CSR_MHPMEVENT27] = { "mhpmevent27", any, read_zero }, | |
2244 | [CSR_MHPMEVENT28] = { "mhpmevent28", any, read_zero }, | |
2245 | [CSR_MHPMEVENT29] = { "mhpmevent29", any, read_zero }, | |
2246 | [CSR_MHPMEVENT30] = { "mhpmevent30", any, read_zero }, | |
2247 | [CSR_MHPMEVENT31] = { "mhpmevent31", any, read_zero }, | |
2248 | ||
2249 | [CSR_HPMCOUNTER3H] = { "hpmcounter3h", ctr32, read_zero }, | |
2250 | [CSR_HPMCOUNTER4H] = { "hpmcounter4h", ctr32, read_zero }, | |
2251 | [CSR_HPMCOUNTER5H] = { "hpmcounter5h", ctr32, read_zero }, | |
2252 | [CSR_HPMCOUNTER6H] = { "hpmcounter6h", ctr32, read_zero }, | |
2253 | [CSR_HPMCOUNTER7H] = { "hpmcounter7h", ctr32, read_zero }, | |
2254 | [CSR_HPMCOUNTER8H] = { "hpmcounter8h", ctr32, read_zero }, | |
2255 | [CSR_HPMCOUNTER9H] = { "hpmcounter9h", ctr32, read_zero }, | |
2256 | [CSR_HPMCOUNTER10H] = { "hpmcounter10h", ctr32, read_zero }, | |
2257 | [CSR_HPMCOUNTER11H] = { "hpmcounter11h", ctr32, read_zero }, | |
2258 | [CSR_HPMCOUNTER12H] = { "hpmcounter12h", ctr32, read_zero }, | |
2259 | [CSR_HPMCOUNTER13H] = { "hpmcounter13h", ctr32, read_zero }, | |
2260 | [CSR_HPMCOUNTER14H] = { "hpmcounter14h", ctr32, read_zero }, | |
2261 | [CSR_HPMCOUNTER15H] = { "hpmcounter15h", ctr32, read_zero }, | |
2262 | [CSR_HPMCOUNTER16H] = { "hpmcounter16h", ctr32, read_zero }, | |
2263 | [CSR_HPMCOUNTER17H] = { "hpmcounter17h", ctr32, read_zero }, | |
2264 | [CSR_HPMCOUNTER18H] = { "hpmcounter18h", ctr32, read_zero }, | |
2265 | [CSR_HPMCOUNTER19H] = { "hpmcounter19h", ctr32, read_zero }, | |
2266 | [CSR_HPMCOUNTER20H] = { "hpmcounter20h", ctr32, read_zero }, | |
2267 | [CSR_HPMCOUNTER21H] = { "hpmcounter21h", ctr32, read_zero }, | |
2268 | [CSR_HPMCOUNTER22H] = { "hpmcounter22h", ctr32, read_zero }, | |
2269 | [CSR_HPMCOUNTER23H] = { "hpmcounter23h", ctr32, read_zero }, | |
2270 | [CSR_HPMCOUNTER24H] = { "hpmcounter24h", ctr32, read_zero }, | |
2271 | [CSR_HPMCOUNTER25H] = { "hpmcounter25h", ctr32, read_zero }, | |
2272 | [CSR_HPMCOUNTER26H] = { "hpmcounter26h", ctr32, read_zero }, | |
2273 | [CSR_HPMCOUNTER27H] = { "hpmcounter27h", ctr32, read_zero }, | |
2274 | [CSR_HPMCOUNTER28H] = { "hpmcounter28h", ctr32, read_zero }, | |
2275 | [CSR_HPMCOUNTER29H] = { "hpmcounter29h", ctr32, read_zero }, | |
2276 | [CSR_HPMCOUNTER30H] = { "hpmcounter30h", ctr32, read_zero }, | |
2277 | [CSR_HPMCOUNTER31H] = { "hpmcounter31h", ctr32, read_zero }, | |
2278 | ||
2279 | [CSR_MHPMCOUNTER3H] = { "mhpmcounter3h", any32, read_zero }, | |
2280 | [CSR_MHPMCOUNTER4H] = { "mhpmcounter4h", any32, read_zero }, | |
2281 | [CSR_MHPMCOUNTER5H] = { "mhpmcounter5h", any32, read_zero }, | |
2282 | [CSR_MHPMCOUNTER6H] = { "mhpmcounter6h", any32, read_zero }, | |
2283 | [CSR_MHPMCOUNTER7H] = { "mhpmcounter7h", any32, read_zero }, | |
2284 | [CSR_MHPMCOUNTER8H] = { "mhpmcounter8h", any32, read_zero }, | |
2285 | [CSR_MHPMCOUNTER9H] = { "mhpmcounter9h", any32, read_zero }, | |
2286 | [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", any32, read_zero }, | |
2287 | [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", any32, read_zero }, | |
2288 | [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", any32, read_zero }, | |
2289 | [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", any32, read_zero }, | |
2290 | [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", any32, read_zero }, | |
2291 | [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", any32, read_zero }, | |
2292 | [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", any32, read_zero }, | |
2293 | [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", any32, read_zero }, | |
2294 | [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", any32, read_zero }, | |
2295 | [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", any32, read_zero }, | |
2296 | [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", any32, read_zero }, | |
2297 | [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", any32, read_zero }, | |
2298 | [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", any32, read_zero }, | |
2299 | [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", any32, read_zero }, | |
2300 | [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", any32, read_zero }, | |
2301 | [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", any32, read_zero }, | |
2302 | [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", any32, read_zero }, | |
2303 | [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", any32, read_zero }, | |
2304 | [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", any32, read_zero }, | |
2305 | [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32, read_zero }, | |
2306 | [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32, read_zero }, | |
2307 | [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32, read_zero }, | |
c7b95171 MC |
2308 | #endif /* !CONFIG_USER_ONLY */ |
2309 | }; |