]>
Commit | Line | Data |
---|---|---|
c7b95171 MC |
1 | /* |
2 | * RISC-V Control and Status Registers. | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017-2018 SiFive, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2 or later, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
21 | #include "qemu/log.h" | |
22 | #include "cpu.h" | |
23 | #include "qemu/main-loop.h" | |
24 | #include "exec/exec-all.h" | |
25 | ||
26 | /* CSR function table */ | |
27 | static riscv_csr_operations csr_ops[]; | |
28 | ||
29 | /* CSR function table constants */ | |
30 | enum { | |
31 | CSR_TABLE_SIZE = 0x1000 | |
32 | }; | |
33 | ||
34 | /* CSR function table public API */ | |
35 | void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) | |
36 | { | |
37 | *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)]; | |
38 | } | |
39 | ||
40 | void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) | |
41 | { | |
42 | csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops; | |
43 | } | |
44 | ||
a88365c1 MC |
45 | /* Predicates */ |
46 | static int fs(CPURISCVState *env, int csrno) | |
47 | { | |
48 | #if !defined(CONFIG_USER_ONLY) | |
b345b480 | 49 | if (!env->debugger && !riscv_cpu_fp_enabled(env)) { |
a88365c1 MC |
50 | return -1; |
51 | } | |
52 | #endif | |
53 | return 0; | |
54 | } | |
55 | ||
56 | static int ctr(CPURISCVState *env, int csrno) | |
57 | { | |
58 | #if !defined(CONFIG_USER_ONLY) | |
0a13a5b8 AF |
59 | CPUState *cs = env_cpu(env); |
60 | RISCVCPU *cpu = RISCV_CPU(cs); | |
61 | uint32_t ctr_en = ~0u; | |
62 | ||
63 | if (!cpu->cfg.ext_counters) { | |
64 | /* The Counters extensions is not enabled */ | |
65 | return -1; | |
66 | } | |
67 | ||
747a43e8 | 68 | /* |
0a13a5b8 AF |
69 | * The counters are always enabled at run time on newer priv specs, as the |
70 | * CSR has changed from controlling that the counters can be read to | |
71 | * controlling that the counters increment. | |
747a43e8 AF |
72 | */ |
73 | if (env->priv_ver > PRIV_VERSION_1_09_1) { | |
74 | return 0; | |
75 | } | |
76 | ||
ff9f31d9 XW |
77 | if (env->priv < PRV_M) { |
78 | ctr_en &= env->mcounteren; | |
79 | } | |
80 | if (env->priv < PRV_S) { | |
81 | ctr_en &= env->scounteren; | |
82 | } | |
83 | if (!(ctr_en & (1u << (csrno & 31)))) { | |
a88365c1 MC |
84 | return -1; |
85 | } | |
86 | #endif | |
87 | return 0; | |
88 | } | |
89 | ||
90 | #if !defined(CONFIG_USER_ONLY) | |
91 | static int any(CPURISCVState *env, int csrno) | |
92 | { | |
93 | return 0; | |
94 | } | |
95 | ||
96 | static int smode(CPURISCVState *env, int csrno) | |
97 | { | |
98 | return -!riscv_has_ext(env, RVS); | |
99 | } | |
100 | ||
101 | static int pmp(CPURISCVState *env, int csrno) | |
102 | { | |
103 | return -!riscv_feature(env, RISCV_FEATURE_PMP); | |
104 | } | |
105 | #endif | |
106 | ||
c7b95171 MC |
107 | /* User Floating-Point CSRs */ |
108 | static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val) | |
109 | { | |
110 | #if !defined(CONFIG_USER_ONLY) | |
b345b480 | 111 | if (!env->debugger && !riscv_cpu_fp_enabled(env)) { |
c7b95171 MC |
112 | return -1; |
113 | } | |
114 | #endif | |
fb738839 | 115 | *val = riscv_cpu_get_fflags(env); |
c7b95171 MC |
116 | return 0; |
117 | } | |
118 | ||
119 | static int write_fflags(CPURISCVState *env, int csrno, target_ulong val) | |
120 | { | |
121 | #if !defined(CONFIG_USER_ONLY) | |
b345b480 | 122 | if (!env->debugger && !riscv_cpu_fp_enabled(env)) { |
c7b95171 MC |
123 | return -1; |
124 | } | |
125 | env->mstatus |= MSTATUS_FS; | |
126 | #endif | |
fb738839 | 127 | riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT)); |
c7b95171 MC |
128 | return 0; |
129 | } | |
130 | ||
131 | static int read_frm(CPURISCVState *env, int csrno, target_ulong *val) | |
132 | { | |
133 | #if !defined(CONFIG_USER_ONLY) | |
b345b480 | 134 | if (!env->debugger && !riscv_cpu_fp_enabled(env)) { |
c7b95171 MC |
135 | return -1; |
136 | } | |
137 | #endif | |
138 | *val = env->frm; | |
139 | return 0; | |
140 | } | |
141 | ||
142 | static int write_frm(CPURISCVState *env, int csrno, target_ulong val) | |
143 | { | |
144 | #if !defined(CONFIG_USER_ONLY) | |
b345b480 | 145 | if (!env->debugger && !riscv_cpu_fp_enabled(env)) { |
c7b95171 MC |
146 | return -1; |
147 | } | |
148 | env->mstatus |= MSTATUS_FS; | |
149 | #endif | |
150 | env->frm = val & (FSR_RD >> FSR_RD_SHIFT); | |
151 | return 0; | |
152 | } | |
153 | ||
154 | static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val) | |
155 | { | |
156 | #if !defined(CONFIG_USER_ONLY) | |
b345b480 | 157 | if (!env->debugger && !riscv_cpu_fp_enabled(env)) { |
c7b95171 MC |
158 | return -1; |
159 | } | |
160 | #endif | |
fb738839 | 161 | *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) |
c7b95171 MC |
162 | | (env->frm << FSR_RD_SHIFT); |
163 | return 0; | |
164 | } | |
165 | ||
166 | static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val) | |
167 | { | |
168 | #if !defined(CONFIG_USER_ONLY) | |
b345b480 | 169 | if (!env->debugger && !riscv_cpu_fp_enabled(env)) { |
c7b95171 MC |
170 | return -1; |
171 | } | |
172 | env->mstatus |= MSTATUS_FS; | |
173 | #endif | |
174 | env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; | |
fb738839 | 175 | riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT); |
c7b95171 MC |
176 | return 0; |
177 | } | |
178 | ||
179 | /* User Timers and Counters */ | |
c7b95171 MC |
180 | static int read_instret(CPURISCVState *env, int csrno, target_ulong *val) |
181 | { | |
c7b95171 MC |
182 | #if !defined(CONFIG_USER_ONLY) |
183 | if (use_icount) { | |
184 | *val = cpu_get_icount(); | |
185 | } else { | |
186 | *val = cpu_get_host_ticks(); | |
187 | } | |
188 | #else | |
189 | *val = cpu_get_host_ticks(); | |
190 | #endif | |
191 | return 0; | |
192 | } | |
193 | ||
194 | #if defined(TARGET_RISCV32) | |
195 | static int read_instreth(CPURISCVState *env, int csrno, target_ulong *val) | |
196 | { | |
c7b95171 MC |
197 | #if !defined(CONFIG_USER_ONLY) |
198 | if (use_icount) { | |
199 | *val = cpu_get_icount() >> 32; | |
200 | } else { | |
201 | *val = cpu_get_host_ticks() >> 32; | |
202 | } | |
203 | #else | |
204 | *val = cpu_get_host_ticks() >> 32; | |
205 | #endif | |
206 | return 0; | |
207 | } | |
208 | #endif /* TARGET_RISCV32 */ | |
209 | ||
210 | #if defined(CONFIG_USER_ONLY) | |
211 | static int read_time(CPURISCVState *env, int csrno, target_ulong *val) | |
212 | { | |
213 | *val = cpu_get_host_ticks(); | |
214 | return 0; | |
215 | } | |
216 | ||
217 | #if defined(TARGET_RISCV32) | |
218 | static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val) | |
219 | { | |
220 | *val = cpu_get_host_ticks() >> 32; | |
221 | return 0; | |
222 | } | |
223 | #endif | |
224 | ||
225 | #else /* CONFIG_USER_ONLY */ | |
226 | ||
227 | /* Machine constants */ | |
228 | ||
229 | #define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP) | |
230 | #define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP) | |
231 | ||
232 | static const target_ulong delegable_ints = S_MODE_INTERRUPTS; | |
233 | static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS; | |
234 | static const target_ulong delegable_excps = | |
235 | (1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | | |
236 | (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | | |
237 | (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | | |
238 | (1ULL << (RISCV_EXCP_BREAKPOINT)) | | |
239 | (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | | |
240 | (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | | |
241 | (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | | |
242 | (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | | |
243 | (1ULL << (RISCV_EXCP_U_ECALL)) | | |
244 | (1ULL << (RISCV_EXCP_S_ECALL)) | | |
ab67a1d0 | 245 | (1ULL << (RISCV_EXCP_VS_ECALL)) | |
c7b95171 MC |
246 | (1ULL << (RISCV_EXCP_M_ECALL)) | |
247 | (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | | |
248 | (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | | |
ab67a1d0 AF |
249 | (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | |
250 | (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | | |
251 | (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | | |
252 | (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)); | |
c7b95171 MC |
253 | static const target_ulong sstatus_v1_9_mask = SSTATUS_SIE | SSTATUS_SPIE | |
254 | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | | |
255 | SSTATUS_SUM | SSTATUS_SD; | |
256 | static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | | |
257 | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | | |
258 | SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD; | |
087b051a | 259 | static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP; |
c7b95171 MC |
260 | |
261 | #if defined(TARGET_RISCV32) | |
262 | static const char valid_vm_1_09[16] = { | |
263 | [VM_1_09_MBARE] = 1, | |
264 | [VM_1_09_SV32] = 1, | |
265 | }; | |
266 | static const char valid_vm_1_10[16] = { | |
267 | [VM_1_10_MBARE] = 1, | |
268 | [VM_1_10_SV32] = 1 | |
269 | }; | |
270 | #elif defined(TARGET_RISCV64) | |
271 | static const char valid_vm_1_09[16] = { | |
272 | [VM_1_09_MBARE] = 1, | |
273 | [VM_1_09_SV39] = 1, | |
274 | [VM_1_09_SV48] = 1, | |
275 | }; | |
276 | static const char valid_vm_1_10[16] = { | |
277 | [VM_1_10_MBARE] = 1, | |
278 | [VM_1_10_SV39] = 1, | |
279 | [VM_1_10_SV48] = 1, | |
280 | [VM_1_10_SV57] = 1 | |
281 | }; | |
282 | #endif /* CONFIG_USER_ONLY */ | |
283 | ||
284 | /* Machine Information Registers */ | |
285 | static int read_zero(CPURISCVState *env, int csrno, target_ulong *val) | |
286 | { | |
287 | return *val = 0; | |
288 | } | |
289 | ||
290 | static int read_mhartid(CPURISCVState *env, int csrno, target_ulong *val) | |
291 | { | |
292 | *val = env->mhartid; | |
293 | return 0; | |
294 | } | |
295 | ||
296 | /* Machine Trap Setup */ | |
297 | static int read_mstatus(CPURISCVState *env, int csrno, target_ulong *val) | |
298 | { | |
299 | *val = env->mstatus; | |
300 | return 0; | |
301 | } | |
302 | ||
303 | static int validate_vm(CPURISCVState *env, target_ulong vm) | |
304 | { | |
305 | return (env->priv_ver >= PRIV_VERSION_1_10_0) ? | |
306 | valid_vm_1_10[vm & 0xf] : valid_vm_1_09[vm & 0xf]; | |
307 | } | |
308 | ||
309 | static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) | |
310 | { | |
311 | target_ulong mstatus = env->mstatus; | |
312 | target_ulong mask = 0; | |
b345b480 | 313 | int dirty; |
c7b95171 MC |
314 | |
315 | /* flush tlb on mstatus fields that affect VM */ | |
316 | if (env->priv_ver <= PRIV_VERSION_1_09_1) { | |
317 | if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | | |
318 | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_VM)) { | |
3109cd98 | 319 | tlb_flush(env_cpu(env)); |
c7b95171 MC |
320 | } |
321 | mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | | |
322 | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | | |
323 | MSTATUS_MPP | MSTATUS_MXR | | |
324 | (validate_vm(env, get_field(val, MSTATUS_VM)) ? | |
325 | MSTATUS_VM : 0); | |
326 | } | |
327 | if (env->priv_ver >= PRIV_VERSION_1_10_0) { | |
1f0419cb | 328 | if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | |
c7b95171 | 329 | MSTATUS_MPRV | MSTATUS_SUM)) { |
3109cd98 | 330 | tlb_flush(env_cpu(env)); |
c7b95171 MC |
331 | } |
332 | mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | | |
333 | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | | |
7f2b5ff1 MC |
334 | MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | |
335 | MSTATUS_TW; | |
1f0419cb AF |
336 | #if defined(TARGET_RISCV64) |
337 | /* | |
338 | * RV32: MPV and MTL are not in mstatus. The current plan is to | |
339 | * add them to mstatush. For now, we just don't support it. | |
340 | */ | |
14115b91 | 341 | mask |= MSTATUS_MTL | MSTATUS_MPV; |
1f0419cb | 342 | #endif |
c7b95171 MC |
343 | } |
344 | ||
345 | mstatus = (mstatus & ~mask) | (val & mask); | |
346 | ||
82f01467 | 347 | dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) | |
b345b480 | 348 | ((mstatus & MSTATUS_XS) == MSTATUS_XS); |
c7b95171 MC |
349 | mstatus = set_field(mstatus, MSTATUS_SD, dirty); |
350 | env->mstatus = mstatus; | |
351 | ||
352 | return 0; | |
353 | } | |
354 | ||
355 | static int read_misa(CPURISCVState *env, int csrno, target_ulong *val) | |
356 | { | |
357 | *val = env->misa; | |
358 | return 0; | |
359 | } | |
360 | ||
f18637cd MC |
361 | static int write_misa(CPURISCVState *env, int csrno, target_ulong val) |
362 | { | |
363 | if (!riscv_feature(env, RISCV_FEATURE_MISA)) { | |
364 | /* drop write to misa */ | |
365 | return 0; | |
366 | } | |
367 | ||
368 | /* 'I' or 'E' must be present */ | |
369 | if (!(val & (RVI | RVE))) { | |
370 | /* It is not, drop write to misa */ | |
371 | return 0; | |
372 | } | |
373 | ||
374 | /* 'E' excludes all other extensions */ | |
375 | if (val & RVE) { | |
376 | /* when we support 'E' we can do "val = RVE;" however | |
377 | * for now we just drop writes if 'E' is present. | |
378 | */ | |
379 | return 0; | |
380 | } | |
381 | ||
382 | /* Mask extensions that are not supported by this hart */ | |
383 | val &= env->misa_mask; | |
384 | ||
385 | /* Mask extensions that are not supported by QEMU */ | |
386 | val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU); | |
387 | ||
388 | /* 'D' depends on 'F', so clear 'D' if 'F' is not present */ | |
389 | if ((val & RVD) && !(val & RVF)) { | |
390 | val &= ~RVD; | |
391 | } | |
392 | ||
393 | /* Suppress 'C' if next instruction is not aligned | |
394 | * TODO: this should check next_pc | |
395 | */ | |
396 | if ((val & RVC) && (GETPC() & ~3) != 0) { | |
397 | val &= ~RVC; | |
398 | } | |
399 | ||
400 | /* misa.MXL writes are not supported by QEMU */ | |
401 | val = (env->misa & MISA_MXL) | (val & ~MISA_MXL); | |
402 | ||
403 | /* flush translation cache */ | |
404 | if (val != env->misa) { | |
3109cd98 | 405 | tb_flush(env_cpu(env)); |
f18637cd MC |
406 | } |
407 | ||
408 | env->misa = val; | |
409 | ||
410 | return 0; | |
411 | } | |
412 | ||
c7b95171 MC |
413 | static int read_medeleg(CPURISCVState *env, int csrno, target_ulong *val) |
414 | { | |
415 | *val = env->medeleg; | |
416 | return 0; | |
417 | } | |
418 | ||
419 | static int write_medeleg(CPURISCVState *env, int csrno, target_ulong val) | |
420 | { | |
421 | env->medeleg = (env->medeleg & ~delegable_excps) | (val & delegable_excps); | |
422 | return 0; | |
423 | } | |
424 | ||
425 | static int read_mideleg(CPURISCVState *env, int csrno, target_ulong *val) | |
426 | { | |
427 | *val = env->mideleg; | |
428 | return 0; | |
429 | } | |
430 | ||
431 | static int write_mideleg(CPURISCVState *env, int csrno, target_ulong val) | |
432 | { | |
433 | env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints); | |
434 | return 0; | |
435 | } | |
436 | ||
437 | static int read_mie(CPURISCVState *env, int csrno, target_ulong *val) | |
438 | { | |
439 | *val = env->mie; | |
440 | return 0; | |
441 | } | |
442 | ||
443 | static int write_mie(CPURISCVState *env, int csrno, target_ulong val) | |
444 | { | |
445 | env->mie = (env->mie & ~all_ints) | (val & all_ints); | |
446 | return 0; | |
447 | } | |
448 | ||
449 | static int read_mtvec(CPURISCVState *env, int csrno, target_ulong *val) | |
450 | { | |
451 | *val = env->mtvec; | |
452 | return 0; | |
453 | } | |
454 | ||
455 | static int write_mtvec(CPURISCVState *env, int csrno, target_ulong val) | |
456 | { | |
457 | /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ | |
acbbb94e MC |
458 | if ((val & 3) < 2) { |
459 | env->mtvec = val; | |
c7b95171 | 460 | } else { |
acbbb94e | 461 | qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n"); |
c7b95171 MC |
462 | } |
463 | return 0; | |
464 | } | |
465 | ||
466 | static int read_mcounteren(CPURISCVState *env, int csrno, target_ulong *val) | |
467 | { | |
468 | if (env->priv_ver < PRIV_VERSION_1_10_0) { | |
469 | return -1; | |
470 | } | |
471 | *val = env->mcounteren; | |
472 | return 0; | |
473 | } | |
474 | ||
475 | static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val) | |
476 | { | |
477 | if (env->priv_ver < PRIV_VERSION_1_10_0) { | |
478 | return -1; | |
479 | } | |
480 | env->mcounteren = val; | |
481 | return 0; | |
482 | } | |
483 | ||
747a43e8 | 484 | /* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ |
c7b95171 MC |
485 | static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val) |
486 | { | |
747a43e8 AF |
487 | if (env->priv_ver > PRIV_VERSION_1_09_1 |
488 | && env->priv_ver < PRIV_VERSION_1_11_0) { | |
c7b95171 MC |
489 | return -1; |
490 | } | |
491 | *val = env->mcounteren; | |
492 | return 0; | |
493 | } | |
494 | ||
747a43e8 | 495 | /* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ |
c7b95171 MC |
496 | static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val) |
497 | { | |
747a43e8 AF |
498 | if (env->priv_ver > PRIV_VERSION_1_09_1 |
499 | && env->priv_ver < PRIV_VERSION_1_11_0) { | |
c7b95171 MC |
500 | return -1; |
501 | } | |
502 | env->mcounteren = val; | |
503 | return 0; | |
504 | } | |
505 | ||
506 | static int read_mucounteren(CPURISCVState *env, int csrno, target_ulong *val) | |
507 | { | |
508 | if (env->priv_ver > PRIV_VERSION_1_09_1) { | |
509 | return -1; | |
510 | } | |
511 | *val = env->scounteren; | |
512 | return 0; | |
513 | } | |
514 | ||
515 | static int write_mucounteren(CPURISCVState *env, int csrno, target_ulong val) | |
516 | { | |
517 | if (env->priv_ver > PRIV_VERSION_1_09_1) { | |
518 | return -1; | |
519 | } | |
520 | env->scounteren = val; | |
521 | return 0; | |
522 | } | |
523 | ||
524 | /* Machine Trap Handling */ | |
525 | static int read_mscratch(CPURISCVState *env, int csrno, target_ulong *val) | |
526 | { | |
527 | *val = env->mscratch; | |
528 | return 0; | |
529 | } | |
530 | ||
531 | static int write_mscratch(CPURISCVState *env, int csrno, target_ulong val) | |
532 | { | |
533 | env->mscratch = val; | |
534 | return 0; | |
535 | } | |
536 | ||
537 | static int read_mepc(CPURISCVState *env, int csrno, target_ulong *val) | |
538 | { | |
539 | *val = env->mepc; | |
540 | return 0; | |
541 | } | |
542 | ||
543 | static int write_mepc(CPURISCVState *env, int csrno, target_ulong val) | |
544 | { | |
545 | env->mepc = val; | |
546 | return 0; | |
547 | } | |
548 | ||
549 | static int read_mcause(CPURISCVState *env, int csrno, target_ulong *val) | |
550 | { | |
551 | *val = env->mcause; | |
552 | return 0; | |
553 | } | |
554 | ||
555 | static int write_mcause(CPURISCVState *env, int csrno, target_ulong val) | |
556 | { | |
557 | env->mcause = val; | |
558 | return 0; | |
559 | } | |
560 | ||
561 | static int read_mbadaddr(CPURISCVState *env, int csrno, target_ulong *val) | |
562 | { | |
563 | *val = env->mbadaddr; | |
564 | return 0; | |
565 | } | |
566 | ||
567 | static int write_mbadaddr(CPURISCVState *env, int csrno, target_ulong val) | |
568 | { | |
569 | env->mbadaddr = val; | |
570 | return 0; | |
571 | } | |
572 | ||
71877e29 MC |
573 | static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value, |
574 | target_ulong new_value, target_ulong write_mask) | |
c7b95171 | 575 | { |
3109cd98 | 576 | RISCVCPU *cpu = env_archcpu(env); |
e3e7039c MC |
577 | /* Allow software control of delegable interrupts not claimed by hardware */ |
578 | target_ulong mask = write_mask & delegable_ints & ~env->miclaim; | |
71877e29 MC |
579 | uint32_t old_mip; |
580 | ||
71877e29 | 581 | if (mask) { |
71877e29 | 582 | old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask)); |
71877e29 | 583 | } else { |
7ec5d303 | 584 | old_mip = env->mip; |
71877e29 | 585 | } |
c7b95171 | 586 | |
71877e29 MC |
587 | if (ret_value) { |
588 | *ret_value = old_mip; | |
589 | } | |
c7b95171 MC |
590 | |
591 | return 0; | |
592 | } | |
593 | ||
594 | /* Supervisor Trap Setup */ | |
595 | static int read_sstatus(CPURISCVState *env, int csrno, target_ulong *val) | |
596 | { | |
597 | target_ulong mask = ((env->priv_ver >= PRIV_VERSION_1_10_0) ? | |
598 | sstatus_v1_10_mask : sstatus_v1_9_mask); | |
599 | *val = env->mstatus & mask; | |
600 | return 0; | |
601 | } | |
602 | ||
603 | static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val) | |
604 | { | |
605 | target_ulong mask = ((env->priv_ver >= PRIV_VERSION_1_10_0) ? | |
606 | sstatus_v1_10_mask : sstatus_v1_9_mask); | |
607 | target_ulong newval = (env->mstatus & ~mask) | (val & mask); | |
608 | return write_mstatus(env, CSR_MSTATUS, newval); | |
609 | } | |
610 | ||
611 | static int read_sie(CPURISCVState *env, int csrno, target_ulong *val) | |
612 | { | |
613 | *val = env->mie & env->mideleg; | |
614 | return 0; | |
615 | } | |
616 | ||
617 | static int write_sie(CPURISCVState *env, int csrno, target_ulong val) | |
618 | { | |
619 | target_ulong newval = (env->mie & ~env->mideleg) | (val & env->mideleg); | |
620 | return write_mie(env, CSR_MIE, newval); | |
621 | } | |
622 | ||
623 | static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val) | |
624 | { | |
625 | *val = env->stvec; | |
626 | return 0; | |
627 | } | |
628 | ||
629 | static int write_stvec(CPURISCVState *env, int csrno, target_ulong val) | |
630 | { | |
631 | /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ | |
acbbb94e MC |
632 | if ((val & 3) < 2) { |
633 | env->stvec = val; | |
c7b95171 | 634 | } else { |
acbbb94e | 635 | qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n"); |
c7b95171 MC |
636 | } |
637 | return 0; | |
638 | } | |
639 | ||
640 | static int read_scounteren(CPURISCVState *env, int csrno, target_ulong *val) | |
641 | { | |
642 | if (env->priv_ver < PRIV_VERSION_1_10_0) { | |
643 | return -1; | |
644 | } | |
645 | *val = env->scounteren; | |
646 | return 0; | |
647 | } | |
648 | ||
649 | static int write_scounteren(CPURISCVState *env, int csrno, target_ulong val) | |
650 | { | |
651 | if (env->priv_ver < PRIV_VERSION_1_10_0) { | |
652 | return -1; | |
653 | } | |
654 | env->scounteren = val; | |
655 | return 0; | |
656 | } | |
657 | ||
658 | /* Supervisor Trap Handling */ | |
659 | static int read_sscratch(CPURISCVState *env, int csrno, target_ulong *val) | |
660 | { | |
661 | *val = env->sscratch; | |
662 | return 0; | |
663 | } | |
664 | ||
665 | static int write_sscratch(CPURISCVState *env, int csrno, target_ulong val) | |
666 | { | |
667 | env->sscratch = val; | |
668 | return 0; | |
669 | } | |
670 | ||
671 | static int read_sepc(CPURISCVState *env, int csrno, target_ulong *val) | |
672 | { | |
673 | *val = env->sepc; | |
674 | return 0; | |
675 | } | |
676 | ||
677 | static int write_sepc(CPURISCVState *env, int csrno, target_ulong val) | |
678 | { | |
679 | env->sepc = val; | |
680 | return 0; | |
681 | } | |
682 | ||
683 | static int read_scause(CPURISCVState *env, int csrno, target_ulong *val) | |
684 | { | |
685 | *val = env->scause; | |
686 | return 0; | |
687 | } | |
688 | ||
689 | static int write_scause(CPURISCVState *env, int csrno, target_ulong val) | |
690 | { | |
691 | env->scause = val; | |
692 | return 0; | |
693 | } | |
694 | ||
695 | static int read_sbadaddr(CPURISCVState *env, int csrno, target_ulong *val) | |
696 | { | |
697 | *val = env->sbadaddr; | |
698 | return 0; | |
699 | } | |
700 | ||
701 | static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val) | |
702 | { | |
703 | env->sbadaddr = val; | |
704 | return 0; | |
705 | } | |
706 | ||
71877e29 MC |
707 | static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value, |
708 | target_ulong new_value, target_ulong write_mask) | |
c7b95171 | 709 | { |
087b051a JB |
710 | int ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value, |
711 | write_mask & env->mideleg & sip_writable_mask); | |
712 | *ret_value &= env->mideleg; | |
713 | return ret; | |
c7b95171 MC |
714 | } |
715 | ||
716 | /* Supervisor Protection and Translation */ | |
717 | static int read_satp(CPURISCVState *env, int csrno, target_ulong *val) | |
718 | { | |
719 | if (!riscv_feature(env, RISCV_FEATURE_MMU)) { | |
720 | *val = 0; | |
721 | } else if (env->priv_ver >= PRIV_VERSION_1_10_0) { | |
7f2b5ff1 MC |
722 | if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { |
723 | return -1; | |
724 | } else { | |
725 | *val = env->satp; | |
726 | } | |
c7b95171 MC |
727 | } else { |
728 | *val = env->sptbr; | |
729 | } | |
730 | return 0; | |
731 | } | |
732 | ||
733 | static int write_satp(CPURISCVState *env, int csrno, target_ulong val) | |
734 | { | |
735 | if (!riscv_feature(env, RISCV_FEATURE_MMU)) { | |
736 | return 0; | |
737 | } | |
738 | if (env->priv_ver <= PRIV_VERSION_1_09_1 && (val ^ env->sptbr)) { | |
3109cd98 | 739 | tlb_flush(env_cpu(env)); |
c7b95171 MC |
740 | env->sptbr = val & (((target_ulong) |
741 | 1 << (TARGET_PHYS_ADDR_SPACE_BITS - PGSHIFT)) - 1); | |
742 | } | |
743 | if (env->priv_ver >= PRIV_VERSION_1_10_0 && | |
744 | validate_vm(env, get_field(val, SATP_MODE)) && | |
745 | ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN))) | |
746 | { | |
7f2b5ff1 MC |
747 | if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { |
748 | return -1; | |
749 | } else { | |
1e0d985f | 750 | if((val ^ env->satp) & SATP_ASID) { |
3109cd98 | 751 | tlb_flush(env_cpu(env)); |
1e0d985f | 752 | } |
7f2b5ff1 MC |
753 | env->satp = val; |
754 | } | |
c7b95171 MC |
755 | } |
756 | return 0; | |
757 | } | |
758 | ||
759 | /* Physical Memory Protection */ | |
760 | static int read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val) | |
761 | { | |
762 | *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0); | |
763 | return 0; | |
764 | } | |
765 | ||
766 | static int write_pmpcfg(CPURISCVState *env, int csrno, target_ulong val) | |
767 | { | |
768 | pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val); | |
769 | return 0; | |
770 | } | |
771 | ||
772 | static int read_pmpaddr(CPURISCVState *env, int csrno, target_ulong *val) | |
773 | { | |
774 | *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0); | |
775 | return 0; | |
776 | } | |
777 | ||
778 | static int write_pmpaddr(CPURISCVState *env, int csrno, target_ulong val) | |
779 | { | |
780 | pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val); | |
781 | return 0; | |
782 | } | |
783 | ||
784 | #endif | |
785 | ||
786 | /* | |
787 | * riscv_csrrw - read and/or update control and status register | |
788 | * | |
789 | * csrr <-> riscv_csrrw(env, csrno, ret_value, 0, 0); | |
790 | * csrrw <-> riscv_csrrw(env, csrno, ret_value, value, -1); | |
791 | * csrrs <-> riscv_csrrw(env, csrno, ret_value, -1, value); | |
792 | * csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value); | |
793 | */ | |
794 | ||
795 | int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, | |
796 | target_ulong new_value, target_ulong write_mask) | |
797 | { | |
798 | int ret; | |
799 | target_ulong old_value; | |
591bddea | 800 | RISCVCPU *cpu = env_archcpu(env); |
c7b95171 MC |
801 | |
802 | /* check privileges and return -1 if check fails */ | |
803 | #if !defined(CONFIG_USER_ONLY) | |
804 | int csr_priv = get_field(csrno, 0x300); | |
805 | int read_only = get_field(csrno, 0xC00) == 3; | |
e6e03dcf BM |
806 | if ((!env->debugger) && (env->priv < csr_priv)) { |
807 | return -1; | |
808 | } | |
809 | if (write_mask && read_only) { | |
c7b95171 MC |
810 | return -1; |
811 | } | |
812 | #endif | |
813 | ||
591bddea PD |
814 | /* ensure the CSR extension is enabled. */ |
815 | if (!cpu->cfg.ext_icsr) { | |
816 | return -1; | |
817 | } | |
818 | ||
a88365c1 MC |
819 | /* check predicate */ |
820 | if (!csr_ops[csrno].predicate || csr_ops[csrno].predicate(env, csrno) < 0) { | |
821 | return -1; | |
822 | } | |
823 | ||
c7b95171 MC |
824 | /* execute combined read/write operation if it exists */ |
825 | if (csr_ops[csrno].op) { | |
826 | return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask); | |
827 | } | |
828 | ||
829 | /* if no accessor exists then return failure */ | |
830 | if (!csr_ops[csrno].read) { | |
831 | return -1; | |
832 | } | |
833 | ||
834 | /* read old value */ | |
835 | ret = csr_ops[csrno].read(env, csrno, &old_value); | |
836 | if (ret < 0) { | |
837 | return ret; | |
838 | } | |
839 | ||
840 | /* write value if writable and write mask set, otherwise drop writes */ | |
841 | if (write_mask) { | |
842 | new_value = (old_value & ~write_mask) | (new_value & write_mask); | |
843 | if (csr_ops[csrno].write) { | |
844 | ret = csr_ops[csrno].write(env, csrno, new_value); | |
845 | if (ret < 0) { | |
846 | return ret; | |
847 | } | |
848 | } | |
849 | } | |
850 | ||
851 | /* return old value */ | |
852 | if (ret_value) { | |
853 | *ret_value = old_value; | |
854 | } | |
855 | ||
856 | return 0; | |
857 | } | |
858 | ||
753e3fe2 JW |
859 | /* |
860 | * Debugger support. If not in user mode, set env->debugger before the | |
861 | * riscv_csrrw call and clear it after the call. | |
862 | */ | |
863 | int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value, | |
864 | target_ulong new_value, target_ulong write_mask) | |
865 | { | |
866 | int ret; | |
867 | #if !defined(CONFIG_USER_ONLY) | |
868 | env->debugger = true; | |
869 | #endif | |
870 | ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask); | |
871 | #if !defined(CONFIG_USER_ONLY) | |
872 | env->debugger = false; | |
873 | #endif | |
874 | return ret; | |
875 | } | |
876 | ||
c7b95171 MC |
877 | /* Control and Status Register function table */ |
878 | static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { | |
879 | /* User Floating-Point CSRs */ | |
a88365c1 MC |
880 | [CSR_FFLAGS] = { fs, read_fflags, write_fflags }, |
881 | [CSR_FRM] = { fs, read_frm, write_frm }, | |
882 | [CSR_FCSR] = { fs, read_fcsr, write_fcsr }, | |
c7b95171 MC |
883 | |
884 | /* User Timers and Counters */ | |
a88365c1 MC |
885 | [CSR_CYCLE] = { ctr, read_instret }, |
886 | [CSR_INSTRET] = { ctr, read_instret }, | |
c7b95171 | 887 | #if defined(TARGET_RISCV32) |
a88365c1 MC |
888 | [CSR_CYCLEH] = { ctr, read_instreth }, |
889 | [CSR_INSTRETH] = { ctr, read_instreth }, | |
c7b95171 MC |
890 | #endif |
891 | ||
892 | /* User-level time CSRs are only available in linux-user | |
893 | * In privileged mode, the monitor emulates these CSRs */ | |
894 | #if defined(CONFIG_USER_ONLY) | |
a88365c1 | 895 | [CSR_TIME] = { ctr, read_time }, |
c7b95171 | 896 | #if defined(TARGET_RISCV32) |
a88365c1 | 897 | [CSR_TIMEH] = { ctr, read_timeh }, |
c7b95171 MC |
898 | #endif |
899 | #endif | |
900 | ||
901 | #if !defined(CONFIG_USER_ONLY) | |
902 | /* Machine Timers and Counters */ | |
a88365c1 MC |
903 | [CSR_MCYCLE] = { any, read_instret }, |
904 | [CSR_MINSTRET] = { any, read_instret }, | |
c7b95171 | 905 | #if defined(TARGET_RISCV32) |
a88365c1 MC |
906 | [CSR_MCYCLEH] = { any, read_instreth }, |
907 | [CSR_MINSTRETH] = { any, read_instreth }, | |
c7b95171 MC |
908 | #endif |
909 | ||
910 | /* Machine Information Registers */ | |
a88365c1 MC |
911 | [CSR_MVENDORID] = { any, read_zero }, |
912 | [CSR_MARCHID] = { any, read_zero }, | |
913 | [CSR_MIMPID] = { any, read_zero }, | |
914 | [CSR_MHARTID] = { any, read_mhartid }, | |
c7b95171 MC |
915 | |
916 | /* Machine Trap Setup */ | |
a88365c1 | 917 | [CSR_MSTATUS] = { any, read_mstatus, write_mstatus }, |
f18637cd | 918 | [CSR_MISA] = { any, read_misa, write_misa }, |
a88365c1 MC |
919 | [CSR_MIDELEG] = { any, read_mideleg, write_mideleg }, |
920 | [CSR_MEDELEG] = { any, read_medeleg, write_medeleg }, | |
921 | [CSR_MIE] = { any, read_mie, write_mie }, | |
922 | [CSR_MTVEC] = { any, read_mtvec, write_mtvec }, | |
923 | [CSR_MCOUNTEREN] = { any, read_mcounteren, write_mcounteren }, | |
c7b95171 MC |
924 | |
925 | /* Legacy Counter Setup (priv v1.9.1) */ | |
a88365c1 MC |
926 | [CSR_MUCOUNTEREN] = { any, read_mucounteren, write_mucounteren }, |
927 | [CSR_MSCOUNTEREN] = { any, read_mscounteren, write_mscounteren }, | |
c7b95171 MC |
928 | |
929 | /* Machine Trap Handling */ | |
a88365c1 MC |
930 | [CSR_MSCRATCH] = { any, read_mscratch, write_mscratch }, |
931 | [CSR_MEPC] = { any, read_mepc, write_mepc }, | |
932 | [CSR_MCAUSE] = { any, read_mcause, write_mcause }, | |
933 | [CSR_MBADADDR] = { any, read_mbadaddr, write_mbadaddr }, | |
934 | [CSR_MIP] = { any, NULL, NULL, rmw_mip }, | |
c7b95171 MC |
935 | |
936 | /* Supervisor Trap Setup */ | |
a88365c1 MC |
937 | [CSR_SSTATUS] = { smode, read_sstatus, write_sstatus }, |
938 | [CSR_SIE] = { smode, read_sie, write_sie }, | |
939 | [CSR_STVEC] = { smode, read_stvec, write_stvec }, | |
940 | [CSR_SCOUNTEREN] = { smode, read_scounteren, write_scounteren }, | |
c7b95171 MC |
941 | |
942 | /* Supervisor Trap Handling */ | |
a88365c1 MC |
943 | [CSR_SSCRATCH] = { smode, read_sscratch, write_sscratch }, |
944 | [CSR_SEPC] = { smode, read_sepc, write_sepc }, | |
945 | [CSR_SCAUSE] = { smode, read_scause, write_scause }, | |
946 | [CSR_SBADADDR] = { smode, read_sbadaddr, write_sbadaddr }, | |
947 | [CSR_SIP] = { smode, NULL, NULL, rmw_sip }, | |
c7b95171 MC |
948 | |
949 | /* Supervisor Protection and Translation */ | |
a88365c1 | 950 | [CSR_SATP] = { smode, read_satp, write_satp }, |
c7b95171 MC |
951 | |
952 | /* Physical Memory Protection */ | |
a88365c1 MC |
953 | [CSR_PMPCFG0 ... CSR_PMPADDR9] = { pmp, read_pmpcfg, write_pmpcfg }, |
954 | [CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr }, | |
c7b95171 MC |
955 | |
956 | /* Performance Counters */ | |
a88365c1 MC |
957 | [CSR_HPMCOUNTER3 ... CSR_HPMCOUNTER31] = { ctr, read_zero }, |
958 | [CSR_MHPMCOUNTER3 ... CSR_MHPMCOUNTER31] = { any, read_zero }, | |
959 | [CSR_MHPMEVENT3 ... CSR_MHPMEVENT31] = { any, read_zero }, | |
c7b95171 | 960 | #if defined(TARGET_RISCV32) |
a88365c1 MC |
961 | [CSR_HPMCOUNTER3H ... CSR_HPMCOUNTER31H] = { ctr, read_zero }, |
962 | [CSR_MHPMCOUNTER3H ... CSR_MHPMCOUNTER31H] = { any, read_zero }, | |
c7b95171 MC |
963 | #endif |
964 | #endif /* !CONFIG_USER_ONLY */ | |
965 | }; |