projects / mirror_qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| 95799e36 BM |
1 | /* |
| 2 | * QEMU RISC-V Native Debug Support | |
| 3 | * | |
| 4 | * Copyright (c) 2022 Wind River Systems, Inc. | |
| 5 | * | |
| 6 | * Author: | |
| 7 | * Bin Meng <bin.meng@windriver.com> | |
| 8 | * | |
| 9 | * This program is free software; you can redistribute it and/or modify it | |
| 10 | * under the terms and conditions of the GNU General Public License, | |
| 11 | * version 2 or later, as published by the Free Software Foundation. | |
| 12 | * | |
| 13 | * This program is distributed in the hope it will be useful, but WITHOUT | |
| 14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
| 16 | * more details. | |
| 17 | * | |
| 18 | * You should have received a copy of the GNU General Public License along with | |
| 19 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
| 20 | */ | |
| 21 | ||
| 22 | #ifndef RISCV_DEBUG_H | |
| 23 | #define RISCV_DEBUG_H | |
| 24 | ||
| 25 | /* trigger indexes implemented */ | |
| 26 | enum { | |
| 27 | TRIGGER_TYPE2_IDX_0 = 0, | |
| 28 | TRIGGER_TYPE2_IDX_1, | |
| 29 | TRIGGER_TYPE2_NUM, | |
| 30 | TRIGGER_NUM = TRIGGER_TYPE2_NUM | |
| 31 | }; | |
| 32 | ||
| 33 | /* register index of tdata CSRs */ | |
| 34 | enum { | |
| 35 | TDATA1 = 0, | |
| 36 | TDATA2, | |
| 37 | TDATA3, | |
| 38 | TDATA_NUM | |
| 39 | }; | |
| 40 | ||
| 41 | typedef enum { | |
| 42 | TRIGGER_TYPE_NO_EXIST = 0, /* trigger does not exist */ | |
| 43 | TRIGGER_TYPE_AD_MATCH = 2, /* address/data match trigger */ | |
| 44 | TRIGGER_TYPE_INST_CNT = 3, /* instruction count trigger */ | |
| 45 | TRIGGER_TYPE_INT = 4, /* interrupt trigger */ | |
| 46 | TRIGGER_TYPE_EXCP = 5, /* exception trigger */ | |
| 47 | TRIGGER_TYPE_AD_MATCH6 = 6, /* new address/data match trigger */ | |
| 48 | TRIGGER_TYPE_EXT_SRC = 7, /* external source trigger */ | |
| 49 | TRIGGER_TYPE_UNAVAIL = 15 /* trigger exists, but unavailable */ | |
| 50 | } trigger_type_t; | |
| 51 | ||
| 52 | typedef struct { | |
| 53 | target_ulong mcontrol; | |
| 54 | target_ulong maddress; | |
| 55 | struct CPUBreakpoint *bp; | |
| 56 | struct CPUWatchpoint *wp; | |
| 57 | } type2_trigger_t; | |
| 58 | ||
| 59 | /* tdata field masks */ | |
| 60 | ||
| 61 | #define RV32_TYPE(t) ((uint32_t)(t) << 28) | |
| 62 | #define RV32_TYPE_MASK (0xf << 28) | |
| 63 | #define RV32_DMODE BIT(27) | |
| 64 | #define RV64_TYPE(t) ((uint64_t)(t) << 60) | |
| 65 | #define RV64_TYPE_MASK (0xfULL << 60) | |
| 66 | #define RV64_DMODE BIT_ULL(59) | |
| 67 | ||
| 68 | /* mcontrol field masks */ | |
| 69 | ||
| 70 | #define TYPE2_LOAD BIT(0) | |
| 71 | #define TYPE2_STORE BIT(1) | |
| 72 | #define TYPE2_EXEC BIT(2) | |
| 73 | #define TYPE2_U BIT(3) | |
| 74 | #define TYPE2_S BIT(4) | |
| 75 | #define TYPE2_M BIT(6) | |
| 76 | #define TYPE2_MATCH (0xf << 7) | |
| 77 | #define TYPE2_CHAIN BIT(11) | |
| 78 | #define TYPE2_ACTION (0xf << 12) | |
| 79 | #define TYPE2_SIZELO (0x3 << 16) | |
| 80 | #define TYPE2_TIMING BIT(18) | |
| 81 | #define TYPE2_SELECT BIT(19) | |
| 82 | #define TYPE2_HIT BIT(20) | |
| 83 | #define TYPE2_SIZEHI (0x3 << 21) /* RV64 only */ | |
| 84 | ||
| 85 | /* access size */ | |
| 86 | enum { | |
| 87 | SIZE_ANY = 0, | |
| 88 | SIZE_1B, | |
| 89 | SIZE_2B, | |
| 90 | SIZE_4B, | |
| 91 | SIZE_6B, | |
| 92 | SIZE_8B, | |
| 93 | SIZE_10B, | |
| 94 | SIZE_12B, | |
| 95 | SIZE_14B, | |
| 96 | SIZE_16B, | |
| 97 | SIZE_NUM = 16 | |
| 98 | }; | |
| 99 | ||
| 100 | bool tdata_available(CPURISCVState *env, int tdata_index); | |
| 101 | ||
| 102 | target_ulong tselect_csr_read(CPURISCVState *env); | |
| 103 | void tselect_csr_write(CPURISCVState *env, target_ulong val); | |
| 104 | ||
| 105 | target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index); | |
| 106 | void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val); | |
| 107 | ||
| 108 | #endif /* RISCV_DEBUG_H */ |