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f798f1e2 MC |
1 | /* |
2 | * RISC-V FPU Emulation Helpers for QEMU. | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2 or later, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along with | |
16 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | ||
19 | #include "qemu/osdep.h" | |
f798f1e2 MC |
20 | #include "cpu.h" |
21 | #include "qemu/host-utils.h" | |
22 | #include "exec/exec-all.h" | |
23 | #include "exec/helper-proto.h" | |
135b03cb | 24 | #include "fpu/softfloat.h" |
121ddbb3 | 25 | #include "internals.h" |
f798f1e2 | 26 | |
fb738839 | 27 | target_ulong riscv_cpu_get_fflags(CPURISCVState *env) |
f798f1e2 MC |
28 | { |
29 | int soft = get_float_exception_flags(&env->fp_status); | |
30 | target_ulong hard = 0; | |
31 | ||
32 | hard |= (soft & float_flag_inexact) ? FPEXC_NX : 0; | |
33 | hard |= (soft & float_flag_underflow) ? FPEXC_UF : 0; | |
34 | hard |= (soft & float_flag_overflow) ? FPEXC_OF : 0; | |
35 | hard |= (soft & float_flag_divbyzero) ? FPEXC_DZ : 0; | |
36 | hard |= (soft & float_flag_invalid) ? FPEXC_NV : 0; | |
37 | ||
38 | return hard; | |
39 | } | |
40 | ||
fb738839 | 41 | void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong hard) |
f798f1e2 MC |
42 | { |
43 | int soft = 0; | |
44 | ||
45 | soft |= (hard & FPEXC_NX) ? float_flag_inexact : 0; | |
46 | soft |= (hard & FPEXC_UF) ? float_flag_underflow : 0; | |
47 | soft |= (hard & FPEXC_OF) ? float_flag_overflow : 0; | |
48 | soft |= (hard & FPEXC_DZ) ? float_flag_divbyzero : 0; | |
49 | soft |= (hard & FPEXC_NV) ? float_flag_invalid : 0; | |
50 | ||
51 | set_float_exception_flags(soft, &env->fp_status); | |
52 | } | |
53 | ||
54 | void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm) | |
55 | { | |
56 | int softrm; | |
57 | ||
58 | if (rm == 7) { | |
59 | rm = env->frm; | |
60 | } | |
61 | switch (rm) { | |
62 | case 0: | |
63 | softrm = float_round_nearest_even; | |
64 | break; | |
65 | case 1: | |
66 | softrm = float_round_to_zero; | |
67 | break; | |
68 | case 2: | |
69 | softrm = float_round_down; | |
70 | break; | |
71 | case 3: | |
72 | softrm = float_round_up; | |
73 | break; | |
74 | case 4: | |
75 | softrm = float_round_ties_away; | |
76 | break; | |
77 | default: | |
fb738839 | 78 | riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); |
f798f1e2 MC |
79 | } |
80 | ||
81 | set_float_rounding_mode(softrm, &env->fp_status); | |
82 | } | |
83 | ||
00c1899f KC |
84 | static uint64_t do_fmadd_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2, |
85 | uint64_t rs3, int flags) | |
86 | { | |
87 | float16 frs1 = check_nanbox_h(rs1); | |
88 | float16 frs2 = check_nanbox_h(rs2); | |
89 | float16 frs3 = check_nanbox_h(rs3); | |
90 | return nanbox_h(float16_muladd(frs1, frs2, frs3, flags, &env->fp_status)); | |
91 | } | |
92 | ||
00e925c5 RH |
93 | static uint64_t do_fmadd_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2, |
94 | uint64_t rs3, int flags) | |
9921e3d3 | 95 | { |
00e925c5 RH |
96 | float32 frs1 = check_nanbox_s(rs1); |
97 | float32 frs2 = check_nanbox_s(rs2); | |
98 | float32 frs3 = check_nanbox_s(rs3); | |
9921e3d3 RH |
99 | return nanbox_s(float32_muladd(frs1, frs2, frs3, flags, &env->fp_status)); |
100 | } | |
101 | ||
f798f1e2 MC |
102 | uint64_t helper_fmadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2, |
103 | uint64_t frs3) | |
104 | { | |
9921e3d3 | 105 | return do_fmadd_s(env, frs1, frs2, frs3, 0); |
f798f1e2 MC |
106 | } |
107 | ||
108 | uint64_t helper_fmadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2, | |
109 | uint64_t frs3) | |
110 | { | |
111 | return float64_muladd(frs1, frs2, frs3, 0, &env->fp_status); | |
112 | } | |
113 | ||
00c1899f KC |
114 | uint64_t helper_fmadd_h(CPURISCVState *env, uint64_t frs1, uint64_t frs2, |
115 | uint64_t frs3) | |
116 | { | |
117 | return do_fmadd_h(env, frs1, frs2, frs3, 0); | |
118 | } | |
119 | ||
f798f1e2 MC |
120 | uint64_t helper_fmsub_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2, |
121 | uint64_t frs3) | |
122 | { | |
9921e3d3 | 123 | return do_fmadd_s(env, frs1, frs2, frs3, float_muladd_negate_c); |
f798f1e2 MC |
124 | } |
125 | ||
126 | uint64_t helper_fmsub_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2, | |
127 | uint64_t frs3) | |
128 | { | |
129 | return float64_muladd(frs1, frs2, frs3, float_muladd_negate_c, | |
130 | &env->fp_status); | |
131 | } | |
132 | ||
00c1899f KC |
133 | uint64_t helper_fmsub_h(CPURISCVState *env, uint64_t frs1, uint64_t frs2, |
134 | uint64_t frs3) | |
135 | { | |
136 | return do_fmadd_h(env, frs1, frs2, frs3, float_muladd_negate_c); | |
137 | } | |
138 | ||
f798f1e2 MC |
139 | uint64_t helper_fnmsub_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2, |
140 | uint64_t frs3) | |
141 | { | |
9921e3d3 | 142 | return do_fmadd_s(env, frs1, frs2, frs3, float_muladd_negate_product); |
f798f1e2 MC |
143 | } |
144 | ||
145 | uint64_t helper_fnmsub_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2, | |
146 | uint64_t frs3) | |
147 | { | |
148 | return float64_muladd(frs1, frs2, frs3, float_muladd_negate_product, | |
149 | &env->fp_status); | |
150 | } | |
151 | ||
00c1899f KC |
152 | uint64_t helper_fnmsub_h(CPURISCVState *env, uint64_t frs1, uint64_t frs2, |
153 | uint64_t frs3) | |
154 | { | |
155 | return do_fmadd_h(env, frs1, frs2, frs3, float_muladd_negate_product); | |
156 | } | |
157 | ||
f798f1e2 MC |
158 | uint64_t helper_fnmadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2, |
159 | uint64_t frs3) | |
160 | { | |
9921e3d3 RH |
161 | return do_fmadd_s(env, frs1, frs2, frs3, |
162 | float_muladd_negate_c | float_muladd_negate_product); | |
f798f1e2 MC |
163 | } |
164 | ||
165 | uint64_t helper_fnmadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2, | |
166 | uint64_t frs3) | |
167 | { | |
168 | return float64_muladd(frs1, frs2, frs3, float_muladd_negate_c | | |
169 | float_muladd_negate_product, &env->fp_status); | |
170 | } | |
171 | ||
00c1899f KC |
172 | uint64_t helper_fnmadd_h(CPURISCVState *env, uint64_t frs1, uint64_t frs2, |
173 | uint64_t frs3) | |
174 | { | |
175 | return do_fmadd_h(env, frs1, frs2, frs3, | |
176 | float_muladd_negate_c | float_muladd_negate_product); | |
177 | } | |
178 | ||
00e925c5 | 179 | uint64_t helper_fadd_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) |
f798f1e2 | 180 | { |
00e925c5 RH |
181 | float32 frs1 = check_nanbox_s(rs1); |
182 | float32 frs2 = check_nanbox_s(rs2); | |
9921e3d3 | 183 | return nanbox_s(float32_add(frs1, frs2, &env->fp_status)); |
f798f1e2 MC |
184 | } |
185 | ||
00e925c5 | 186 | uint64_t helper_fsub_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) |
f798f1e2 | 187 | { |
00e925c5 RH |
188 | float32 frs1 = check_nanbox_s(rs1); |
189 | float32 frs2 = check_nanbox_s(rs2); | |
9921e3d3 | 190 | return nanbox_s(float32_sub(frs1, frs2, &env->fp_status)); |
f798f1e2 MC |
191 | } |
192 | ||
00e925c5 | 193 | uint64_t helper_fmul_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) |
f798f1e2 | 194 | { |
00e925c5 RH |
195 | float32 frs1 = check_nanbox_s(rs1); |
196 | float32 frs2 = check_nanbox_s(rs2); | |
9921e3d3 | 197 | return nanbox_s(float32_mul(frs1, frs2, &env->fp_status)); |
f798f1e2 MC |
198 | } |
199 | ||
00e925c5 | 200 | uint64_t helper_fdiv_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) |
f798f1e2 | 201 | { |
00e925c5 RH |
202 | float32 frs1 = check_nanbox_s(rs1); |
203 | float32 frs2 = check_nanbox_s(rs2); | |
9921e3d3 | 204 | return nanbox_s(float32_div(frs1, frs2, &env->fp_status)); |
f798f1e2 MC |
205 | } |
206 | ||
00e925c5 | 207 | uint64_t helper_fmin_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) |
f798f1e2 | 208 | { |
00e925c5 RH |
209 | float32 frs1 = check_nanbox_s(rs1); |
210 | float32 frs2 = check_nanbox_s(rs2); | |
15161e42 CMC |
211 | return nanbox_s(env->priv_ver < PRIV_VERSION_1_11_0 ? |
212 | float32_minnum(frs1, frs2, &env->fp_status) : | |
213 | float32_minimum_number(frs1, frs2, &env->fp_status)); | |
f798f1e2 MC |
214 | } |
215 | ||
00e925c5 | 216 | uint64_t helper_fmax_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) |
f798f1e2 | 217 | { |
00e925c5 RH |
218 | float32 frs1 = check_nanbox_s(rs1); |
219 | float32 frs2 = check_nanbox_s(rs2); | |
15161e42 CMC |
220 | return nanbox_s(env->priv_ver < PRIV_VERSION_1_11_0 ? |
221 | float32_maxnum(frs1, frs2, &env->fp_status) : | |
222 | float32_maximum_number(frs1, frs2, &env->fp_status)); | |
f798f1e2 MC |
223 | } |
224 | ||
00e925c5 | 225 | uint64_t helper_fsqrt_s(CPURISCVState *env, uint64_t rs1) |
f798f1e2 | 226 | { |
00e925c5 | 227 | float32 frs1 = check_nanbox_s(rs1); |
9921e3d3 | 228 | return nanbox_s(float32_sqrt(frs1, &env->fp_status)); |
f798f1e2 MC |
229 | } |
230 | ||
00e925c5 | 231 | target_ulong helper_fle_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) |
f798f1e2 | 232 | { |
00e925c5 RH |
233 | float32 frs1 = check_nanbox_s(rs1); |
234 | float32 frs2 = check_nanbox_s(rs2); | |
f798f1e2 MC |
235 | return float32_le(frs1, frs2, &env->fp_status); |
236 | } | |
237 | ||
00e925c5 | 238 | target_ulong helper_flt_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) |
f798f1e2 | 239 | { |
00e925c5 RH |
240 | float32 frs1 = check_nanbox_s(rs1); |
241 | float32 frs2 = check_nanbox_s(rs2); | |
f798f1e2 MC |
242 | return float32_lt(frs1, frs2, &env->fp_status); |
243 | } | |
244 | ||
00e925c5 | 245 | target_ulong helper_feq_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) |
f798f1e2 | 246 | { |
00e925c5 RH |
247 | float32 frs1 = check_nanbox_s(rs1); |
248 | float32 frs2 = check_nanbox_s(rs2); | |
f798f1e2 MC |
249 | return float32_eq_quiet(frs1, frs2, &env->fp_status); |
250 | } | |
251 | ||
00e925c5 | 252 | target_ulong helper_fcvt_w_s(CPURISCVState *env, uint64_t rs1) |
f798f1e2 | 253 | { |
00e925c5 | 254 | float32 frs1 = check_nanbox_s(rs1); |
f798f1e2 MC |
255 | return float32_to_int32(frs1, &env->fp_status); |
256 | } | |
257 | ||
00e925c5 | 258 | target_ulong helper_fcvt_wu_s(CPURISCVState *env, uint64_t rs1) |
f798f1e2 | 259 | { |
00e925c5 | 260 | float32 frs1 = check_nanbox_s(rs1); |
f798f1e2 MC |
261 | return (int32_t)float32_to_uint32(frs1, &env->fp_status); |
262 | } | |
263 | ||
daf866b6 | 264 | target_ulong helper_fcvt_l_s(CPURISCVState *env, uint64_t rs1) |
f798f1e2 | 265 | { |
00e925c5 | 266 | float32 frs1 = check_nanbox_s(rs1); |
f798f1e2 MC |
267 | return float32_to_int64(frs1, &env->fp_status); |
268 | } | |
269 | ||
daf866b6 | 270 | target_ulong helper_fcvt_lu_s(CPURISCVState *env, uint64_t rs1) |
f798f1e2 | 271 | { |
00e925c5 | 272 | float32 frs1 = check_nanbox_s(rs1); |
f798f1e2 MC |
273 | return float32_to_uint64(frs1, &env->fp_status); |
274 | } | |
f798f1e2 MC |
275 | |
276 | uint64_t helper_fcvt_s_w(CPURISCVState *env, target_ulong rs1) | |
277 | { | |
9921e3d3 | 278 | return nanbox_s(int32_to_float32((int32_t)rs1, &env->fp_status)); |
f798f1e2 MC |
279 | } |
280 | ||
281 | uint64_t helper_fcvt_s_wu(CPURISCVState *env, target_ulong rs1) | |
282 | { | |
9921e3d3 | 283 | return nanbox_s(uint32_to_float32((uint32_t)rs1, &env->fp_status)); |
f798f1e2 MC |
284 | } |
285 | ||
daf866b6 | 286 | uint64_t helper_fcvt_s_l(CPURISCVState *env, target_ulong rs1) |
f798f1e2 | 287 | { |
9921e3d3 | 288 | return nanbox_s(int64_to_float32(rs1, &env->fp_status)); |
f798f1e2 MC |
289 | } |
290 | ||
daf866b6 | 291 | uint64_t helper_fcvt_s_lu(CPURISCVState *env, target_ulong rs1) |
f798f1e2 | 292 | { |
9921e3d3 | 293 | return nanbox_s(uint64_to_float32(rs1, &env->fp_status)); |
f798f1e2 | 294 | } |
f798f1e2 | 295 | |
00e925c5 | 296 | target_ulong helper_fclass_s(uint64_t rs1) |
f798f1e2 | 297 | { |
00e925c5 | 298 | float32 frs1 = check_nanbox_s(rs1); |
121ddbb3 | 299 | return fclass_s(frs1); |
f798f1e2 MC |
300 | } |
301 | ||
302 | uint64_t helper_fadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) | |
303 | { | |
304 | return float64_add(frs1, frs2, &env->fp_status); | |
305 | } | |
306 | ||
307 | uint64_t helper_fsub_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) | |
308 | { | |
309 | return float64_sub(frs1, frs2, &env->fp_status); | |
310 | } | |
311 | ||
312 | uint64_t helper_fmul_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) | |
313 | { | |
314 | return float64_mul(frs1, frs2, &env->fp_status); | |
315 | } | |
316 | ||
317 | uint64_t helper_fdiv_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) | |
318 | { | |
319 | return float64_div(frs1, frs2, &env->fp_status); | |
320 | } | |
321 | ||
322 | uint64_t helper_fmin_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) | |
323 | { | |
15161e42 CMC |
324 | return env->priv_ver < PRIV_VERSION_1_11_0 ? |
325 | float64_minnum(frs1, frs2, &env->fp_status) : | |
326 | float64_minimum_number(frs1, frs2, &env->fp_status); | |
f798f1e2 MC |
327 | } |
328 | ||
329 | uint64_t helper_fmax_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) | |
330 | { | |
15161e42 CMC |
331 | return env->priv_ver < PRIV_VERSION_1_11_0 ? |
332 | float64_maxnum(frs1, frs2, &env->fp_status) : | |
333 | float64_maximum_number(frs1, frs2, &env->fp_status); | |
f798f1e2 MC |
334 | } |
335 | ||
336 | uint64_t helper_fcvt_s_d(CPURISCVState *env, uint64_t rs1) | |
337 | { | |
9921e3d3 | 338 | return nanbox_s(float64_to_float32(rs1, &env->fp_status)); |
f798f1e2 MC |
339 | } |
340 | ||
341 | uint64_t helper_fcvt_d_s(CPURISCVState *env, uint64_t rs1) | |
342 | { | |
00e925c5 RH |
343 | float32 frs1 = check_nanbox_s(rs1); |
344 | return float32_to_float64(frs1, &env->fp_status); | |
f798f1e2 MC |
345 | } |
346 | ||
347 | uint64_t helper_fsqrt_d(CPURISCVState *env, uint64_t frs1) | |
348 | { | |
349 | return float64_sqrt(frs1, &env->fp_status); | |
350 | } | |
351 | ||
352 | target_ulong helper_fle_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) | |
353 | { | |
354 | return float64_le(frs1, frs2, &env->fp_status); | |
355 | } | |
356 | ||
357 | target_ulong helper_flt_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) | |
358 | { | |
359 | return float64_lt(frs1, frs2, &env->fp_status); | |
360 | } | |
361 | ||
362 | target_ulong helper_feq_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) | |
363 | { | |
364 | return float64_eq_quiet(frs1, frs2, &env->fp_status); | |
365 | } | |
366 | ||
367 | target_ulong helper_fcvt_w_d(CPURISCVState *env, uint64_t frs1) | |
368 | { | |
369 | return float64_to_int32(frs1, &env->fp_status); | |
370 | } | |
371 | ||
372 | target_ulong helper_fcvt_wu_d(CPURISCVState *env, uint64_t frs1) | |
373 | { | |
374 | return (int32_t)float64_to_uint32(frs1, &env->fp_status); | |
375 | } | |
376 | ||
daf866b6 | 377 | target_ulong helper_fcvt_l_d(CPURISCVState *env, uint64_t frs1) |
f798f1e2 MC |
378 | { |
379 | return float64_to_int64(frs1, &env->fp_status); | |
380 | } | |
381 | ||
daf866b6 | 382 | target_ulong helper_fcvt_lu_d(CPURISCVState *env, uint64_t frs1) |
f798f1e2 MC |
383 | { |
384 | return float64_to_uint64(frs1, &env->fp_status); | |
385 | } | |
f798f1e2 MC |
386 | |
387 | uint64_t helper_fcvt_d_w(CPURISCVState *env, target_ulong rs1) | |
388 | { | |
389 | return int32_to_float64((int32_t)rs1, &env->fp_status); | |
390 | } | |
391 | ||
392 | uint64_t helper_fcvt_d_wu(CPURISCVState *env, target_ulong rs1) | |
393 | { | |
394 | return uint32_to_float64((uint32_t)rs1, &env->fp_status); | |
395 | } | |
396 | ||
daf866b6 | 397 | uint64_t helper_fcvt_d_l(CPURISCVState *env, target_ulong rs1) |
f798f1e2 MC |
398 | { |
399 | return int64_to_float64(rs1, &env->fp_status); | |
400 | } | |
401 | ||
daf866b6 | 402 | uint64_t helper_fcvt_d_lu(CPURISCVState *env, target_ulong rs1) |
f798f1e2 MC |
403 | { |
404 | return uint64_to_float64(rs1, &env->fp_status); | |
405 | } | |
f798f1e2 MC |
406 | |
407 | target_ulong helper_fclass_d(uint64_t frs1) | |
408 | { | |
121ddbb3 | 409 | return fclass_d(frs1); |
f798f1e2 | 410 | } |
00c1899f KC |
411 | |
412 | uint64_t helper_fadd_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) | |
413 | { | |
414 | float16 frs1 = check_nanbox_h(rs1); | |
415 | float16 frs2 = check_nanbox_h(rs2); | |
416 | return nanbox_h(float16_add(frs1, frs2, &env->fp_status)); | |
417 | } | |
418 | ||
419 | uint64_t helper_fsub_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) | |
420 | { | |
421 | float16 frs1 = check_nanbox_h(rs1); | |
422 | float16 frs2 = check_nanbox_h(rs2); | |
423 | return nanbox_h(float16_sub(frs1, frs2, &env->fp_status)); | |
424 | } | |
425 | ||
426 | uint64_t helper_fmul_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) | |
427 | { | |
428 | float16 frs1 = check_nanbox_h(rs1); | |
429 | float16 frs2 = check_nanbox_h(rs2); | |
430 | return nanbox_h(float16_mul(frs1, frs2, &env->fp_status)); | |
431 | } | |
432 | ||
433 | uint64_t helper_fdiv_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) | |
434 | { | |
435 | float16 frs1 = check_nanbox_h(rs1); | |
436 | float16 frs2 = check_nanbox_h(rs2); | |
437 | return nanbox_h(float16_div(frs1, frs2, &env->fp_status)); | |
438 | } | |
439 | ||
440 | uint64_t helper_fmin_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) | |
441 | { | |
442 | float16 frs1 = check_nanbox_h(rs1); | |
443 | float16 frs2 = check_nanbox_h(rs2); | |
444 | return nanbox_h(env->priv_ver < PRIV_VERSION_1_11_0 ? | |
445 | float16_minnum(frs1, frs2, &env->fp_status) : | |
446 | float16_minimum_number(frs1, frs2, &env->fp_status)); | |
447 | } | |
448 | ||
449 | uint64_t helper_fmax_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) | |
450 | { | |
451 | float16 frs1 = check_nanbox_h(rs1); | |
452 | float16 frs2 = check_nanbox_h(rs2); | |
453 | return nanbox_h(env->priv_ver < PRIV_VERSION_1_11_0 ? | |
454 | float16_maxnum(frs1, frs2, &env->fp_status) : | |
455 | float16_maximum_number(frs1, frs2, &env->fp_status)); | |
456 | } | |
457 | ||
458 | uint64_t helper_fsqrt_h(CPURISCVState *env, uint64_t rs1) | |
459 | { | |
460 | float16 frs1 = check_nanbox_h(rs1); | |
461 | return nanbox_h(float16_sqrt(frs1, &env->fp_status)); | |
462 | } | |
7b03c8e5 KC |
463 | |
464 | target_ulong helper_fcvt_w_h(CPURISCVState *env, uint64_t rs1) | |
465 | { | |
466 | float16 frs1 = check_nanbox_h(rs1); | |
467 | return float16_to_int32(frs1, &env->fp_status); | |
468 | } | |
469 | ||
470 | target_ulong helper_fcvt_wu_h(CPURISCVState *env, uint64_t rs1) | |
471 | { | |
472 | float16 frs1 = check_nanbox_h(rs1); | |
473 | return (int32_t)float16_to_uint32(frs1, &env->fp_status); | |
474 | } | |
475 | ||
476 | target_ulong helper_fcvt_l_h(CPURISCVState *env, uint64_t rs1) | |
477 | { | |
478 | float16 frs1 = check_nanbox_h(rs1); | |
479 | return float16_to_int64(frs1, &env->fp_status); | |
480 | } | |
481 | ||
482 | target_ulong helper_fcvt_lu_h(CPURISCVState *env, uint64_t rs1) | |
483 | { | |
484 | float16 frs1 = check_nanbox_h(rs1); | |
485 | return float16_to_uint64(frs1, &env->fp_status); | |
486 | } | |
487 | ||
488 | uint64_t helper_fcvt_h_w(CPURISCVState *env, target_ulong rs1) | |
489 | { | |
490 | return nanbox_h(int32_to_float16((int32_t)rs1, &env->fp_status)); | |
491 | } | |
492 | ||
493 | uint64_t helper_fcvt_h_wu(CPURISCVState *env, target_ulong rs1) | |
494 | { | |
495 | return nanbox_h(uint32_to_float16((uint32_t)rs1, &env->fp_status)); | |
496 | } | |
497 | ||
498 | uint64_t helper_fcvt_h_l(CPURISCVState *env, target_ulong rs1) | |
499 | { | |
500 | return nanbox_h(int64_to_float16(rs1, &env->fp_status)); | |
501 | } | |
502 | ||
503 | uint64_t helper_fcvt_h_lu(CPURISCVState *env, target_ulong rs1) | |
504 | { | |
505 | return nanbox_h(uint64_to_float16(rs1, &env->fp_status)); | |
506 | } | |
507 | ||
508 | uint64_t helper_fcvt_h_s(CPURISCVState *env, uint64_t rs1) | |
509 | { | |
510 | float32 frs1 = check_nanbox_s(rs1); | |
511 | return nanbox_h(float32_to_float16(frs1, true, &env->fp_status)); | |
512 | } | |
513 | ||
514 | uint64_t helper_fcvt_s_h(CPURISCVState *env, uint64_t rs1) | |
515 | { | |
516 | float16 frs1 = check_nanbox_h(rs1); | |
517 | return nanbox_s(float16_to_float32(frs1, true, &env->fp_status)); | |
518 | } | |
519 | ||
520 | uint64_t helper_fcvt_h_d(CPURISCVState *env, uint64_t rs1) | |
521 | { | |
522 | return nanbox_h(float64_to_float16(rs1, true, &env->fp_status)); | |
523 | } | |
524 | ||
525 | uint64_t helper_fcvt_d_h(CPURISCVState *env, uint64_t rs1) | |
526 | { | |
527 | float16 frs1 = check_nanbox_h(rs1); | |
528 | return float16_to_float64(frs1, true, &env->fp_status); | |
529 | } |