[mirror_qemu.git] / target / riscv / insn32.decode

#
# RISC-V translation routines for the RVXI Base Integer Instruction Set.
#
# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
#                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
#
# This program is free software; you can redistribute it and/or modify it
# under the terms and conditions of the GNU General Public License,
# version 2 or later, as published by the Free Software Foundation.
#
# This program is distributed in the hope it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
# more details.
#
# You should have received a copy of the GNU General Public License along with
# this program.  If not, see <http://www.gnu.org/licenses/>.

# Fields:
%rs3       27:5
%rs2       20:5
%rs1       15:5
%rd        7:5

%sh10    20:10
%csr    20:12
%rm     12:3
%nf     29:3                     !function=ex_plus_1

# immediates:
%imm_i    20:s12
%imm_s    25:s7 7:5
%imm_b    31:s1 7:1 25:6 8:4     !function=ex_shift_1
%imm_j    31:s1 12:8 20:1 21:10  !function=ex_shift_1
%imm_u    12:s20                 !function=ex_shift_12

# Argument sets:
&empty
&b    imm rs2 rs1
&i    imm rs1 rd
&j    imm rd
&r    rd rs1 rs2
&s    imm rs1 rs2
&u    imm rd
&shift     shamt rs1 rd
&atomic    aq rl rs2 rs1 rd
&rwdvm     vm wd rd rs1 rs2
&r2nfvm    vm rd rs1 nf
&rnfvm     vm rd rs1 rs2 nf

# Formats 32:
@r       .......   ..... ..... ... ..... ....... &r                %rs2 %rs1 %rd
@i       ............    ..... ... ..... ....... &i      imm=%imm_i     %rs1 %rd
@b       .......   ..... ..... ... ..... ....... &b      imm=%imm_b %rs2 %rs1
@s       .......   ..... ..... ... ..... ....... &s      imm=%imm_s %rs2 %rs1
@u       ....................      ..... ....... &u      imm=%imm_u          %rd
@j       ....................      ..... ....... &j      imm=%imm_j          %rd

@sh      ......  ...... .....  ... ..... ....... &shift  shamt=%sh10      %rs1 %rd
@csr     ............   .....  ... ..... .......               %csr     %rs1 %rd

@atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0     %rs1 %rd
@atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2      %rs1 %rd

@r4_rm   ..... ..  ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd
@r_rm    .......   ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
@r2_rm   .......   ..... ..... ... ..... ....... %rs1 %rm %rd
@r2      .......   ..... ..... ... ..... ....... %rs1 %rd
@r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd
@r_nfvm  ... ... vm:1 ..... ..... ... ..... ....... &rnfvm %nf %rs2 %rs1 %rd
@r_wdvm  ..... wd:1 vm:1 ..... ..... ... ..... ....... &rwdvm %rs2 %rs1 %rd
@r2_zimm . zimm:11  ..... ... ..... ....... %rs1 %rd

@hfence_gvma ....... ..... .....   ... ..... ....... %rs2 %rs1
@hfence_vvma ....... ..... .....   ... ..... ....... %rs2 %rs1

@sfence_vma ....... ..... .....   ... ..... ....... %rs2 %rs1
@sfence_vm  ....... ..... .....   ... ..... ....... %rs1


# *** Privileged Instructions ***
ecall       000000000000     00000 000 00000 1110011
ebreak      000000000001     00000 000 00000 1110011
uret        0000000    00010 00000 000 00000 1110011
sret        0001000    00010 00000 000 00000 1110011
mret        0011000    00010 00000 000 00000 1110011
wfi         0001000    00101 00000 000 00000 1110011
sfence_vma  0001001    ..... ..... 000 00000 1110011 @sfence_vma
sfence_vm   0001000    00100 ..... 000 00000 1110011 @sfence_vm

# *** RV32I Base Instruction Set ***
lui      ....................       ..... 0110111 @u
auipc    ....................       ..... 0010111 @u
jal      ....................       ..... 1101111 @j
jalr     ............     ..... 000 ..... 1100111 @i
beq      ....... .....    ..... 000 ..... 1100011 @b
bne      ....... .....    ..... 001 ..... 1100011 @b
blt      ....... .....    ..... 100 ..... 1100011 @b
bge      ....... .....    ..... 101 ..... 1100011 @b
bltu     ....... .....    ..... 110 ..... 1100011 @b
bgeu     ....... .....    ..... 111 ..... 1100011 @b
lb       ............     ..... 000 ..... 0000011 @i
lh       ............     ..... 001 ..... 0000011 @i
lw       ............     ..... 010 ..... 0000011 @i
lbu      ............     ..... 100 ..... 0000011 @i
lhu      ............     ..... 101 ..... 0000011 @i
sb       .......  .....   ..... 000 ..... 0100011 @s
sh       .......  .....   ..... 001 ..... 0100011 @s
sw       .......  .....   ..... 010 ..... 0100011 @s
addi     ............     ..... 000 ..... 0010011 @i
slti     ............     ..... 010 ..... 0010011 @i
sltiu    ............     ..... 011 ..... 0010011 @i
xori     ............     ..... 100 ..... 0010011 @i
ori      ............     ..... 110 ..... 0010011 @i
andi     ............     ..... 111 ..... 0010011 @i
slli     00.... ......    ..... 001 ..... 0010011 @sh
srli     00.... ......    ..... 101 ..... 0010011 @sh
srai     01.... ......    ..... 101 ..... 0010011 @sh
add      0000000 .....    ..... 000 ..... 0110011 @r
sub      0100000 .....    ..... 000 ..... 0110011 @r
sll      0000000 .....    ..... 001 ..... 0110011 @r
slt      0000000 .....    ..... 010 ..... 0110011 @r
sltu     0000000 .....    ..... 011 ..... 0110011 @r
xor      0000000 .....    ..... 100 ..... 0110011 @r
srl      0000000 .....    ..... 101 ..... 0110011 @r
sra      0100000 .....    ..... 101 ..... 0110011 @r
or       0000000 .....    ..... 110 ..... 0110011 @r
and      0000000 .....    ..... 111 ..... 0110011 @r
fence    ---- pred:4 succ:4 ----- 000 ----- 0001111
fence_i  ---- ----   ----   ----- 001 ----- 0001111
csrrw    ............     ..... 001 ..... 1110011 @csr
csrrs    ............     ..... 010 ..... 1110011 @csr
csrrc    ............     ..... 011 ..... 1110011 @csr
csrrwi   ............     ..... 101 ..... 1110011 @csr
csrrsi   ............     ..... 110 ..... 1110011 @csr
csrrci   ............     ..... 111 ..... 1110011 @csr

# *** RV32M Standard Extension ***
mul      0000001 .....  ..... 000 ..... 0110011 @r
mulh     0000001 .....  ..... 001 ..... 0110011 @r
mulhsu   0000001 .....  ..... 010 ..... 0110011 @r
mulhu    0000001 .....  ..... 011 ..... 0110011 @r
div      0000001 .....  ..... 100 ..... 0110011 @r
divu     0000001 .....  ..... 101 ..... 0110011 @r
rem      0000001 .....  ..... 110 ..... 0110011 @r
remu     0000001 .....  ..... 111 ..... 0110011 @r

# *** RV32A Standard Extension ***
lr_w       00010 . . 00000 ..... 010 ..... 0101111 @atom_ld
sc_w       00011 . . ..... ..... 010 ..... 0101111 @atom_st
amoswap_w  00001 . . ..... ..... 010 ..... 0101111 @atom_st
amoadd_w   00000 . . ..... ..... 010 ..... 0101111 @atom_st
amoxor_w   00100 . . ..... ..... 010 ..... 0101111 @atom_st
amoand_w   01100 . . ..... ..... 010 ..... 0101111 @atom_st
amoor_w    01000 . . ..... ..... 010 ..... 0101111 @atom_st
amomin_w   10000 . . ..... ..... 010 ..... 0101111 @atom_st
amomax_w   10100 . . ..... ..... 010 ..... 0101111 @atom_st
amominu_w  11000 . . ..... ..... 010 ..... 0101111 @atom_st
amomaxu_w  11100 . . ..... ..... 010 ..... 0101111 @atom_st

# *** RV32F Standard Extension ***
flw        ............   ..... 010 ..... 0000111 @i
fsw        .......  ..... ..... 010 ..... 0100111 @s
fmadd_s    ..... 00 ..... ..... ... ..... 1000011 @r4_rm
fmsub_s    ..... 00 ..... ..... ... ..... 1000111 @r4_rm
fnmsub_s   ..... 00 ..... ..... ... ..... 1001011 @r4_rm
fnmadd_s   ..... 00 ..... ..... ... ..... 1001111 @r4_rm
fadd_s     0000000  ..... ..... ... ..... 1010011 @r_rm
fsub_s     0000100  ..... ..... ... ..... 1010011 @r_rm
fmul_s     0001000  ..... ..... ... ..... 1010011 @r_rm
fdiv_s     0001100  ..... ..... ... ..... 1010011 @r_rm
fsqrt_s    0101100  00000 ..... ... ..... 1010011 @r2_rm
fsgnj_s    0010000  ..... ..... 000 ..... 1010011 @r
fsgnjn_s   0010000  ..... ..... 001 ..... 1010011 @r
fsgnjx_s   0010000  ..... ..... 010 ..... 1010011 @r
fmin_s     0010100  ..... ..... 000 ..... 1010011 @r
fmax_s     0010100  ..... ..... 001 ..... 1010011 @r
fcvt_w_s   1100000  00000 ..... ... ..... 1010011 @r2_rm
fcvt_wu_s  1100000  00001 ..... ... ..... 1010011 @r2_rm
fmv_x_w    1110000  00000 ..... 000 ..... 1010011 @r2
feq_s      1010000  ..... ..... 010 ..... 1010011 @r
flt_s      1010000  ..... ..... 001 ..... 1010011 @r
fle_s      1010000  ..... ..... 000 ..... 1010011 @r
fclass_s   1110000  00000 ..... 001 ..... 1010011 @r2
fcvt_s_w   1101000  00000 ..... ... ..... 1010011 @r2_rm
fcvt_s_wu  1101000  00001 ..... ... ..... 1010011 @r2_rm
fmv_w_x    1111000  00000 ..... 000 ..... 1010011 @r2

# *** RV32D Standard Extension ***
fld        ............   ..... 011 ..... 0000111 @i
fsd        ....... .....  ..... 011 ..... 0100111 @s
fmadd_d    ..... 01 ..... ..... ... ..... 1000011 @r4_rm
fmsub_d    ..... 01 ..... ..... ... ..... 1000111 @r4_rm
fnmsub_d   ..... 01 ..... ..... ... ..... 1001011 @r4_rm
fnmadd_d   ..... 01 ..... ..... ... ..... 1001111 @r4_rm
fadd_d     0000001  ..... ..... ... ..... 1010011 @r_rm
fsub_d     0000101  ..... ..... ... ..... 1010011 @r_rm
fmul_d     0001001  ..... ..... ... ..... 1010011 @r_rm
fdiv_d     0001101  ..... ..... ... ..... 1010011 @r_rm
fsqrt_d    0101101  00000 ..... ... ..... 1010011 @r2_rm
fsgnj_d    0010001  ..... ..... 000 ..... 1010011 @r
fsgnjn_d   0010001  ..... ..... 001 ..... 1010011 @r
fsgnjx_d   0010001  ..... ..... 010 ..... 1010011 @r
fmin_d     0010101  ..... ..... 000 ..... 1010011 @r
fmax_d     0010101  ..... ..... 001 ..... 1010011 @r
fcvt_s_d   0100000  00001 ..... ... ..... 1010011 @r2_rm
fcvt_d_s   0100001  00000 ..... ... ..... 1010011 @r2_rm
feq_d      1010001  ..... ..... 010 ..... 1010011 @r
flt_d      1010001  ..... ..... 001 ..... 1010011 @r
fle_d      1010001  ..... ..... 000 ..... 1010011 @r
fclass_d   1110001  00000 ..... 001 ..... 1010011 @r2
fcvt_w_d   1100001  00000 ..... ... ..... 1010011 @r2_rm
fcvt_wu_d  1100001  00001 ..... ... ..... 1010011 @r2_rm
fcvt_d_w   1101001  00000 ..... ... ..... 1010011 @r2_rm
fcvt_d_wu  1101001  00001 ..... ... ..... 1010011 @r2_rm

# *** RV32H Base Instruction Set ***
hfence_gvma 0110001  .....  ..... 000 00000 1110011 @hfence_gvma
hfence_vvma 0010001  .....  ..... 000 00000 1110011 @hfence_vvma

# *** RV32V Extension ***

# *** Vector loads and stores are encoded within LOADFP/STORE-FP ***
vlb_v      ... 100 . 00000 ..... 000 ..... 0000111 @r2_nfvm
vlh_v      ... 100 . 00000 ..... 101 ..... 0000111 @r2_nfvm
vlw_v      ... 100 . 00000 ..... 110 ..... 0000111 @r2_nfvm
vle_v      ... 000 . 00000 ..... 111 ..... 0000111 @r2_nfvm
vlbu_v     ... 000 . 00000 ..... 000 ..... 0000111 @r2_nfvm
vlhu_v     ... 000 . 00000 ..... 101 ..... 0000111 @r2_nfvm
vlwu_v     ... 000 . 00000 ..... 110 ..... 0000111 @r2_nfvm
vlbff_v    ... 100 . 10000 ..... 000 ..... 0000111 @r2_nfvm
vlhff_v    ... 100 . 10000 ..... 101 ..... 0000111 @r2_nfvm
vlwff_v    ... 100 . 10000 ..... 110 ..... 0000111 @r2_nfvm
vleff_v    ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm
vlbuff_v   ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm
vlhuff_v   ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm
vlwuff_v   ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm
vsb_v      ... 000 . 00000 ..... 000 ..... 0100111 @r2_nfvm
vsh_v      ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm
vsw_v      ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm
vse_v      ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm

vlsb_v     ... 110 . ..... ..... 000 ..... 0000111 @r_nfvm
vlsh_v     ... 110 . ..... ..... 101 ..... 0000111 @r_nfvm
vlsw_v     ... 110 . ..... ..... 110 ..... 0000111 @r_nfvm
vlse_v     ... 010 . ..... ..... 111 ..... 0000111 @r_nfvm
vlsbu_v    ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm
vlshu_v    ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm
vlswu_v    ... 010 . ..... ..... 110 ..... 0000111 @r_nfvm
vssb_v     ... 010 . ..... ..... 000 ..... 0100111 @r_nfvm
vssh_v     ... 010 . ..... ..... 101 ..... 0100111 @r_nfvm
vssw_v     ... 010 . ..... ..... 110 ..... 0100111 @r_nfvm
vsse_v     ... 010 . ..... ..... 111 ..... 0100111 @r_nfvm

vlxb_v     ... 111 . ..... ..... 000 ..... 0000111 @r_nfvm
vlxh_v     ... 111 . ..... ..... 101 ..... 0000111 @r_nfvm
vlxw_v     ... 111 . ..... ..... 110 ..... 0000111 @r_nfvm
vlxe_v     ... 011 . ..... ..... 111 ..... 0000111 @r_nfvm
vlxbu_v    ... 011 . ..... ..... 000 ..... 0000111 @r_nfvm
vlxhu_v    ... 011 . ..... ..... 101 ..... 0000111 @r_nfvm
vlxwu_v    ... 011 . ..... ..... 110 ..... 0000111 @r_nfvm
# Vector ordered-indexed and unordered-indexed store insns.
vsxb_v     ... -11 . ..... ..... 000 ..... 0100111 @r_nfvm
vsxh_v     ... -11 . ..... ..... 101 ..... 0100111 @r_nfvm
vsxw_v     ... -11 . ..... ..... 110 ..... 0100111 @r_nfvm
vsxe_v     ... -11 . ..... ..... 111 ..... 0100111 @r_nfvm

#*** Vector AMO operations are encoded under the standard AMO major opcode ***
vamoswapw_v     00001 . . ..... ..... 110 ..... 0101111 @r_wdvm
vamoaddw_v      00000 . . ..... ..... 110 ..... 0101111 @r_wdvm
vamoxorw_v      00100 . . ..... ..... 110 ..... 0101111 @r_wdvm
vamoandw_v      01100 . . ..... ..... 110 ..... 0101111 @r_wdvm
vamoorw_v       01000 . . ..... ..... 110 ..... 0101111 @r_wdvm
vamominw_v      10000 . . ..... ..... 110 ..... 0101111 @r_wdvm
vamomaxw_v      10100 . . ..... ..... 110 ..... 0101111 @r_wdvm
vamominuw_v     11000 . . ..... ..... 110 ..... 0101111 @r_wdvm
vamomaxuw_v     11100 . . ..... ..... 110 ..... 0101111 @r_wdvm

# *** new major opcode OP-V ***
vsetvli         0 ........... ..... 111 ..... 1010111  @r2_zimm
vsetvl          1000000 ..... ..... 111 ..... 1010111  @r
Commit	Line	Data
2a53cff4 BK	1	#
	2	# RISC-V translation routines for the RVXI Base Integer Instruction Set.
	3	#
	4	# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
	5	# Bastian Koppelmann, kbastian@mail.uni-paderborn.de
	6	#
	7	# This program is free software; you can redistribute it and/or modify it
	8	# under the terms and conditions of the GNU General Public License,
	9	# version 2 or later, as published by the Free Software Foundation.
	10	#
	11	# This program is distributed in the hope it will be useful, but WITHOUT
	12	# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	14	# more details.
	15	#
	16	# You should have received a copy of the GNU General Public License along with
	17	# this program. If not, see <http://www.gnu.org/licenses/>.
	18
	19	# Fields:
6f0e74ff	20	%rs3 27:5
3cca75a6 BK	21	%rs2 20:5
3cca75a6 BK	22	%rs1 15:5
2a53cff4 BK	23	%rd 7:5
2a53cff4 BK	24
b73a987b	25	%sh10 20:10
771fbe15	26	%csr 20:12
6f0e74ff	27	%rm 12:3
751538d5	28	%nf 29:3 !function=ex_plus_1
b73a987b	29
2a53cff4	30	# immediates:
3cca75a6	31	%imm_i 20:s12
c1000d4e	32	%imm_s 25:s7 7:5
3cca75a6 BK	33	%imm_b 31:s1 7:1 25:6 8:4 !function=ex_shift_1
3cca75a6 BK	34	%imm_j 31:s1 12:8 20:1 21:10 !function=ex_shift_1
2a53cff4 BK	35	%imm_u 12:s20 !function=ex_shift_12
2a53cff4 BK	36
3cca75a6	37	# Argument sets:
e7617997	38	&empty
3cca75a6	39	&b imm rs2 rs1
7a50d3e2	40	&i imm rs1 rd
e7617997	41	&j imm rd
f2ab1728	42	&r rd rs1 rs2
e7617997 RH	43	&s imm rs1 rs2
e7617997 RH	44	&u imm rd
b73a987b	45	&shift shamt rs1 rd
3b77c289	46	&atomic aq rl rs2 rs1 rd
268fcca6	47	&rwdvm vm wd rd rs1 rs2
751538d5 LZ	48	&r2nfvm vm rd rs1 nf
751538d5 LZ	49	&rnfvm vm rd rs1 rs2 nf
3cca75a6	50
2a53cff4	51	# Formats 32:
f2ab1728	52	@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd
7a50d3e2	53	@i ............ ..... ... ..... ....... &i imm=%imm_i %rs1 %rd
3cca75a6	54	@b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1
e7617997 RH	55	@s ....... ..... ..... ... ..... ....... &s imm=%imm_s %rs2 %rs1
	56	@u .................... ..... ....... &u imm=%imm_u %rd
	57	@j .................... ..... ....... &j imm=%imm_j %rd
2a53cff4	58
b73a987b	59	@sh ...... ...... ..... ... ..... ....... &shift shamt=%sh10 %rs1 %rd
771fbe15	60	@csr ............ ..... ... ..... ....... %csr %rs1 %rd
b73a987b	61
3b77c289 BK	62	@atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd
	63	@atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2 %rs1 %rd
	64
6f0e74ff BK	65	@r4_rm ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd
	66	@r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
	67	@r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd
	68	@r2 ....... ..... ..... ... ..... ....... %rs1 %rd
751538d5 LZ	69	@r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd
751538d5 LZ	70	@r_nfvm ... ... vm:1 ..... ..... ... ..... ....... &rnfvm %nf %rs2 %rs1 %rd
268fcca6	71	@r_wdvm ..... wd:1 vm:1 ..... ..... ... ..... ....... &rwdvm %rs2 %rs1 %rd
2b7168fc	72	@r2_zimm . zimm:11 ..... ... ..... ....... %rs1 %rd
6f0e74ff	73
895c412c	74	@hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1
b8429ded	75	@hfence_vvma ....... ..... ..... ... ..... ....... %rs2 %rs1
895c412c	76
4ba79c47 BK	77	@sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1
	78	@sfence_vm ....... ..... ..... ... ..... ....... %rs1
	79
	80
	81	# * Privileged Instructions *
895c412c AF	82	ecall 000000000000 00000 000 00000 1110011
	83	ebreak 000000000001 00000 000 00000 1110011
	84	uret 0000000 00010 00000 000 00000 1110011
	85	sret 0001000 00010 00000 000 00000 1110011
895c412c AF	86	mret 0011000 00010 00000 000 00000 1110011
895c412c AF	87	wfi 0001000 00101 00000 000 00000 1110011
895c412c AF	88	sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma
895c412c AF	89	sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm
4ba79c47	90
2a53cff4 BK	91	# * RV32I Base Instruction Set *
	92	lui .................... ..... 0110111 @u
	93	auipc .................... ..... 0010111 @u
3cca75a6 BK	94	jal .................... ..... 1101111 @j
	95	jalr ............ ..... 000 ..... 1100111 @i
	96	beq ....... ..... ..... 000 ..... 1100011 @b
	97	bne ....... ..... ..... 001 ..... 1100011 @b
	98	blt ....... ..... ..... 100 ..... 1100011 @b
	99	bge ....... ..... ..... 101 ..... 1100011 @b
	100	bltu ....... ..... ..... 110 ..... 1100011 @b
	101	bgeu ....... ..... ..... 111 ..... 1100011 @b
c1000d4e BK	102	lb ............ ..... 000 ..... 0000011 @i
	103	lh ............ ..... 001 ..... 0000011 @i
	104	lw ............ ..... 010 ..... 0000011 @i
	105	lbu ............ ..... 100 ..... 0000011 @i
	106	lhu ............ ..... 101 ..... 0000011 @i
	107	sb ....... ..... ..... 000 ..... 0100011 @s
	108	sh ....... ..... ..... 001 ..... 0100011 @s
	109	sw ....... ..... ..... 010 ..... 0100011 @s
b73a987b BK	110	addi ............ ..... 000 ..... 0010011 @i
	111	slti ............ ..... 010 ..... 0010011 @i
	112	sltiu ............ ..... 011 ..... 0010011 @i
	113	xori ............ ..... 100 ..... 0010011 @i
	114	ori ............ ..... 110 ..... 0010011 @i
	115	andi ............ ..... 111 ..... 0010011 @i
	116	slli 00.... ...... ..... 001 ..... 0010011 @sh
	117	srli 00.... ...... ..... 101 ..... 0010011 @sh
	118	srai 01.... ...... ..... 101 ..... 0010011 @sh
	119	add 0000000 ..... ..... 000 ..... 0110011 @r
	120	sub 0100000 ..... ..... 000 ..... 0110011 @r
	121	sll 0000000 ..... ..... 001 ..... 0110011 @r
	122	slt 0000000 ..... ..... 010 ..... 0110011 @r
	123	sltu 0000000 ..... ..... 011 ..... 0110011 @r
	124	xor 0000000 ..... ..... 100 ..... 0110011 @r
	125	srl 0000000 ..... ..... 101 ..... 0110011 @r
	126	sra 0100000 ..... ..... 101 ..... 0110011 @r
	127	or 0000000 ..... ..... 110 ..... 0110011 @r
	128	and 0000000 ..... ..... 111 ..... 0110011 @r
0c865e85 BK	129	fence ---- pred:4 succ:4 ----- 000 ----- 0001111
0c865e85 BK	130	fence_i ---- ---- ---- ----- 001 ----- 0001111
771fbe15 BK	131	csrrw ............ ..... 001 ..... 1110011 @csr
	132	csrrs ............ ..... 010 ..... 1110011 @csr
	133	csrrc ............ ..... 011 ..... 1110011 @csr
	134	csrrwi ............ ..... 101 ..... 1110011 @csr
	135	csrrsi ............ ..... 110 ..... 1110011 @csr
	136	csrrci ............ ..... 111 ..... 1110011 @csr
d2e2c1e4 BK	137
	138	# * RV32M Standard Extension *
	139	mul 0000001 ..... ..... 000 ..... 0110011 @r
	140	mulh 0000001 ..... ..... 001 ..... 0110011 @r
	141	mulhsu 0000001 ..... ..... 010 ..... 0110011 @r
	142	mulhu 0000001 ..... ..... 011 ..... 0110011 @r
	143	div 0000001 ..... ..... 100 ..... 0110011 @r
	144	divu 0000001 ..... ..... 101 ..... 0110011 @r
	145	rem 0000001 ..... ..... 110 ..... 0110011 @r
	146	remu 0000001 ..... ..... 111 ..... 0110011 @r
3b77c289 BK	147
	148	# * RV32A Standard Extension *
	149	lr_w 00010 . . 00000 ..... 010 ..... 0101111 @atom_ld
	150	sc_w 00011 . . ..... ..... 010 ..... 0101111 @atom_st
	151	amoswap_w 00001 . . ..... ..... 010 ..... 0101111 @atom_st
	152	amoadd_w 00000 . . ..... ..... 010 ..... 0101111 @atom_st
	153	amoxor_w 00100 . . ..... ..... 010 ..... 0101111 @atom_st
	154	amoand_w 01100 . . ..... ..... 010 ..... 0101111 @atom_st
	155	amoor_w 01000 . . ..... ..... 010 ..... 0101111 @atom_st
	156	amomin_w 10000 . . ..... ..... 010 ..... 0101111 @atom_st
	157	amomax_w 10100 . . ..... ..... 010 ..... 0101111 @atom_st
	158	amominu_w 11000 . . ..... ..... 010 ..... 0101111 @atom_st
	159	amomaxu_w 11100 . . ..... ..... 010 ..... 0101111 @atom_st
6f0e74ff BK	160
	161	# * RV32F Standard Extension *
	162	flw ............ ..... 010 ..... 0000111 @i
	163	fsw ....... ..... ..... 010 ..... 0100111 @s
	164	fmadd_s ..... 00 ..... ..... ... ..... 1000011 @r4_rm
	165	fmsub_s ..... 00 ..... ..... ... ..... 1000111 @r4_rm
	166	fnmsub_s ..... 00 ..... ..... ... ..... 1001011 @r4_rm
	167	fnmadd_s ..... 00 ..... ..... ... ..... 1001111 @r4_rm
	168	fadd_s 0000000 ..... ..... ... ..... 1010011 @r_rm
	169	fsub_s 0000100 ..... ..... ... ..... 1010011 @r_rm
	170	fmul_s 0001000 ..... ..... ... ..... 1010011 @r_rm
	171	fdiv_s 0001100 ..... ..... ... ..... 1010011 @r_rm
	172	fsqrt_s 0101100 00000 ..... ... ..... 1010011 @r2_rm
	173	fsgnj_s 0010000 ..... ..... 000 ..... 1010011 @r
	174	fsgnjn_s 0010000 ..... ..... 001 ..... 1010011 @r
	175	fsgnjx_s 0010000 ..... ..... 010 ..... 1010011 @r
	176	fmin_s 0010100 ..... ..... 000 ..... 1010011 @r
	177	fmax_s 0010100 ..... ..... 001 ..... 1010011 @r
	178	fcvt_w_s 1100000 00000 ..... ... ..... 1010011 @r2_rm
	179	fcvt_wu_s 1100000 00001 ..... ... ..... 1010011 @r2_rm
	180	fmv_x_w 1110000 00000 ..... 000 ..... 1010011 @r2
	181	feq_s 1010000 ..... ..... 010 ..... 1010011 @r
	182	flt_s 1010000 ..... ..... 001 ..... 1010011 @r
	183	fle_s 1010000 ..... ..... 000 ..... 1010011 @r
	184	fclass_s 1110000 00000 ..... 001 ..... 1010011 @r2
	185	fcvt_s_w 1101000 00000 ..... ... ..... 1010011 @r2_rm
	186	fcvt_s_wu 1101000 00001 ..... ... ..... 1010011 @r2_rm
	187	fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2
97f8b493 BK	188
	189	# * RV32D Standard Extension *
	190	fld ............ ..... 011 ..... 0000111 @i
	191	fsd ....... ..... ..... 011 ..... 0100111 @s
	192	fmadd_d ..... 01 ..... ..... ... ..... 1000011 @r4_rm
	193	fmsub_d ..... 01 ..... ..... ... ..... 1000111 @r4_rm
	194	fnmsub_d ..... 01 ..... ..... ... ..... 1001011 @r4_rm
	195	fnmadd_d ..... 01 ..... ..... ... ..... 1001111 @r4_rm
	196	fadd_d 0000001 ..... ..... ... ..... 1010011 @r_rm
	197	fsub_d 0000101 ..... ..... ... ..... 1010011 @r_rm
	198	fmul_d 0001001 ..... ..... ... ..... 1010011 @r_rm
	199	fdiv_d 0001101 ..... ..... ... ..... 1010011 @r_rm
	200	fsqrt_d 0101101 00000 ..... ... ..... 1010011 @r2_rm
	201	fsgnj_d 0010001 ..... ..... 000 ..... 1010011 @r
	202	fsgnjn_d 0010001 ..... ..... 001 ..... 1010011 @r
	203	fsgnjx_d 0010001 ..... ..... 010 ..... 1010011 @r
	204	fmin_d 0010101 ..... ..... 000 ..... 1010011 @r
	205	fmax_d 0010101 ..... ..... 001 ..... 1010011 @r
	206	fcvt_s_d 0100000 00001 ..... ... ..... 1010011 @r2_rm
	207	fcvt_d_s 0100001 00000 ..... ... ..... 1010011 @r2_rm
	208	feq_d 1010001 ..... ..... 010 ..... 1010011 @r
	209	flt_d 1010001 ..... ..... 001 ..... 1010011 @r
	210	fle_d 1010001 ..... ..... 000 ..... 1010011 @r
	211	fclass_d 1110001 00000 ..... 001 ..... 1010011 @r2
	212	fcvt_w_d 1100001 00000 ..... ... ..... 1010011 @r2_rm
	213	fcvt_wu_d 1100001 00001 ..... ... ..... 1010011 @r2_rm
	214	fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm
	215	fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm
b8429ded AF	216
	217	# * RV32H Base Instruction Set *
	218	hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma
	219	hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma
2b7168fc LZ	220
2b7168fc LZ	221	# * RV32V Extension *
751538d5 LZ	222
	223	# * Vector loads and stores are encoded within LOADFP/STORE-FP *
	224	vlb_v ... 100 . 00000 ..... 000 ..... 0000111 @r2_nfvm
	225	vlh_v ... 100 . 00000 ..... 101 ..... 0000111 @r2_nfvm
	226	vlw_v ... 100 . 00000 ..... 110 ..... 0000111 @r2_nfvm
	227	vle_v ... 000 . 00000 ..... 111 ..... 0000111 @r2_nfvm
	228	vlbu_v ... 000 . 00000 ..... 000 ..... 0000111 @r2_nfvm
	229	vlhu_v ... 000 . 00000 ..... 101 ..... 0000111 @r2_nfvm
	230	vlwu_v ... 000 . 00000 ..... 110 ..... 0000111 @r2_nfvm
022b4ecf LZ	231	vlbff_v ... 100 . 10000 ..... 000 ..... 0000111 @r2_nfvm
	232	vlhff_v ... 100 . 10000 ..... 101 ..... 0000111 @r2_nfvm
	233	vlwff_v ... 100 . 10000 ..... 110 ..... 0000111 @r2_nfvm
	234	vleff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm
	235	vlbuff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm
	236	vlhuff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm
	237	vlwuff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm
751538d5 LZ	238	vsb_v ... 000 . 00000 ..... 000 ..... 0100111 @r2_nfvm
	239	vsh_v ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm
	240	vsw_v ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm
	241	vse_v ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm
	242
	243	vlsb_v ... 110 . ..... ..... 000 ..... 0000111 @r_nfvm
	244	vlsh_v ... 110 . ..... ..... 101 ..... 0000111 @r_nfvm
	245	vlsw_v ... 110 . ..... ..... 110 ..... 0000111 @r_nfvm
	246	vlse_v ... 010 . ..... ..... 111 ..... 0000111 @r_nfvm
	247	vlsbu_v ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm
	248	vlshu_v ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm
	249	vlswu_v ... 010 . ..... ..... 110 ..... 0000111 @r_nfvm
	250	vssb_v ... 010 . ..... ..... 000 ..... 0100111 @r_nfvm
	251	vssh_v ... 010 . ..... ..... 101 ..... 0100111 @r_nfvm
	252	vssw_v ... 010 . ..... ..... 110 ..... 0100111 @r_nfvm
	253	vsse_v ... 010 . ..... ..... 111 ..... 0100111 @r_nfvm
	254
f732560e LZ	255	vlxb_v ... 111 . ..... ..... 000 ..... 0000111 @r_nfvm
	256	vlxh_v ... 111 . ..... ..... 101 ..... 0000111 @r_nfvm
	257	vlxw_v ... 111 . ..... ..... 110 ..... 0000111 @r_nfvm
	258	vlxe_v ... 011 . ..... ..... 111 ..... 0000111 @r_nfvm
	259	vlxbu_v ... 011 . ..... ..... 000 ..... 0000111 @r_nfvm
	260	vlxhu_v ... 011 . ..... ..... 101 ..... 0000111 @r_nfvm
	261	vlxwu_v ... 011 . ..... ..... 110 ..... 0000111 @r_nfvm
	262	# Vector ordered-indexed and unordered-indexed store insns.
	263	vsxb_v ... -11 . ..... ..... 000 ..... 0100111 @r_nfvm
	264	vsxh_v ... -11 . ..... ..... 101 ..... 0100111 @r_nfvm
	265	vsxw_v ... -11 . ..... ..... 110 ..... 0100111 @r_nfvm
	266	vsxe_v ... -11 . ..... ..... 111 ..... 0100111 @r_nfvm
	267
268fcca6 LZ	268	#* Vector AMO operations are encoded under the standard AMO major opcode *
	269	vamoswapw_v 00001 . . ..... ..... 110 ..... 0101111 @r_wdvm
	270	vamoaddw_v 00000 . . ..... ..... 110 ..... 0101111 @r_wdvm
	271	vamoxorw_v 00100 . . ..... ..... 110 ..... 0101111 @r_wdvm
	272	vamoandw_v 01100 . . ..... ..... 110 ..... 0101111 @r_wdvm
	273	vamoorw_v 01000 . . ..... ..... 110 ..... 0101111 @r_wdvm
	274	vamominw_v 10000 . . ..... ..... 110 ..... 0101111 @r_wdvm
	275	vamomaxw_v 10100 . . ..... ..... 110 ..... 0101111 @r_wdvm
	276	vamominuw_v 11000 . . ..... ..... 110 ..... 0101111 @r_wdvm
	277	vamomaxuw_v 11100 . . ..... ..... 110 ..... 0101111 @r_wdvm
	278
751538d5	279	# * new major opcode OP-V *
2b7168fc LZ	280	vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
2b7168fc LZ	281	vsetvl 1000000 ..... ..... 111 ..... 1010111 @r