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[mirror_qemu.git] / target / riscv / insn_trans / trans_rvv.inc.c
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2b7168fc
LZ		 1/*
2 * RISC-V translation routines for the RVV Standard Extension.
3 *
4 * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 */
751538d5
LZ		 18#include "tcg/tcg-op-gvec.h"
19#include "tcg/tcg-gvec-desc.h"
20#include "internals.h"
2b7168fc
LZ		 21
22static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
23{
24 TCGv s1, s2, dst;
25
26 if (!has_ext(ctx, RVV)) {
27 return false;
28 }
29
30 s2 = tcg_temp_new();
31 dst = tcg_temp_new();
32
33 /* Using x0 as the rs1 register specifier, encodes an infinite AVL */
34 if (a->rs1 == 0) {
35 /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
36 s1 = tcg_const_tl(RV_VLEN_MAX);
37 } else {
38 s1 = tcg_temp_new();
39 gen_get_gpr(s1, a->rs1);
40 }
41 gen_get_gpr(s2, a->rs2);
42 gen_helper_vsetvl(dst, cpu_env, s1, s2);
43 gen_set_gpr(a->rd, dst);
44 tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
45 lookup_and_goto_ptr(ctx);
46 ctx->base.is_jmp = DISAS_NORETURN;
47
48 tcg_temp_free(s1);
49 tcg_temp_free(s2);
50 tcg_temp_free(dst);
51 return true;
52}
53
54static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a)
55{
56 TCGv s1, s2, dst;
57
58 if (!has_ext(ctx, RVV)) {
59 return false;
60 }
61
62 s2 = tcg_const_tl(a->zimm);
63 dst = tcg_temp_new();
64
65 /* Using x0 as the rs1 register specifier, encodes an infinite AVL */
66 if (a->rs1 == 0) {
67 /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
68 s1 = tcg_const_tl(RV_VLEN_MAX);
69 } else {
70 s1 = tcg_temp_new();
71 gen_get_gpr(s1, a->rs1);
72 }
73 gen_helper_vsetvl(dst, cpu_env, s1, s2);
74 gen_set_gpr(a->rd, dst);
75 gen_goto_tb(ctx, 0, ctx->pc_succ_insn);
76 ctx->base.is_jmp = DISAS_NORETURN;
77
78 tcg_temp_free(s1);
79 tcg_temp_free(s2);
80 tcg_temp_free(dst);
81 return true;
82}
751538d5
LZ		 83
84/* vector register offset from env */
85static uint32_t vreg_ofs(DisasContext *s, int reg)
86{
87 return offsetof(CPURISCVState, vreg) + reg * s->vlen / 8;
88}
89
90/* check functions */
91
92/*
93 * In cpu_get_tb_cpu_state(), set VILL if RVV was not present.
94 * So RVV is also be checked in this function.
95 */
96static bool vext_check_isa_ill(DisasContext *s)
97{
98 return !s->vill;
99}
100
101/*
102 * There are two rules check here.
103 *
104 * 1. Vector register numbers are multiples of LMUL. (Section 3.2)
105 *
106 * 2. For all widening instructions, the destination LMUL value must also be
107 * a supported LMUL value. (Section 11.2)
108 */
109static bool vext_check_reg(DisasContext *s, uint32_t reg, bool widen)
110{
111 /*
112 * The destination vector register group results are arranged as if both
113 * SEW and LMUL were at twice their current settings. (Section 11.2).
114 */
115 int legal = widen ? 2 << s->lmul : 1 << s->lmul;
116
117 return !((s->lmul == 0x3 && widen) || (reg % legal));
118}
119
120/*
121 * There are two rules check here.
122 *
123 * 1. The destination vector register group for a masked vector instruction can
124 * only overlap the source mask register (v0) when LMUL=1. (Section 5.3)
125 *
126 * 2. In widen instructions and some other insturctions, like vslideup.vx,
127 * there is no need to check whether LMUL=1.
128 */
129static bool vext_check_overlap_mask(DisasContext *s, uint32_t vd, bool vm,
130 bool force)
131{
132 return (vm != 0 || vd != 0) || (!force && (s->lmul == 0));
133}
134
135/* The LMUL setting must be such that LMUL * NFIELDS <= 8. (Section 7.8) */
136static bool vext_check_nf(DisasContext *s, uint32_t nf)
137{
138 return (1 << s->lmul) * nf <= 8;
139}
140
8fcdf776
LZ		 141/*
142 * The destination vector register group cannot overlap a source vector register
143 * group of a different element width. (Section 11.2)
144 */
145static inline bool vext_check_overlap_group(int rd, int dlen, int rs, int slen)
146{
147 return ((rd >= rs + slen) || (rs >= rd + dlen));
148}
751538d5
LZ		 149/* common translation macro */
150#define GEN_VEXT_TRANS(NAME, SEQ, ARGTYPE, OP, CHECK) \
151static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE *a)\
152{ \
153 if (CHECK(s, a)) { \
154 return OP(s, a, SEQ); \
155 } \
156 return false; \
157}
158
159/*
160 *** unit stride load and store
161 */
162typedef void gen_helper_ldst_us(TCGv_ptr, TCGv_ptr, TCGv,
163 TCGv_env, TCGv_i32);
164
165static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
166 gen_helper_ldst_us *fn, DisasContext *s)
167{
168 TCGv_ptr dest, mask;
169 TCGv base;
170 TCGv_i32 desc;
171
172 TCGLabel *over = gen_new_label();
173 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
174
175 dest = tcg_temp_new_ptr();
176 mask = tcg_temp_new_ptr();
177 base = tcg_temp_new();
178
179 /*
180 * As simd_desc supports at most 256 bytes, and in this implementation,
181 * the max vector group length is 2048 bytes. So split it into two parts.
182 *
183 * The first part is vlen in bytes, encoded in maxsz of simd_desc.
184 * The second part is lmul, encoded in data of simd_desc.
185 */
186 desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
187
188 gen_get_gpr(base, rs1);
189 tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
190 tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
191
192 fn(dest, mask, base, cpu_env, desc);
193
194 tcg_temp_free_ptr(dest);
195 tcg_temp_free_ptr(mask);
196 tcg_temp_free(base);
197 tcg_temp_free_i32(desc);
198 gen_set_label(over);
199 return true;
200}
201
202static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
203{
204 uint32_t data = 0;
205 gen_helper_ldst_us *fn;
206 static gen_helper_ldst_us * const fns[2][7][4] = {
207 /* masked unit stride load */
208 { { gen_helper_vlb_v_b_mask, gen_helper_vlb_v_h_mask,
209 gen_helper_vlb_v_w_mask, gen_helper_vlb_v_d_mask },
210 { NULL, gen_helper_vlh_v_h_mask,
211 gen_helper_vlh_v_w_mask, gen_helper_vlh_v_d_mask },
212 { NULL, NULL,
213 gen_helper_vlw_v_w_mask, gen_helper_vlw_v_d_mask },
214 { gen_helper_vle_v_b_mask, gen_helper_vle_v_h_mask,
215 gen_helper_vle_v_w_mask, gen_helper_vle_v_d_mask },
216 { gen_helper_vlbu_v_b_mask, gen_helper_vlbu_v_h_mask,
217 gen_helper_vlbu_v_w_mask, gen_helper_vlbu_v_d_mask },
218 { NULL, gen_helper_vlhu_v_h_mask,
219 gen_helper_vlhu_v_w_mask, gen_helper_vlhu_v_d_mask },
220 { NULL, NULL,
221 gen_helper_vlwu_v_w_mask, gen_helper_vlwu_v_d_mask } },
222 /* unmasked unit stride load */
223 { { gen_helper_vlb_v_b, gen_helper_vlb_v_h,
224 gen_helper_vlb_v_w, gen_helper_vlb_v_d },
225 { NULL, gen_helper_vlh_v_h,
226 gen_helper_vlh_v_w, gen_helper_vlh_v_d },
227 { NULL, NULL,
228 gen_helper_vlw_v_w, gen_helper_vlw_v_d },
229 { gen_helper_vle_v_b, gen_helper_vle_v_h,
230 gen_helper_vle_v_w, gen_helper_vle_v_d },
231 { gen_helper_vlbu_v_b, gen_helper_vlbu_v_h,
232 gen_helper_vlbu_v_w, gen_helper_vlbu_v_d },
233 { NULL, gen_helper_vlhu_v_h,
234 gen_helper_vlhu_v_w, gen_helper_vlhu_v_d },
235 { NULL, NULL,
236 gen_helper_vlwu_v_w, gen_helper_vlwu_v_d } }
237 };
238
239 fn = fns[a->vm][seq][s->sew];
240 if (fn == NULL) {
241 return false;
242 }
243
244 data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
245 data = FIELD_DP32(data, VDATA, VM, a->vm);
246 data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
247 data = FIELD_DP32(data, VDATA, NF, a->nf);
248 return ldst_us_trans(a->rd, a->rs1, data, fn, s);
249}
250
251static bool ld_us_check(DisasContext *s, arg_r2nfvm* a)
252{
253 return (vext_check_isa_ill(s) &&
254 vext_check_overlap_mask(s, a->rd, a->vm, false) &&
255 vext_check_reg(s, a->rd, false) &&
256 vext_check_nf(s, a->nf));
257}
258
259GEN_VEXT_TRANS(vlb_v, 0, r2nfvm, ld_us_op, ld_us_check)
260GEN_VEXT_TRANS(vlh_v, 1, r2nfvm, ld_us_op, ld_us_check)
261GEN_VEXT_TRANS(vlw_v, 2, r2nfvm, ld_us_op, ld_us_check)
262GEN_VEXT_TRANS(vle_v, 3, r2nfvm, ld_us_op, ld_us_check)
263GEN_VEXT_TRANS(vlbu_v, 4, r2nfvm, ld_us_op, ld_us_check)
264GEN_VEXT_TRANS(vlhu_v, 5, r2nfvm, ld_us_op, ld_us_check)
265GEN_VEXT_TRANS(vlwu_v, 6, r2nfvm, ld_us_op, ld_us_check)
266
267static bool st_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
268{
269 uint32_t data = 0;
270 gen_helper_ldst_us *fn;
271 static gen_helper_ldst_us * const fns[2][4][4] = {
272 /* masked unit stride load and store */
273 { { gen_helper_vsb_v_b_mask, gen_helper_vsb_v_h_mask,
274 gen_helper_vsb_v_w_mask, gen_helper_vsb_v_d_mask },
275 { NULL, gen_helper_vsh_v_h_mask,
276 gen_helper_vsh_v_w_mask, gen_helper_vsh_v_d_mask },
277 { NULL, NULL,
278 gen_helper_vsw_v_w_mask, gen_helper_vsw_v_d_mask },
279 { gen_helper_vse_v_b_mask, gen_helper_vse_v_h_mask,
280 gen_helper_vse_v_w_mask, gen_helper_vse_v_d_mask } },
281 /* unmasked unit stride store */
282 { { gen_helper_vsb_v_b, gen_helper_vsb_v_h,
283 gen_helper_vsb_v_w, gen_helper_vsb_v_d },
284 { NULL, gen_helper_vsh_v_h,
285 gen_helper_vsh_v_w, gen_helper_vsh_v_d },
286 { NULL, NULL,
287 gen_helper_vsw_v_w, gen_helper_vsw_v_d },
288 { gen_helper_vse_v_b, gen_helper_vse_v_h,
289 gen_helper_vse_v_w, gen_helper_vse_v_d } }
290 };
291
292 fn = fns[a->vm][seq][s->sew];
293 if (fn == NULL) {
294 return false;
295 }
296
297 data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
298 data = FIELD_DP32(data, VDATA, VM, a->vm);
299 data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
300 data = FIELD_DP32(data, VDATA, NF, a->nf);
301 return ldst_us_trans(a->rd, a->rs1, data, fn, s);
302}
303
304static bool st_us_check(DisasContext *s, arg_r2nfvm* a)
305{
306 return (vext_check_isa_ill(s) &&
307 vext_check_reg(s, a->rd, false) &&
308 vext_check_nf(s, a->nf));
309}
310
311GEN_VEXT_TRANS(vsb_v, 0, r2nfvm, st_us_op, st_us_check)
312GEN_VEXT_TRANS(vsh_v, 1, r2nfvm, st_us_op, st_us_check)
313GEN_VEXT_TRANS(vsw_v, 2, r2nfvm, st_us_op, st_us_check)
314GEN_VEXT_TRANS(vse_v, 3, r2nfvm, st_us_op, st_us_check)
315
316/*
317 *** stride load and store
318 */
319typedef void gen_helper_ldst_stride(TCGv_ptr, TCGv_ptr, TCGv,
320 TCGv, TCGv_env, TCGv_i32);
321
322static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
323 uint32_t data, gen_helper_ldst_stride *fn,
324 DisasContext *s)
325{
326 TCGv_ptr dest, mask;
327 TCGv base, stride;
328 TCGv_i32 desc;
329
330 TCGLabel *over = gen_new_label();
331 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
332
333 dest = tcg_temp_new_ptr();
334 mask = tcg_temp_new_ptr();
335 base = tcg_temp_new();
336 stride = tcg_temp_new();
337 desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
338
339 gen_get_gpr(base, rs1);
340 gen_get_gpr(stride, rs2);
341 tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
342 tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
343
344 fn(dest, mask, base, stride, cpu_env, desc);
345
346 tcg_temp_free_ptr(dest);
347 tcg_temp_free_ptr(mask);
348 tcg_temp_free(base);
349 tcg_temp_free(stride);
350 tcg_temp_free_i32(desc);
351 gen_set_label(over);
352 return true;
353}
354
355static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
356{
357 uint32_t data = 0;
358 gen_helper_ldst_stride *fn;
359 static gen_helper_ldst_stride * const fns[7][4] = {
360 { gen_helper_vlsb_v_b, gen_helper_vlsb_v_h,
361 gen_helper_vlsb_v_w, gen_helper_vlsb_v_d },
362 { NULL, gen_helper_vlsh_v_h,
363 gen_helper_vlsh_v_w, gen_helper_vlsh_v_d },
364 { NULL, NULL,
365 gen_helper_vlsw_v_w, gen_helper_vlsw_v_d },
366 { gen_helper_vlse_v_b, gen_helper_vlse_v_h,
367 gen_helper_vlse_v_w, gen_helper_vlse_v_d },
368 { gen_helper_vlsbu_v_b, gen_helper_vlsbu_v_h,
369 gen_helper_vlsbu_v_w, gen_helper_vlsbu_v_d },
370 { NULL, gen_helper_vlshu_v_h,
371 gen_helper_vlshu_v_w, gen_helper_vlshu_v_d },
372 { NULL, NULL,
373 gen_helper_vlswu_v_w, gen_helper_vlswu_v_d },
374 };
375
376 fn = fns[seq][s->sew];
377 if (fn == NULL) {
378 return false;
379 }
380
381 data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
382 data = FIELD_DP32(data, VDATA, VM, a->vm);
383 data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
384 data = FIELD_DP32(data, VDATA, NF, a->nf);
385 return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);
386}
387
388static bool ld_stride_check(DisasContext *s, arg_rnfvm* a)
389{
390 return (vext_check_isa_ill(s) &&
391 vext_check_overlap_mask(s, a->rd, a->vm, false) &&
392 vext_check_reg(s, a->rd, false) &&
393 vext_check_nf(s, a->nf));
394}
395
396GEN_VEXT_TRANS(vlsb_v, 0, rnfvm, ld_stride_op, ld_stride_check)
397GEN_VEXT_TRANS(vlsh_v, 1, rnfvm, ld_stride_op, ld_stride_check)
398GEN_VEXT_TRANS(vlsw_v, 2, rnfvm, ld_stride_op, ld_stride_check)
399GEN_VEXT_TRANS(vlse_v, 3, rnfvm, ld_stride_op, ld_stride_check)
400GEN_VEXT_TRANS(vlsbu_v, 4, rnfvm, ld_stride_op, ld_stride_check)
401GEN_VEXT_TRANS(vlshu_v, 5, rnfvm, ld_stride_op, ld_stride_check)
402GEN_VEXT_TRANS(vlswu_v, 6, rnfvm, ld_stride_op, ld_stride_check)
403
404static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
405{
406 uint32_t data = 0;
407 gen_helper_ldst_stride *fn;
408 static gen_helper_ldst_stride * const fns[4][4] = {
409 /* masked stride store */
410 { gen_helper_vssb_v_b, gen_helper_vssb_v_h,
411 gen_helper_vssb_v_w, gen_helper_vssb_v_d },
412 { NULL, gen_helper_vssh_v_h,
413 gen_helper_vssh_v_w, gen_helper_vssh_v_d },
414 { NULL, NULL,
415 gen_helper_vssw_v_w, gen_helper_vssw_v_d },
416 { gen_helper_vsse_v_b, gen_helper_vsse_v_h,
417 gen_helper_vsse_v_w, gen_helper_vsse_v_d }
418 };
419
420 data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
421 data = FIELD_DP32(data, VDATA, VM, a->vm);
422 data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
423 data = FIELD_DP32(data, VDATA, NF, a->nf);
424 fn = fns[seq][s->sew];
425 if (fn == NULL) {
426 return false;
427 }
428
429 return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);
430}
431
432static bool st_stride_check(DisasContext *s, arg_rnfvm* a)
433{
434 return (vext_check_isa_ill(s) &&
435 vext_check_reg(s, a->rd, false) &&
436 vext_check_nf(s, a->nf));
437}
438
439GEN_VEXT_TRANS(vssb_v, 0, rnfvm, st_stride_op, st_stride_check)
440GEN_VEXT_TRANS(vssh_v, 1, rnfvm, st_stride_op, st_stride_check)
441GEN_VEXT_TRANS(vssw_v, 2, rnfvm, st_stride_op, st_stride_check)
442GEN_VEXT_TRANS(vsse_v, 3, rnfvm, st_stride_op, st_stride_check)
f732560e
LZ		 443
444/*
445 *** index load and store
446 */
447typedef void gen_helper_ldst_index(TCGv_ptr, TCGv_ptr, TCGv,
448 TCGv_ptr, TCGv_env, TCGv_i32);
449
450static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
451 uint32_t data, gen_helper_ldst_index *fn,
452 DisasContext *s)
453{
454 TCGv_ptr dest, mask, index;
455 TCGv base;
456 TCGv_i32 desc;
457
458 TCGLabel *over = gen_new_label();
459 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
460
461 dest = tcg_temp_new_ptr();
462 mask = tcg_temp_new_ptr();
463 index = tcg_temp_new_ptr();
464 base = tcg_temp_new();
465 desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
466
467 gen_get_gpr(base, rs1);
468 tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
469 tcg_gen_addi_ptr(index, cpu_env, vreg_ofs(s, vs2));
470 tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
471
472 fn(dest, mask, base, index, cpu_env, desc);
473
474 tcg_temp_free_ptr(dest);
475 tcg_temp_free_ptr(mask);
476 tcg_temp_free_ptr(index);
477 tcg_temp_free(base);
478 tcg_temp_free_i32(desc);
479 gen_set_label(over);
480 return true;
481}
482
483static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
484{
485 uint32_t data = 0;
486 gen_helper_ldst_index *fn;
487 static gen_helper_ldst_index * const fns[7][4] = {
488 { gen_helper_vlxb_v_b, gen_helper_vlxb_v_h,
489 gen_helper_vlxb_v_w, gen_helper_vlxb_v_d },
490 { NULL, gen_helper_vlxh_v_h,
491 gen_helper_vlxh_v_w, gen_helper_vlxh_v_d },
492 { NULL, NULL,
493 gen_helper_vlxw_v_w, gen_helper_vlxw_v_d },
494 { gen_helper_vlxe_v_b, gen_helper_vlxe_v_h,
495 gen_helper_vlxe_v_w, gen_helper_vlxe_v_d },
496 { gen_helper_vlxbu_v_b, gen_helper_vlxbu_v_h,
497 gen_helper_vlxbu_v_w, gen_helper_vlxbu_v_d },
498 { NULL, gen_helper_vlxhu_v_h,
499 gen_helper_vlxhu_v_w, gen_helper_vlxhu_v_d },
500 { NULL, NULL,
501 gen_helper_vlxwu_v_w, gen_helper_vlxwu_v_d },
502 };
503
504 fn = fns[seq][s->sew];
505 if (fn == NULL) {
506 return false;
507 }
508
509 data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
510 data = FIELD_DP32(data, VDATA, VM, a->vm);
511 data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
512 data = FIELD_DP32(data, VDATA, NF, a->nf);
513 return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s);
514}
515
516static bool ld_index_check(DisasContext *s, arg_rnfvm* a)
517{
518 return (vext_check_isa_ill(s) &&
519 vext_check_overlap_mask(s, a->rd, a->vm, false) &&
520 vext_check_reg(s, a->rd, false) &&
521 vext_check_reg(s, a->rs2, false) &&
522 vext_check_nf(s, a->nf));
523}
524
525GEN_VEXT_TRANS(vlxb_v, 0, rnfvm, ld_index_op, ld_index_check)
526GEN_VEXT_TRANS(vlxh_v, 1, rnfvm, ld_index_op, ld_index_check)
527GEN_VEXT_TRANS(vlxw_v, 2, rnfvm, ld_index_op, ld_index_check)
528GEN_VEXT_TRANS(vlxe_v, 3, rnfvm, ld_index_op, ld_index_check)
529GEN_VEXT_TRANS(vlxbu_v, 4, rnfvm, ld_index_op, ld_index_check)
530GEN_VEXT_TRANS(vlxhu_v, 5, rnfvm, ld_index_op, ld_index_check)
531GEN_VEXT_TRANS(vlxwu_v, 6, rnfvm, ld_index_op, ld_index_check)
532
533static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
534{
535 uint32_t data = 0;
536 gen_helper_ldst_index *fn;
537 static gen_helper_ldst_index * const fns[4][4] = {
538 { gen_helper_vsxb_v_b, gen_helper_vsxb_v_h,
539 gen_helper_vsxb_v_w, gen_helper_vsxb_v_d },
540 { NULL, gen_helper_vsxh_v_h,
541 gen_helper_vsxh_v_w, gen_helper_vsxh_v_d },
542 { NULL, NULL,
543 gen_helper_vsxw_v_w, gen_helper_vsxw_v_d },
544 { gen_helper_vsxe_v_b, gen_helper_vsxe_v_h,
545 gen_helper_vsxe_v_w, gen_helper_vsxe_v_d }
546 };
547
548 fn = fns[seq][s->sew];
549 if (fn == NULL) {
550 return false;
551 }
552
553 data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
554 data = FIELD_DP32(data, VDATA, VM, a->vm);
555 data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
556 data = FIELD_DP32(data, VDATA, NF, a->nf);
557 return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s);
558}
559
560static bool st_index_check(DisasContext *s, arg_rnfvm* a)
561{
562 return (vext_check_isa_ill(s) &&
563 vext_check_reg(s, a->rd, false) &&
564 vext_check_reg(s, a->rs2, false) &&
565 vext_check_nf(s, a->nf));
566}
567
568GEN_VEXT_TRANS(vsxb_v, 0, rnfvm, st_index_op, st_index_check)
569GEN_VEXT_TRANS(vsxh_v, 1, rnfvm, st_index_op, st_index_check)
570GEN_VEXT_TRANS(vsxw_v, 2, rnfvm, st_index_op, st_index_check)
571GEN_VEXT_TRANS(vsxe_v, 3, rnfvm, st_index_op, st_index_check)
022b4ecf
LZ		 572
573/*
574 *** unit stride fault-only-first load
575 */
576static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
577 gen_helper_ldst_us *fn, DisasContext *s)
578{
579 TCGv_ptr dest, mask;
580 TCGv base;
581 TCGv_i32 desc;
582
583 TCGLabel *over = gen_new_label();
584 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
585
586 dest = tcg_temp_new_ptr();
587 mask = tcg_temp_new_ptr();
588 base = tcg_temp_new();
589 desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
590
591 gen_get_gpr(base, rs1);
592 tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
593 tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
594
595 fn(dest, mask, base, cpu_env, desc);
596
597 tcg_temp_free_ptr(dest);
598 tcg_temp_free_ptr(mask);
599 tcg_temp_free(base);
600 tcg_temp_free_i32(desc);
601 gen_set_label(over);
602 return true;
603}
604
605static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
606{
607 uint32_t data = 0;
608 gen_helper_ldst_us *fn;
609 static gen_helper_ldst_us * const fns[7][4] = {
610 { gen_helper_vlbff_v_b, gen_helper_vlbff_v_h,
611 gen_helper_vlbff_v_w, gen_helper_vlbff_v_d },
612 { NULL, gen_helper_vlhff_v_h,
613 gen_helper_vlhff_v_w, gen_helper_vlhff_v_d },
614 { NULL, NULL,
615 gen_helper_vlwff_v_w, gen_helper_vlwff_v_d },
616 { gen_helper_vleff_v_b, gen_helper_vleff_v_h,
617 gen_helper_vleff_v_w, gen_helper_vleff_v_d },
618 { gen_helper_vlbuff_v_b, gen_helper_vlbuff_v_h,
619 gen_helper_vlbuff_v_w, gen_helper_vlbuff_v_d },
620 { NULL, gen_helper_vlhuff_v_h,
621 gen_helper_vlhuff_v_w, gen_helper_vlhuff_v_d },
622 { NULL, NULL,
623 gen_helper_vlwuff_v_w, gen_helper_vlwuff_v_d }
624 };
625
626 fn = fns[seq][s->sew];
627 if (fn == NULL) {
628 return false;
629 }
630
631 data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
632 data = FIELD_DP32(data, VDATA, VM, a->vm);
633 data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
634 data = FIELD_DP32(data, VDATA, NF, a->nf);
635 return ldff_trans(a->rd, a->rs1, data, fn, s);
636}
637
638GEN_VEXT_TRANS(vlbff_v, 0, r2nfvm, ldff_op, ld_us_check)
639GEN_VEXT_TRANS(vlhff_v, 1, r2nfvm, ldff_op, ld_us_check)
640GEN_VEXT_TRANS(vlwff_v, 2, r2nfvm, ldff_op, ld_us_check)
641GEN_VEXT_TRANS(vleff_v, 3, r2nfvm, ldff_op, ld_us_check)
642GEN_VEXT_TRANS(vlbuff_v, 4, r2nfvm, ldff_op, ld_us_check)
643GEN_VEXT_TRANS(vlhuff_v, 5, r2nfvm, ldff_op, ld_us_check)
644GEN_VEXT_TRANS(vlwuff_v, 6, r2nfvm, ldff_op, ld_us_check)
268fcca6
LZ		 645
646/*
647 *** vector atomic operation
648 */
649typedef void gen_helper_amo(TCGv_ptr, TCGv_ptr, TCGv, TCGv_ptr,
650 TCGv_env, TCGv_i32);
651
652static bool amo_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
653 uint32_t data, gen_helper_amo *fn, DisasContext *s)
654{
655 TCGv_ptr dest, mask, index;
656 TCGv base;
657 TCGv_i32 desc;
658
659 TCGLabel *over = gen_new_label();
660 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
661
662 dest = tcg_temp_new_ptr();
663 mask = tcg_temp_new_ptr();
664 index = tcg_temp_new_ptr();
665 base = tcg_temp_new();
666 desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
667
668 gen_get_gpr(base, rs1);
669 tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
670 tcg_gen_addi_ptr(index, cpu_env, vreg_ofs(s, vs2));
671 tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
672
673 fn(dest, mask, base, index, cpu_env, desc);
674
675 tcg_temp_free_ptr(dest);
676 tcg_temp_free_ptr(mask);
677 tcg_temp_free_ptr(index);
678 tcg_temp_free(base);
679 tcg_temp_free_i32(desc);
680 gen_set_label(over);
681 return true;
682}
683
684static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
685{
686 uint32_t data = 0;
687 gen_helper_amo *fn;
688 static gen_helper_amo *const fnsw[9] = {
689 /* no atomic operation */
690 gen_helper_vamoswapw_v_w,
691 gen_helper_vamoaddw_v_w,
692 gen_helper_vamoxorw_v_w,
693 gen_helper_vamoandw_v_w,
694 gen_helper_vamoorw_v_w,
695 gen_helper_vamominw_v_w,
696 gen_helper_vamomaxw_v_w,
697 gen_helper_vamominuw_v_w,
698 gen_helper_vamomaxuw_v_w
699 };
700#ifdef TARGET_RISCV64
701 static gen_helper_amo *const fnsd[18] = {
702 gen_helper_vamoswapw_v_d,
703 gen_helper_vamoaddw_v_d,
704 gen_helper_vamoxorw_v_d,
705 gen_helper_vamoandw_v_d,
706 gen_helper_vamoorw_v_d,
707 gen_helper_vamominw_v_d,
708 gen_helper_vamomaxw_v_d,
709 gen_helper_vamominuw_v_d,
710 gen_helper_vamomaxuw_v_d,
711 gen_helper_vamoswapd_v_d,
712 gen_helper_vamoaddd_v_d,
713 gen_helper_vamoxord_v_d,
714 gen_helper_vamoandd_v_d,
715 gen_helper_vamoord_v_d,
716 gen_helper_vamomind_v_d,
717 gen_helper_vamomaxd_v_d,
718 gen_helper_vamominud_v_d,
719 gen_helper_vamomaxud_v_d
720 };
721#endif
722
723 if (tb_cflags(s->base.tb) & CF_PARALLEL) {
724 gen_helper_exit_atomic(cpu_env);
725 s->base.is_jmp = DISAS_NORETURN;
726 return true;
727 } else {
728 if (s->sew == 3) {
729#ifdef TARGET_RISCV64
730 fn = fnsd[seq];
731#else
732 /* Check done in amo_check(). */
733 g_assert_not_reached();
734#endif
735 } else {
736 fn = fnsw[seq];
737 }
738 }
739
740 data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
741 data = FIELD_DP32(data, VDATA, VM, a->vm);
742 data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
743 data = FIELD_DP32(data, VDATA, WD, a->wd);
744 return amo_trans(a->rd, a->rs1, a->rs2, data, fn, s);
745}
746/*
747 * There are two rules check here.
748 *
749 * 1. SEW must be at least as wide as the AMO memory element size.
750 *
751 * 2. If SEW is greater than XLEN, an illegal instruction exception is raised.
752 */
753static bool amo_check(DisasContext *s, arg_rwdvm* a)
754{
755 return (!s->vill && has_ext(s, RVA) &&
756 (!a->wd || vext_check_overlap_mask(s, a->rd, a->vm, false)) &&
757 vext_check_reg(s, a->rd, false) &&
758 vext_check_reg(s, a->rs2, false) &&
759 ((1 << s->sew) <= sizeof(target_ulong)) &&
760 ((1 << s->sew) >= 4));
761}
762
763GEN_VEXT_TRANS(vamoswapw_v, 0, rwdvm, amo_op, amo_check)
764GEN_VEXT_TRANS(vamoaddw_v, 1, rwdvm, amo_op, amo_check)
765GEN_VEXT_TRANS(vamoxorw_v, 2, rwdvm, amo_op, amo_check)
766GEN_VEXT_TRANS(vamoandw_v, 3, rwdvm, amo_op, amo_check)
767GEN_VEXT_TRANS(vamoorw_v, 4, rwdvm, amo_op, amo_check)
768GEN_VEXT_TRANS(vamominw_v, 5, rwdvm, amo_op, amo_check)
769GEN_VEXT_TRANS(vamomaxw_v, 6, rwdvm, amo_op, amo_check)
770GEN_VEXT_TRANS(vamominuw_v, 7, rwdvm, amo_op, amo_check)
771GEN_VEXT_TRANS(vamomaxuw_v, 8, rwdvm, amo_op, amo_check)
772#ifdef TARGET_RISCV64
773GEN_VEXT_TRANS(vamoswapd_v, 9, rwdvm, amo_op, amo_check)
774GEN_VEXT_TRANS(vamoaddd_v, 10, rwdvm, amo_op, amo_check)
775GEN_VEXT_TRANS(vamoxord_v, 11, rwdvm, amo_op, amo_check)
776GEN_VEXT_TRANS(vamoandd_v, 12, rwdvm, amo_op, amo_check)
777GEN_VEXT_TRANS(vamoord_v, 13, rwdvm, amo_op, amo_check)
778GEN_VEXT_TRANS(vamomind_v, 14, rwdvm, amo_op, amo_check)
779GEN_VEXT_TRANS(vamomaxd_v, 15, rwdvm, amo_op, amo_check)
780GEN_VEXT_TRANS(vamominud_v, 16, rwdvm, amo_op, amo_check)
781GEN_VEXT_TRANS(vamomaxud_v, 17, rwdvm, amo_op, amo_check)
782#endif
43740e3a
LZ		 783
784/*
785 *** Vector Integer Arithmetic Instructions
786 */
787#define MAXSZ(s) (s->vlen >> (3 - s->lmul))
788
789static bool opivv_check(DisasContext *s, arg_rmrr *a)
790{
791 return (vext_check_isa_ill(s) &&
792 vext_check_overlap_mask(s, a->rd, a->vm, false) &&
793 vext_check_reg(s, a->rd, false) &&
794 vext_check_reg(s, a->rs2, false) &&
795 vext_check_reg(s, a->rs1, false));
796}
797
798typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
799 uint32_t, uint32_t, uint32_t);
800
801static inline bool
802do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
803 gen_helper_gvec_4_ptr *fn)
804{
805 TCGLabel *over = gen_new_label();
806 if (!opivv_check(s, a)) {
807 return false;
808 }
809
810 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
811
812 if (a->vm && s->vl_eq_vlmax) {
813 gvec_fn(s->sew, vreg_ofs(s, a->rd),
814 vreg_ofs(s, a->rs2), vreg_ofs(s, a->rs1),
815 MAXSZ(s), MAXSZ(s));
816 } else {
817 uint32_t data = 0;
818
819 data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
820 data = FIELD_DP32(data, VDATA, VM, a->vm);
821 data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
822 tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
823 vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
824 cpu_env, 0, s->vlen / 8, data, fn);
825 }
826 gen_set_label(over);
827 return true;
828}
829
830/* OPIVV with GVEC IR */
831#define GEN_OPIVV_GVEC_TRANS(NAME, SUF) \
832static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
833{ \
834 static gen_helper_gvec_4_ptr * const fns[4] = { \
835 gen_helper_##NAME##_b, gen_helper_##NAME##_h, \
836 gen_helper_##NAME##_w, gen_helper_##NAME##_d, \
837 }; \
838 return do_opivv_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \
839}
840
841GEN_OPIVV_GVEC_TRANS(vadd_vv, add)
842GEN_OPIVV_GVEC_TRANS(vsub_vv, sub)
843
844typedef void gen_helper_opivx(TCGv_ptr, TCGv_ptr, TCGv, TCGv_ptr,
845 TCGv_env, TCGv_i32);
846
847static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
848 gen_helper_opivx *fn, DisasContext *s)
849{
850 TCGv_ptr dest, src2, mask;
851 TCGv src1;
852 TCGv_i32 desc;
853 uint32_t data = 0;
854
855 TCGLabel *over = gen_new_label();
856 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
857
858 dest = tcg_temp_new_ptr();
859 mask = tcg_temp_new_ptr();
860 src2 = tcg_temp_new_ptr();
861 src1 = tcg_temp_new();
862 gen_get_gpr(src1, rs1);
863
864 data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
865 data = FIELD_DP32(data, VDATA, VM, vm);
866 data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
867 desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
868
869 tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
870 tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
871 tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
872
873 fn(dest, mask, src1, src2, cpu_env, desc);
874
875 tcg_temp_free_ptr(dest);
876 tcg_temp_free_ptr(mask);
877 tcg_temp_free_ptr(src2);
878 tcg_temp_free(src1);
879 tcg_temp_free_i32(desc);
880 gen_set_label(over);
881 return true;
882}
883
884static bool opivx_check(DisasContext *s, arg_rmrr *a)
885{
886 return (vext_check_isa_ill(s) &&
887 vext_check_overlap_mask(s, a->rd, a->vm, false) &&
888 vext_check_reg(s, a->rd, false) &&
889 vext_check_reg(s, a->rs2, false));
890}
891
892typedef void GVecGen2sFn(unsigned, uint32_t, uint32_t, TCGv_i64,
893 uint32_t, uint32_t);
894
895static inline bool
896do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn *gvec_fn,
897 gen_helper_opivx *fn)
898{
899 if (!opivx_check(s, a)) {
900 return false;
901 }
902
903 if (a->vm && s->vl_eq_vlmax) {
904 TCGv_i64 src1 = tcg_temp_new_i64();
905 TCGv tmp = tcg_temp_new();
906
907 gen_get_gpr(tmp, a->rs1);
908 tcg_gen_ext_tl_i64(src1, tmp);
909 gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
910 src1, MAXSZ(s), MAXSZ(s));
911
912 tcg_temp_free_i64(src1);
913 tcg_temp_free(tmp);
914 return true;
915 }
916 return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
917}
918
919/* OPIVX with GVEC IR */
920#define GEN_OPIVX_GVEC_TRANS(NAME, SUF) \
921static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
922{ \
923 static gen_helper_opivx * const fns[4] = { \
924 gen_helper_##NAME##_b, gen_helper_##NAME##_h, \
925 gen_helper_##NAME##_w, gen_helper_##NAME##_d, \
926 }; \
927 return do_opivx_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \
928}
929
930GEN_OPIVX_GVEC_TRANS(vadd_vx, adds)
931GEN_OPIVX_GVEC_TRANS(vsub_vx, subs)
932
933static void gen_vec_rsub8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
934{
935 tcg_gen_vec_sub8_i64(d, b, a);
936}
937
938static void gen_vec_rsub16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
939{
940 tcg_gen_vec_sub8_i64(d, b, a);
941}
942
943static void gen_rsub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
944{
945 tcg_gen_sub_i32(ret, arg2, arg1);
946}
947
948static void gen_rsub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
949{
950 tcg_gen_sub_i64(ret, arg2, arg1);
951}
952
953static void gen_rsub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
954{
955 tcg_gen_sub_vec(vece, r, b, a);
956}
957
958static void tcg_gen_gvec_rsubs(unsigned vece, uint32_t dofs, uint32_t aofs,
959 TCGv_i64 c, uint32_t oprsz, uint32_t maxsz)
960{
961 static const GVecGen2s rsub_op[4] = {
962 { .fni8 = gen_vec_rsub8_i64,
963 .fniv = gen_rsub_vec,
964 .fno = gen_helper_vec_rsubs8,
965 .vece = MO_8 },
966 { .fni8 = gen_vec_rsub16_i64,
967 .fniv = gen_rsub_vec,
968 .fno = gen_helper_vec_rsubs16,
969 .vece = MO_16 },
970 { .fni4 = gen_rsub_i32,
971 .fniv = gen_rsub_vec,
972 .fno = gen_helper_vec_rsubs32,
973 .vece = MO_32 },
974 { .fni8 = gen_rsub_i64,
975 .fniv = gen_rsub_vec,
976 .fno = gen_helper_vec_rsubs64,
977 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
978 .vece = MO_64 },
979 };
980
981 tcg_debug_assert(vece <= MO_64);
982 tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, c, &rsub_op[vece]);
983}
984
985GEN_OPIVX_GVEC_TRANS(vrsub_vx, rsubs)
986
987static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
988 gen_helper_opivx *fn, DisasContext *s, int zx)
989{
990 TCGv_ptr dest, src2, mask;
991 TCGv src1;
992 TCGv_i32 desc;
993 uint32_t data = 0;
994
995 TCGLabel *over = gen_new_label();
996 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
997
998 dest = tcg_temp_new_ptr();
999 mask = tcg_temp_new_ptr();
1000 src2 = tcg_temp_new_ptr();
1001 if (zx) {
1002 src1 = tcg_const_tl(imm);
1003 } else {
1004 src1 = tcg_const_tl(sextract64(imm, 0, 5));
1005 }
1006 data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
1007 data = FIELD_DP32(data, VDATA, VM, vm);
1008 data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
1009 desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
1010
1011 tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
1012 tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
1013 tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
1014
1015 fn(dest, mask, src1, src2, cpu_env, desc);
1016
1017 tcg_temp_free_ptr(dest);
1018 tcg_temp_free_ptr(mask);
1019 tcg_temp_free_ptr(src2);
1020 tcg_temp_free(src1);
1021 tcg_temp_free_i32(desc);
1022 gen_set_label(over);
1023 return true;
1024}
1025
1026typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t,
1027 uint32_t, uint32_t);
1028
1029static inline bool
1030do_opivi_gvec(DisasContext *s, arg_rmrr *a, GVecGen2iFn *gvec_fn,
1031 gen_helper_opivx *fn, int zx)
1032{
1033 if (!opivx_check(s, a)) {
1034 return false;
1035 }
1036
1037 if (a->vm && s->vl_eq_vlmax) {
1038 if (zx) {
1039 gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
1040 extract64(a->rs1, 0, 5), MAXSZ(s), MAXSZ(s));
1041 } else {
1042 gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
1043 sextract64(a->rs1, 0, 5), MAXSZ(s), MAXSZ(s));
1044 }
1045 } else {
1046 return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, zx);
1047 }
1048 return true;
1049}
1050
1051/* OPIVI with GVEC IR */
1052#define GEN_OPIVI_GVEC_TRANS(NAME, ZX, OPIVX, SUF) \
1053static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
1054{ \
1055 static gen_helper_opivx * const fns[4] = { \
1056 gen_helper_##OPIVX##_b, gen_helper_##OPIVX##_h, \
1057 gen_helper_##OPIVX##_w, gen_helper_##OPIVX##_d, \
1058 }; \
1059 return do_opivi_gvec(s, a, tcg_gen_gvec_##SUF, \
1060 fns[s->sew], ZX); \
1061}
1062
1063GEN_OPIVI_GVEC_TRANS(vadd_vi, 0, vadd_vx, addi)
1064
1065static void tcg_gen_gvec_rsubi(unsigned vece, uint32_t dofs, uint32_t aofs,
1066 int64_t c, uint32_t oprsz, uint32_t maxsz)
1067{
1068 TCGv_i64 tmp = tcg_const_i64(c);
1069 tcg_gen_gvec_rsubs(vece, dofs, aofs, tmp, oprsz, maxsz);
1070 tcg_temp_free_i64(tmp);
1071}
1072
1073GEN_OPIVI_GVEC_TRANS(vrsub_vi, 0, vrsub_vx, rsubi)
8fcdf776
LZ		 1074
1075/* Vector Widening Integer Add/Subtract */
1076
1077/* OPIVV with WIDEN */
1078static bool opivv_widen_check(DisasContext *s, arg_rmrr *a)
1079{
1080 return (vext_check_isa_ill(s) &&
1081 vext_check_overlap_mask(s, a->rd, a->vm, true) &&
1082 vext_check_reg(s, a->rd, true) &&
1083 vext_check_reg(s, a->rs2, false) &&
1084 vext_check_reg(s, a->rs1, false) &&
1085 vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2,
1086 1 << s->lmul) &&
1087 vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1,
1088 1 << s->lmul) &&
1089 (s->lmul < 0x3) && (s->sew < 0x3));
1090}
1091
1092static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
1093 gen_helper_gvec_4_ptr *fn,
1094 bool (*checkfn)(DisasContext *, arg_rmrr *))
1095{
1096 if (checkfn(s, a)) {
1097 uint32_t data = 0;
1098 TCGLabel *over = gen_new_label();
1099 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
1100
1101 data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
1102 data = FIELD_DP32(data, VDATA, VM, a->vm);
1103 data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
1104 tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
1105 vreg_ofs(s, a->rs1),
1106 vreg_ofs(s, a->rs2),
1107 cpu_env, 0, s->vlen / 8,
1108 data, fn);
1109 gen_set_label(over);
1110 return true;
1111 }
1112 return false;
1113}
1114
1115#define GEN_OPIVV_WIDEN_TRANS(NAME, CHECK) \
1116static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
1117{ \
1118 static gen_helper_gvec_4_ptr * const fns[3] = { \
1119 gen_helper_##NAME##_b, \
1120 gen_helper_##NAME##_h, \
1121 gen_helper_##NAME##_w \
1122 }; \
1123 return do_opivv_widen(s, a, fns[s->sew], CHECK); \
1124}
1125
1126GEN_OPIVV_WIDEN_TRANS(vwaddu_vv, opivv_widen_check)
1127GEN_OPIVV_WIDEN_TRANS(vwadd_vv, opivv_widen_check)
1128GEN_OPIVV_WIDEN_TRANS(vwsubu_vv, opivv_widen_check)
1129GEN_OPIVV_WIDEN_TRANS(vwsub_vv, opivv_widen_check)
1130
1131/* OPIVX with WIDEN */
1132static bool opivx_widen_check(DisasContext *s, arg_rmrr *a)
1133{
1134 return (vext_check_isa_ill(s) &&
1135 vext_check_overlap_mask(s, a->rd, a->vm, true) &&
1136 vext_check_reg(s, a->rd, true) &&
1137 vext_check_reg(s, a->rs2, false) &&
1138 vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2,
1139 1 << s->lmul) &&
1140 (s->lmul < 0x3) && (s->sew < 0x3));
1141}
1142
1143static bool do_opivx_widen(DisasContext *s, arg_rmrr *a,
1144 gen_helper_opivx *fn)
1145{
1146 if (opivx_widen_check(s, a)) {
1147 return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
1148 }
1149 return true;
1150}
1151
1152#define GEN_OPIVX_WIDEN_TRANS(NAME) \
1153static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
1154{ \
1155 static gen_helper_opivx * const fns[3] = { \
1156 gen_helper_##NAME##_b, \
1157 gen_helper_##NAME##_h, \
1158 gen_helper_##NAME##_w \
1159 }; \
1160 return do_opivx_widen(s, a, fns[s->sew]); \
1161}
1162
1163GEN_OPIVX_WIDEN_TRANS(vwaddu_vx)
1164GEN_OPIVX_WIDEN_TRANS(vwadd_vx)
1165GEN_OPIVX_WIDEN_TRANS(vwsubu_vx)
1166GEN_OPIVX_WIDEN_TRANS(vwsub_vx)
1167
1168/* WIDEN OPIVV with WIDEN */
1169static bool opiwv_widen_check(DisasContext *s, arg_rmrr *a)
1170{
1171 return (vext_check_isa_ill(s) &&
1172 vext_check_overlap_mask(s, a->rd, a->vm, true) &&
1173 vext_check_reg(s, a->rd, true) &&
1174 vext_check_reg(s, a->rs2, true) &&
1175 vext_check_reg(s, a->rs1, false) &&
1176 vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1,
1177 1 << s->lmul) &&
1178 (s->lmul < 0x3) && (s->sew < 0x3));
1179}
1180
1181static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
1182 gen_helper_gvec_4_ptr *fn)
1183{
1184 if (opiwv_widen_check(s, a)) {
1185 uint32_t data = 0;
1186 TCGLabel *over = gen_new_label();
1187 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
1188
1189 data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
1190 data = FIELD_DP32(data, VDATA, VM, a->vm);
1191 data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
1192 tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
1193 vreg_ofs(s, a->rs1),
1194 vreg_ofs(s, a->rs2),
1195 cpu_env, 0, s->vlen / 8, data, fn);
1196 gen_set_label(over);
1197 return true;
1198 }
1199 return false;
1200}
1201
1202#define GEN_OPIWV_WIDEN_TRANS(NAME) \
1203static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
1204{ \
1205 static gen_helper_gvec_4_ptr * const fns[3] = { \
1206 gen_helper_##NAME##_b, \
1207 gen_helper_##NAME##_h, \
1208 gen_helper_##NAME##_w \
1209 }; \
1210 return do_opiwv_widen(s, a, fns[s->sew]); \
1211}
1212
1213GEN_OPIWV_WIDEN_TRANS(vwaddu_wv)
1214GEN_OPIWV_WIDEN_TRANS(vwadd_wv)
1215GEN_OPIWV_WIDEN_TRANS(vwsubu_wv)
1216GEN_OPIWV_WIDEN_TRANS(vwsub_wv)
1217
1218/* WIDEN OPIVX with WIDEN */
1219static bool opiwx_widen_check(DisasContext *s, arg_rmrr *a)
1220{
1221 return (vext_check_isa_ill(s) &&
1222 vext_check_overlap_mask(s, a->rd, a->vm, true) &&
1223 vext_check_reg(s, a->rd, true) &&
1224 vext_check_reg(s, a->rs2, true) &&
1225 (s->lmul < 0x3) && (s->sew < 0x3));
1226}
1227
1228static bool do_opiwx_widen(DisasContext *s, arg_rmrr *a,
1229 gen_helper_opivx *fn)
1230{
1231 if (opiwx_widen_check(s, a)) {
1232 return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
1233 }
1234 return false;
1235}
1236
1237#define GEN_OPIWX_WIDEN_TRANS(NAME) \
1238static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
1239{ \
1240 static gen_helper_opivx * const fns[3] = { \
1241 gen_helper_##NAME##_b, \
1242 gen_helper_##NAME##_h, \
1243 gen_helper_##NAME##_w \
1244 }; \
1245 return do_opiwx_widen(s, a, fns[s->sew]); \
1246}
1247
1248GEN_OPIWX_WIDEN_TRANS(vwaddu_wx)
1249GEN_OPIWX_WIDEN_TRANS(vwadd_wx)
1250GEN_OPIWX_WIDEN_TRANS(vwsubu_wx)
1251GEN_OPIWX_WIDEN_TRANS(vwsub_wx)
3a6f8f68
LZ		 1252
1253/* Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions */
1254/* OPIVV without GVEC IR */
1255#define GEN_OPIVV_TRANS(NAME, CHECK) \
1256static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
1257{ \
1258 if (CHECK(s, a)) { \
1259 uint32_t data = 0; \
1260 static gen_helper_gvec_4_ptr * const fns[4] = { \
1261 gen_helper_##NAME##_b, gen_helper_##NAME##_h, \
1262 gen_helper_##NAME##_w, gen_helper_##NAME##_d, \
1263 }; \
1264 TCGLabel *over = gen_new_label(); \
1265 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
1266 \
1267 data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
1268 data = FIELD_DP32(data, VDATA, VM, a->vm); \
1269 data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
1270 tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
1271 vreg_ofs(s, a->rs1), \
1272 vreg_ofs(s, a->rs2), cpu_env, 0, \
1273 s->vlen / 8, data, fns[s->sew]); \
1274 gen_set_label(over); \
1275 return true; \
1276 } \
1277 return false; \
1278}
1279
1280/*
1281 * For vadc and vsbc, an illegal instruction exception is raised if the
1282 * destination vector register is v0 and LMUL > 1. (Section 12.3)
1283 */
1284static bool opivv_vadc_check(DisasContext *s, arg_rmrr *a)
1285{
1286 return (vext_check_isa_ill(s) &&
1287 vext_check_reg(s, a->rd, false) &&
1288 vext_check_reg(s, a->rs2, false) &&
1289 vext_check_reg(s, a->rs1, false) &&
1290 ((a->rd != 0) || (s->lmul == 0)));
1291}
1292
1293GEN_OPIVV_TRANS(vadc_vvm, opivv_vadc_check)
1294GEN_OPIVV_TRANS(vsbc_vvm, opivv_vadc_check)
1295
1296/*
1297 * For vmadc and vmsbc, an illegal instruction exception is raised if the
1298 * destination vector register overlaps a source vector register group.
1299 */
1300static bool opivv_vmadc_check(DisasContext *s, arg_rmrr *a)
1301{
1302 return (vext_check_isa_ill(s) &&
1303 vext_check_reg(s, a->rs2, false) &&
1304 vext_check_reg(s, a->rs1, false) &&
1305 vext_check_overlap_group(a->rd, 1, a->rs1, 1 << s->lmul) &&
1306 vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul));
1307}
1308
1309GEN_OPIVV_TRANS(vmadc_vvm, opivv_vmadc_check)
1310GEN_OPIVV_TRANS(vmsbc_vvm, opivv_vmadc_check)
1311
1312static bool opivx_vadc_check(DisasContext *s, arg_rmrr *a)
1313{
1314 return (vext_check_isa_ill(s) &&
1315 vext_check_reg(s, a->rd, false) &&
1316 vext_check_reg(s, a->rs2, false) &&
1317 ((a->rd != 0) || (s->lmul == 0)));
1318}
1319
1320/* OPIVX without GVEC IR */
1321#define GEN_OPIVX_TRANS(NAME, CHECK) \
1322static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
1323{ \
1324 if (CHECK(s, a)) { \
1325 static gen_helper_opivx * const fns[4] = { \
1326 gen_helper_##NAME##_b, gen_helper_##NAME##_h, \
1327 gen_helper_##NAME##_w, gen_helper_##NAME##_d, \
1328 }; \
1329 \
1330 return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s);\
1331 } \
1332 return false; \
1333}
1334
1335GEN_OPIVX_TRANS(vadc_vxm, opivx_vadc_check)
1336GEN_OPIVX_TRANS(vsbc_vxm, opivx_vadc_check)
1337
1338static bool opivx_vmadc_check(DisasContext *s, arg_rmrr *a)
1339{
1340 return (vext_check_isa_ill(s) &&
1341 vext_check_reg(s, a->rs2, false) &&
1342 vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul));
1343}
1344
1345GEN_OPIVX_TRANS(vmadc_vxm, opivx_vmadc_check)
1346GEN_OPIVX_TRANS(vmsbc_vxm, opivx_vmadc_check)
1347
1348/* OPIVI without GVEC IR */
1349#define GEN_OPIVI_TRANS(NAME, ZX, OPIVX, CHECK) \
1350static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
1351{ \
1352 if (CHECK(s, a)) { \
1353 static gen_helper_opivx * const fns[4] = { \
1354 gen_helper_##OPIVX##_b, gen_helper_##OPIVX##_h, \
1355 gen_helper_##OPIVX##_w, gen_helper_##OPIVX##_d, \
1356 }; \
1357 return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, \
1358 fns[s->sew], s, ZX); \
1359 } \
1360 return false; \
1361}
1362
1363GEN_OPIVI_TRANS(vadc_vim, 0, vadc_vxm, opivx_vadc_check)
1364GEN_OPIVI_TRANS(vmadc_vim, 0, vmadc_vxm, opivx_vmadc_check)
d3842924
LZ		 1365
1366/* Vector Bitwise Logical Instructions */
1367GEN_OPIVV_GVEC_TRANS(vand_vv, and)
1368GEN_OPIVV_GVEC_TRANS(vor_vv, or)
1369GEN_OPIVV_GVEC_TRANS(vxor_vv, xor)
1370GEN_OPIVX_GVEC_TRANS(vand_vx, ands)
1371GEN_OPIVX_GVEC_TRANS(vor_vx, ors)
1372GEN_OPIVX_GVEC_TRANS(vxor_vx, xors)
1373GEN_OPIVI_GVEC_TRANS(vand_vi, 0, vand_vx, andi)
1374GEN_OPIVI_GVEC_TRANS(vor_vi, 0, vor_vx, ori)
1375GEN_OPIVI_GVEC_TRANS(vxor_vi, 0, vxor_vx, xori)
3277d955
LZ		 1376
1377/* Vector Single-Width Bit Shift Instructions */
1378GEN_OPIVV_GVEC_TRANS(vsll_vv, shlv)
1379GEN_OPIVV_GVEC_TRANS(vsrl_vv, shrv)
1380GEN_OPIVV_GVEC_TRANS(vsra_vv, sarv)
1381
1382typedef void GVecGen2sFn32(unsigned, uint32_t, uint32_t, TCGv_i32,
1383 uint32_t, uint32_t);
1384
1385static inline bool
1386do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a, GVecGen2sFn32 *gvec_fn,
1387 gen_helper_opivx *fn)
1388{
1389 if (!opivx_check(s, a)) {
1390 return false;
1391 }
1392
1393 if (a->vm && s->vl_eq_vlmax) {
1394 TCGv_i32 src1 = tcg_temp_new_i32();
1395 TCGv tmp = tcg_temp_new();
1396
1397 gen_get_gpr(tmp, a->rs1);
1398 tcg_gen_trunc_tl_i32(src1, tmp);
1399 tcg_gen_extract_i32(src1, src1, 0, s->sew + 3);
1400 gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
1401 src1, MAXSZ(s), MAXSZ(s));
1402
1403 tcg_temp_free_i32(src1);
1404 tcg_temp_free(tmp);
1405 return true;
1406 }
1407 return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
1408}
1409
1410#define GEN_OPIVX_GVEC_SHIFT_TRANS(NAME, SUF) \
1411static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
1412{ \
1413 static gen_helper_opivx * const fns[4] = { \
1414 gen_helper_##NAME##_b, gen_helper_##NAME##_h, \
1415 gen_helper_##NAME##_w, gen_helper_##NAME##_d, \
1416 }; \
1417 \
1418 return do_opivx_gvec_shift(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \
1419}
1420
1421GEN_OPIVX_GVEC_SHIFT_TRANS(vsll_vx, shls)
1422GEN_OPIVX_GVEC_SHIFT_TRANS(vsrl_vx, shrs)
1423GEN_OPIVX_GVEC_SHIFT_TRANS(vsra_vx, sars)
1424
1425GEN_OPIVI_GVEC_TRANS(vsll_vi, 1, vsll_vx, shli)
1426GEN_OPIVI_GVEC_TRANS(vsrl_vi, 1, vsrl_vx, shri)
1427GEN_OPIVI_GVEC_TRANS(vsra_vi, 1, vsra_vx, sari)
7689b028
LZ		 1428
1429/* Vector Narrowing Integer Right Shift Instructions */
1430static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a)
1431{
1432 return (vext_check_isa_ill(s) &&
1433 vext_check_overlap_mask(s, a->rd, a->vm, false) &&
1434 vext_check_reg(s, a->rd, false) &&
1435 vext_check_reg(s, a->rs2, true) &&
1436 vext_check_reg(s, a->rs1, false) &&
1437 vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2,
1438 2 << s->lmul) &&
1439 (s->lmul < 0x3) && (s->sew < 0x3));
1440}
1441
1442/* OPIVV with NARROW */
1443#define GEN_OPIVV_NARROW_TRANS(NAME) \
1444static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
1445{ \
1446 if (opivv_narrow_check(s, a)) { \
1447 uint32_t data = 0; \
1448 static gen_helper_gvec_4_ptr * const fns[3] = { \
1449 gen_helper_##NAME##_b, \
1450 gen_helper_##NAME##_h, \
1451 gen_helper_##NAME##_w, \
1452 }; \
1453 TCGLabel *over = gen_new_label(); \
1454 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
1455 \
1456 data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
1457 data = FIELD_DP32(data, VDATA, VM, a->vm); \
1458 data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
1459 tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
1460 vreg_ofs(s, a->rs1), \
1461 vreg_ofs(s, a->rs2), cpu_env, 0, \
1462 s->vlen / 8, data, fns[s->sew]); \
1463 gen_set_label(over); \
1464 return true; \
1465 } \
1466 return false; \
1467}
1468GEN_OPIVV_NARROW_TRANS(vnsra_vv)
1469GEN_OPIVV_NARROW_TRANS(vnsrl_vv)
1470
1471static bool opivx_narrow_check(DisasContext *s, arg_rmrr *a)
1472{
1473 return (vext_check_isa_ill(s) &&
1474 vext_check_overlap_mask(s, a->rd, a->vm, false) &&
1475 vext_check_reg(s, a->rd, false) &&
1476 vext_check_reg(s, a->rs2, true) &&
1477 vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2,
1478 2 << s->lmul) &&
1479 (s->lmul < 0x3) && (s->sew < 0x3));
1480}
1481
1482/* OPIVX with NARROW */
1483#define GEN_OPIVX_NARROW_TRANS(NAME) \
1484static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
1485{ \
1486 if (opivx_narrow_check(s, a)) { \
1487 static gen_helper_opivx * const fns[3] = { \
1488 gen_helper_##NAME##_b, \
1489 gen_helper_##NAME##_h, \
1490 gen_helper_##NAME##_w, \
1491 }; \
1492 return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s);\
1493 } \
1494 return false; \
1495}
1496
1497GEN_OPIVX_NARROW_TRANS(vnsra_vx)
1498GEN_OPIVX_NARROW_TRANS(vnsrl_vx)
1499
1500/* OPIVI with NARROW */
1501#define GEN_OPIVI_NARROW_TRANS(NAME, ZX, OPIVX) \
1502static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
1503{ \
1504 if (opivx_narrow_check(s, a)) { \
1505 static gen_helper_opivx * const fns[3] = { \
1506 gen_helper_##OPIVX##_b, \
1507 gen_helper_##OPIVX##_h, \
1508 gen_helper_##OPIVX##_w, \
1509 }; \
1510 return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, \
1511 fns[s->sew], s, ZX); \
1512 } \
1513 return false; \
1514}
1515
1516GEN_OPIVI_NARROW_TRANS(vnsra_vi, 1, vnsra_vx)
1517GEN_OPIVI_NARROW_TRANS(vnsrl_vi, 1, vnsrl_vx)
1366fc79
LZ		 1518
1519/* Vector Integer Comparison Instructions */
1520/*
1521 * For all comparison instructions, an illegal instruction exception is raised
1522 * if the destination vector register overlaps a source vector register group
1523 * and LMUL > 1.
1524 */
1525static bool opivv_cmp_check(DisasContext *s, arg_rmrr *a)
1526{
1527 return (vext_check_isa_ill(s) &&
1528 vext_check_reg(s, a->rs2, false) &&
1529 vext_check_reg(s, a->rs1, false) &&
1530 ((vext_check_overlap_group(a->rd, 1, a->rs1, 1 << s->lmul) &&
1531 vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul)) ||
1532 (s->lmul == 0)));
1533}
1534GEN_OPIVV_TRANS(vmseq_vv, opivv_cmp_check)
1535GEN_OPIVV_TRANS(vmsne_vv, opivv_cmp_check)
1536GEN_OPIVV_TRANS(vmsltu_vv, opivv_cmp_check)
1537GEN_OPIVV_TRANS(vmslt_vv, opivv_cmp_check)
1538GEN_OPIVV_TRANS(vmsleu_vv, opivv_cmp_check)
1539GEN_OPIVV_TRANS(vmsle_vv, opivv_cmp_check)
1540
1541static bool opivx_cmp_check(DisasContext *s, arg_rmrr *a)
1542{
1543 return (vext_check_isa_ill(s) &&
1544 vext_check_reg(s, a->rs2, false) &&
1545 (vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul) ||
1546 (s->lmul == 0)));
1547}
1548
1549GEN_OPIVX_TRANS(vmseq_vx, opivx_cmp_check)
1550GEN_OPIVX_TRANS(vmsne_vx, opivx_cmp_check)
1551GEN_OPIVX_TRANS(vmsltu_vx, opivx_cmp_check)
1552GEN_OPIVX_TRANS(vmslt_vx, opivx_cmp_check)
1553GEN_OPIVX_TRANS(vmsleu_vx, opivx_cmp_check)
1554GEN_OPIVX_TRANS(vmsle_vx, opivx_cmp_check)
1555GEN_OPIVX_TRANS(vmsgtu_vx, opivx_cmp_check)
1556GEN_OPIVX_TRANS(vmsgt_vx, opivx_cmp_check)
1557
1558GEN_OPIVI_TRANS(vmseq_vi, 0, vmseq_vx, opivx_cmp_check)
1559GEN_OPIVI_TRANS(vmsne_vi, 0, vmsne_vx, opivx_cmp_check)
1560GEN_OPIVI_TRANS(vmsleu_vi, 1, vmsleu_vx, opivx_cmp_check)
1561GEN_OPIVI_TRANS(vmsle_vi, 0, vmsle_vx, opivx_cmp_check)
1562GEN_OPIVI_TRANS(vmsgtu_vi, 1, vmsgtu_vx, opivx_cmp_check)
1563GEN_OPIVI_TRANS(vmsgt_vi, 0, vmsgt_vx, opivx_cmp_check)
558fa779
LZ		 1564
1565/* Vector Integer Min/Max Instructions */
1566GEN_OPIVV_GVEC_TRANS(vminu_vv, umin)
1567GEN_OPIVV_GVEC_TRANS(vmin_vv, smin)
1568GEN_OPIVV_GVEC_TRANS(vmaxu_vv, umax)
1569GEN_OPIVV_GVEC_TRANS(vmax_vv, smax)
1570GEN_OPIVX_TRANS(vminu_vx, opivx_check)
1571GEN_OPIVX_TRANS(vmin_vx, opivx_check)
1572GEN_OPIVX_TRANS(vmaxu_vx, opivx_check)
1573GEN_OPIVX_TRANS(vmax_vx, opivx_check)
958b85f3
LZ		 1574
1575/* Vector Single-Width Integer Multiply Instructions */
1576GEN_OPIVV_GVEC_TRANS(vmul_vv, mul)
1577GEN_OPIVV_TRANS(vmulh_vv, opivv_check)
1578GEN_OPIVV_TRANS(vmulhu_vv, opivv_check)
1579GEN_OPIVV_TRANS(vmulhsu_vv, opivv_check)
1580GEN_OPIVX_GVEC_TRANS(vmul_vx, muls)
1581GEN_OPIVX_TRANS(vmulh_vx, opivx_check)
1582GEN_OPIVX_TRANS(vmulhu_vx, opivx_check)
1583GEN_OPIVX_TRANS(vmulhsu_vx, opivx_check)
85e6658c
LZ		 1584
1585/* Vector Integer Divide Instructions */
1586GEN_OPIVV_TRANS(vdivu_vv, opivv_check)
1587GEN_OPIVV_TRANS(vdiv_vv, opivv_check)
1588GEN_OPIVV_TRANS(vremu_vv, opivv_check)
1589GEN_OPIVV_TRANS(vrem_vv, opivv_check)
1590GEN_OPIVX_TRANS(vdivu_vx, opivx_check)
1591GEN_OPIVX_TRANS(vdiv_vx, opivx_check)
1592GEN_OPIVX_TRANS(vremu_vx, opivx_check)
1593GEN_OPIVX_TRANS(vrem_vx, opivx_check)
97b1cba3
LZ		 1594
1595/* Vector Widening Integer Multiply Instructions */
1596GEN_OPIVV_WIDEN_TRANS(vwmul_vv, opivv_widen_check)
1597GEN_OPIVV_WIDEN_TRANS(vwmulu_vv, opivv_widen_check)
1598GEN_OPIVV_WIDEN_TRANS(vwmulsu_vv, opivv_widen_check)
1599GEN_OPIVX_WIDEN_TRANS(vwmul_vx)
1600GEN_OPIVX_WIDEN_TRANS(vwmulu_vx)
1601GEN_OPIVX_WIDEN_TRANS(vwmulsu_vx)
54df813a
LZ		 1602
1603/* Vector Single-Width Integer Multiply-Add Instructions */
1604GEN_OPIVV_TRANS(vmacc_vv, opivv_check)
1605GEN_OPIVV_TRANS(vnmsac_vv, opivv_check)
1606GEN_OPIVV_TRANS(vmadd_vv, opivv_check)
1607GEN_OPIVV_TRANS(vnmsub_vv, opivv_check)
1608GEN_OPIVX_TRANS(vmacc_vx, opivx_check)
1609GEN_OPIVX_TRANS(vnmsac_vx, opivx_check)
1610GEN_OPIVX_TRANS(vmadd_vx, opivx_check)
1611GEN_OPIVX_TRANS(vnmsub_vx, opivx_check)
2b587b33
LZ		 1612
1613/* Vector Widening Integer Multiply-Add Instructions */
1614GEN_OPIVV_WIDEN_TRANS(vwmaccu_vv, opivv_widen_check)
1615GEN_OPIVV_WIDEN_TRANS(vwmacc_vv, opivv_widen_check)
1616GEN_OPIVV_WIDEN_TRANS(vwmaccsu_vv, opivv_widen_check)
1617GEN_OPIVX_WIDEN_TRANS(vwmaccu_vx)
1618GEN_OPIVX_WIDEN_TRANS(vwmacc_vx)
1619GEN_OPIVX_WIDEN_TRANS(vwmaccsu_vx)
1620GEN_OPIVX_WIDEN_TRANS(vwmaccus_vx)
f020a7a1
LZ		 1621
1622/* Vector Integer Merge and Move Instructions */
1623static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
1624{
1625 if (vext_check_isa_ill(s) &&
1626 vext_check_reg(s, a->rd, false) &&
1627 vext_check_reg(s, a->rs1, false)) {
1628
1629 if (s->vl_eq_vlmax) {
1630 tcg_gen_gvec_mov(s->sew, vreg_ofs(s, a->rd),
1631 vreg_ofs(s, a->rs1),
1632 MAXSZ(s), MAXSZ(s));
1633 } else {
1634 uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
1635 static gen_helper_gvec_2_ptr * const fns[4] = {
1636 gen_helper_vmv_v_v_b, gen_helper_vmv_v_v_h,
1637 gen_helper_vmv_v_v_w, gen_helper_vmv_v_v_d,
1638 };
1639 TCGLabel *over = gen_new_label();
1640 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
1641
1642 tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
1643 cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
1644 gen_set_label(over);
1645 }
1646 return true;
1647 }
1648 return false;
1649}
1650
1651typedef void gen_helper_vmv_vx(TCGv_ptr, TCGv_i64, TCGv_env, TCGv_i32);
1652static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
1653{
1654 if (vext_check_isa_ill(s) &&
1655 vext_check_reg(s, a->rd, false)) {
1656
1657 TCGv s1;
1658 TCGLabel *over = gen_new_label();
1659 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
1660
1661 s1 = tcg_temp_new();
1662 gen_get_gpr(s1, a->rs1);
1663
1664 if (s->vl_eq_vlmax) {
1665 tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd),
1666 MAXSZ(s), MAXSZ(s), s1);
1667 } else {
1668 TCGv_i32 desc ;
1669 TCGv_i64 s1_i64 = tcg_temp_new_i64();
1670 TCGv_ptr dest = tcg_temp_new_ptr();
1671 uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
1672 static gen_helper_vmv_vx * const fns[4] = {
1673 gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h,
1674 gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d,
1675 };
1676
1677 tcg_gen_ext_tl_i64(s1_i64, s1);
1678 desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
1679 tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
1680 fns[s->sew](dest, s1_i64, cpu_env, desc);
1681
1682 tcg_temp_free_ptr(dest);
1683 tcg_temp_free_i32(desc);
1684 tcg_temp_free_i64(s1_i64);
1685 }
1686
1687 tcg_temp_free(s1);
1688 gen_set_label(over);
1689 return true;
1690 }
1691 return false;
1692}
1693
1694static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
1695{
1696 if (vext_check_isa_ill(s) &&
1697 vext_check_reg(s, a->rd, false)) {
1698
1699 int64_t simm = sextract64(a->rs1, 0, 5);
1700 if (s->vl_eq_vlmax) {
1701 tcg_gen_gvec_dup_imm(s->sew, vreg_ofs(s, a->rd),
1702 MAXSZ(s), MAXSZ(s), simm);
1703 } else {
1704 TCGv_i32 desc;
1705 TCGv_i64 s1;
1706 TCGv_ptr dest;
1707 uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
1708 static gen_helper_vmv_vx * const fns[4] = {
1709 gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h,
1710 gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d,
1711 };
1712 TCGLabel *over = gen_new_label();
1713 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
1714
1715 s1 = tcg_const_i64(simm);
1716 dest = tcg_temp_new_ptr();
1717 desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
1718 tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
1719 fns[s->sew](dest, s1, cpu_env, desc);
1720
1721 tcg_temp_free_ptr(dest);
1722 tcg_temp_free_i32(desc);
1723 tcg_temp_free_i64(s1);
1724 gen_set_label(over);
1725 }
1726 return true;
1727 }
1728 return false;
1729}
1730
1731GEN_OPIVV_TRANS(vmerge_vvm, opivv_vadc_check)
1732GEN_OPIVX_TRANS(vmerge_vxm, opivx_vadc_check)
1733GEN_OPIVI_TRANS(vmerge_vim, 0, vmerge_vxm, opivx_vadc_check)
eb2650e3
LZ		 1734
1735/*
1736 *** Vector Fixed-Point Arithmetic Instructions
1737 */
1738
1739/* Vector Single-Width Saturating Add and Subtract */
1740GEN_OPIVV_TRANS(vsaddu_vv, opivv_check)
1741GEN_OPIVV_TRANS(vsadd_vv, opivv_check)
1742GEN_OPIVV_TRANS(vssubu_vv, opivv_check)
1743GEN_OPIVV_TRANS(vssub_vv, opivv_check)
1744GEN_OPIVX_TRANS(vsaddu_vx, opivx_check)
1745GEN_OPIVX_TRANS(vsadd_vx, opivx_check)
1746GEN_OPIVX_TRANS(vssubu_vx, opivx_check)
1747GEN_OPIVX_TRANS(vssub_vx, opivx_check)
1748GEN_OPIVI_TRANS(vsaddu_vi, 1, vsaddu_vx, opivx_check)
1749GEN_OPIVI_TRANS(vsadd_vi, 0, vsadd_vx, opivx_check)
b7aee481
LZ		 1750
1751/* Vector Single-Width Averaging Add and Subtract */
1752GEN_OPIVV_TRANS(vaadd_vv, opivv_check)
1753GEN_OPIVV_TRANS(vasub_vv, opivv_check)
1754GEN_OPIVX_TRANS(vaadd_vx, opivx_check)
1755GEN_OPIVX_TRANS(vasub_vx, opivx_check)
1756GEN_OPIVI_TRANS(vaadd_vi, 0, vaadd_vx, opivx_check)
9f0ff9e5
LZ		 1757
1758/* Vector Single-Width Fractional Multiply with Rounding and Saturation */
1759GEN_OPIVV_TRANS(vsmul_vv, opivv_check)
1760GEN_OPIVX_TRANS(vsmul_vx, opivx_check)
0a1eaf00
LZ		 1761
1762/* Vector Widening Saturating Scaled Multiply-Add */
1763GEN_OPIVV_WIDEN_TRANS(vwsmaccu_vv, opivv_widen_check)
1764GEN_OPIVV_WIDEN_TRANS(vwsmacc_vv, opivv_widen_check)
1765GEN_OPIVV_WIDEN_TRANS(vwsmaccsu_vv, opivv_widen_check)
1766GEN_OPIVX_WIDEN_TRANS(vwsmaccu_vx)
1767GEN_OPIVX_WIDEN_TRANS(vwsmacc_vx)
1768GEN_OPIVX_WIDEN_TRANS(vwsmaccsu_vx)
1769GEN_OPIVX_WIDEN_TRANS(vwsmaccus_vx)
04a61406
LZ		 1770
1771/* Vector Single-Width Scaling Shift Instructions */
1772GEN_OPIVV_TRANS(vssrl_vv, opivv_check)
1773GEN_OPIVV_TRANS(vssra_vv, opivv_check)
1774GEN_OPIVX_TRANS(vssrl_vx, opivx_check)
1775GEN_OPIVX_TRANS(vssra_vx, opivx_check)
1776GEN_OPIVI_TRANS(vssrl_vi, 1, vssrl_vx, opivx_check)
1777GEN_OPIVI_TRANS(vssra_vi, 0, vssra_vx, opivx_check)
9ff3d287
LZ		 1778
1779/* Vector Narrowing Fixed-Point Clip Instructions */
1780GEN_OPIVV_NARROW_TRANS(vnclipu_vv)
1781GEN_OPIVV_NARROW_TRANS(vnclip_vv)
1782GEN_OPIVX_NARROW_TRANS(vnclipu_vx)
1783GEN_OPIVX_NARROW_TRANS(vnclip_vx)
1784GEN_OPIVI_NARROW_TRANS(vnclipu_vi, 1, vnclipu_vx)
1785GEN_OPIVI_NARROW_TRANS(vnclip_vi, 1, vnclip_vx)
ce2a0343
LZ		 1786
1787/*
1788 *** Vector Float Point Arithmetic Instructions
1789 */
1790/* Vector Single-Width Floating-Point Add/Subtract Instructions */
1791
1792/*
1793 * If the current SEW does not correspond to a supported IEEE floating-point
1794 * type, an illegal instruction exception is raised.
1795 */
1796static bool opfvv_check(DisasContext *s, arg_rmrr *a)
1797{
1798 return (vext_check_isa_ill(s) &&
1799 vext_check_overlap_mask(s, a->rd, a->vm, false) &&
1800 vext_check_reg(s, a->rd, false) &&
1801 vext_check_reg(s, a->rs2, false) &&
1802 vext_check_reg(s, a->rs1, false) &&
1803 (s->sew != 0));
1804}
1805
1806/* OPFVV without GVEC IR */
1807#define GEN_OPFVV_TRANS(NAME, CHECK) \
1808static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
1809{ \
1810 if (CHECK(s, a)) { \
1811 uint32_t data = 0; \
1812 static gen_helper_gvec_4_ptr * const fns[3] = { \
1813 gen_helper_##NAME##_h, \
1814 gen_helper_##NAME##_w, \
1815 gen_helper_##NAME##_d, \
1816 }; \
1817 TCGLabel *over = gen_new_label(); \
1818 gen_set_rm(s, 7); \
1819 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
1820 \
1821 data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
1822 data = FIELD_DP32(data, VDATA, VM, a->vm); \
1823 data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
1824 tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
1825 vreg_ofs(s, a->rs1), \
1826 vreg_ofs(s, a->rs2), cpu_env, 0, \
1827 s->vlen / 8, data, fns[s->sew - 1]); \
1828 gen_set_label(over); \
1829 return true; \
1830 } \
1831 return false; \
1832}
1833GEN_OPFVV_TRANS(vfadd_vv, opfvv_check)
1834GEN_OPFVV_TRANS(vfsub_vv, opfvv_check)
1835
1836typedef void gen_helper_opfvf(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv_ptr,
1837 TCGv_env, TCGv_i32);
1838
1839static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
1840 uint32_t data, gen_helper_opfvf *fn, DisasContext *s)
1841{
1842 TCGv_ptr dest, src2, mask;
1843 TCGv_i32 desc;
1844
1845 TCGLabel *over = gen_new_label();
1846 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
1847
1848 dest = tcg_temp_new_ptr();
1849 mask = tcg_temp_new_ptr();
1850 src2 = tcg_temp_new_ptr();
1851 desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
1852
1853 tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
1854 tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
1855 tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
1856
1857 fn(dest, mask, cpu_fpr[rs1], src2, cpu_env, desc);
1858
1859 tcg_temp_free_ptr(dest);
1860 tcg_temp_free_ptr(mask);
1861 tcg_temp_free_ptr(src2);
1862 tcg_temp_free_i32(desc);
1863 gen_set_label(over);
1864 return true;
1865}
1866
1867static bool opfvf_check(DisasContext *s, arg_rmrr *a)
1868{
1869/*
1870 * If the current SEW does not correspond to a supported IEEE floating-point
1871 * type, an illegal instruction exception is raised
1872 */
1873 return (vext_check_isa_ill(s) &&
1874 vext_check_overlap_mask(s, a->rd, a->vm, false) &&
1875 vext_check_reg(s, a->rd, false) &&
1876 vext_check_reg(s, a->rs2, false) &&
1877 (s->sew != 0));
1878}
1879
1880/* OPFVF without GVEC IR */
1881#define GEN_OPFVF_TRANS(NAME, CHECK) \
1882static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
1883{ \
1884 if (CHECK(s, a)) { \
1885 uint32_t data = 0; \
1886 static gen_helper_opfvf *const fns[3] = { \
1887 gen_helper_##NAME##_h, \
1888 gen_helper_##NAME##_w, \
1889 gen_helper_##NAME##_d, \
1890 }; \
1891 gen_set_rm(s, 7); \
1892 data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
1893 data = FIELD_DP32(data, VDATA, VM, a->vm); \
1894 data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
1895 return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
1896 fns[s->sew - 1], s); \
1897 } \
1898 return false; \
1899}
1900
1901GEN_OPFVF_TRANS(vfadd_vf, opfvf_check)
1902GEN_OPFVF_TRANS(vfsub_vf, opfvf_check)
1903GEN_OPFVF_TRANS(vfrsub_vf, opfvf_check)
eeffab2e
LZ		 1904
1905/* Vector Widening Floating-Point Add/Subtract Instructions */
1906static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
1907{
1908 return (vext_check_isa_ill(s) &&
1909 vext_check_overlap_mask(s, a->rd, a->vm, true) &&
1910 vext_check_reg(s, a->rd, true) &&
1911 vext_check_reg(s, a->rs2, false) &&
1912 vext_check_reg(s, a->rs1, false) &&
1913 vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2,
1914 1 << s->lmul) &&
1915 vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1,
1916 1 << s->lmul) &&
1917 (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
1918}
1919
1920/* OPFVV with WIDEN */
1921#define GEN_OPFVV_WIDEN_TRANS(NAME, CHECK) \
1922static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
1923{ \
1924 if (CHECK(s, a)) { \
1925 uint32_t data = 0; \
1926 static gen_helper_gvec_4_ptr * const fns[2] = { \
1927 gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
1928 }; \
1929 TCGLabel *over = gen_new_label(); \
1930 gen_set_rm(s, 7); \
1931 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
1932 \
1933 data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
1934 data = FIELD_DP32(data, VDATA, VM, a->vm); \
1935 data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
1936 tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
1937 vreg_ofs(s, a->rs1), \
1938 vreg_ofs(s, a->rs2), cpu_env, 0, \
1939 s->vlen / 8, data, fns[s->sew - 1]); \
1940 gen_set_label(over); \
1941 return true; \
1942 } \
1943 return false; \
1944}
1945
1946GEN_OPFVV_WIDEN_TRANS(vfwadd_vv, opfvv_widen_check)
1947GEN_OPFVV_WIDEN_TRANS(vfwsub_vv, opfvv_widen_check)
1948
1949static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
1950{
1951 return (vext_check_isa_ill(s) &&
1952 vext_check_overlap_mask(s, a->rd, a->vm, true) &&
1953 vext_check_reg(s, a->rd, true) &&
1954 vext_check_reg(s, a->rs2, false) &&
1955 vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2,
1956 1 << s->lmul) &&
1957 (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
1958}
1959
1960/* OPFVF with WIDEN */
1961#define GEN_OPFVF_WIDEN_TRANS(NAME) \
1962static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
1963{ \
1964 if (opfvf_widen_check(s, a)) { \
1965 uint32_t data = 0; \
1966 static gen_helper_opfvf *const fns[2] = { \
1967 gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
1968 }; \
1969 gen_set_rm(s, 7); \
1970 data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
1971 data = FIELD_DP32(data, VDATA, VM, a->vm); \
1972 data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
1973 return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
1974 fns[s->sew - 1], s); \
1975 } \
1976 return false; \
1977}
1978
1979GEN_OPFVF_WIDEN_TRANS(vfwadd_vf)
1980GEN_OPFVF_WIDEN_TRANS(vfwsub_vf)
1981
1982static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
1983{
1984 return (vext_check_isa_ill(s) &&
1985 vext_check_overlap_mask(s, a->rd, a->vm, true) &&
1986 vext_check_reg(s, a->rd, true) &&
1987 vext_check_reg(s, a->rs2, true) &&
1988 vext_check_reg(s, a->rs1, false) &&
1989 vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1,
1990 1 << s->lmul) &&
1991 (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
1992}
1993
1994/* WIDEN OPFVV with WIDEN */
1995#define GEN_OPFWV_WIDEN_TRANS(NAME) \
1996static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
1997{ \
1998 if (opfwv_widen_check(s, a)) { \
1999 uint32_t data = 0; \
2000 static gen_helper_gvec_4_ptr * const fns[2] = { \
2001 gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
2002 }; \
2003 TCGLabel *over = gen_new_label(); \
2004 gen_set_rm(s, 7); \
2005 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
2006 \
2007 data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
2008 data = FIELD_DP32(data, VDATA, VM, a->vm); \
2009 data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
2010 tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
2011 vreg_ofs(s, a->rs1), \
2012 vreg_ofs(s, a->rs2), cpu_env, 0, \
2013 s->vlen / 8, data, fns[s->sew - 1]); \
2014 gen_set_label(over); \
2015 return true; \
2016 } \
2017 return false; \
2018}
2019
2020GEN_OPFWV_WIDEN_TRANS(vfwadd_wv)
2021GEN_OPFWV_WIDEN_TRANS(vfwsub_wv)
2022
2023static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
2024{
2025 return (vext_check_isa_ill(s) &&
2026 vext_check_overlap_mask(s, a->rd, a->vm, true) &&
2027 vext_check_reg(s, a->rd, true) &&
2028 vext_check_reg(s, a->rs2, true) &&
2029 (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
2030}
2031
2032/* WIDEN OPFVF with WIDEN */
2033#define GEN_OPFWF_WIDEN_TRANS(NAME) \
2034static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
2035{ \
2036 if (opfwf_widen_check(s, a)) { \
2037 uint32_t data = 0; \
2038 static gen_helper_opfvf *const fns[2] = { \
2039 gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
2040 }; \
2041 gen_set_rm(s, 7); \
2042 data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
2043 data = FIELD_DP32(data, VDATA, VM, a->vm); \
2044 data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
2045 return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
2046 fns[s->sew - 1], s); \
2047 } \
2048 return false; \
2049}
2050
2051GEN_OPFWF_WIDEN_TRANS(vfwadd_wf)
2052GEN_OPFWF_WIDEN_TRANS(vfwsub_wf)
0e0057cb
LZ		 2053
2054/* Vector Single-Width Floating-Point Multiply/Divide Instructions */
2055GEN_OPFVV_TRANS(vfmul_vv, opfvv_check)
2056GEN_OPFVV_TRANS(vfdiv_vv, opfvv_check)
2057GEN_OPFVF_TRANS(vfmul_vf, opfvf_check)
2058GEN_OPFVF_TRANS(vfdiv_vf, opfvf_check)
2059GEN_OPFVF_TRANS(vfrdiv_vf, opfvf_check)
f7c7b7cd
LZ		 2060
2061/* Vector Widening Floating-Point Multiply */
2062GEN_OPFVV_WIDEN_TRANS(vfwmul_vv, opfvv_widen_check)
2063GEN_OPFVF_WIDEN_TRANS(vfwmul_vf)
4aa5a8fe
LZ		 2064
2065/* Vector Single-Width Floating-Point Fused Multiply-Add Instructions */
2066GEN_OPFVV_TRANS(vfmacc_vv, opfvv_check)
2067GEN_OPFVV_TRANS(vfnmacc_vv, opfvv_check)
2068GEN_OPFVV_TRANS(vfmsac_vv, opfvv_check)
2069GEN_OPFVV_TRANS(vfnmsac_vv, opfvv_check)
2070GEN_OPFVV_TRANS(vfmadd_vv, opfvv_check)
2071GEN_OPFVV_TRANS(vfnmadd_vv, opfvv_check)
2072GEN_OPFVV_TRANS(vfmsub_vv, opfvv_check)
2073GEN_OPFVV_TRANS(vfnmsub_vv, opfvv_check)
2074GEN_OPFVF_TRANS(vfmacc_vf, opfvf_check)
2075GEN_OPFVF_TRANS(vfnmacc_vf, opfvf_check)
2076GEN_OPFVF_TRANS(vfmsac_vf, opfvf_check)
2077GEN_OPFVF_TRANS(vfnmsac_vf, opfvf_check)
2078GEN_OPFVF_TRANS(vfmadd_vf, opfvf_check)
2079GEN_OPFVF_TRANS(vfnmadd_vf, opfvf_check)
2080GEN_OPFVF_TRANS(vfmsub_vf, opfvf_check)
2081GEN_OPFVF_TRANS(vfnmsub_vf, opfvf_check)
0dd50959
LZ		 2082
2083/* Vector Widening Floating-Point Fused Multiply-Add Instructions */
2084GEN_OPFVV_WIDEN_TRANS(vfwmacc_vv, opfvv_widen_check)
2085GEN_OPFVV_WIDEN_TRANS(vfwnmacc_vv, opfvv_widen_check)
2086GEN_OPFVV_WIDEN_TRANS(vfwmsac_vv, opfvv_widen_check)
2087GEN_OPFVV_WIDEN_TRANS(vfwnmsac_vv, opfvv_widen_check)
2088GEN_OPFVF_WIDEN_TRANS(vfwmacc_vf)
2089GEN_OPFVF_WIDEN_TRANS(vfwnmacc_vf)
2090GEN_OPFVF_WIDEN_TRANS(vfwmsac_vf)
2091GEN_OPFVF_WIDEN_TRANS(vfwnmsac_vf)
d9e4ce72
LZ		 2092
2093/* Vector Floating-Point Square-Root Instruction */
2094
2095/*
2096 * If the current SEW does not correspond to a supported IEEE floating-point
2097 * type, an illegal instruction exception is raised
2098 */
2099static bool opfv_check(DisasContext *s, arg_rmr *a)
2100{
2101 return (vext_check_isa_ill(s) &&
2102 vext_check_overlap_mask(s, a->rd, a->vm, false) &&
2103 vext_check_reg(s, a->rd, false) &&
2104 vext_check_reg(s, a->rs2, false) &&
2105 (s->sew != 0));
2106}
2107
2108#define GEN_OPFV_TRANS(NAME, CHECK) \
2109static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
2110{ \
2111 if (CHECK(s, a)) { \
2112 uint32_t data = 0; \
2113 static gen_helper_gvec_3_ptr * const fns[3] = { \
2114 gen_helper_##NAME##_h, \
2115 gen_helper_##NAME##_w, \
2116 gen_helper_##NAME##_d, \
2117 }; \
2118 TCGLabel *over = gen_new_label(); \
2119 gen_set_rm(s, 7); \
2120 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
2121 \
2122 data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
2123 data = FIELD_DP32(data, VDATA, VM, a->vm); \
2124 data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
2125 tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
2126 vreg_ofs(s, a->rs2), cpu_env, 0, \
2127 s->vlen / 8, data, fns[s->sew - 1]); \
2128 gen_set_label(over); \
2129 return true; \
2130 } \
2131 return false; \
2132}
2133
2134GEN_OPFV_TRANS(vfsqrt_v, opfv_check)
230b53dd
LZ		 2135
2136/* Vector Floating-Point MIN/MAX Instructions */
2137GEN_OPFVV_TRANS(vfmin_vv, opfvv_check)
2138GEN_OPFVV_TRANS(vfmax_vv, opfvv_check)
2139GEN_OPFVF_TRANS(vfmin_vf, opfvf_check)
2140GEN_OPFVF_TRANS(vfmax_vf, opfvf_check)
1d426b81
LZ		 2141
2142/* Vector Floating-Point Sign-Injection Instructions */
2143GEN_OPFVV_TRANS(vfsgnj_vv, opfvv_check)
2144GEN_OPFVV_TRANS(vfsgnjn_vv, opfvv_check)
2145GEN_OPFVV_TRANS(vfsgnjx_vv, opfvv_check)
2146GEN_OPFVF_TRANS(vfsgnj_vf, opfvf_check)
2147GEN_OPFVF_TRANS(vfsgnjn_vf, opfvf_check)
2148GEN_OPFVF_TRANS(vfsgnjx_vf, opfvf_check)
2a68e9e5
LZ		 2149
2150/* Vector Floating-Point Compare Instructions */
2151static bool opfvv_cmp_check(DisasContext *s, arg_rmrr *a)
2152{
2153 return (vext_check_isa_ill(s) &&
2154 vext_check_reg(s, a->rs2, false) &&
2155 vext_check_reg(s, a->rs1, false) &&
2156 (s->sew != 0) &&
2157 ((vext_check_overlap_group(a->rd, 1, a->rs1, 1 << s->lmul) &&
2158 vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul)) ||
2159 (s->lmul == 0)));
2160}
2161
2162GEN_OPFVV_TRANS(vmfeq_vv, opfvv_cmp_check)
2163GEN_OPFVV_TRANS(vmfne_vv, opfvv_cmp_check)
2164GEN_OPFVV_TRANS(vmflt_vv, opfvv_cmp_check)
2165GEN_OPFVV_TRANS(vmfle_vv, opfvv_cmp_check)
2166GEN_OPFVV_TRANS(vmford_vv, opfvv_cmp_check)
2167
2168static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a)
2169{
2170 return (vext_check_isa_ill(s) &&
2171 vext_check_reg(s, a->rs2, false) &&
2172 (s->sew != 0) &&
2173 (vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul) ||
2174 (s->lmul == 0)));
2175}
2176
2177GEN_OPFVF_TRANS(vmfeq_vf, opfvf_cmp_check)
2178GEN_OPFVF_TRANS(vmfne_vf, opfvf_cmp_check)
2179GEN_OPFVF_TRANS(vmflt_vf, opfvf_cmp_check)
2180GEN_OPFVF_TRANS(vmfle_vf, opfvf_cmp_check)
2181GEN_OPFVF_TRANS(vmfgt_vf, opfvf_cmp_check)
2182GEN_OPFVF_TRANS(vmfge_vf, opfvf_cmp_check)
2183GEN_OPFVF_TRANS(vmford_vf, opfvf_cmp_check)
121ddbb3
LZ		 2184
2185/* Vector Floating-Point Classify Instruction */
2186GEN_OPFV_TRANS(vfclass_v, opfv_check)
64ab5846
LZ		 2187
2188/* Vector Floating-Point Merge Instruction */
2189GEN_OPFVF_TRANS(vfmerge_vfm, opfvf_check)
2190
2191static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
2192{
2193 if (vext_check_isa_ill(s) &&
2194 vext_check_reg(s, a->rd, false) &&
2195 (s->sew != 0)) {
2196
2197 if (s->vl_eq_vlmax) {
2198 tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
2199 MAXSZ(s), MAXSZ(s), cpu_fpr[a->rs1]);
2200 } else {
2201 TCGv_ptr dest;
2202 TCGv_i32 desc;
2203 uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
2204 static gen_helper_vmv_vx * const fns[3] = {
2205 gen_helper_vmv_v_x_h,
2206 gen_helper_vmv_v_x_w,
2207 gen_helper_vmv_v_x_d,
2208 };
2209 TCGLabel *over = gen_new_label();
2210 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
2211
2212 dest = tcg_temp_new_ptr();
2213 desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
2214 tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
2215 fns[s->sew - 1](dest, cpu_fpr[a->rs1], cpu_env, desc);
2216
2217 tcg_temp_free_ptr(dest);
2218 tcg_temp_free_i32(desc);
2219 gen_set_label(over);
2220 }
2221 return true;
2222 }
2223 return false;
2224}
92100973
LZ		 2225
2226/* Single-Width Floating-Point/Integer Type-Convert Instructions */
2227GEN_OPFV_TRANS(vfcvt_xu_f_v, opfv_check)
2228GEN_OPFV_TRANS(vfcvt_x_f_v, opfv_check)
2229GEN_OPFV_TRANS(vfcvt_f_xu_v, opfv_check)
2230GEN_OPFV_TRANS(vfcvt_f_x_v, opfv_check)
4514b7b1
LZ		 2231
2232/* Widening Floating-Point/Integer Type-Convert Instructions */
2233
2234/*
2235 * If the current SEW does not correspond to a supported IEEE floating-point
2236 * type, an illegal instruction exception is raised
2237 */
2238static bool opfv_widen_check(DisasContext *s, arg_rmr *a)
2239{
2240 return (vext_check_isa_ill(s) &&
2241 vext_check_overlap_mask(s, a->rd, a->vm, true) &&
2242 vext_check_reg(s, a->rd, true) &&
2243 vext_check_reg(s, a->rs2, false) &&
2244 vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2,
2245 1 << s->lmul) &&
2246 (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
2247}
2248
2249#define GEN_OPFV_WIDEN_TRANS(NAME) \
2250static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
2251{ \
2252 if (opfv_widen_check(s, a)) { \
2253 uint32_t data = 0; \
2254 static gen_helper_gvec_3_ptr * const fns[2] = { \
2255 gen_helper_##NAME##_h, \
2256 gen_helper_##NAME##_w, \
2257 }; \
2258 TCGLabel *over = gen_new_label(); \
2259 gen_set_rm(s, 7); \
2260 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
2261 \
2262 data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
2263 data = FIELD_DP32(data, VDATA, VM, a->vm); \
2264 data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
2265 tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
2266 vreg_ofs(s, a->rs2), cpu_env, 0, \
2267 s->vlen / 8, data, fns[s->sew - 1]); \
2268 gen_set_label(over); \
2269 return true; \
2270 } \
2271 return false; \
2272}
2273
2274GEN_OPFV_WIDEN_TRANS(vfwcvt_xu_f_v)
2275GEN_OPFV_WIDEN_TRANS(vfwcvt_x_f_v)
2276GEN_OPFV_WIDEN_TRANS(vfwcvt_f_xu_v)
2277GEN_OPFV_WIDEN_TRANS(vfwcvt_f_x_v)
2278GEN_OPFV_WIDEN_TRANS(vfwcvt_f_f_v)
878d406e
LZ		 2279
2280/* Narrowing Floating-Point/Integer Type-Convert Instructions */
2281
2282/*
2283 * If the current SEW does not correspond to a supported IEEE floating-point
2284 * type, an illegal instruction exception is raised
2285 */
2286static bool opfv_narrow_check(DisasContext *s, arg_rmr *a)
2287{
2288 return (vext_check_isa_ill(s) &&
2289 vext_check_overlap_mask(s, a->rd, a->vm, false) &&
2290 vext_check_reg(s, a->rd, false) &&
2291 vext_check_reg(s, a->rs2, true) &&
2292 vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2,
2293 2 << s->lmul) &&
2294 (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
2295}
2296
2297#define GEN_OPFV_NARROW_TRANS(NAME) \
2298static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
2299{ \
2300 if (opfv_narrow_check(s, a)) { \
2301 uint32_t data = 0; \
2302 static gen_helper_gvec_3_ptr * const fns[2] = { \
2303 gen_helper_##NAME##_h, \
2304 gen_helper_##NAME##_w, \
2305 }; \
2306 TCGLabel *over = gen_new_label(); \
2307 gen_set_rm(s, 7); \
2308 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
2309 \
2310 data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
2311 data = FIELD_DP32(data, VDATA, VM, a->vm); \
2312 data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
2313 tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
2314 vreg_ofs(s, a->rs2), cpu_env, 0, \
2315 s->vlen / 8, data, fns[s->sew - 1]); \
2316 gen_set_label(over); \
2317 return true; \
2318 } \
2319 return false; \
2320}
2321
2322GEN_OPFV_NARROW_TRANS(vfncvt_xu_f_v)
2323GEN_OPFV_NARROW_TRANS(vfncvt_x_f_v)
2324GEN_OPFV_NARROW_TRANS(vfncvt_f_xu_v)
2325GEN_OPFV_NARROW_TRANS(vfncvt_f_x_v)
2326GEN_OPFV_NARROW_TRANS(vfncvt_f_f_v)
fe5c9ab1
LZ		 2327
2328/*
2329 *** Vector Reduction Operations
2330 */
2331/* Vector Single-Width Integer Reduction Instructions */
2332static bool reduction_check(DisasContext *s, arg_rmrr *a)
2333{
2334 return vext_check_isa_ill(s) && vext_check_reg(s, a->rs2, false);
2335}
2336
2337GEN_OPIVV_TRANS(vredsum_vs, reduction_check)
2338GEN_OPIVV_TRANS(vredmaxu_vs, reduction_check)
2339GEN_OPIVV_TRANS(vredmax_vs, reduction_check)
2340GEN_OPIVV_TRANS(vredminu_vs, reduction_check)
2341GEN_OPIVV_TRANS(vredmin_vs, reduction_check)
2342GEN_OPIVV_TRANS(vredand_vs, reduction_check)
2343GEN_OPIVV_TRANS(vredor_vs, reduction_check)
2344GEN_OPIVV_TRANS(vredxor_vs, reduction_check)
bba71820
LZ		 2345
2346/* Vector Widening Integer Reduction Instructions */
2347GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_check)
2348GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_check)
523547f1
LZ		 2349
2350/* Vector Single-Width Floating-Point Reduction Instructions */
2351GEN_OPFVV_TRANS(vfredsum_vs, reduction_check)
2352GEN_OPFVV_TRANS(vfredmax_vs, reduction_check)
2353GEN_OPFVV_TRANS(vfredmin_vs, reduction_check)
696b0c26
LZ		 2354
2355/* Vector Widening Floating-Point Reduction Instructions */
2356GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_check)
c21f34ae
LZ		 2357
2358/*
2359 *** Vector Mask Operations
2360 */
2361
2362/* Vector Mask-Register Logical Instructions */
2363#define GEN_MM_TRANS(NAME) \
2364static bool trans_##NAME(DisasContext *s, arg_r *a) \
2365{ \
2366 if (vext_check_isa_ill(s)) { \
2367 uint32_t data = 0; \
2368 gen_helper_gvec_4_ptr *fn = gen_helper_##NAME; \
2369 TCGLabel *over = gen_new_label(); \
2370 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
2371 \
2372 data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
2373 data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
2374 tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
2375 vreg_ofs(s, a->rs1), \
2376 vreg_ofs(s, a->rs2), cpu_env, 0, \
2377 s->vlen / 8, data, fn); \
2378 gen_set_label(over); \
2379 return true; \
2380 } \
2381 return false; \
2382}
2383
2384GEN_MM_TRANS(vmand_mm)
2385GEN_MM_TRANS(vmnand_mm)
2386GEN_MM_TRANS(vmandnot_mm)
2387GEN_MM_TRANS(vmxor_mm)
2388GEN_MM_TRANS(vmor_mm)
2389GEN_MM_TRANS(vmnor_mm)
2390GEN_MM_TRANS(vmornot_mm)
2391GEN_MM_TRANS(vmxnor_mm)
2e88f551
LZ		 2392
2393/* Vector mask population count vmpopc */
2394static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
2395{
2396 if (vext_check_isa_ill(s)) {
2397 TCGv_ptr src2, mask;
2398 TCGv dst;
2399 TCGv_i32 desc;
2400 uint32_t data = 0;
2401 data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
2402 data = FIELD_DP32(data, VDATA, VM, a->vm);
2403 data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
2404
2405 mask = tcg_temp_new_ptr();
2406 src2 = tcg_temp_new_ptr();
2407 dst = tcg_temp_new();
2408 desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
2409
2410 tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
2411 tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
2412
2413 gen_helper_vmpopc_m(dst, mask, src2, cpu_env, desc);
2414 gen_set_gpr(a->rd, dst);
2415
2416 tcg_temp_free_ptr(mask);
2417 tcg_temp_free_ptr(src2);
2418 tcg_temp_free(dst);
2419 tcg_temp_free_i32(desc);
2420 return true;
2421 }
2422 return false;
2423}
0db67e1c
LZ		 2424
2425/* vmfirst find-first-set mask bit */
2426static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a)
2427{
2428 if (vext_check_isa_ill(s)) {
2429 TCGv_ptr src2, mask;
2430 TCGv dst;
2431 TCGv_i32 desc;
2432 uint32_t data = 0;
2433 data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
2434 data = FIELD_DP32(data, VDATA, VM, a->vm);
2435 data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
2436
2437 mask = tcg_temp_new_ptr();
2438 src2 = tcg_temp_new_ptr();
2439 dst = tcg_temp_new();
2440 desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
2441
2442 tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
2443 tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
2444
2445 gen_helper_vmfirst_m(dst, mask, src2, cpu_env, desc);
2446 gen_set_gpr(a->rd, dst);
2447
2448 tcg_temp_free_ptr(mask);
2449 tcg_temp_free_ptr(src2);
2450 tcg_temp_free(dst);
2451 tcg_temp_free_i32(desc);
2452 return true;
2453 }
2454 return false;
2455}
81fbf7da
LZ		 2456
2457/* vmsbf.m set-before-first mask bit */
2458/* vmsif.m set-includ-first mask bit */
2459/* vmsof.m set-only-first mask bit */
2460#define GEN_M_TRANS(NAME) \
2461static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
2462{ \
2463 if (vext_check_isa_ill(s)) { \
2464 uint32_t data = 0; \
2465 gen_helper_gvec_3_ptr *fn = gen_helper_##NAME; \
2466 TCGLabel *over = gen_new_label(); \
2467 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
2468 \
2469 data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
2470 data = FIELD_DP32(data, VDATA, VM, a->vm); \
2471 data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
2472 tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \
2473 vreg_ofs(s, 0), vreg_ofs(s, a->rs2), \
2474 cpu_env, 0, s->vlen / 8, data, fn); \
2475 gen_set_label(over); \
2476 return true; \
2477 } \
2478 return false; \
2479}
2480
2481GEN_M_TRANS(vmsbf_m)
2482GEN_M_TRANS(vmsif_m)
2483GEN_M_TRANS(vmsof_m)
78d90cfe
LZ		 2484
2485/* Vector Iota Instruction */
2486static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
2487{
2488 if (vext_check_isa_ill(s) &&
2489 vext_check_reg(s, a->rd, false) &&
2490 vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2, 1) &&
2491 (a->vm != 0 || a->rd != 0)) {
2492 uint32_t data = 0;
2493 TCGLabel *over = gen_new_label();
2494 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
2495
2496 data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
2497 data = FIELD_DP32(data, VDATA, VM, a->vm);
2498 data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
2499 static gen_helper_gvec_3_ptr * const fns[4] = {
2500 gen_helper_viota_m_b, gen_helper_viota_m_h,
2501 gen_helper_viota_m_w, gen_helper_viota_m_d,
2502 };
2503 tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
2504 vreg_ofs(s, a->rs2), cpu_env, 0,
2505 s->vlen / 8, data, fns[s->sew]);
2506 gen_set_label(over);
2507 return true;
2508 }
2509 return false;
2510}
126bec3f
LZ		 2511
2512/* Vector Element Index Instruction */
2513static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
2514{
2515 if (vext_check_isa_ill(s) &&
2516 vext_check_reg(s, a->rd, false) &&
2517 vext_check_overlap_mask(s, a->rd, a->vm, false)) {
2518 uint32_t data = 0;
2519 TCGLabel *over = gen_new_label();
2520 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
2521
2522 data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
2523 data = FIELD_DP32(data, VDATA, VM, a->vm);
2524 data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
2525 static gen_helper_gvec_2_ptr * const fns[4] = {
2526 gen_helper_vid_v_b, gen_helper_vid_v_h,
2527 gen_helper_vid_v_w, gen_helper_vid_v_d,
2528 };
2529 tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
2530 cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
2531 gen_set_label(over);
2532 return true;
2533 }
2534 return false;
2535}
90355f39
LZ		 2536
2537/*
2538 *** Vector Permutation Instructions
2539 */
2540
2541/* Integer Extract Instruction */
2542
2543static void load_element(TCGv_i64 dest, TCGv_ptr base,
2544 int ofs, int sew)
2545{
2546 switch (sew) {
2547 case MO_8:
2548 tcg_gen_ld8u_i64(dest, base, ofs);
2549 break;
2550 case MO_16:
2551 tcg_gen_ld16u_i64(dest, base, ofs);
2552 break;
2553 case MO_32:
2554 tcg_gen_ld32u_i64(dest, base, ofs);
2555 break;
2556 case MO_64:
2557 tcg_gen_ld_i64(dest, base, ofs);
2558 break;
2559 default:
2560 g_assert_not_reached();
2561 break;
2562 }
2563}
2564
2565/* offset of the idx element with base regsiter r */
2566static uint32_t endian_ofs(DisasContext *s, int r, int idx)
2567{
2568#ifdef HOST_WORDS_BIGENDIAN
2569 return vreg_ofs(s, r) + ((idx ^ (7 >> s->sew)) << s->sew);
2570#else
2571 return vreg_ofs(s, r) + (idx << s->sew);
2572#endif
2573}
2574
2575/* adjust the index according to the endian */
2576static void endian_adjust(TCGv_i32 ofs, int sew)
2577{
2578#ifdef HOST_WORDS_BIGENDIAN
2579 tcg_gen_xori_i32(ofs, ofs, 7 >> sew);
2580#endif
2581}
2582
2583/* Load idx >= VLMAX ? 0 : vreg[idx] */
2584static void vec_element_loadx(DisasContext *s, TCGv_i64 dest,
2585 int vreg, TCGv idx, int vlmax)
2586{
2587 TCGv_i32 ofs = tcg_temp_new_i32();
2588 TCGv_ptr base = tcg_temp_new_ptr();
2589 TCGv_i64 t_idx = tcg_temp_new_i64();
2590 TCGv_i64 t_vlmax, t_zero;
2591
2592 /*
2593 * Mask the index to the length so that we do
2594 * not produce an out-of-range load.
2595 */
2596 tcg_gen_trunc_tl_i32(ofs, idx);
2597 tcg_gen_andi_i32(ofs, ofs, vlmax - 1);
2598
2599 /* Convert the index to an offset. */
2600 endian_adjust(ofs, s->sew);
2601 tcg_gen_shli_i32(ofs, ofs, s->sew);
2602
2603 /* Convert the index to a pointer. */
2604 tcg_gen_ext_i32_ptr(base, ofs);
2605 tcg_gen_add_ptr(base, base, cpu_env);
2606
2607 /* Perform the load. */
2608 load_element(dest, base,
2609 vreg_ofs(s, vreg), s->sew);
2610 tcg_temp_free_ptr(base);
2611 tcg_temp_free_i32(ofs);
2612
2613 /* Flush out-of-range indexing to zero. */
2614 t_vlmax = tcg_const_i64(vlmax);
2615 t_zero = tcg_const_i64(0);
2616 tcg_gen_extu_tl_i64(t_idx, idx);
2617
2618 tcg_gen_movcond_i64(TCG_COND_LTU, dest, t_idx,
2619 t_vlmax, dest, t_zero);
2620
2621 tcg_temp_free_i64(t_vlmax);
2622 tcg_temp_free_i64(t_zero);
2623 tcg_temp_free_i64(t_idx);
2624}
2625
2626static void vec_element_loadi(DisasContext *s, TCGv_i64 dest,
2627 int vreg, int idx)
2628{
2629 load_element(dest, cpu_env, endian_ofs(s, vreg, idx), s->sew);
2630}
2631
2632static bool trans_vext_x_v(DisasContext *s, arg_r *a)
2633{
2634 TCGv_i64 tmp = tcg_temp_new_i64();
2635 TCGv dest = tcg_temp_new();
2636
2637 if (a->rs1 == 0) {
2638 /* Special case vmv.x.s rd, vs2. */
2639 vec_element_loadi(s, tmp, a->rs2, 0);
2640 } else {
2641 /* This instruction ignores LMUL and vector register groups */
2642 int vlmax = s->vlen >> (3 + s->sew);
2643 vec_element_loadx(s, tmp, a->rs2, cpu_gpr[a->rs1], vlmax);
2644 }
2645 tcg_gen_trunc_i64_tl(dest, tmp);
2646 gen_set_gpr(a->rd, dest);
2647
2648 tcg_temp_free(dest);
2649 tcg_temp_free_i64(tmp);
2650 return true;
2651}
9fc08be6
LZ		 2652
2653/* Integer Scalar Move Instruction */
2654
2655static void store_element(TCGv_i64 val, TCGv_ptr base,
2656 int ofs, int sew)
2657{
2658 switch (sew) {
2659 case MO_8:
2660 tcg_gen_st8_i64(val, base, ofs);
2661 break;
2662 case MO_16:
2663 tcg_gen_st16_i64(val, base, ofs);
2664 break;
2665 case MO_32:
2666 tcg_gen_st32_i64(val, base, ofs);
2667 break;
2668 case MO_64:
2669 tcg_gen_st_i64(val, base, ofs);
2670 break;
2671 default:
2672 g_assert_not_reached();
2673 break;
2674 }
2675}
2676
2677/*
2678 * Store vreg[idx] = val.
2679 * The index must be in range of VLMAX.
2680 */
2681static void vec_element_storei(DisasContext *s, int vreg,
2682 int idx, TCGv_i64 val)
2683{
2684 store_element(val, cpu_env, endian_ofs(s, vreg, idx), s->sew);
2685}
2686
2687/* vmv.s.x vd, rs1 # vd[0] = rs1 */
2688static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
2689{
2690 if (vext_check_isa_ill(s)) {
2691 /* This instruction ignores LMUL and vector register groups */
2692 int maxsz = s->vlen >> 3;
2693 TCGv_i64 t1;
2694 TCGLabel *over = gen_new_label();
2695
2696 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
2697 tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), maxsz, maxsz, 0);
2698 if (a->rs1 == 0) {
2699 goto done;
2700 }
2701
2702 t1 = tcg_temp_new_i64();
2703 tcg_gen_extu_tl_i64(t1, cpu_gpr[a->rs1]);
2704 vec_element_storei(s, a->rd, 0, t1);
2705 tcg_temp_free_i64(t1);
2706 done:
2707 gen_set_label(over);
2708 return true;
2709 }
2710 return false;
2711}
2843420a
LZ		 2712
2713/* Floating-Point Scalar Move Instructions */
2714static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a)
2715{
2716 if (!s->vill && has_ext(s, RVF) &&
2717 (s->mstatus_fs != 0) && (s->sew != 0)) {
2718 unsigned int len = 8 << s->sew;
2719
2720 vec_element_loadi(s, cpu_fpr[a->rd], a->rs2, 0);
2721 if (len < 64) {
2722 tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd],
2723 MAKE_64BIT_MASK(len, 64 - len));
2724 }
2725
2726 mark_fs_dirty(s);
2727 return true;
2728 }
2729 return false;
2730}
2731
2732/* vfmv.s.f vd, rs1 # vd[0] = rs1 (vs2=0) */
2733static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
2734{
2735 if (!s->vill && has_ext(s, RVF) && (s->sew != 0)) {
2736 TCGv_i64 t1;
2737 /* The instructions ignore LMUL and vector register group. */
2738 uint32_t vlmax = s->vlen >> 3;
2739
2740 /* if vl == 0, skip vector register write back */
2741 TCGLabel *over = gen_new_label();
2742 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
2743
2744 /* zeroed all elements */
2745 tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), vlmax, vlmax, 0);
2746
2747 /* NaN-box f[rs1] as necessary for SEW */
2748 t1 = tcg_temp_new_i64();
2749 if (s->sew == MO_64 && !has_ext(s, RVD)) {
2750 tcg_gen_ori_i64(t1, cpu_fpr[a->rs1], MAKE_64BIT_MASK(32, 32));
2751 } else {
2752 tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]);
2753 }
2754 vec_element_storei(s, a->rd, 0, t1);
2755 tcg_temp_free_i64(t1);
2756 gen_set_label(over);
2757 return true;
2758 }
2759 return false;
2760}
ec17e036
LZ		 2761
2762/* Vector Slide Instructions */
2763static bool slideup_check(DisasContext *s, arg_rmrr *a)
2764{
2765 return (vext_check_isa_ill(s) &&
2766 vext_check_overlap_mask(s, a->rd, a->vm, true) &&
2767 vext_check_reg(s, a->rd, false) &&
2768 vext_check_reg(s, a->rs2, false) &&
2769 (a->rd != a->rs2));
2770}
2771
2772GEN_OPIVX_TRANS(vslideup_vx, slideup_check)
2773GEN_OPIVX_TRANS(vslide1up_vx, slideup_check)
2774GEN_OPIVI_TRANS(vslideup_vi, 1, vslideup_vx, slideup_check)
2775
2776GEN_OPIVX_TRANS(vslidedown_vx, opivx_check)
2777GEN_OPIVX_TRANS(vslide1down_vx, opivx_check)
2778GEN_OPIVI_TRANS(vslidedown_vi, 1, vslidedown_vx, opivx_check)
e4b83d5c
LZ		 2779
2780/* Vector Register Gather Instruction */
2781static bool vrgather_vv_check(DisasContext *s, arg_rmrr *a)
2782{
2783 return (vext_check_isa_ill(s) &&
2784 vext_check_overlap_mask(s, a->rd, a->vm, true) &&
2785 vext_check_reg(s, a->rd, false) &&
2786 vext_check_reg(s, a->rs1, false) &&
2787 vext_check_reg(s, a->rs2, false) &&
2788 (a->rd != a->rs2) && (a->rd != a->rs1));
2789}
2790
2791GEN_OPIVV_TRANS(vrgather_vv, vrgather_vv_check)
2792
2793static bool vrgather_vx_check(DisasContext *s, arg_rmrr *a)
2794{
2795 return (vext_check_isa_ill(s) &&
2796 vext_check_overlap_mask(s, a->rd, a->vm, true) &&
2797 vext_check_reg(s, a->rd, false) &&
2798 vext_check_reg(s, a->rs2, false) &&
2799 (a->rd != a->rs2));
2800}
2801
2802/* vrgather.vx vd, vs2, rs1, vm # vd[i] = (x[rs1] >= VLMAX) ? 0 : vs2[rs1] */
2803static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a)
2804{
2805 if (!vrgather_vx_check(s, a)) {
2806 return false;
2807 }
2808
2809 if (a->vm && s->vl_eq_vlmax) {
2810 int vlmax = s->vlen / s->mlen;
2811 TCGv_i64 dest = tcg_temp_new_i64();
2812
2813 if (a->rs1 == 0) {
2814 vec_element_loadi(s, dest, a->rs2, 0);
2815 } else {
2816 vec_element_loadx(s, dest, a->rs2, cpu_gpr[a->rs1], vlmax);
2817 }
2818
2819 tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
2820 MAXSZ(s), MAXSZ(s), dest);
2821 tcg_temp_free_i64(dest);
2822 } else {
2823 static gen_helper_opivx * const fns[4] = {
2824 gen_helper_vrgather_vx_b, gen_helper_vrgather_vx_h,
2825 gen_helper_vrgather_vx_w, gen_helper_vrgather_vx_d
2826 };
2827 return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s);
2828 }
2829 return true;
2830}
2831
2832/* vrgather.vi vd, vs2, imm, vm # vd[i] = (imm >= VLMAX) ? 0 : vs2[imm] */
2833static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a)
2834{
2835 if (!vrgather_vx_check(s, a)) {
2836 return false;
2837 }
2838
2839 if (a->vm && s->vl_eq_vlmax) {
2840 if (a->rs1 >= s->vlen / s->mlen) {
2841 tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd),
2842 MAXSZ(s), MAXSZ(s), 0);
2843 } else {
2844 tcg_gen_gvec_dup_mem(s->sew, vreg_ofs(s, a->rd),
2845 endian_ofs(s, a->rs2, a->rs1),
2846 MAXSZ(s), MAXSZ(s));
2847 }
2848 } else {
2849 static gen_helper_opivx * const fns[4] = {
2850 gen_helper_vrgather_vx_b, gen_helper_vrgather_vx_h,
2851 gen_helper_vrgather_vx_w, gen_helper_vrgather_vx_d
2852 };
2853 return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s, 1);
2854 }
2855 return true;
2856}
31bf42a2
LZ		 2857
2858/* Vector Compress Instruction */
2859static bool vcompress_vm_check(DisasContext *s, arg_r *a)
2860{
2861 return (vext_check_isa_ill(s) &&
2862 vext_check_reg(s, a->rd, false) &&
2863 vext_check_reg(s, a->rs2, false) &&
2864 vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs1, 1) &&
2865 (a->rd != a->rs2));
2866}
2867
2868static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
2869{
2870 if (vcompress_vm_check(s, a)) {
2871 uint32_t data = 0;
2872 static gen_helper_gvec_4_ptr * const fns[4] = {
2873 gen_helper_vcompress_vm_b, gen_helper_vcompress_vm_h,
2874 gen_helper_vcompress_vm_w, gen_helper_vcompress_vm_d,
2875 };
2876 TCGLabel *over = gen_new_label();
2877 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
2878
2879 data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
2880 data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
2881 tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
2882 vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
2883 cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
2884 gen_set_label(over);
2885 return true;
2886 }
2887 return false;
2888}
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