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f476f177 LZ |
1 | /* |
2 | * QEMU RISC-V CPU -- internal functions and types | |
3 | * | |
4 | * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2 or later, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along with | |
16 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | ||
19 | #ifndef RISCV_CPU_INTERNALS_H | |
20 | #define RISCV_CPU_INTERNALS_H | |
21 | ||
22 | #include "hw/registerfields.h" | |
23 | ||
751538d5 | 24 | /* share data between vector helpers and decode code */ |
f9298de5 FC |
25 | FIELD(VDATA, VM, 0, 1) |
26 | FIELD(VDATA, LMUL, 1, 3) | |
27 | FIELD(VDATA, NF, 4, 4) | |
28 | FIELD(VDATA, WD, 4, 1) | |
121ddbb3 LZ |
29 | |
30 | /* float point classify helpers */ | |
31 | target_ulong fclass_h(uint64_t frs1); | |
32 | target_ulong fclass_s(uint64_t frs1); | |
33 | target_ulong fclass_d(uint64_t frs1); | |
9fc08be6 | 34 | |
f7697f0e YJ |
35 | #ifndef CONFIG_USER_ONLY |
36 | extern const VMStateDescription vmstate_riscv_cpu; | |
37 | #endif | |
38 | ||
9921e3d3 RH |
39 | static inline uint64_t nanbox_s(float32 f) |
40 | { | |
41 | return f | MAKE_64BIT_MASK(32, 32); | |
42 | } | |
43 | ||
00e925c5 RH |
44 | static inline float32 check_nanbox_s(uint64_t f) |
45 | { | |
46 | uint64_t mask = MAKE_64BIT_MASK(32, 32); | |
47 | ||
48 | if (likely((f & mask) == mask)) { | |
49 | return (uint32_t)f; | |
50 | } else { | |
51 | return 0x7fc00000u; /* default qnan */ | |
52 | } | |
53 | } | |
54 | ||
00c1899f KC |
55 | static inline uint64_t nanbox_h(float16 f) |
56 | { | |
57 | return f | MAKE_64BIT_MASK(16, 48); | |
58 | } | |
59 | ||
60 | static inline float16 check_nanbox_h(uint64_t f) | |
61 | { | |
62 | uint64_t mask = MAKE_64BIT_MASK(16, 48); | |
63 | ||
64 | if (likely((f & mask) == mask)) { | |
65 | return (uint16_t)f; | |
66 | } else { | |
67 | return 0x7E00u; /* default qnan */ | |
68 | } | |
69 | } | |
70 | ||
f476f177 | 71 | #endif |