[mirror_qemu.git] / target / riscv / machine.c

/*
 * RISC-V VMState Description
 *
 * Copyright (c) 2020 Huawei Technologies Co., Ltd
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2 or later, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "cpu.h"
#include "qemu/error-report.h"
#include "sysemu/kvm.h"
#include "migration/cpu.h"
#include "sysemu/cpu-timers.h"
#include "debug.h"

static bool pmp_needed(void *opaque)
{
    RISCVCPU *cpu = opaque;

    return cpu->cfg.pmp;
}

static int pmp_post_load(void *opaque, int version_id)
{
    RISCVCPU *cpu = opaque;
    CPURISCVState *env = &cpu->env;
    int i;

    for (i = 0; i < MAX_RISCV_PMPS; i++) {
        pmp_update_rule_addr(env, i);
    }
    pmp_update_rule_nums(env);

    return 0;
}

static const VMStateDescription vmstate_pmp_entry = {
    .name = "cpu/pmp/entry",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINTTL(addr_reg, pmp_entry_t),
        VMSTATE_UINT8(cfg_reg, pmp_entry_t),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_pmp = {
    .name = "cpu/pmp",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = pmp_needed,
    .post_load = pmp_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_STRUCT_ARRAY(env.pmp_state.pmp, RISCVCPU, MAX_RISCV_PMPS,
                             0, vmstate_pmp_entry, pmp_entry_t),
        VMSTATE_END_OF_LIST()
    }
};

static bool hyper_needed(void *opaque)
{
    RISCVCPU *cpu = opaque;
    CPURISCVState *env = &cpu->env;

    return riscv_has_ext(env, RVH);
}

static const VMStateDescription vmstate_hyper = {
    .name = "cpu/hyper",
    .version_id = 2,
    .minimum_version_id = 2,
    .needed = hyper_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINTTL(env.hstatus, RISCVCPU),
        VMSTATE_UINTTL(env.hedeleg, RISCVCPU),
        VMSTATE_UINT64(env.hideleg, RISCVCPU),
        VMSTATE_UINTTL(env.hcounteren, RISCVCPU),
        VMSTATE_UINTTL(env.htval, RISCVCPU),
        VMSTATE_UINTTL(env.htinst, RISCVCPU),
        VMSTATE_UINTTL(env.hgatp, RISCVCPU),
        VMSTATE_UINTTL(env.hgeie, RISCVCPU),
        VMSTATE_UINTTL(env.hgeip, RISCVCPU),
        VMSTATE_UINT64(env.htimedelta, RISCVCPU),
        VMSTATE_UINT64(env.vstimecmp, RISCVCPU),

        VMSTATE_UINTTL(env.hvictl, RISCVCPU),
        VMSTATE_UINT8_ARRAY(env.hviprio, RISCVCPU, 64),

        VMSTATE_UINT64(env.vsstatus, RISCVCPU),
        VMSTATE_UINTTL(env.vstvec, RISCVCPU),
        VMSTATE_UINTTL(env.vsscratch, RISCVCPU),
        VMSTATE_UINTTL(env.vsepc, RISCVCPU),
        VMSTATE_UINTTL(env.vscause, RISCVCPU),
        VMSTATE_UINTTL(env.vstval, RISCVCPU),
        VMSTATE_UINTTL(env.vsatp, RISCVCPU),
        VMSTATE_UINTTL(env.vsiselect, RISCVCPU),

        VMSTATE_UINTTL(env.mtval2, RISCVCPU),
        VMSTATE_UINTTL(env.mtinst, RISCVCPU),

        VMSTATE_UINTTL(env.stvec_hs, RISCVCPU),
        VMSTATE_UINTTL(env.sscratch_hs, RISCVCPU),
        VMSTATE_UINTTL(env.sepc_hs, RISCVCPU),
        VMSTATE_UINTTL(env.scause_hs, RISCVCPU),
        VMSTATE_UINTTL(env.stval_hs, RISCVCPU),
        VMSTATE_UINTTL(env.satp_hs, RISCVCPU),
        VMSTATE_UINT64(env.mstatus_hs, RISCVCPU),

        VMSTATE_END_OF_LIST()
    }
};

static bool vector_needed(void *opaque)
{
    RISCVCPU *cpu = opaque;
    CPURISCVState *env = &cpu->env;

    return riscv_has_ext(env, RVV);
}

static const VMStateDescription vmstate_vector = {
    .name = "cpu/vector",
    .version_id = 2,
    .minimum_version_id = 2,
    .needed = vector_needed,
    .fields = (VMStateField[]) {
            VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64),
            VMSTATE_UINTTL(env.vxrm, RISCVCPU),
            VMSTATE_UINTTL(env.vxsat, RISCVCPU),
            VMSTATE_UINTTL(env.vl, RISCVCPU),
            VMSTATE_UINTTL(env.vstart, RISCVCPU),
            VMSTATE_UINTTL(env.vtype, RISCVCPU),
            VMSTATE_BOOL(env.vill, RISCVCPU),
            VMSTATE_END_OF_LIST()
        }
};

static bool pointermasking_needed(void *opaque)
{
    RISCVCPU *cpu = opaque;
    CPURISCVState *env = &cpu->env;

    return riscv_has_ext(env, RVJ);
}

static const VMStateDescription vmstate_pointermasking = {
    .name = "cpu/pointer_masking",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = pointermasking_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINTTL(env.mmte, RISCVCPU),
        VMSTATE_UINTTL(env.mpmmask, RISCVCPU),
        VMSTATE_UINTTL(env.mpmbase, RISCVCPU),
        VMSTATE_UINTTL(env.spmmask, RISCVCPU),
        VMSTATE_UINTTL(env.spmbase, RISCVCPU),
        VMSTATE_UINTTL(env.upmmask, RISCVCPU),
        VMSTATE_UINTTL(env.upmbase, RISCVCPU),

        VMSTATE_END_OF_LIST()
    }
};

static bool rv128_needed(void *opaque)
{
    RISCVCPU *cpu = opaque;
    CPURISCVState *env = &cpu->env;

    return env->misa_mxl_max == MXL_RV128;
}

static const VMStateDescription vmstate_rv128 = {
    .name = "cpu/rv128",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = rv128_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINTTL_ARRAY(env.gprh, RISCVCPU, 32),
        VMSTATE_UINT64(env.mscratchh, RISCVCPU),
        VMSTATE_UINT64(env.sscratchh, RISCVCPU),
        VMSTATE_END_OF_LIST()
    }
};

static bool kvmtimer_needed(void *opaque)
{
    return kvm_enabled();
}

static int cpu_post_load(void *opaque, int version_id)
{
    RISCVCPU *cpu = opaque;
    CPURISCVState *env = &cpu->env;

    env->kvm_timer_dirty = true;
    return 0;
}

static const VMStateDescription vmstate_kvmtimer = {
    .name = "cpu/kvmtimer",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = kvmtimer_needed,
    .post_load = cpu_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU),
        VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU),
        VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU),
        VMSTATE_END_OF_LIST()
    }
};

static bool debug_needed(void *opaque)
{
    RISCVCPU *cpu = opaque;

    return cpu->cfg.debug;
}

static int debug_post_load(void *opaque, int version_id)
{
    RISCVCPU *cpu = opaque;
    CPURISCVState *env = &cpu->env;

    if (icount_enabled()) {
        env->itrigger_enabled = riscv_itrigger_enabled(env);
    }

    return 0;
}

static const VMStateDescription vmstate_debug = {
    .name = "cpu/debug",
    .version_id = 2,
    .minimum_version_id = 2,
    .needed = debug_needed,
    .post_load = debug_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_UINTTL(env.trigger_cur, RISCVCPU),
        VMSTATE_UINTTL_ARRAY(env.tdata1, RISCVCPU, RV_MAX_TRIGGERS),
        VMSTATE_UINTTL_ARRAY(env.tdata2, RISCVCPU, RV_MAX_TRIGGERS),
        VMSTATE_UINTTL_ARRAY(env.tdata3, RISCVCPU, RV_MAX_TRIGGERS),
        VMSTATE_END_OF_LIST()
    }
};

static int riscv_cpu_post_load(void *opaque, int version_id)
{
    RISCVCPU *cpu = opaque;
    CPURISCVState *env = &cpu->env;

    env->xl = cpu_recompute_xl(env);
    riscv_cpu_update_mask(env);
    return 0;
}

static bool smstateen_needed(void *opaque)
{
    RISCVCPU *cpu = opaque;

    return cpu->cfg.ext_smstateen;
}

static const VMStateDescription vmstate_smstateen = {
    .name = "cpu/smtateen",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = smstateen_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINT64_ARRAY(env.mstateen, RISCVCPU, 4),
        VMSTATE_UINT64_ARRAY(env.hstateen, RISCVCPU, 4),
        VMSTATE_UINT64_ARRAY(env.sstateen, RISCVCPU, 4),
        VMSTATE_END_OF_LIST()
    }
};

static bool envcfg_needed(void *opaque)
{
    RISCVCPU *cpu = opaque;
    CPURISCVState *env = &cpu->env;

    return (env->priv_ver >= PRIV_VERSION_1_12_0 ? 1 : 0);
}

static const VMStateDescription vmstate_envcfg = {
    .name = "cpu/envcfg",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = envcfg_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINT64(env.menvcfg, RISCVCPU),
        VMSTATE_UINTTL(env.senvcfg, RISCVCPU),
        VMSTATE_UINT64(env.henvcfg, RISCVCPU),
        VMSTATE_END_OF_LIST()
    }
};

static bool pmu_needed(void *opaque)
{
    RISCVCPU *cpu = opaque;

    return cpu->cfg.pmu_num;
}

static const VMStateDescription vmstate_pmu_ctr_state = {
    .name = "cpu/pmu",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = pmu_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINTTL(mhpmcounter_val, PMUCTRState),
        VMSTATE_UINTTL(mhpmcounterh_val, PMUCTRState),
        VMSTATE_UINTTL(mhpmcounter_prev, PMUCTRState),
        VMSTATE_UINTTL(mhpmcounterh_prev, PMUCTRState),
        VMSTATE_BOOL(started, PMUCTRState),
        VMSTATE_END_OF_LIST()
    }
};

const VMStateDescription vmstate_riscv_cpu = {
    .name = "cpu",
    .version_id = 6,
    .minimum_version_id = 6,
    .post_load = riscv_cpu_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
        VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
        VMSTATE_UINT8_ARRAY(env.miprio, RISCVCPU, 64),
        VMSTATE_UINT8_ARRAY(env.siprio, RISCVCPU, 64),
        VMSTATE_UINTTL(env.pc, RISCVCPU),
        VMSTATE_UINTTL(env.load_res, RISCVCPU),
        VMSTATE_UINTTL(env.load_val, RISCVCPU),
        VMSTATE_UINTTL(env.frm, RISCVCPU),
        VMSTATE_UINTTL(env.badaddr, RISCVCPU),
        VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU),
        VMSTATE_UINTTL(env.priv_ver, RISCVCPU),
        VMSTATE_UINTTL(env.vext_ver, RISCVCPU),
        VMSTATE_UINT32(env.misa_mxl, RISCVCPU),
        VMSTATE_UINT32(env.misa_ext, RISCVCPU),
        VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU),
        VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU),
        VMSTATE_UINT32(env.features, RISCVCPU),
        VMSTATE_UINTTL(env.priv, RISCVCPU),
        VMSTATE_UINTTL(env.virt, RISCVCPU),
        VMSTATE_UINT64(env.resetvec, RISCVCPU),
        VMSTATE_UINTTL(env.mhartid, RISCVCPU),
        VMSTATE_UINT64(env.mstatus, RISCVCPU),
        VMSTATE_UINT64(env.mip, RISCVCPU),
        VMSTATE_UINT64(env.miclaim, RISCVCPU),
        VMSTATE_UINT64(env.mie, RISCVCPU),
        VMSTATE_UINT64(env.mideleg, RISCVCPU),
        VMSTATE_UINTTL(env.satp, RISCVCPU),
        VMSTATE_UINTTL(env.stval, RISCVCPU),
        VMSTATE_UINTTL(env.medeleg, RISCVCPU),
        VMSTATE_UINTTL(env.stvec, RISCVCPU),
        VMSTATE_UINTTL(env.sepc, RISCVCPU),
        VMSTATE_UINTTL(env.scause, RISCVCPU),
        VMSTATE_UINTTL(env.mtvec, RISCVCPU),
        VMSTATE_UINTTL(env.mepc, RISCVCPU),
        VMSTATE_UINTTL(env.mcause, RISCVCPU),
        VMSTATE_UINTTL(env.mtval, RISCVCPU),
        VMSTATE_UINTTL(env.miselect, RISCVCPU),
        VMSTATE_UINTTL(env.siselect, RISCVCPU),
        VMSTATE_UINTTL(env.scounteren, RISCVCPU),
        VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
        VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU),
        VMSTATE_STRUCT_ARRAY(env.pmu_ctrs, RISCVCPU, RV_MAX_MHPMCOUNTERS, 0,
                             vmstate_pmu_ctr_state, PMUCTRState),
        VMSTATE_UINTTL_ARRAY(env.mhpmevent_val, RISCVCPU, RV_MAX_MHPMEVENTS),
        VMSTATE_UINTTL_ARRAY(env.mhpmeventh_val, RISCVCPU, RV_MAX_MHPMEVENTS),
        VMSTATE_UINTTL(env.sscratch, RISCVCPU),
        VMSTATE_UINTTL(env.mscratch, RISCVCPU),
        VMSTATE_UINT64(env.stimecmp, RISCVCPU),

        VMSTATE_END_OF_LIST()
    },
    .subsections = (const VMStateDescription * []) {
        &vmstate_pmp,
        &vmstate_hyper,
        &vmstate_vector,
        &vmstate_pointermasking,
        &vmstate_rv128,
        &vmstate_kvmtimer,
        &vmstate_envcfg,
        &vmstate_debug,
        &vmstate_smstateen,
        NULL
    }
};
Commit	Line	Data
f7697f0e YJ	1	/*
	2	* RISC-V VMState Description
	3	*
	4	* Copyright (c) 2020 Huawei Technologies Co., Ltd
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms and conditions of the GNU General Public License,
	8	* version 2 or later, as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	* more details.
	14	*
	15	* You should have received a copy of the GNU General Public License along with
	16	* this program. If not, see <http://www.gnu.org/licenses/>.
	17	*/
	18
	19	#include "qemu/osdep.h"
	20	#include "cpu.h"
	21	#include "qemu/error-report.h"
	22	#include "sysemu/kvm.h"
	23	#include "migration/cpu.h"
577f0286 LZ	24	#include "sysemu/cpu-timers.h"
577f0286 LZ	25	#include "debug.h"
f7697f0e	26
24beb03e YJ	27	static bool pmp_needed(void *opaque)
	28	{
	29	RISCVCPU *cpu = opaque;
24beb03e	30
3fe40ef5	31	return cpu->cfg.pmp;
24beb03e YJ	32	}
	33
	34	static int pmp_post_load(void *opaque, int version_id)
	35	{
	36	RISCVCPU *cpu = opaque;
	37	CPURISCVState *env = &cpu->env;
	38	int i;
	39
	40	for (i = 0; i < MAX_RISCV_PMPS; i++) {
	41	pmp_update_rule_addr(env, i);
	42	}
	43	pmp_update_rule_nums(env);
	44
	45	return 0;
	46	}
	47
	48	static const VMStateDescription vmstate_pmp_entry = {
	49	.name = "cpu/pmp/entry",
	50	.version_id = 1,
	51	.minimum_version_id = 1,
	52	.fields = (VMStateField[]) {
	53	VMSTATE_UINTTL(addr_reg, pmp_entry_t),
	54	VMSTATE_UINT8(cfg_reg, pmp_entry_t),
	55	VMSTATE_END_OF_LIST()
	56	}
	57	};
	58
	59	static const VMStateDescription vmstate_pmp = {
	60	.name = "cpu/pmp",
	61	.version_id = 1,
	62	.minimum_version_id = 1,
	63	.needed = pmp_needed,
	64	.post_load = pmp_post_load,
	65	.fields = (VMStateField[]) {
	66	VMSTATE_STRUCT_ARRAY(env.pmp_state.pmp, RISCVCPU, MAX_RISCV_PMPS,
	67	0, vmstate_pmp_entry, pmp_entry_t),
	68	VMSTATE_END_OF_LIST()
	69	}
	70	};
	71
35e07821 YJ	72	static bool hyper_needed(void *opaque)
	73	{
	74	RISCVCPU *cpu = opaque;
	75	CPURISCVState *env = &cpu->env;
	76
	77	return riscv_has_ext(env, RVH);
	78	}
	79
edcc4e40 BM	80	static const VMStateDescription vmstate_hyper = {
edcc4e40 BM	81	.name = "cpu/hyper",
cd032fe7 AP	82	.version_id = 2,
cd032fe7 AP	83	.minimum_version_id = 2,
edcc4e40 BM	84	.needed = hyper_needed,
	85	.fields = (VMStateField[]) {
	86	VMSTATE_UINTTL(env.hstatus, RISCVCPU),
	87	VMSTATE_UINTTL(env.hedeleg, RISCVCPU),
d028ac75	88	VMSTATE_UINT64(env.hideleg, RISCVCPU),
edcc4e40 BM	89	VMSTATE_UINTTL(env.hcounteren, RISCVCPU),
	90	VMSTATE_UINTTL(env.htval, RISCVCPU),
	91	VMSTATE_UINTTL(env.htinst, RISCVCPU),
	92	VMSTATE_UINTTL(env.hgatp, RISCVCPU),
cd032fe7 AP	93	VMSTATE_UINTTL(env.hgeie, RISCVCPU),
cd032fe7 AP	94	VMSTATE_UINTTL(env.hgeip, RISCVCPU),
edcc4e40	95	VMSTATE_UINT64(env.htimedelta, RISCVCPU),
3ec0fe18	96	VMSTATE_UINT64(env.vstimecmp, RISCVCPU),
2b602398 AP	97
2b602398 AP	98	VMSTATE_UINTTL(env.hvictl, RISCVCPU),
43dc93af	99	VMSTATE_UINT8_ARRAY(env.hviprio, RISCVCPU, 64),
bb02edcd	100
edcc4e40 BM	101	VMSTATE_UINT64(env.vsstatus, RISCVCPU),
	102	VMSTATE_UINTTL(env.vstvec, RISCVCPU),
	103	VMSTATE_UINTTL(env.vsscratch, RISCVCPU),
	104	VMSTATE_UINTTL(env.vsepc, RISCVCPU),
	105	VMSTATE_UINTTL(env.vscause, RISCVCPU),
	106	VMSTATE_UINTTL(env.vstval, RISCVCPU),
	107	VMSTATE_UINTTL(env.vsatp, RISCVCPU),
d1ceff40	108	VMSTATE_UINTTL(env.vsiselect, RISCVCPU),
bb02edcd	109
edcc4e40 BM	110	VMSTATE_UINTTL(env.mtval2, RISCVCPU),
	111	VMSTATE_UINTTL(env.mtinst, RISCVCPU),
	112
	113	VMSTATE_UINTTL(env.stvec_hs, RISCVCPU),
	114	VMSTATE_UINTTL(env.sscratch_hs, RISCVCPU),
	115	VMSTATE_UINTTL(env.sepc_hs, RISCVCPU),
	116	VMSTATE_UINTTL(env.scause_hs, RISCVCPU),
	117	VMSTATE_UINTTL(env.stval_hs, RISCVCPU),
	118	VMSTATE_UINTTL(env.satp_hs, RISCVCPU),
	119	VMSTATE_UINT64(env.mstatus_hs, RISCVCPU),
	120
	121	VMSTATE_END_OF_LIST()
	122	}
	123	};
	124
	125	static bool vector_needed(void *opaque)
b1c279e1 AB	126	{
	127	RISCVCPU *cpu = opaque;
	128	CPURISCVState *env = &cpu->env;
	129
edcc4e40	130	return riscv_has_ext(env, RVV);
b1c279e1 AB	131	}
b1c279e1 AB	132
bb02edcd YJ	133	static const VMStateDescription vmstate_vector = {
bb02edcd YJ	134	.name = "cpu/vector",
d96a271a LZ	135	.version_id = 2,
d96a271a LZ	136	.minimum_version_id = 2,
bb02edcd YJ	137	.needed = vector_needed,
	138	.fields = (VMStateField[]) {
	139	VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64),
	140	VMSTATE_UINTTL(env.vxrm, RISCVCPU),
	141	VMSTATE_UINTTL(env.vxsat, RISCVCPU),
	142	VMSTATE_UINTTL(env.vl, RISCVCPU),
	143	VMSTATE_UINTTL(env.vstart, RISCVCPU),
	144	VMSTATE_UINTTL(env.vtype, RISCVCPU),
d96a271a	145	VMSTATE_BOOL(env.vill, RISCVCPU),
bb02edcd YJ	146	VMSTATE_END_OF_LIST()
	147	}
	148	};
	149
edcc4e40 BM	150	static bool pointermasking_needed(void *opaque)
	151	{
	152	RISCVCPU *cpu = opaque;
	153	CPURISCVState *env = &cpu->env;
	154
	155	return riscv_has_ext(env, RVJ);
	156	}
	157
b1c279e1 AB	158	static const VMStateDescription vmstate_pointermasking = {
	159	.name = "cpu/pointer_masking",
	160	.version_id = 1,
	161	.minimum_version_id = 1,
	162	.needed = pointermasking_needed,
	163	.fields = (VMStateField[]) {
	164	VMSTATE_UINTTL(env.mmte, RISCVCPU),
	165	VMSTATE_UINTTL(env.mpmmask, RISCVCPU),
	166	VMSTATE_UINTTL(env.mpmbase, RISCVCPU),
	167	VMSTATE_UINTTL(env.spmmask, RISCVCPU),
	168	VMSTATE_UINTTL(env.spmbase, RISCVCPU),
	169	VMSTATE_UINTTL(env.upmmask, RISCVCPU),
	170	VMSTATE_UINTTL(env.upmbase, RISCVCPU),
	171
	172	VMSTATE_END_OF_LIST()
	173	}
	174	};
	175
2b547084 FP	176	static bool rv128_needed(void *opaque)
	177	{
	178	RISCVCPU *cpu = opaque;
	179	CPURISCVState *env = &cpu->env;
	180
	181	return env->misa_mxl_max == MXL_RV128;
	182	}
	183
	184	static const VMStateDescription vmstate_rv128 = {
	185	.name = "cpu/rv128",
	186	.version_id = 1,
	187	.minimum_version_id = 1,
	188	.needed = rv128_needed,
	189	.fields = (VMStateField[]) {
	190	VMSTATE_UINTTL_ARRAY(env.gprh, RISCVCPU, 32),
2c64ab66 FP	191	VMSTATE_UINT64(env.mscratchh, RISCVCPU),
2c64ab66 FP	192	VMSTATE_UINT64(env.sscratchh, RISCVCPU),
2b547084 FP	193	VMSTATE_END_OF_LIST()
	194	}
	195	};
	196
1eb9a5da YJ	197	static bool kvmtimer_needed(void *opaque)
	198	{
	199	return kvm_enabled();
	200	}
	201
	202	static int cpu_post_load(void *opaque, int version_id)
	203	{
	204	RISCVCPU *cpu = opaque;
	205	CPURISCVState *env = &cpu->env;
	206
	207	env->kvm_timer_dirty = true;
	208	return 0;
	209	}
	210
	211	static const VMStateDescription vmstate_kvmtimer = {
	212	.name = "cpu/kvmtimer",
	213	.version_id = 1,
	214	.minimum_version_id = 1,
	215	.needed = kvmtimer_needed,
	216	.post_load = cpu_post_load,
	217	.fields = (VMStateField[]) {
	218	VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU),
	219	VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU),
	220	VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU),
38b4e781 BM	221	VMSTATE_END_OF_LIST()
	222	}
	223	};
	224
	225	static bool debug_needed(void *opaque)
	226	{
	227	RISCVCPU *cpu = opaque;
38b4e781	228
cdfb2905	229	return cpu->cfg.debug;
38b4e781	230	}
1eb9a5da	231
577f0286 LZ	232	static int debug_post_load(void *opaque, int version_id)
	233	{
	234	RISCVCPU *cpu = opaque;
	235	CPURISCVState *env = &cpu->env;
	236
	237	if (icount_enabled()) {
	238	env->itrigger_enabled = riscv_itrigger_enabled(env);
	239	}
	240
	241	return 0;
	242	}
	243
38b4e781 BM	244	static const VMStateDescription vmstate_debug = {
38b4e781 BM	245	.name = "cpu/debug",
9495c488 FC	246	.version_id = 2,
9495c488 FC	247	.minimum_version_id = 2,
38b4e781	248	.needed = debug_needed,
577f0286	249	.post_load = debug_post_load,
38b4e781 BM	250	.fields = (VMStateField[]) {
38b4e781 BM	251	VMSTATE_UINTTL(env.trigger_cur, RISCVCPU),
9495c488 FC	252	VMSTATE_UINTTL_ARRAY(env.tdata1, RISCVCPU, RV_MAX_TRIGGERS),
	253	VMSTATE_UINTTL_ARRAY(env.tdata2, RISCVCPU, RV_MAX_TRIGGERS),
	254	VMSTATE_UINTTL_ARRAY(env.tdata3, RISCVCPU, RV_MAX_TRIGGERS),
1eb9a5da YJ	255	VMSTATE_END_OF_LIST()
	256	}
	257	};
	258
440544e1 LZ	259	static int riscv_cpu_post_load(void *opaque, int version_id)
	260	{
	261	RISCVCPU *cpu = opaque;
	262	CPURISCVState *env = &cpu->env;
	263
	264	env->xl = cpu_recompute_xl(env);
40bfa5f6	265	riscv_cpu_update_mask(env);
440544e1 LZ	266	return 0;
	267	}
	268
3bee0e40 MC	269	static bool smstateen_needed(void *opaque)
	270	{
	271	RISCVCPU *cpu = opaque;
	272
	273	return cpu->cfg.ext_smstateen;
	274	}
	275
	276	static const VMStateDescription vmstate_smstateen = {
	277	.name = "cpu/smtateen",
	278	.version_id = 1,
	279	.minimum_version_id = 1,
	280	.needed = smstateen_needed,
	281	.fields = (VMStateField[]) {
	282	VMSTATE_UINT64_ARRAY(env.mstateen, RISCVCPU, 4),
	283	VMSTATE_UINT64_ARRAY(env.hstateen, RISCVCPU, 4),
	284	VMSTATE_UINT64_ARRAY(env.sstateen, RISCVCPU, 4),
	285	VMSTATE_END_OF_LIST()
	286	}
	287	};
	288
29a9ec9b AP	289	static bool envcfg_needed(void *opaque)
	290	{
	291	RISCVCPU *cpu = opaque;
	292	CPURISCVState *env = &cpu->env;
	293
	294	return (env->priv_ver >= PRIV_VERSION_1_12_0 ? 1 : 0);
	295	}
	296
	297	static const VMStateDescription vmstate_envcfg = {
	298	.name = "cpu/envcfg",
	299	.version_id = 1,
	300	.minimum_version_id = 1,
	301	.needed = envcfg_needed,
	302	.fields = (VMStateField[]) {
	303	VMSTATE_UINT64(env.menvcfg, RISCVCPU),
	304	VMSTATE_UINTTL(env.senvcfg, RISCVCPU),
	305	VMSTATE_UINT64(env.henvcfg, RISCVCPU),
3780e337 AP	306	VMSTATE_END_OF_LIST()
	307	}
	308	};
	309
	310	static bool pmu_needed(void *opaque)
	311	{
	312	RISCVCPU *cpu = opaque;
29a9ec9b	313
3780e337 AP	314	return cpu->cfg.pmu_num;
	315	}
	316
	317	static const VMStateDescription vmstate_pmu_ctr_state = {
	318	.name = "cpu/pmu",
	319	.version_id = 1,
	320	.minimum_version_id = 1,
	321	.needed = pmu_needed,
	322	.fields = (VMStateField[]) {
	323	VMSTATE_UINTTL(mhpmcounter_val, PMUCTRState),
	324	VMSTATE_UINTTL(mhpmcounterh_val, PMUCTRState),
	325	VMSTATE_UINTTL(mhpmcounter_prev, PMUCTRState),
	326	VMSTATE_UINTTL(mhpmcounterh_prev, PMUCTRState),
	327	VMSTATE_BOOL(started, PMUCTRState),
29a9ec9b AP	328	VMSTATE_END_OF_LIST()
	329	}
	330	};
	331
f7697f0e YJ	332	const VMStateDescription vmstate_riscv_cpu = {
f7697f0e YJ	333	.name = "cpu",
1237c2d6 BM	334	.version_id = 6,
1237c2d6 BM	335	.minimum_version_id = 6,
440544e1	336	.post_load = riscv_cpu_post_load,
f7697f0e YJ	337	.fields = (VMStateField[]) {
	338	VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
	339	VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
43dc93af AP	340	VMSTATE_UINT8_ARRAY(env.miprio, RISCVCPU, 64),
43dc93af AP	341	VMSTATE_UINT8_ARRAY(env.siprio, RISCVCPU, 64),
f7697f0e YJ	342	VMSTATE_UINTTL(env.pc, RISCVCPU),
	343	VMSTATE_UINTTL(env.load_res, RISCVCPU),
	344	VMSTATE_UINTTL(env.load_val, RISCVCPU),
	345	VMSTATE_UINTTL(env.frm, RISCVCPU),
	346	VMSTATE_UINTTL(env.badaddr, RISCVCPU),
	347	VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU),
	348	VMSTATE_UINTTL(env.priv_ver, RISCVCPU),
	349	VMSTATE_UINTTL(env.vext_ver, RISCVCPU),
e91a7227 RH	350	VMSTATE_UINT32(env.misa_mxl, RISCVCPU),
	351	VMSTATE_UINT32(env.misa_ext, RISCVCPU),
	352	VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU),
	353	VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU),
f7697f0e YJ	354	VMSTATE_UINT32(env.features, RISCVCPU),
	355	VMSTATE_UINTTL(env.priv, RISCVCPU),
	356	VMSTATE_UINTTL(env.virt, RISCVCPU),
277b210d	357	VMSTATE_UINT64(env.resetvec, RISCVCPU),
f7697f0e YJ	358	VMSTATE_UINTTL(env.mhartid, RISCVCPU),
f7697f0e YJ	359	VMSTATE_UINT64(env.mstatus, RISCVCPU),
d028ac75 AP	360	VMSTATE_UINT64(env.mip, RISCVCPU),
	361	VMSTATE_UINT64(env.miclaim, RISCVCPU),
	362	VMSTATE_UINT64(env.mie, RISCVCPU),
	363	VMSTATE_UINT64(env.mideleg, RISCVCPU),
f7697f0e	364	VMSTATE_UINTTL(env.satp, RISCVCPU),
ac12b601	365	VMSTATE_UINTTL(env.stval, RISCVCPU),
f7697f0e YJ	366	VMSTATE_UINTTL(env.medeleg, RISCVCPU),
	367	VMSTATE_UINTTL(env.stvec, RISCVCPU),
	368	VMSTATE_UINTTL(env.sepc, RISCVCPU),
	369	VMSTATE_UINTTL(env.scause, RISCVCPU),
	370	VMSTATE_UINTTL(env.mtvec, RISCVCPU),
	371	VMSTATE_UINTTL(env.mepc, RISCVCPU),
	372	VMSTATE_UINTTL(env.mcause, RISCVCPU),
	373	VMSTATE_UINTTL(env.mtval, RISCVCPU),
d1ceff40 AP	374	VMSTATE_UINTTL(env.miselect, RISCVCPU),
d1ceff40 AP	375	VMSTATE_UINTTL(env.siselect, RISCVCPU),
f7697f0e YJ	376	VMSTATE_UINTTL(env.scounteren, RISCVCPU),
f7697f0e YJ	377	VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
b1675eeb	378	VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU),
3780e337 AP	379	VMSTATE_STRUCT_ARRAY(env.pmu_ctrs, RISCVCPU, RV_MAX_MHPMCOUNTERS, 0,
3780e337 AP	380	vmstate_pmu_ctr_state, PMUCTRState),
621f35bb	381	VMSTATE_UINTTL_ARRAY(env.mhpmevent_val, RISCVCPU, RV_MAX_MHPMEVENTS),
14664483	382	VMSTATE_UINTTL_ARRAY(env.mhpmeventh_val, RISCVCPU, RV_MAX_MHPMEVENTS),
f7697f0e YJ	383	VMSTATE_UINTTL(env.sscratch, RISCVCPU),
f7697f0e YJ	384	VMSTATE_UINTTL(env.mscratch, RISCVCPU),
43888c2f	385	VMSTATE_UINT64(env.stimecmp, RISCVCPU),
f7697f0e YJ	386
f7697f0e YJ	387	VMSTATE_END_OF_LIST()
24beb03e YJ	388	},
	389	.subsections = (const VMStateDescription * []) {
	390	&vmstate_pmp,
35e07821	391	&vmstate_hyper,
bb02edcd	392	&vmstate_vector,
b1c279e1	393	&vmstate_pointermasking,
2b547084	394	&vmstate_rv128,
1eb9a5da	395	&vmstate_kvmtimer,
29a9ec9b	396	&vmstate_envcfg,
38b4e781	397	&vmstate_debug,
3bee0e40	398	&vmstate_smstateen,
24beb03e	399	NULL
f7697f0e YJ	400	}
f7697f0e YJ	401	};