[mirror_qemu.git] / target / riscv / machine.c

/*
 * RISC-V VMState Description
 *
 * Copyright (c) 2020 Huawei Technologies Co., Ltd
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2 or later, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "cpu.h"
#include "qemu/error-report.h"
#include "sysemu/kvm.h"
#include "migration/cpu.h"
#include "sysemu/cpu-timers.h"
#include "debug.h"

static bool pmp_needed(void *opaque)
{
    RISCVCPU *cpu = opaque;
    CPURISCVState *env = &cpu->env;

    return riscv_feature(env, RISCV_FEATURE_PMP);
}

static int pmp_post_load(void *opaque, int version_id)
{
    RISCVCPU *cpu = opaque;
    CPURISCVState *env = &cpu->env;
    int i;

    for (i = 0; i < MAX_RISCV_PMPS; i++) {
        pmp_update_rule_addr(env, i);
    }
    pmp_update_rule_nums(env);

    return 0;
}

static const VMStateDescription vmstate_pmp_entry = {
    .name = "cpu/pmp/entry",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINTTL(addr_reg, pmp_entry_t),
        VMSTATE_UINT8(cfg_reg, pmp_entry_t),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_pmp = {
    .name = "cpu/pmp",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = pmp_needed,
    .post_load = pmp_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_STRUCT_ARRAY(env.pmp_state.pmp, RISCVCPU, MAX_RISCV_PMPS,
                             0, vmstate_pmp_entry, pmp_entry_t),
        VMSTATE_END_OF_LIST()
    }
};

static bool hyper_needed(void *opaque)
{
    RISCVCPU *cpu = opaque;
    CPURISCVState *env = &cpu->env;

    return riscv_has_ext(env, RVH);
}

static const VMStateDescription vmstate_hyper = {
    .name = "cpu/hyper",
    .version_id = 2,
    .minimum_version_id = 2,
    .needed = hyper_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINTTL(env.hstatus, RISCVCPU),
        VMSTATE_UINTTL(env.hedeleg, RISCVCPU),
        VMSTATE_UINT64(env.hideleg, RISCVCPU),
        VMSTATE_UINTTL(env.hcounteren, RISCVCPU),
        VMSTATE_UINTTL(env.htval, RISCVCPU),
        VMSTATE_UINTTL(env.htinst, RISCVCPU),
        VMSTATE_UINTTL(env.hgatp, RISCVCPU),
        VMSTATE_UINTTL(env.hgeie, RISCVCPU),
        VMSTATE_UINTTL(env.hgeip, RISCVCPU),
        VMSTATE_UINT64(env.htimedelta, RISCVCPU),
        VMSTATE_UINT64(env.vstimecmp, RISCVCPU),

        VMSTATE_UINTTL(env.hvictl, RISCVCPU),
        VMSTATE_UINT8_ARRAY(env.hviprio, RISCVCPU, 64),

        VMSTATE_UINT64(env.vsstatus, RISCVCPU),
        VMSTATE_UINTTL(env.vstvec, RISCVCPU),
        VMSTATE_UINTTL(env.vsscratch, RISCVCPU),
        VMSTATE_UINTTL(env.vsepc, RISCVCPU),
        VMSTATE_UINTTL(env.vscause, RISCVCPU),
        VMSTATE_UINTTL(env.vstval, RISCVCPU),
        VMSTATE_UINTTL(env.vsatp, RISCVCPU),
        VMSTATE_UINTTL(env.vsiselect, RISCVCPU),

        VMSTATE_UINTTL(env.mtval2, RISCVCPU),
        VMSTATE_UINTTL(env.mtinst, RISCVCPU),

        VMSTATE_UINTTL(env.stvec_hs, RISCVCPU),
        VMSTATE_UINTTL(env.sscratch_hs, RISCVCPU),
        VMSTATE_UINTTL(env.sepc_hs, RISCVCPU),
        VMSTATE_UINTTL(env.scause_hs, RISCVCPU),
        VMSTATE_UINTTL(env.stval_hs, RISCVCPU),
        VMSTATE_UINTTL(env.satp_hs, RISCVCPU),
        VMSTATE_UINT64(env.mstatus_hs, RISCVCPU),

        VMSTATE_END_OF_LIST()
    }
};

static bool vector_needed(void *opaque)
{
    RISCVCPU *cpu = opaque;
    CPURISCVState *env = &cpu->env;

    return riscv_has_ext(env, RVV);
}

static const VMStateDescription vmstate_vector = {
    .name = "cpu/vector",
    .version_id = 2,
    .minimum_version_id = 2,
    .needed = vector_needed,
    .fields = (VMStateField[]) {
            VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64),
            VMSTATE_UINTTL(env.vxrm, RISCVCPU),
            VMSTATE_UINTTL(env.vxsat, RISCVCPU),
            VMSTATE_UINTTL(env.vl, RISCVCPU),
            VMSTATE_UINTTL(env.vstart, RISCVCPU),
            VMSTATE_UINTTL(env.vtype, RISCVCPU),
            VMSTATE_BOOL(env.vill, RISCVCPU),
            VMSTATE_END_OF_LIST()
        }
};

static bool pointermasking_needed(void *opaque)
{
    RISCVCPU *cpu = opaque;
    CPURISCVState *env = &cpu->env;

    return riscv_has_ext(env, RVJ);
}

static const VMStateDescription vmstate_pointermasking = {
    .name = "cpu/pointer_masking",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = pointermasking_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINTTL(env.mmte, RISCVCPU),
        VMSTATE_UINTTL(env.mpmmask, RISCVCPU),
        VMSTATE_UINTTL(env.mpmbase, RISCVCPU),
        VMSTATE_UINTTL(env.spmmask, RISCVCPU),
        VMSTATE_UINTTL(env.spmbase, RISCVCPU),
        VMSTATE_UINTTL(env.upmmask, RISCVCPU),
        VMSTATE_UINTTL(env.upmbase, RISCVCPU),

        VMSTATE_END_OF_LIST()
    }
};

static bool rv128_needed(void *opaque)
{
    RISCVCPU *cpu = opaque;
    CPURISCVState *env = &cpu->env;

    return env->misa_mxl_max == MXL_RV128;
}

static const VMStateDescription vmstate_rv128 = {
    .name = "cpu/rv128",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = rv128_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINTTL_ARRAY(env.gprh, RISCVCPU, 32),
        VMSTATE_UINT64(env.mscratchh, RISCVCPU),
        VMSTATE_UINT64(env.sscratchh, RISCVCPU),
        VMSTATE_END_OF_LIST()
    }
};

static bool kvmtimer_needed(void *opaque)
{
    return kvm_enabled();
}

static int cpu_post_load(void *opaque, int version_id)
{
    RISCVCPU *cpu = opaque;
    CPURISCVState *env = &cpu->env;

    env->kvm_timer_dirty = true;
    return 0;
}

static const VMStateDescription vmstate_kvmtimer = {
    .name = "cpu/kvmtimer",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = kvmtimer_needed,
    .post_load = cpu_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU),
        VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU),
        VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU),
        VMSTATE_END_OF_LIST()
    }
};

static bool debug_needed(void *opaque)
{
    RISCVCPU *cpu = opaque;
    CPURISCVState *env = &cpu->env;

    return riscv_feature(env, RISCV_FEATURE_DEBUG);
}

static int debug_post_load(void *opaque, int version_id)
{
    RISCVCPU *cpu = opaque;
    CPURISCVState *env = &cpu->env;

    if (icount_enabled()) {
        env->itrigger_enabled = riscv_itrigger_enabled(env);
    }

    return 0;
}

static const VMStateDescription vmstate_debug = {
    .name = "cpu/debug",
    .version_id = 2,
    .minimum_version_id = 2,
    .needed = debug_needed,
    .post_load = debug_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_UINTTL(env.trigger_cur, RISCVCPU),
        VMSTATE_UINTTL_ARRAY(env.tdata1, RISCVCPU, RV_MAX_TRIGGERS),
        VMSTATE_UINTTL_ARRAY(env.tdata2, RISCVCPU, RV_MAX_TRIGGERS),
        VMSTATE_UINTTL_ARRAY(env.tdata3, RISCVCPU, RV_MAX_TRIGGERS),
        VMSTATE_END_OF_LIST()
    }
};

static int riscv_cpu_post_load(void *opaque, int version_id)
{
    RISCVCPU *cpu = opaque;
    CPURISCVState *env = &cpu->env;

    env->xl = cpu_recompute_xl(env);
    riscv_cpu_update_mask(env);
    return 0;
}

static bool smstateen_needed(void *opaque)
{
    RISCVCPU *cpu = opaque;

    return cpu->cfg.ext_smstateen;
}

static const VMStateDescription vmstate_smstateen = {
    .name = "cpu/smtateen",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = smstateen_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINT64_ARRAY(env.mstateen, RISCVCPU, 4),
        VMSTATE_UINT64_ARRAY(env.hstateen, RISCVCPU, 4),
        VMSTATE_UINT64_ARRAY(env.sstateen, RISCVCPU, 4),
        VMSTATE_END_OF_LIST()
    }
};

static bool envcfg_needed(void *opaque)
{
    RISCVCPU *cpu = opaque;
    CPURISCVState *env = &cpu->env;

    return (env->priv_ver >= PRIV_VERSION_1_12_0 ? 1 : 0);
}

static const VMStateDescription vmstate_envcfg = {
    .name = "cpu/envcfg",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = envcfg_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINT64(env.menvcfg, RISCVCPU),
        VMSTATE_UINTTL(env.senvcfg, RISCVCPU),
        VMSTATE_UINT64(env.henvcfg, RISCVCPU),
        VMSTATE_END_OF_LIST()
    }
};

static bool pmu_needed(void *opaque)
{
    RISCVCPU *cpu = opaque;

    return cpu->cfg.pmu_num;
}

static const VMStateDescription vmstate_pmu_ctr_state = {
    .name = "cpu/pmu",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = pmu_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINTTL(mhpmcounter_val, PMUCTRState),
        VMSTATE_UINTTL(mhpmcounterh_val, PMUCTRState),
        VMSTATE_UINTTL(mhpmcounter_prev, PMUCTRState),
        VMSTATE_UINTTL(mhpmcounterh_prev, PMUCTRState),
        VMSTATE_BOOL(started, PMUCTRState),
        VMSTATE_END_OF_LIST()
    }
};

const VMStateDescription vmstate_riscv_cpu = {
    .name = "cpu",
    .version_id = 6,
    .minimum_version_id = 6,
    .post_load = riscv_cpu_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
        VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
        VMSTATE_UINT8_ARRAY(env.miprio, RISCVCPU, 64),
        VMSTATE_UINT8_ARRAY(env.siprio, RISCVCPU, 64),
        VMSTATE_UINTTL(env.pc, RISCVCPU),
        VMSTATE_UINTTL(env.load_res, RISCVCPU),
        VMSTATE_UINTTL(env.load_val, RISCVCPU),
        VMSTATE_UINTTL(env.frm, RISCVCPU),
        VMSTATE_UINTTL(env.badaddr, RISCVCPU),
        VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU),
        VMSTATE_UINTTL(env.priv_ver, RISCVCPU),
        VMSTATE_UINTTL(env.vext_ver, RISCVCPU),
        VMSTATE_UINT32(env.misa_mxl, RISCVCPU),
        VMSTATE_UINT32(env.misa_ext, RISCVCPU),
        VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU),
        VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU),
        VMSTATE_UINT32(env.features, RISCVCPU),
        VMSTATE_UINTTL(env.priv, RISCVCPU),
        VMSTATE_UINTTL(env.virt, RISCVCPU),
        VMSTATE_UINT64(env.resetvec, RISCVCPU),
        VMSTATE_UINTTL(env.mhartid, RISCVCPU),
        VMSTATE_UINT64(env.mstatus, RISCVCPU),
        VMSTATE_UINT64(env.mip, RISCVCPU),
        VMSTATE_UINT64(env.miclaim, RISCVCPU),
        VMSTATE_UINT64(env.mie, RISCVCPU),
        VMSTATE_UINT64(env.mideleg, RISCVCPU),
        VMSTATE_UINTTL(env.satp, RISCVCPU),
        VMSTATE_UINTTL(env.stval, RISCVCPU),
        VMSTATE_UINTTL(env.medeleg, RISCVCPU),
        VMSTATE_UINTTL(env.stvec, RISCVCPU),
        VMSTATE_UINTTL(env.sepc, RISCVCPU),
        VMSTATE_UINTTL(env.scause, RISCVCPU),
        VMSTATE_UINTTL(env.mtvec, RISCVCPU),
        VMSTATE_UINTTL(env.mepc, RISCVCPU),
        VMSTATE_UINTTL(env.mcause, RISCVCPU),
        VMSTATE_UINTTL(env.mtval, RISCVCPU),
        VMSTATE_UINTTL(env.miselect, RISCVCPU),
        VMSTATE_UINTTL(env.siselect, RISCVCPU),
        VMSTATE_UINTTL(env.scounteren, RISCVCPU),
        VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
        VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU),
        VMSTATE_STRUCT_ARRAY(env.pmu_ctrs, RISCVCPU, RV_MAX_MHPMCOUNTERS, 0,
                             vmstate_pmu_ctr_state, PMUCTRState),
        VMSTATE_UINTTL_ARRAY(env.mhpmevent_val, RISCVCPU, RV_MAX_MHPMEVENTS),
        VMSTATE_UINTTL_ARRAY(env.mhpmeventh_val, RISCVCPU, RV_MAX_MHPMEVENTS),
        VMSTATE_UINTTL(env.sscratch, RISCVCPU),
        VMSTATE_UINTTL(env.mscratch, RISCVCPU),
        VMSTATE_UINT64(env.stimecmp, RISCVCPU),

        VMSTATE_END_OF_LIST()
    },
    .subsections = (const VMStateDescription * []) {
        &vmstate_pmp,
        &vmstate_hyper,
        &vmstate_vector,
        &vmstate_pointermasking,
        &vmstate_rv128,
        &vmstate_kvmtimer,
        &vmstate_envcfg,
        &vmstate_debug,
        &vmstate_smstateen,
        NULL
    }
};
Commit	Line	Data
f7697f0e YJ	1	/*
	2	* RISC-V VMState Description
	3	*
	4	* Copyright (c) 2020 Huawei Technologies Co., Ltd
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms and conditions of the GNU General Public License,
	8	* version 2 or later, as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	* more details.
	14	*
	15	* You should have received a copy of the GNU General Public License along with
	16	* this program. If not, see <http://www.gnu.org/licenses/>.
	17	*/
	18
	19	#include "qemu/osdep.h"
	20	#include "cpu.h"
	21	#include "qemu/error-report.h"
	22	#include "sysemu/kvm.h"
	23	#include "migration/cpu.h"
577f0286 LZ	24	#include "sysemu/cpu-timers.h"
577f0286 LZ	25	#include "debug.h"
f7697f0e	26
24beb03e YJ	27	static bool pmp_needed(void *opaque)
	28	{
	29	RISCVCPU *cpu = opaque;
	30	CPURISCVState *env = &cpu->env;
	31
	32	return riscv_feature(env, RISCV_FEATURE_PMP);
	33	}
	34
	35	static int pmp_post_load(void *opaque, int version_id)
	36	{
	37	RISCVCPU *cpu = opaque;
	38	CPURISCVState *env = &cpu->env;
	39	int i;
	40
	41	for (i = 0; i < MAX_RISCV_PMPS; i++) {
	42	pmp_update_rule_addr(env, i);
	43	}
	44	pmp_update_rule_nums(env);
	45
	46	return 0;
	47	}
	48
	49	static const VMStateDescription vmstate_pmp_entry = {
	50	.name = "cpu/pmp/entry",
	51	.version_id = 1,
	52	.minimum_version_id = 1,
	53	.fields = (VMStateField[]) {
	54	VMSTATE_UINTTL(addr_reg, pmp_entry_t),
	55	VMSTATE_UINT8(cfg_reg, pmp_entry_t),
	56	VMSTATE_END_OF_LIST()
	57	}
	58	};
	59
	60	static const VMStateDescription vmstate_pmp = {
	61	.name = "cpu/pmp",
	62	.version_id = 1,
	63	.minimum_version_id = 1,
	64	.needed = pmp_needed,
	65	.post_load = pmp_post_load,
	66	.fields = (VMStateField[]) {
	67	VMSTATE_STRUCT_ARRAY(env.pmp_state.pmp, RISCVCPU, MAX_RISCV_PMPS,
	68	0, vmstate_pmp_entry, pmp_entry_t),
	69	VMSTATE_END_OF_LIST()
	70	}
	71	};
	72
35e07821 YJ	73	static bool hyper_needed(void *opaque)
	74	{
	75	RISCVCPU *cpu = opaque;
	76	CPURISCVState *env = &cpu->env;
	77
	78	return riscv_has_ext(env, RVH);
	79	}
	80
edcc4e40 BM	81	static const VMStateDescription vmstate_hyper = {
edcc4e40 BM	82	.name = "cpu/hyper",
cd032fe7 AP	83	.version_id = 2,
cd032fe7 AP	84	.minimum_version_id = 2,
edcc4e40 BM	85	.needed = hyper_needed,
	86	.fields = (VMStateField[]) {
	87	VMSTATE_UINTTL(env.hstatus, RISCVCPU),
	88	VMSTATE_UINTTL(env.hedeleg, RISCVCPU),
d028ac75	89	VMSTATE_UINT64(env.hideleg, RISCVCPU),
edcc4e40 BM	90	VMSTATE_UINTTL(env.hcounteren, RISCVCPU),
	91	VMSTATE_UINTTL(env.htval, RISCVCPU),
	92	VMSTATE_UINTTL(env.htinst, RISCVCPU),
	93	VMSTATE_UINTTL(env.hgatp, RISCVCPU),
cd032fe7 AP	94	VMSTATE_UINTTL(env.hgeie, RISCVCPU),
cd032fe7 AP	95	VMSTATE_UINTTL(env.hgeip, RISCVCPU),
edcc4e40	96	VMSTATE_UINT64(env.htimedelta, RISCVCPU),
3ec0fe18	97	VMSTATE_UINT64(env.vstimecmp, RISCVCPU),
2b602398 AP	98
2b602398 AP	99	VMSTATE_UINTTL(env.hvictl, RISCVCPU),
43dc93af	100	VMSTATE_UINT8_ARRAY(env.hviprio, RISCVCPU, 64),
bb02edcd	101
edcc4e40 BM	102	VMSTATE_UINT64(env.vsstatus, RISCVCPU),
	103	VMSTATE_UINTTL(env.vstvec, RISCVCPU),
	104	VMSTATE_UINTTL(env.vsscratch, RISCVCPU),
	105	VMSTATE_UINTTL(env.vsepc, RISCVCPU),
	106	VMSTATE_UINTTL(env.vscause, RISCVCPU),
	107	VMSTATE_UINTTL(env.vstval, RISCVCPU),
	108	VMSTATE_UINTTL(env.vsatp, RISCVCPU),
d1ceff40	109	VMSTATE_UINTTL(env.vsiselect, RISCVCPU),
bb02edcd	110
edcc4e40 BM	111	VMSTATE_UINTTL(env.mtval2, RISCVCPU),
	112	VMSTATE_UINTTL(env.mtinst, RISCVCPU),
	113
	114	VMSTATE_UINTTL(env.stvec_hs, RISCVCPU),
	115	VMSTATE_UINTTL(env.sscratch_hs, RISCVCPU),
	116	VMSTATE_UINTTL(env.sepc_hs, RISCVCPU),
	117	VMSTATE_UINTTL(env.scause_hs, RISCVCPU),
	118	VMSTATE_UINTTL(env.stval_hs, RISCVCPU),
	119	VMSTATE_UINTTL(env.satp_hs, RISCVCPU),
	120	VMSTATE_UINT64(env.mstatus_hs, RISCVCPU),
	121
	122	VMSTATE_END_OF_LIST()
	123	}
	124	};
	125
	126	static bool vector_needed(void *opaque)
b1c279e1 AB	127	{
	128	RISCVCPU *cpu = opaque;
	129	CPURISCVState *env = &cpu->env;
	130
edcc4e40	131	return riscv_has_ext(env, RVV);
b1c279e1 AB	132	}
b1c279e1 AB	133
bb02edcd YJ	134	static const VMStateDescription vmstate_vector = {
bb02edcd YJ	135	.name = "cpu/vector",
d96a271a LZ	136	.version_id = 2,
d96a271a LZ	137	.minimum_version_id = 2,
bb02edcd YJ	138	.needed = vector_needed,
	139	.fields = (VMStateField[]) {
	140	VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64),
	141	VMSTATE_UINTTL(env.vxrm, RISCVCPU),
	142	VMSTATE_UINTTL(env.vxsat, RISCVCPU),
	143	VMSTATE_UINTTL(env.vl, RISCVCPU),
	144	VMSTATE_UINTTL(env.vstart, RISCVCPU),
	145	VMSTATE_UINTTL(env.vtype, RISCVCPU),
d96a271a	146	VMSTATE_BOOL(env.vill, RISCVCPU),
bb02edcd YJ	147	VMSTATE_END_OF_LIST()
	148	}
	149	};
	150
edcc4e40 BM	151	static bool pointermasking_needed(void *opaque)
	152	{
	153	RISCVCPU *cpu = opaque;
	154	CPURISCVState *env = &cpu->env;
	155
	156	return riscv_has_ext(env, RVJ);
	157	}
	158
b1c279e1 AB	159	static const VMStateDescription vmstate_pointermasking = {
	160	.name = "cpu/pointer_masking",
	161	.version_id = 1,
	162	.minimum_version_id = 1,
	163	.needed = pointermasking_needed,
	164	.fields = (VMStateField[]) {
	165	VMSTATE_UINTTL(env.mmte, RISCVCPU),
	166	VMSTATE_UINTTL(env.mpmmask, RISCVCPU),
	167	VMSTATE_UINTTL(env.mpmbase, RISCVCPU),
	168	VMSTATE_UINTTL(env.spmmask, RISCVCPU),
	169	VMSTATE_UINTTL(env.spmbase, RISCVCPU),
	170	VMSTATE_UINTTL(env.upmmask, RISCVCPU),
	171	VMSTATE_UINTTL(env.upmbase, RISCVCPU),
	172
	173	VMSTATE_END_OF_LIST()
	174	}
	175	};
	176
2b547084 FP	177	static bool rv128_needed(void *opaque)
	178	{
	179	RISCVCPU *cpu = opaque;
	180	CPURISCVState *env = &cpu->env;
	181
	182	return env->misa_mxl_max == MXL_RV128;
	183	}
	184
	185	static const VMStateDescription vmstate_rv128 = {
	186	.name = "cpu/rv128",
	187	.version_id = 1,
	188	.minimum_version_id = 1,
	189	.needed = rv128_needed,
	190	.fields = (VMStateField[]) {
	191	VMSTATE_UINTTL_ARRAY(env.gprh, RISCVCPU, 32),
2c64ab66 FP	192	VMSTATE_UINT64(env.mscratchh, RISCVCPU),
2c64ab66 FP	193	VMSTATE_UINT64(env.sscratchh, RISCVCPU),
2b547084 FP	194	VMSTATE_END_OF_LIST()
	195	}
	196	};
	197
1eb9a5da YJ	198	static bool kvmtimer_needed(void *opaque)
	199	{
	200	return kvm_enabled();
	201	}
	202
	203	static int cpu_post_load(void *opaque, int version_id)
	204	{
	205	RISCVCPU *cpu = opaque;
	206	CPURISCVState *env = &cpu->env;
	207
	208	env->kvm_timer_dirty = true;
	209	return 0;
	210	}
	211
	212	static const VMStateDescription vmstate_kvmtimer = {
	213	.name = "cpu/kvmtimer",
	214	.version_id = 1,
	215	.minimum_version_id = 1,
	216	.needed = kvmtimer_needed,
	217	.post_load = cpu_post_load,
	218	.fields = (VMStateField[]) {
	219	VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU),
	220	VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU),
	221	VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU),
38b4e781 BM	222	VMSTATE_END_OF_LIST()
	223	}
	224	};
	225
	226	static bool debug_needed(void *opaque)
	227	{
	228	RISCVCPU *cpu = opaque;
	229	CPURISCVState *env = &cpu->env;
	230
	231	return riscv_feature(env, RISCV_FEATURE_DEBUG);
	232	}
1eb9a5da	233
577f0286 LZ	234	static int debug_post_load(void *opaque, int version_id)
	235	{
	236	RISCVCPU *cpu = opaque;
	237	CPURISCVState *env = &cpu->env;
	238
	239	if (icount_enabled()) {
	240	env->itrigger_enabled = riscv_itrigger_enabled(env);
	241	}
	242
	243	return 0;
	244	}
	245
38b4e781 BM	246	static const VMStateDescription vmstate_debug = {
38b4e781 BM	247	.name = "cpu/debug",
9495c488 FC	248	.version_id = 2,
9495c488 FC	249	.minimum_version_id = 2,
38b4e781	250	.needed = debug_needed,
577f0286	251	.post_load = debug_post_load,
38b4e781 BM	252	.fields = (VMStateField[]) {
38b4e781 BM	253	VMSTATE_UINTTL(env.trigger_cur, RISCVCPU),
9495c488 FC	254	VMSTATE_UINTTL_ARRAY(env.tdata1, RISCVCPU, RV_MAX_TRIGGERS),
	255	VMSTATE_UINTTL_ARRAY(env.tdata2, RISCVCPU, RV_MAX_TRIGGERS),
	256	VMSTATE_UINTTL_ARRAY(env.tdata3, RISCVCPU, RV_MAX_TRIGGERS),
1eb9a5da YJ	257	VMSTATE_END_OF_LIST()
	258	}
	259	};
	260
440544e1 LZ	261	static int riscv_cpu_post_load(void *opaque, int version_id)
	262	{
	263	RISCVCPU *cpu = opaque;
	264	CPURISCVState *env = &cpu->env;
	265
	266	env->xl = cpu_recompute_xl(env);
40bfa5f6	267	riscv_cpu_update_mask(env);
440544e1 LZ	268	return 0;
	269	}
	270
3bee0e40 MC	271	static bool smstateen_needed(void *opaque)
	272	{
	273	RISCVCPU *cpu = opaque;
	274
	275	return cpu->cfg.ext_smstateen;
	276	}
	277
	278	static const VMStateDescription vmstate_smstateen = {
	279	.name = "cpu/smtateen",
	280	.version_id = 1,
	281	.minimum_version_id = 1,
	282	.needed = smstateen_needed,
	283	.fields = (VMStateField[]) {
	284	VMSTATE_UINT64_ARRAY(env.mstateen, RISCVCPU, 4),
	285	VMSTATE_UINT64_ARRAY(env.hstateen, RISCVCPU, 4),
	286	VMSTATE_UINT64_ARRAY(env.sstateen, RISCVCPU, 4),
	287	VMSTATE_END_OF_LIST()
	288	}
	289	};
	290
29a9ec9b AP	291	static bool envcfg_needed(void *opaque)
	292	{
	293	RISCVCPU *cpu = opaque;
	294	CPURISCVState *env = &cpu->env;
	295
	296	return (env->priv_ver >= PRIV_VERSION_1_12_0 ? 1 : 0);
	297	}
	298
	299	static const VMStateDescription vmstate_envcfg = {
	300	.name = "cpu/envcfg",
	301	.version_id = 1,
	302	.minimum_version_id = 1,
	303	.needed = envcfg_needed,
	304	.fields = (VMStateField[]) {
	305	VMSTATE_UINT64(env.menvcfg, RISCVCPU),
	306	VMSTATE_UINTTL(env.senvcfg, RISCVCPU),
	307	VMSTATE_UINT64(env.henvcfg, RISCVCPU),
3780e337 AP	308	VMSTATE_END_OF_LIST()
	309	}
	310	};
	311
	312	static bool pmu_needed(void *opaque)
	313	{
	314	RISCVCPU *cpu = opaque;
29a9ec9b	315
3780e337 AP	316	return cpu->cfg.pmu_num;
	317	}
	318
	319	static const VMStateDescription vmstate_pmu_ctr_state = {
	320	.name = "cpu/pmu",
	321	.version_id = 1,
	322	.minimum_version_id = 1,
	323	.needed = pmu_needed,
	324	.fields = (VMStateField[]) {
	325	VMSTATE_UINTTL(mhpmcounter_val, PMUCTRState),
	326	VMSTATE_UINTTL(mhpmcounterh_val, PMUCTRState),
	327	VMSTATE_UINTTL(mhpmcounter_prev, PMUCTRState),
	328	VMSTATE_UINTTL(mhpmcounterh_prev, PMUCTRState),
	329	VMSTATE_BOOL(started, PMUCTRState),
29a9ec9b AP	330	VMSTATE_END_OF_LIST()
	331	}
	332	};
	333
f7697f0e YJ	334	const VMStateDescription vmstate_riscv_cpu = {
f7697f0e YJ	335	.name = "cpu",
1237c2d6 BM	336	.version_id = 6,
1237c2d6 BM	337	.minimum_version_id = 6,
440544e1	338	.post_load = riscv_cpu_post_load,
f7697f0e YJ	339	.fields = (VMStateField[]) {
	340	VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
	341	VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
43dc93af AP	342	VMSTATE_UINT8_ARRAY(env.miprio, RISCVCPU, 64),
43dc93af AP	343	VMSTATE_UINT8_ARRAY(env.siprio, RISCVCPU, 64),
f7697f0e YJ	344	VMSTATE_UINTTL(env.pc, RISCVCPU),
	345	VMSTATE_UINTTL(env.load_res, RISCVCPU),
	346	VMSTATE_UINTTL(env.load_val, RISCVCPU),
	347	VMSTATE_UINTTL(env.frm, RISCVCPU),
	348	VMSTATE_UINTTL(env.badaddr, RISCVCPU),
	349	VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU),
	350	VMSTATE_UINTTL(env.priv_ver, RISCVCPU),
	351	VMSTATE_UINTTL(env.vext_ver, RISCVCPU),
e91a7227 RH	352	VMSTATE_UINT32(env.misa_mxl, RISCVCPU),
	353	VMSTATE_UINT32(env.misa_ext, RISCVCPU),
	354	VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU),
	355	VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU),
f7697f0e YJ	356	VMSTATE_UINT32(env.features, RISCVCPU),
	357	VMSTATE_UINTTL(env.priv, RISCVCPU),
	358	VMSTATE_UINTTL(env.virt, RISCVCPU),
277b210d	359	VMSTATE_UINT64(env.resetvec, RISCVCPU),
f7697f0e YJ	360	VMSTATE_UINTTL(env.mhartid, RISCVCPU),
f7697f0e YJ	361	VMSTATE_UINT64(env.mstatus, RISCVCPU),
d028ac75 AP	362	VMSTATE_UINT64(env.mip, RISCVCPU),
	363	VMSTATE_UINT64(env.miclaim, RISCVCPU),
	364	VMSTATE_UINT64(env.mie, RISCVCPU),
	365	VMSTATE_UINT64(env.mideleg, RISCVCPU),
f7697f0e	366	VMSTATE_UINTTL(env.satp, RISCVCPU),
ac12b601	367	VMSTATE_UINTTL(env.stval, RISCVCPU),
f7697f0e YJ	368	VMSTATE_UINTTL(env.medeleg, RISCVCPU),
	369	VMSTATE_UINTTL(env.stvec, RISCVCPU),
	370	VMSTATE_UINTTL(env.sepc, RISCVCPU),
	371	VMSTATE_UINTTL(env.scause, RISCVCPU),
	372	VMSTATE_UINTTL(env.mtvec, RISCVCPU),
	373	VMSTATE_UINTTL(env.mepc, RISCVCPU),
	374	VMSTATE_UINTTL(env.mcause, RISCVCPU),
	375	VMSTATE_UINTTL(env.mtval, RISCVCPU),
d1ceff40 AP	376	VMSTATE_UINTTL(env.miselect, RISCVCPU),
d1ceff40 AP	377	VMSTATE_UINTTL(env.siselect, RISCVCPU),
f7697f0e YJ	378	VMSTATE_UINTTL(env.scounteren, RISCVCPU),
f7697f0e YJ	379	VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
b1675eeb	380	VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU),
3780e337 AP	381	VMSTATE_STRUCT_ARRAY(env.pmu_ctrs, RISCVCPU, RV_MAX_MHPMCOUNTERS, 0,
3780e337 AP	382	vmstate_pmu_ctr_state, PMUCTRState),
621f35bb	383	VMSTATE_UINTTL_ARRAY(env.mhpmevent_val, RISCVCPU, RV_MAX_MHPMEVENTS),
14664483	384	VMSTATE_UINTTL_ARRAY(env.mhpmeventh_val, RISCVCPU, RV_MAX_MHPMEVENTS),
f7697f0e YJ	385	VMSTATE_UINTTL(env.sscratch, RISCVCPU),
f7697f0e YJ	386	VMSTATE_UINTTL(env.mscratch, RISCVCPU),
43888c2f	387	VMSTATE_UINT64(env.stimecmp, RISCVCPU),
f7697f0e YJ	388
f7697f0e YJ	389	VMSTATE_END_OF_LIST()
24beb03e YJ	390	},
	391	.subsections = (const VMStateDescription * []) {
	392	&vmstate_pmp,
35e07821	393	&vmstate_hyper,
bb02edcd	394	&vmstate_vector,
b1c279e1	395	&vmstate_pointermasking,
2b547084	396	&vmstate_rv128,
1eb9a5da	397	&vmstate_kvmtimer,
29a9ec9b	398	&vmstate_envcfg,
38b4e781	399	&vmstate_debug,
3bee0e40	400	&vmstate_smstateen,
24beb03e	401	NULL
f7697f0e YJ	402	}
f7697f0e YJ	403	};