[mirror_qemu.git] / target / riscv / machine.c

/*
 * RISC-V VMState Description
 *
 * Copyright (c) 2020 Huawei Technologies Co., Ltd
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2 or later, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "cpu.h"
#include "qemu/error-report.h"
#include "sysemu/kvm.h"
#include "migration/cpu.h"

static bool pmp_needed(void *opaque)
{
    RISCVCPU *cpu = opaque;
    CPURISCVState *env = &cpu->env;

    return riscv_feature(env, RISCV_FEATURE_PMP);
}

static int pmp_post_load(void *opaque, int version_id)
{
    RISCVCPU *cpu = opaque;
    CPURISCVState *env = &cpu->env;
    int i;

    for (i = 0; i < MAX_RISCV_PMPS; i++) {
        pmp_update_rule_addr(env, i);
    }
    pmp_update_rule_nums(env);

    return 0;
}

static const VMStateDescription vmstate_pmp_entry = {
    .name = "cpu/pmp/entry",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINTTL(addr_reg, pmp_entry_t),
        VMSTATE_UINT8(cfg_reg, pmp_entry_t),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_pmp = {
    .name = "cpu/pmp",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = pmp_needed,
    .post_load = pmp_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_STRUCT_ARRAY(env.pmp_state.pmp, RISCVCPU, MAX_RISCV_PMPS,
                             0, vmstate_pmp_entry, pmp_entry_t),
        VMSTATE_END_OF_LIST()
    }
};

static bool hyper_needed(void *opaque)
{
    RISCVCPU *cpu = opaque;
    CPURISCVState *env = &cpu->env;

    return riscv_has_ext(env, RVH);
}

static const VMStateDescription vmstate_hyper = {
    .name = "cpu/hyper",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = hyper_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINTTL(env.hstatus, RISCVCPU),
        VMSTATE_UINTTL(env.hedeleg, RISCVCPU),
        VMSTATE_UINTTL(env.hideleg, RISCVCPU),
        VMSTATE_UINTTL(env.hcounteren, RISCVCPU),
        VMSTATE_UINTTL(env.htval, RISCVCPU),
        VMSTATE_UINTTL(env.htinst, RISCVCPU),
        VMSTATE_UINTTL(env.hgatp, RISCVCPU),
        VMSTATE_UINT64(env.htimedelta, RISCVCPU),

        VMSTATE_UINT64(env.vsstatus, RISCVCPU),
        VMSTATE_UINTTL(env.vstvec, RISCVCPU),
        VMSTATE_UINTTL(env.vsscratch, RISCVCPU),
        VMSTATE_UINTTL(env.vsepc, RISCVCPU),
        VMSTATE_UINTTL(env.vscause, RISCVCPU),
        VMSTATE_UINTTL(env.vstval, RISCVCPU),
        VMSTATE_UINTTL(env.vsatp, RISCVCPU),

        VMSTATE_UINTTL(env.mtval2, RISCVCPU),
        VMSTATE_UINTTL(env.mtinst, RISCVCPU),

        VMSTATE_UINTTL(env.stvec_hs, RISCVCPU),
        VMSTATE_UINTTL(env.sscratch_hs, RISCVCPU),
        VMSTATE_UINTTL(env.sepc_hs, RISCVCPU),
        VMSTATE_UINTTL(env.scause_hs, RISCVCPU),
        VMSTATE_UINTTL(env.stval_hs, RISCVCPU),
        VMSTATE_UINTTL(env.satp_hs, RISCVCPU),
        VMSTATE_UINT64(env.mstatus_hs, RISCVCPU),

        VMSTATE_END_OF_LIST()
    }
};

static bool vector_needed(void *opaque)
{
    RISCVCPU *cpu = opaque;
    CPURISCVState *env = &cpu->env;

    return riscv_has_ext(env, RVV);
}

static const VMStateDescription vmstate_vector = {
    .name = "cpu/vector",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = vector_needed,
    .fields = (VMStateField[]) {
            VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64),
            VMSTATE_UINTTL(env.vxrm, RISCVCPU),
            VMSTATE_UINTTL(env.vxsat, RISCVCPU),
            VMSTATE_UINTTL(env.vl, RISCVCPU),
            VMSTATE_UINTTL(env.vstart, RISCVCPU),
            VMSTATE_UINTTL(env.vtype, RISCVCPU),
            VMSTATE_END_OF_LIST()
        }
};

static bool pointermasking_needed(void *opaque)
{
    RISCVCPU *cpu = opaque;
    CPURISCVState *env = &cpu->env;

    return riscv_has_ext(env, RVJ);
}

static const VMStateDescription vmstate_pointermasking = {
    .name = "cpu/pointer_masking",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = pointermasking_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINTTL(env.mmte, RISCVCPU),
        VMSTATE_UINTTL(env.mpmmask, RISCVCPU),
        VMSTATE_UINTTL(env.mpmbase, RISCVCPU),
        VMSTATE_UINTTL(env.spmmask, RISCVCPU),
        VMSTATE_UINTTL(env.spmbase, RISCVCPU),
        VMSTATE_UINTTL(env.upmmask, RISCVCPU),
        VMSTATE_UINTTL(env.upmbase, RISCVCPU),

        VMSTATE_END_OF_LIST()
    }
};

static bool rv128_needed(void *opaque)
{
    RISCVCPU *cpu = opaque;
    CPURISCVState *env = &cpu->env;

    return env->misa_mxl_max == MXL_RV128;
}

static const VMStateDescription vmstate_rv128 = {
    .name = "cpu/rv128",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = rv128_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINTTL_ARRAY(env.gprh, RISCVCPU, 32),
        VMSTATE_UINT64(env.mscratchh, RISCVCPU),
        VMSTATE_UINT64(env.sscratchh, RISCVCPU),
        VMSTATE_END_OF_LIST()
    }
};

static bool kvmtimer_needed(void *opaque)
{
    return kvm_enabled();
}

static int cpu_post_load(void *opaque, int version_id)
{
    RISCVCPU *cpu = opaque;
    CPURISCVState *env = &cpu->env;

    env->kvm_timer_dirty = true;
    return 0;
}

static const VMStateDescription vmstate_kvmtimer = {
    .name = "cpu/kvmtimer",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = kvmtimer_needed,
    .post_load = cpu_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU),
        VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU),
        VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU),

        VMSTATE_END_OF_LIST()
    }
};

static int riscv_cpu_post_load(void *opaque, int version_id)
{
    RISCVCPU *cpu = opaque;
    CPURISCVState *env = &cpu->env;

    env->xl = cpu_recompute_xl(env);
    return 0;
}

const VMStateDescription vmstate_riscv_cpu = {
    .name = "cpu",
    .version_id = 3,
    .minimum_version_id = 3,
    .post_load = riscv_cpu_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
        VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
        VMSTATE_UINTTL(env.pc, RISCVCPU),
        VMSTATE_UINTTL(env.load_res, RISCVCPU),
        VMSTATE_UINTTL(env.load_val, RISCVCPU),
        VMSTATE_UINTTL(env.frm, RISCVCPU),
        VMSTATE_UINTTL(env.badaddr, RISCVCPU),
        VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU),
        VMSTATE_UINTTL(env.priv_ver, RISCVCPU),
        VMSTATE_UINTTL(env.vext_ver, RISCVCPU),
        VMSTATE_UINT32(env.misa_mxl, RISCVCPU),
        VMSTATE_UINT32(env.misa_ext, RISCVCPU),
        VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU),
        VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU),
        VMSTATE_UINT32(env.features, RISCVCPU),
        VMSTATE_UINTTL(env.priv, RISCVCPU),
        VMSTATE_UINTTL(env.virt, RISCVCPU),
        VMSTATE_UINTTL(env.resetvec, RISCVCPU),
        VMSTATE_UINTTL(env.mhartid, RISCVCPU),
        VMSTATE_UINT64(env.mstatus, RISCVCPU),
        VMSTATE_UINTTL(env.mip, RISCVCPU),
        VMSTATE_UINT32(env.miclaim, RISCVCPU),
        VMSTATE_UINTTL(env.mie, RISCVCPU),
        VMSTATE_UINTTL(env.mideleg, RISCVCPU),
        VMSTATE_UINTTL(env.satp, RISCVCPU),
        VMSTATE_UINTTL(env.stval, RISCVCPU),
        VMSTATE_UINTTL(env.medeleg, RISCVCPU),
        VMSTATE_UINTTL(env.stvec, RISCVCPU),
        VMSTATE_UINTTL(env.sepc, RISCVCPU),
        VMSTATE_UINTTL(env.scause, RISCVCPU),
        VMSTATE_UINTTL(env.mtvec, RISCVCPU),
        VMSTATE_UINTTL(env.mepc, RISCVCPU),
        VMSTATE_UINTTL(env.mcause, RISCVCPU),
        VMSTATE_UINTTL(env.mtval, RISCVCPU),
        VMSTATE_UINTTL(env.scounteren, RISCVCPU),
        VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
        VMSTATE_UINTTL(env.sscratch, RISCVCPU),
        VMSTATE_UINTTL(env.mscratch, RISCVCPU),
        VMSTATE_UINT64(env.mfromhost, RISCVCPU),
        VMSTATE_UINT64(env.mtohost, RISCVCPU),
        VMSTATE_UINT64(env.timecmp, RISCVCPU),

        VMSTATE_END_OF_LIST()
    },
    .subsections = (const VMStateDescription * []) {
        &vmstate_pmp,
        &vmstate_hyper,
        &vmstate_vector,
        &vmstate_pointermasking,
        &vmstate_rv128,
        &vmstate_kvmtimer,
        NULL
    }
};
Commit	Line	Data
f7697f0e YJ	1	/*
	2	* RISC-V VMState Description
	3	*
	4	* Copyright (c) 2020 Huawei Technologies Co., Ltd
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms and conditions of the GNU General Public License,
	8	* version 2 or later, as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	* more details.
	14	*
	15	* You should have received a copy of the GNU General Public License along with
	16	* this program. If not, see <http://www.gnu.org/licenses/>.
	17	*/
	18
	19	#include "qemu/osdep.h"
	20	#include "cpu.h"
	21	#include "qemu/error-report.h"
	22	#include "sysemu/kvm.h"
	23	#include "migration/cpu.h"
	24
24beb03e YJ	25	static bool pmp_needed(void *opaque)
	26	{
	27	RISCVCPU *cpu = opaque;
	28	CPURISCVState *env = &cpu->env;
	29
	30	return riscv_feature(env, RISCV_FEATURE_PMP);
	31	}
	32
	33	static int pmp_post_load(void *opaque, int version_id)
	34	{
	35	RISCVCPU *cpu = opaque;
	36	CPURISCVState *env = &cpu->env;
	37	int i;
	38
	39	for (i = 0; i < MAX_RISCV_PMPS; i++) {
	40	pmp_update_rule_addr(env, i);
	41	}
	42	pmp_update_rule_nums(env);
	43
	44	return 0;
	45	}
	46
	47	static const VMStateDescription vmstate_pmp_entry = {
	48	.name = "cpu/pmp/entry",
	49	.version_id = 1,
	50	.minimum_version_id = 1,
	51	.fields = (VMStateField[]) {
	52	VMSTATE_UINTTL(addr_reg, pmp_entry_t),
	53	VMSTATE_UINT8(cfg_reg, pmp_entry_t),
	54	VMSTATE_END_OF_LIST()
	55	}
	56	};
	57
	58	static const VMStateDescription vmstate_pmp = {
	59	.name = "cpu/pmp",
	60	.version_id = 1,
	61	.minimum_version_id = 1,
	62	.needed = pmp_needed,
	63	.post_load = pmp_post_load,
	64	.fields = (VMStateField[]) {
	65	VMSTATE_STRUCT_ARRAY(env.pmp_state.pmp, RISCVCPU, MAX_RISCV_PMPS,
	66	0, vmstate_pmp_entry, pmp_entry_t),
	67	VMSTATE_END_OF_LIST()
	68	}
	69	};
	70
35e07821 YJ	71	static bool hyper_needed(void *opaque)
	72	{
	73	RISCVCPU *cpu = opaque;
	74	CPURISCVState *env = &cpu->env;
	75
	76	return riscv_has_ext(env, RVH);
	77	}
	78
edcc4e40 BM	79	static const VMStateDescription vmstate_hyper = {
	80	.name = "cpu/hyper",
	81	.version_id = 1,
	82	.minimum_version_id = 1,
	83	.needed = hyper_needed,
	84	.fields = (VMStateField[]) {
	85	VMSTATE_UINTTL(env.hstatus, RISCVCPU),
	86	VMSTATE_UINTTL(env.hedeleg, RISCVCPU),
	87	VMSTATE_UINTTL(env.hideleg, RISCVCPU),
	88	VMSTATE_UINTTL(env.hcounteren, RISCVCPU),
	89	VMSTATE_UINTTL(env.htval, RISCVCPU),
	90	VMSTATE_UINTTL(env.htinst, RISCVCPU),
	91	VMSTATE_UINTTL(env.hgatp, RISCVCPU),
	92	VMSTATE_UINT64(env.htimedelta, RISCVCPU),
bb02edcd	93
edcc4e40 BM	94	VMSTATE_UINT64(env.vsstatus, RISCVCPU),
	95	VMSTATE_UINTTL(env.vstvec, RISCVCPU),
	96	VMSTATE_UINTTL(env.vsscratch, RISCVCPU),
	97	VMSTATE_UINTTL(env.vsepc, RISCVCPU),
	98	VMSTATE_UINTTL(env.vscause, RISCVCPU),
	99	VMSTATE_UINTTL(env.vstval, RISCVCPU),
	100	VMSTATE_UINTTL(env.vsatp, RISCVCPU),
bb02edcd	101
edcc4e40 BM	102	VMSTATE_UINTTL(env.mtval2, RISCVCPU),
	103	VMSTATE_UINTTL(env.mtinst, RISCVCPU),
	104
	105	VMSTATE_UINTTL(env.stvec_hs, RISCVCPU),
	106	VMSTATE_UINTTL(env.sscratch_hs, RISCVCPU),
	107	VMSTATE_UINTTL(env.sepc_hs, RISCVCPU),
	108	VMSTATE_UINTTL(env.scause_hs, RISCVCPU),
	109	VMSTATE_UINTTL(env.stval_hs, RISCVCPU),
	110	VMSTATE_UINTTL(env.satp_hs, RISCVCPU),
	111	VMSTATE_UINT64(env.mstatus_hs, RISCVCPU),
	112
	113	VMSTATE_END_OF_LIST()
	114	}
	115	};
	116
	117	static bool vector_needed(void *opaque)
b1c279e1 AB	118	{
	119	RISCVCPU *cpu = opaque;
	120	CPURISCVState *env = &cpu->env;
	121
edcc4e40	122	return riscv_has_ext(env, RVV);
b1c279e1 AB	123	}
b1c279e1 AB	124
bb02edcd YJ	125	static const VMStateDescription vmstate_vector = {
	126	.name = "cpu/vector",
	127	.version_id = 1,
	128	.minimum_version_id = 1,
	129	.needed = vector_needed,
	130	.fields = (VMStateField[]) {
	131	VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64),
	132	VMSTATE_UINTTL(env.vxrm, RISCVCPU),
	133	VMSTATE_UINTTL(env.vxsat, RISCVCPU),
	134	VMSTATE_UINTTL(env.vl, RISCVCPU),
	135	VMSTATE_UINTTL(env.vstart, RISCVCPU),
	136	VMSTATE_UINTTL(env.vtype, RISCVCPU),
	137	VMSTATE_END_OF_LIST()
	138	}
	139	};
	140
edcc4e40 BM	141	static bool pointermasking_needed(void *opaque)
	142	{
	143	RISCVCPU *cpu = opaque;
	144	CPURISCVState *env = &cpu->env;
	145
	146	return riscv_has_ext(env, RVJ);
	147	}
	148
b1c279e1 AB	149	static const VMStateDescription vmstate_pointermasking = {
	150	.name = "cpu/pointer_masking",
	151	.version_id = 1,
	152	.minimum_version_id = 1,
	153	.needed = pointermasking_needed,
	154	.fields = (VMStateField[]) {
	155	VMSTATE_UINTTL(env.mmte, RISCVCPU),
	156	VMSTATE_UINTTL(env.mpmmask, RISCVCPU),
	157	VMSTATE_UINTTL(env.mpmbase, RISCVCPU),
	158	VMSTATE_UINTTL(env.spmmask, RISCVCPU),
	159	VMSTATE_UINTTL(env.spmbase, RISCVCPU),
	160	VMSTATE_UINTTL(env.upmmask, RISCVCPU),
	161	VMSTATE_UINTTL(env.upmbase, RISCVCPU),
	162
	163	VMSTATE_END_OF_LIST()
	164	}
	165	};
	166
2b547084 FP	167	static bool rv128_needed(void *opaque)
	168	{
	169	RISCVCPU *cpu = opaque;
	170	CPURISCVState *env = &cpu->env;
	171
	172	return env->misa_mxl_max == MXL_RV128;
	173	}
	174
	175	static const VMStateDescription vmstate_rv128 = {
	176	.name = "cpu/rv128",
	177	.version_id = 1,
	178	.minimum_version_id = 1,
	179	.needed = rv128_needed,
	180	.fields = (VMStateField[]) {
	181	VMSTATE_UINTTL_ARRAY(env.gprh, RISCVCPU, 32),
2c64ab66 FP	182	VMSTATE_UINT64(env.mscratchh, RISCVCPU),
2c64ab66 FP	183	VMSTATE_UINT64(env.sscratchh, RISCVCPU),
2b547084 FP	184	VMSTATE_END_OF_LIST()
	185	}
	186	};
	187
1eb9a5da YJ	188	static bool kvmtimer_needed(void *opaque)
	189	{
	190	return kvm_enabled();
	191	}
	192
	193	static int cpu_post_load(void *opaque, int version_id)
	194	{
	195	RISCVCPU *cpu = opaque;
	196	CPURISCVState *env = &cpu->env;
	197
	198	env->kvm_timer_dirty = true;
	199	return 0;
	200	}
	201
	202	static const VMStateDescription vmstate_kvmtimer = {
	203	.name = "cpu/kvmtimer",
	204	.version_id = 1,
	205	.minimum_version_id = 1,
	206	.needed = kvmtimer_needed,
	207	.post_load = cpu_post_load,
	208	.fields = (VMStateField[]) {
	209	VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU),
	210	VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU),
	211	VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU),
	212
	213	VMSTATE_END_OF_LIST()
	214	}
	215	};
	216
440544e1 LZ	217	static int riscv_cpu_post_load(void *opaque, int version_id)
	218	{
	219	RISCVCPU *cpu = opaque;
	220	CPURISCVState *env = &cpu->env;
	221
	222	env->xl = cpu_recompute_xl(env);
	223	return 0;
	224	}
	225
f7697f0e YJ	226	const VMStateDescription vmstate_riscv_cpu = {
f7697f0e YJ	227	.name = "cpu",
e91a7227 RH	228	.version_id = 3,
e91a7227 RH	229	.minimum_version_id = 3,
440544e1	230	.post_load = riscv_cpu_post_load,
f7697f0e YJ	231	.fields = (VMStateField[]) {
	232	VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
	233	VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
	234	VMSTATE_UINTTL(env.pc, RISCVCPU),
	235	VMSTATE_UINTTL(env.load_res, RISCVCPU),
	236	VMSTATE_UINTTL(env.load_val, RISCVCPU),
	237	VMSTATE_UINTTL(env.frm, RISCVCPU),
	238	VMSTATE_UINTTL(env.badaddr, RISCVCPU),
	239	VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU),
	240	VMSTATE_UINTTL(env.priv_ver, RISCVCPU),
	241	VMSTATE_UINTTL(env.vext_ver, RISCVCPU),
e91a7227 RH	242	VMSTATE_UINT32(env.misa_mxl, RISCVCPU),
	243	VMSTATE_UINT32(env.misa_ext, RISCVCPU),
	244	VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU),
	245	VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU),
f7697f0e YJ	246	VMSTATE_UINT32(env.features, RISCVCPU),
	247	VMSTATE_UINTTL(env.priv, RISCVCPU),
	248	VMSTATE_UINTTL(env.virt, RISCVCPU),
	249	VMSTATE_UINTTL(env.resetvec, RISCVCPU),
	250	VMSTATE_UINTTL(env.mhartid, RISCVCPU),
	251	VMSTATE_UINT64(env.mstatus, RISCVCPU),
	252	VMSTATE_UINTTL(env.mip, RISCVCPU),
	253	VMSTATE_UINT32(env.miclaim, RISCVCPU),
	254	VMSTATE_UINTTL(env.mie, RISCVCPU),
	255	VMSTATE_UINTTL(env.mideleg, RISCVCPU),
f7697f0e	256	VMSTATE_UINTTL(env.satp, RISCVCPU),
ac12b601	257	VMSTATE_UINTTL(env.stval, RISCVCPU),
f7697f0e YJ	258	VMSTATE_UINTTL(env.medeleg, RISCVCPU),
	259	VMSTATE_UINTTL(env.stvec, RISCVCPU),
	260	VMSTATE_UINTTL(env.sepc, RISCVCPU),
	261	VMSTATE_UINTTL(env.scause, RISCVCPU),
	262	VMSTATE_UINTTL(env.mtvec, RISCVCPU),
	263	VMSTATE_UINTTL(env.mepc, RISCVCPU),
	264	VMSTATE_UINTTL(env.mcause, RISCVCPU),
	265	VMSTATE_UINTTL(env.mtval, RISCVCPU),
	266	VMSTATE_UINTTL(env.scounteren, RISCVCPU),
	267	VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
	268	VMSTATE_UINTTL(env.sscratch, RISCVCPU),
	269	VMSTATE_UINTTL(env.mscratch, RISCVCPU),
	270	VMSTATE_UINT64(env.mfromhost, RISCVCPU),
	271	VMSTATE_UINT64(env.mtohost, RISCVCPU),
	272	VMSTATE_UINT64(env.timecmp, RISCVCPU),
	273
	274	VMSTATE_END_OF_LIST()
24beb03e YJ	275	},
	276	.subsections = (const VMStateDescription * []) {
	277	&vmstate_pmp,
35e07821	278	&vmstate_hyper,
bb02edcd	279	&vmstate_vector,
b1c279e1	280	&vmstate_pointermasking,
2b547084	281	&vmstate_rv128,
1eb9a5da	282	&vmstate_kvmtimer,
24beb03e	283	NULL
f7697f0e YJ	284	}
f7697f0e YJ	285	};