[mirror_qemu.git] / target / riscv / machine.c

/*
 * RISC-V VMState Description
 *
 * Copyright (c) 2020 Huawei Technologies Co., Ltd
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2 or later, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "cpu.h"
#include "qemu/error-report.h"
#include "sysemu/kvm.h"
#include "migration/cpu.h"

static bool pmp_needed(void *opaque)
{
    RISCVCPU *cpu = opaque;
    CPURISCVState *env = &cpu->env;

    return riscv_feature(env, RISCV_FEATURE_PMP);
}

static int pmp_post_load(void *opaque, int version_id)
{
    RISCVCPU *cpu = opaque;
    CPURISCVState *env = &cpu->env;
    int i;

    for (i = 0; i < MAX_RISCV_PMPS; i++) {
        pmp_update_rule_addr(env, i);
    }
    pmp_update_rule_nums(env);

    return 0;
}

static const VMStateDescription vmstate_pmp_entry = {
    .name = "cpu/pmp/entry",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINTTL(addr_reg, pmp_entry_t),
        VMSTATE_UINT8(cfg_reg, pmp_entry_t),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_pmp = {
    .name = "cpu/pmp",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = pmp_needed,
    .post_load = pmp_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_STRUCT_ARRAY(env.pmp_state.pmp, RISCVCPU, MAX_RISCV_PMPS,
                             0, vmstate_pmp_entry, pmp_entry_t),
        VMSTATE_END_OF_LIST()
    }
};

static bool hyper_needed(void *opaque)
{
    RISCVCPU *cpu = opaque;
    CPURISCVState *env = &cpu->env;

    return riscv_has_ext(env, RVH);
}

static const VMStateDescription vmstate_hyper = {
    .name = "cpu/hyper",
    .version_id = 2,
    .minimum_version_id = 2,
    .needed = hyper_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINTTL(env.hstatus, RISCVCPU),
        VMSTATE_UINTTL(env.hedeleg, RISCVCPU),
        VMSTATE_UINT64(env.hideleg, RISCVCPU),
        VMSTATE_UINTTL(env.hcounteren, RISCVCPU),
        VMSTATE_UINTTL(env.htval, RISCVCPU),
        VMSTATE_UINTTL(env.htinst, RISCVCPU),
        VMSTATE_UINTTL(env.hgatp, RISCVCPU),
        VMSTATE_UINTTL(env.hgeie, RISCVCPU),
        VMSTATE_UINTTL(env.hgeip, RISCVCPU),
        VMSTATE_UINT64(env.htimedelta, RISCVCPU),
        VMSTATE_UINT64(env.vstimecmp, RISCVCPU),

        VMSTATE_UINTTL(env.hvictl, RISCVCPU),
        VMSTATE_UINT8_ARRAY(env.hviprio, RISCVCPU, 64),

        VMSTATE_UINT64(env.vsstatus, RISCVCPU),
        VMSTATE_UINTTL(env.vstvec, RISCVCPU),
        VMSTATE_UINTTL(env.vsscratch, RISCVCPU),
        VMSTATE_UINTTL(env.vsepc, RISCVCPU),
        VMSTATE_UINTTL(env.vscause, RISCVCPU),
        VMSTATE_UINTTL(env.vstval, RISCVCPU),
        VMSTATE_UINTTL(env.vsatp, RISCVCPU),
        VMSTATE_UINTTL(env.vsiselect, RISCVCPU),

        VMSTATE_UINTTL(env.mtval2, RISCVCPU),
        VMSTATE_UINTTL(env.mtinst, RISCVCPU),

        VMSTATE_UINTTL(env.stvec_hs, RISCVCPU),
        VMSTATE_UINTTL(env.sscratch_hs, RISCVCPU),
        VMSTATE_UINTTL(env.sepc_hs, RISCVCPU),
        VMSTATE_UINTTL(env.scause_hs, RISCVCPU),
        VMSTATE_UINTTL(env.stval_hs, RISCVCPU),
        VMSTATE_UINTTL(env.satp_hs, RISCVCPU),
        VMSTATE_UINT64(env.mstatus_hs, RISCVCPU),

        VMSTATE_END_OF_LIST()
    }
};

static bool vector_needed(void *opaque)
{
    RISCVCPU *cpu = opaque;
    CPURISCVState *env = &cpu->env;

    return riscv_has_ext(env, RVV);
}

static const VMStateDescription vmstate_vector = {
    .name = "cpu/vector",
    .version_id = 2,
    .minimum_version_id = 2,
    .needed = vector_needed,
    .fields = (VMStateField[]) {
            VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64),
            VMSTATE_UINTTL(env.vxrm, RISCVCPU),
            VMSTATE_UINTTL(env.vxsat, RISCVCPU),
            VMSTATE_UINTTL(env.vl, RISCVCPU),
            VMSTATE_UINTTL(env.vstart, RISCVCPU),
            VMSTATE_UINTTL(env.vtype, RISCVCPU),
            VMSTATE_BOOL(env.vill, RISCVCPU),
            VMSTATE_END_OF_LIST()
        }
};

static bool pointermasking_needed(void *opaque)
{
    RISCVCPU *cpu = opaque;
    CPURISCVState *env = &cpu->env;

    return riscv_has_ext(env, RVJ);
}

static const VMStateDescription vmstate_pointermasking = {
    .name = "cpu/pointer_masking",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = pointermasking_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINTTL(env.mmte, RISCVCPU),
        VMSTATE_UINTTL(env.mpmmask, RISCVCPU),
        VMSTATE_UINTTL(env.mpmbase, RISCVCPU),
        VMSTATE_UINTTL(env.spmmask, RISCVCPU),
        VMSTATE_UINTTL(env.spmbase, RISCVCPU),
        VMSTATE_UINTTL(env.upmmask, RISCVCPU),
        VMSTATE_UINTTL(env.upmbase, RISCVCPU),

        VMSTATE_END_OF_LIST()
    }
};

static bool rv128_needed(void *opaque)
{
    RISCVCPU *cpu = opaque;
    CPURISCVState *env = &cpu->env;

    return env->misa_mxl_max == MXL_RV128;
}

static const VMStateDescription vmstate_rv128 = {
    .name = "cpu/rv128",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = rv128_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINTTL_ARRAY(env.gprh, RISCVCPU, 32),
        VMSTATE_UINT64(env.mscratchh, RISCVCPU),
        VMSTATE_UINT64(env.sscratchh, RISCVCPU),
        VMSTATE_END_OF_LIST()
    }
};

static bool kvmtimer_needed(void *opaque)
{
    return kvm_enabled();
}

static int cpu_post_load(void *opaque, int version_id)
{
    RISCVCPU *cpu = opaque;
    CPURISCVState *env = &cpu->env;

    env->kvm_timer_dirty = true;
    return 0;
}

static const VMStateDescription vmstate_kvmtimer = {
    .name = "cpu/kvmtimer",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = kvmtimer_needed,
    .post_load = cpu_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU),
        VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU),
        VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU),
        VMSTATE_END_OF_LIST()
    }
};

static bool debug_needed(void *opaque)
{
    RISCVCPU *cpu = opaque;
    CPURISCVState *env = &cpu->env;

    return riscv_feature(env, RISCV_FEATURE_DEBUG);
}

static const VMStateDescription vmstate_debug = {
    .name = "cpu/debug",
    .version_id = 2,
    .minimum_version_id = 2,
    .needed = debug_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINTTL(env.trigger_cur, RISCVCPU),
        VMSTATE_UINTTL_ARRAY(env.tdata1, RISCVCPU, RV_MAX_TRIGGERS),
        VMSTATE_UINTTL_ARRAY(env.tdata2, RISCVCPU, RV_MAX_TRIGGERS),
        VMSTATE_UINTTL_ARRAY(env.tdata3, RISCVCPU, RV_MAX_TRIGGERS),
        VMSTATE_END_OF_LIST()
    }
};

static int riscv_cpu_post_load(void *opaque, int version_id)
{
    RISCVCPU *cpu = opaque;
    CPURISCVState *env = &cpu->env;

    env->xl = cpu_recompute_xl(env);
    riscv_cpu_update_mask(env);
    return 0;
}

static bool smstateen_needed(void *opaque)
{
    RISCVCPU *cpu = opaque;

    return cpu->cfg.ext_smstateen;
}

static const VMStateDescription vmstate_smstateen = {
    .name = "cpu/smtateen",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = smstateen_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINT64_ARRAY(env.mstateen, RISCVCPU, 4),
        VMSTATE_UINT64_ARRAY(env.hstateen, RISCVCPU, 4),
        VMSTATE_UINT64_ARRAY(env.sstateen, RISCVCPU, 4),
        VMSTATE_END_OF_LIST()
    }
};

static bool envcfg_needed(void *opaque)
{
    RISCVCPU *cpu = opaque;
    CPURISCVState *env = &cpu->env;

    return (env->priv_ver >= PRIV_VERSION_1_12_0 ? 1 : 0);
}

static const VMStateDescription vmstate_envcfg = {
    .name = "cpu/envcfg",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = envcfg_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINT64(env.menvcfg, RISCVCPU),
        VMSTATE_UINTTL(env.senvcfg, RISCVCPU),
        VMSTATE_UINT64(env.henvcfg, RISCVCPU),
        VMSTATE_END_OF_LIST()
    }
};

static bool pmu_needed(void *opaque)
{
    RISCVCPU *cpu = opaque;

    return cpu->cfg.pmu_num;
}

static const VMStateDescription vmstate_pmu_ctr_state = {
    .name = "cpu/pmu",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = pmu_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINTTL(mhpmcounter_val, PMUCTRState),
        VMSTATE_UINTTL(mhpmcounterh_val, PMUCTRState),
        VMSTATE_UINTTL(mhpmcounter_prev, PMUCTRState),
        VMSTATE_UINTTL(mhpmcounterh_prev, PMUCTRState),
        VMSTATE_BOOL(started, PMUCTRState),
        VMSTATE_END_OF_LIST()
    }
};

const VMStateDescription vmstate_riscv_cpu = {
    .name = "cpu",
    .version_id = 5,
    .minimum_version_id = 5,
    .post_load = riscv_cpu_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
        VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
        VMSTATE_UINT8_ARRAY(env.miprio, RISCVCPU, 64),
        VMSTATE_UINT8_ARRAY(env.siprio, RISCVCPU, 64),
        VMSTATE_UINTTL(env.pc, RISCVCPU),
        VMSTATE_UINTTL(env.load_res, RISCVCPU),
        VMSTATE_UINTTL(env.load_val, RISCVCPU),
        VMSTATE_UINTTL(env.frm, RISCVCPU),
        VMSTATE_UINTTL(env.badaddr, RISCVCPU),
        VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU),
        VMSTATE_UINTTL(env.priv_ver, RISCVCPU),
        VMSTATE_UINTTL(env.vext_ver, RISCVCPU),
        VMSTATE_UINT32(env.misa_mxl, RISCVCPU),
        VMSTATE_UINT32(env.misa_ext, RISCVCPU),
        VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU),
        VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU),
        VMSTATE_UINT32(env.features, RISCVCPU),
        VMSTATE_UINTTL(env.priv, RISCVCPU),
        VMSTATE_UINTTL(env.virt, RISCVCPU),
        VMSTATE_UINT64(env.resetvec, RISCVCPU),
        VMSTATE_UINTTL(env.mhartid, RISCVCPU),
        VMSTATE_UINT64(env.mstatus, RISCVCPU),
        VMSTATE_UINT64(env.mip, RISCVCPU),
        VMSTATE_UINT64(env.miclaim, RISCVCPU),
        VMSTATE_UINT64(env.mie, RISCVCPU),
        VMSTATE_UINT64(env.mideleg, RISCVCPU),
        VMSTATE_UINTTL(env.satp, RISCVCPU),
        VMSTATE_UINTTL(env.stval, RISCVCPU),
        VMSTATE_UINTTL(env.medeleg, RISCVCPU),
        VMSTATE_UINTTL(env.stvec, RISCVCPU),
        VMSTATE_UINTTL(env.sepc, RISCVCPU),
        VMSTATE_UINTTL(env.scause, RISCVCPU),
        VMSTATE_UINTTL(env.mtvec, RISCVCPU),
        VMSTATE_UINTTL(env.mepc, RISCVCPU),
        VMSTATE_UINTTL(env.mcause, RISCVCPU),
        VMSTATE_UINTTL(env.mtval, RISCVCPU),
        VMSTATE_UINTTL(env.miselect, RISCVCPU),
        VMSTATE_UINTTL(env.siselect, RISCVCPU),
        VMSTATE_UINTTL(env.scounteren, RISCVCPU),
        VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
        VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU),
        VMSTATE_STRUCT_ARRAY(env.pmu_ctrs, RISCVCPU, RV_MAX_MHPMCOUNTERS, 0,
                             vmstate_pmu_ctr_state, PMUCTRState),
        VMSTATE_UINTTL_ARRAY(env.mhpmevent_val, RISCVCPU, RV_MAX_MHPMEVENTS),
        VMSTATE_UINTTL_ARRAY(env.mhpmeventh_val, RISCVCPU, RV_MAX_MHPMEVENTS),
        VMSTATE_UINTTL(env.sscratch, RISCVCPU),
        VMSTATE_UINTTL(env.mscratch, RISCVCPU),
        VMSTATE_UINT64(env.mfromhost, RISCVCPU),
        VMSTATE_UINT64(env.mtohost, RISCVCPU),
        VMSTATE_UINT64(env.stimecmp, RISCVCPU),

        VMSTATE_END_OF_LIST()
    },
    .subsections = (const VMStateDescription * []) {
        &vmstate_pmp,
        &vmstate_hyper,
        &vmstate_vector,
        &vmstate_pointermasking,
        &vmstate_rv128,
        &vmstate_kvmtimer,
        &vmstate_envcfg,
        &vmstate_debug,
        &vmstate_smstateen,
        NULL
    }
};
Commit	Line	Data
f7697f0e YJ	1	/*
	2	* RISC-V VMState Description
	3	*
	4	* Copyright (c) 2020 Huawei Technologies Co., Ltd
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms and conditions of the GNU General Public License,
	8	* version 2 or later, as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	* more details.
	14	*
	15	* You should have received a copy of the GNU General Public License along with
	16	* this program. If not, see <http://www.gnu.org/licenses/>.
	17	*/
	18
	19	#include "qemu/osdep.h"
	20	#include "cpu.h"
	21	#include "qemu/error-report.h"
	22	#include "sysemu/kvm.h"
	23	#include "migration/cpu.h"
	24
24beb03e YJ	25	static bool pmp_needed(void *opaque)
	26	{
	27	RISCVCPU *cpu = opaque;
	28	CPURISCVState *env = &cpu->env;
	29
	30	return riscv_feature(env, RISCV_FEATURE_PMP);
	31	}
	32
	33	static int pmp_post_load(void *opaque, int version_id)
	34	{
	35	RISCVCPU *cpu = opaque;
	36	CPURISCVState *env = &cpu->env;
	37	int i;
	38
	39	for (i = 0; i < MAX_RISCV_PMPS; i++) {
	40	pmp_update_rule_addr(env, i);
	41	}
	42	pmp_update_rule_nums(env);
	43
	44	return 0;
	45	}
	46
	47	static const VMStateDescription vmstate_pmp_entry = {
	48	.name = "cpu/pmp/entry",
	49	.version_id = 1,
	50	.minimum_version_id = 1,
	51	.fields = (VMStateField[]) {
	52	VMSTATE_UINTTL(addr_reg, pmp_entry_t),
	53	VMSTATE_UINT8(cfg_reg, pmp_entry_t),
	54	VMSTATE_END_OF_LIST()
	55	}
	56	};
	57
	58	static const VMStateDescription vmstate_pmp = {
	59	.name = "cpu/pmp",
	60	.version_id = 1,
	61	.minimum_version_id = 1,
	62	.needed = pmp_needed,
	63	.post_load = pmp_post_load,
	64	.fields = (VMStateField[]) {
	65	VMSTATE_STRUCT_ARRAY(env.pmp_state.pmp, RISCVCPU, MAX_RISCV_PMPS,
	66	0, vmstate_pmp_entry, pmp_entry_t),
	67	VMSTATE_END_OF_LIST()
	68	}
	69	};
	70
35e07821 YJ	71	static bool hyper_needed(void *opaque)
	72	{
	73	RISCVCPU *cpu = opaque;
	74	CPURISCVState *env = &cpu->env;
	75
	76	return riscv_has_ext(env, RVH);
	77	}
	78
edcc4e40 BM	79	static const VMStateDescription vmstate_hyper = {
edcc4e40 BM	80	.name = "cpu/hyper",
cd032fe7 AP	81	.version_id = 2,
cd032fe7 AP	82	.minimum_version_id = 2,
edcc4e40 BM	83	.needed = hyper_needed,
	84	.fields = (VMStateField[]) {
	85	VMSTATE_UINTTL(env.hstatus, RISCVCPU),
	86	VMSTATE_UINTTL(env.hedeleg, RISCVCPU),
d028ac75	87	VMSTATE_UINT64(env.hideleg, RISCVCPU),
edcc4e40 BM	88	VMSTATE_UINTTL(env.hcounteren, RISCVCPU),
	89	VMSTATE_UINTTL(env.htval, RISCVCPU),
	90	VMSTATE_UINTTL(env.htinst, RISCVCPU),
	91	VMSTATE_UINTTL(env.hgatp, RISCVCPU),
cd032fe7 AP	92	VMSTATE_UINTTL(env.hgeie, RISCVCPU),
cd032fe7 AP	93	VMSTATE_UINTTL(env.hgeip, RISCVCPU),
edcc4e40	94	VMSTATE_UINT64(env.htimedelta, RISCVCPU),
3ec0fe18	95	VMSTATE_UINT64(env.vstimecmp, RISCVCPU),
2b602398 AP	96
2b602398 AP	97	VMSTATE_UINTTL(env.hvictl, RISCVCPU),
43dc93af	98	VMSTATE_UINT8_ARRAY(env.hviprio, RISCVCPU, 64),
bb02edcd	99
edcc4e40 BM	100	VMSTATE_UINT64(env.vsstatus, RISCVCPU),
	101	VMSTATE_UINTTL(env.vstvec, RISCVCPU),
	102	VMSTATE_UINTTL(env.vsscratch, RISCVCPU),
	103	VMSTATE_UINTTL(env.vsepc, RISCVCPU),
	104	VMSTATE_UINTTL(env.vscause, RISCVCPU),
	105	VMSTATE_UINTTL(env.vstval, RISCVCPU),
	106	VMSTATE_UINTTL(env.vsatp, RISCVCPU),
d1ceff40	107	VMSTATE_UINTTL(env.vsiselect, RISCVCPU),
bb02edcd	108
edcc4e40 BM	109	VMSTATE_UINTTL(env.mtval2, RISCVCPU),
	110	VMSTATE_UINTTL(env.mtinst, RISCVCPU),
	111
	112	VMSTATE_UINTTL(env.stvec_hs, RISCVCPU),
	113	VMSTATE_UINTTL(env.sscratch_hs, RISCVCPU),
	114	VMSTATE_UINTTL(env.sepc_hs, RISCVCPU),
	115	VMSTATE_UINTTL(env.scause_hs, RISCVCPU),
	116	VMSTATE_UINTTL(env.stval_hs, RISCVCPU),
	117	VMSTATE_UINTTL(env.satp_hs, RISCVCPU),
	118	VMSTATE_UINT64(env.mstatus_hs, RISCVCPU),
	119
	120	VMSTATE_END_OF_LIST()
	121	}
	122	};
	123
	124	static bool vector_needed(void *opaque)
b1c279e1 AB	125	{
	126	RISCVCPU *cpu = opaque;
	127	CPURISCVState *env = &cpu->env;
	128
edcc4e40	129	return riscv_has_ext(env, RVV);
b1c279e1 AB	130	}
b1c279e1 AB	131
bb02edcd YJ	132	static const VMStateDescription vmstate_vector = {
bb02edcd YJ	133	.name = "cpu/vector",
d96a271a LZ	134	.version_id = 2,
d96a271a LZ	135	.minimum_version_id = 2,
bb02edcd YJ	136	.needed = vector_needed,
	137	.fields = (VMStateField[]) {
	138	VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64),
	139	VMSTATE_UINTTL(env.vxrm, RISCVCPU),
	140	VMSTATE_UINTTL(env.vxsat, RISCVCPU),
	141	VMSTATE_UINTTL(env.vl, RISCVCPU),
	142	VMSTATE_UINTTL(env.vstart, RISCVCPU),
	143	VMSTATE_UINTTL(env.vtype, RISCVCPU),
d96a271a	144	VMSTATE_BOOL(env.vill, RISCVCPU),
bb02edcd YJ	145	VMSTATE_END_OF_LIST()
	146	}
	147	};
	148
edcc4e40 BM	149	static bool pointermasking_needed(void *opaque)
	150	{
	151	RISCVCPU *cpu = opaque;
	152	CPURISCVState *env = &cpu->env;
	153
	154	return riscv_has_ext(env, RVJ);
	155	}
	156
b1c279e1 AB	157	static const VMStateDescription vmstate_pointermasking = {
	158	.name = "cpu/pointer_masking",
	159	.version_id = 1,
	160	.minimum_version_id = 1,
	161	.needed = pointermasking_needed,
	162	.fields = (VMStateField[]) {
	163	VMSTATE_UINTTL(env.mmte, RISCVCPU),
	164	VMSTATE_UINTTL(env.mpmmask, RISCVCPU),
	165	VMSTATE_UINTTL(env.mpmbase, RISCVCPU),
	166	VMSTATE_UINTTL(env.spmmask, RISCVCPU),
	167	VMSTATE_UINTTL(env.spmbase, RISCVCPU),
	168	VMSTATE_UINTTL(env.upmmask, RISCVCPU),
	169	VMSTATE_UINTTL(env.upmbase, RISCVCPU),
	170
	171	VMSTATE_END_OF_LIST()
	172	}
	173	};
	174
2b547084 FP	175	static bool rv128_needed(void *opaque)
	176	{
	177	RISCVCPU *cpu = opaque;
	178	CPURISCVState *env = &cpu->env;
	179
	180	return env->misa_mxl_max == MXL_RV128;
	181	}
	182
	183	static const VMStateDescription vmstate_rv128 = {
	184	.name = "cpu/rv128",
	185	.version_id = 1,
	186	.minimum_version_id = 1,
	187	.needed = rv128_needed,
	188	.fields = (VMStateField[]) {
	189	VMSTATE_UINTTL_ARRAY(env.gprh, RISCVCPU, 32),
2c64ab66 FP	190	VMSTATE_UINT64(env.mscratchh, RISCVCPU),
2c64ab66 FP	191	VMSTATE_UINT64(env.sscratchh, RISCVCPU),
2b547084 FP	192	VMSTATE_END_OF_LIST()
	193	}
	194	};
	195
1eb9a5da YJ	196	static bool kvmtimer_needed(void *opaque)
	197	{
	198	return kvm_enabled();
	199	}
	200
	201	static int cpu_post_load(void *opaque, int version_id)
	202	{
	203	RISCVCPU *cpu = opaque;
	204	CPURISCVState *env = &cpu->env;
	205
	206	env->kvm_timer_dirty = true;
	207	return 0;
	208	}
	209
	210	static const VMStateDescription vmstate_kvmtimer = {
	211	.name = "cpu/kvmtimer",
	212	.version_id = 1,
	213	.minimum_version_id = 1,
	214	.needed = kvmtimer_needed,
	215	.post_load = cpu_post_load,
	216	.fields = (VMStateField[]) {
	217	VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU),
	218	VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU),
	219	VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU),
38b4e781 BM	220	VMSTATE_END_OF_LIST()
	221	}
	222	};
	223
	224	static bool debug_needed(void *opaque)
	225	{
	226	RISCVCPU *cpu = opaque;
	227	CPURISCVState *env = &cpu->env;
	228
	229	return riscv_feature(env, RISCV_FEATURE_DEBUG);
	230	}
1eb9a5da	231
38b4e781 BM	232	static const VMStateDescription vmstate_debug = {
38b4e781 BM	233	.name = "cpu/debug",
9495c488 FC	234	.version_id = 2,
9495c488 FC	235	.minimum_version_id = 2,
38b4e781 BM	236	.needed = debug_needed,
	237	.fields = (VMStateField[]) {
	238	VMSTATE_UINTTL(env.trigger_cur, RISCVCPU),
9495c488 FC	239	VMSTATE_UINTTL_ARRAY(env.tdata1, RISCVCPU, RV_MAX_TRIGGERS),
	240	VMSTATE_UINTTL_ARRAY(env.tdata2, RISCVCPU, RV_MAX_TRIGGERS),
	241	VMSTATE_UINTTL_ARRAY(env.tdata3, RISCVCPU, RV_MAX_TRIGGERS),
1eb9a5da YJ	242	VMSTATE_END_OF_LIST()
	243	}
	244	};
	245
440544e1 LZ	246	static int riscv_cpu_post_load(void *opaque, int version_id)
	247	{
	248	RISCVCPU *cpu = opaque;
	249	CPURISCVState *env = &cpu->env;
	250
	251	env->xl = cpu_recompute_xl(env);
40bfa5f6	252	riscv_cpu_update_mask(env);
440544e1 LZ	253	return 0;
	254	}
	255
3bee0e40 MC	256	static bool smstateen_needed(void *opaque)
	257	{
	258	RISCVCPU *cpu = opaque;
	259
	260	return cpu->cfg.ext_smstateen;
	261	}
	262
	263	static const VMStateDescription vmstate_smstateen = {
	264	.name = "cpu/smtateen",
	265	.version_id = 1,
	266	.minimum_version_id = 1,
	267	.needed = smstateen_needed,
	268	.fields = (VMStateField[]) {
	269	VMSTATE_UINT64_ARRAY(env.mstateen, RISCVCPU, 4),
	270	VMSTATE_UINT64_ARRAY(env.hstateen, RISCVCPU, 4),
	271	VMSTATE_UINT64_ARRAY(env.sstateen, RISCVCPU, 4),
	272	VMSTATE_END_OF_LIST()
	273	}
	274	};
	275
29a9ec9b AP	276	static bool envcfg_needed(void *opaque)
	277	{
	278	RISCVCPU *cpu = opaque;
	279	CPURISCVState *env = &cpu->env;
	280
	281	return (env->priv_ver >= PRIV_VERSION_1_12_0 ? 1 : 0);
	282	}
	283
	284	static const VMStateDescription vmstate_envcfg = {
	285	.name = "cpu/envcfg",
	286	.version_id = 1,
	287	.minimum_version_id = 1,
	288	.needed = envcfg_needed,
	289	.fields = (VMStateField[]) {
	290	VMSTATE_UINT64(env.menvcfg, RISCVCPU),
	291	VMSTATE_UINTTL(env.senvcfg, RISCVCPU),
	292	VMSTATE_UINT64(env.henvcfg, RISCVCPU),
3780e337 AP	293	VMSTATE_END_OF_LIST()
	294	}
	295	};
	296
	297	static bool pmu_needed(void *opaque)
	298	{
	299	RISCVCPU *cpu = opaque;
29a9ec9b	300
3780e337 AP	301	return cpu->cfg.pmu_num;
	302	}
	303
	304	static const VMStateDescription vmstate_pmu_ctr_state = {
	305	.name = "cpu/pmu",
	306	.version_id = 1,
	307	.minimum_version_id = 1,
	308	.needed = pmu_needed,
	309	.fields = (VMStateField[]) {
	310	VMSTATE_UINTTL(mhpmcounter_val, PMUCTRState),
	311	VMSTATE_UINTTL(mhpmcounterh_val, PMUCTRState),
	312	VMSTATE_UINTTL(mhpmcounter_prev, PMUCTRState),
	313	VMSTATE_UINTTL(mhpmcounterh_prev, PMUCTRState),
	314	VMSTATE_BOOL(started, PMUCTRState),
29a9ec9b AP	315	VMSTATE_END_OF_LIST()
	316	}
	317	};
	318
f7697f0e YJ	319	const VMStateDescription vmstate_riscv_cpu = {
f7697f0e YJ	320	.name = "cpu",
277b210d AF	321	.version_id = 5,
277b210d AF	322	.minimum_version_id = 5,
440544e1	323	.post_load = riscv_cpu_post_load,
f7697f0e YJ	324	.fields = (VMStateField[]) {
	325	VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
	326	VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
43dc93af AP	327	VMSTATE_UINT8_ARRAY(env.miprio, RISCVCPU, 64),
43dc93af AP	328	VMSTATE_UINT8_ARRAY(env.siprio, RISCVCPU, 64),
f7697f0e YJ	329	VMSTATE_UINTTL(env.pc, RISCVCPU),
	330	VMSTATE_UINTTL(env.load_res, RISCVCPU),
	331	VMSTATE_UINTTL(env.load_val, RISCVCPU),
	332	VMSTATE_UINTTL(env.frm, RISCVCPU),
	333	VMSTATE_UINTTL(env.badaddr, RISCVCPU),
	334	VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU),
	335	VMSTATE_UINTTL(env.priv_ver, RISCVCPU),
	336	VMSTATE_UINTTL(env.vext_ver, RISCVCPU),
e91a7227 RH	337	VMSTATE_UINT32(env.misa_mxl, RISCVCPU),
	338	VMSTATE_UINT32(env.misa_ext, RISCVCPU),
	339	VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU),
	340	VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU),
f7697f0e YJ	341	VMSTATE_UINT32(env.features, RISCVCPU),
	342	VMSTATE_UINTTL(env.priv, RISCVCPU),
	343	VMSTATE_UINTTL(env.virt, RISCVCPU),
277b210d	344	VMSTATE_UINT64(env.resetvec, RISCVCPU),
f7697f0e YJ	345	VMSTATE_UINTTL(env.mhartid, RISCVCPU),
f7697f0e YJ	346	VMSTATE_UINT64(env.mstatus, RISCVCPU),
d028ac75 AP	347	VMSTATE_UINT64(env.mip, RISCVCPU),
	348	VMSTATE_UINT64(env.miclaim, RISCVCPU),
	349	VMSTATE_UINT64(env.mie, RISCVCPU),
	350	VMSTATE_UINT64(env.mideleg, RISCVCPU),
f7697f0e	351	VMSTATE_UINTTL(env.satp, RISCVCPU),
ac12b601	352	VMSTATE_UINTTL(env.stval, RISCVCPU),
f7697f0e YJ	353	VMSTATE_UINTTL(env.medeleg, RISCVCPU),
	354	VMSTATE_UINTTL(env.stvec, RISCVCPU),
	355	VMSTATE_UINTTL(env.sepc, RISCVCPU),
	356	VMSTATE_UINTTL(env.scause, RISCVCPU),
	357	VMSTATE_UINTTL(env.mtvec, RISCVCPU),
	358	VMSTATE_UINTTL(env.mepc, RISCVCPU),
	359	VMSTATE_UINTTL(env.mcause, RISCVCPU),
	360	VMSTATE_UINTTL(env.mtval, RISCVCPU),
d1ceff40 AP	361	VMSTATE_UINTTL(env.miselect, RISCVCPU),
d1ceff40 AP	362	VMSTATE_UINTTL(env.siselect, RISCVCPU),
f7697f0e YJ	363	VMSTATE_UINTTL(env.scounteren, RISCVCPU),
f7697f0e YJ	364	VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
b1675eeb	365	VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU),
3780e337 AP	366	VMSTATE_STRUCT_ARRAY(env.pmu_ctrs, RISCVCPU, RV_MAX_MHPMCOUNTERS, 0,
3780e337 AP	367	vmstate_pmu_ctr_state, PMUCTRState),
621f35bb	368	VMSTATE_UINTTL_ARRAY(env.mhpmevent_val, RISCVCPU, RV_MAX_MHPMEVENTS),
14664483	369	VMSTATE_UINTTL_ARRAY(env.mhpmeventh_val, RISCVCPU, RV_MAX_MHPMEVENTS),
f7697f0e YJ	370	VMSTATE_UINTTL(env.sscratch, RISCVCPU),
	371	VMSTATE_UINTTL(env.mscratch, RISCVCPU),
	372	VMSTATE_UINT64(env.mfromhost, RISCVCPU),
	373	VMSTATE_UINT64(env.mtohost, RISCVCPU),
43888c2f	374	VMSTATE_UINT64(env.stimecmp, RISCVCPU),
f7697f0e YJ	375
f7697f0e YJ	376	VMSTATE_END_OF_LIST()
24beb03e YJ	377	},
	378	.subsections = (const VMStateDescription * []) {
	379	&vmstate_pmp,
35e07821	380	&vmstate_hyper,
bb02edcd	381	&vmstate_vector,
b1c279e1	382	&vmstate_pointermasking,
2b547084	383	&vmstate_rv128,
1eb9a5da	384	&vmstate_kvmtimer,
29a9ec9b	385	&vmstate_envcfg,
38b4e781	386	&vmstate_debug,
3bee0e40	387	&vmstate_smstateen,
24beb03e	388	NULL
f7697f0e YJ	389	}
f7697f0e YJ	390	};