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0c3e702a MC |
1 | /* |
2 | * RISC-V Emulation Helpers for QEMU. | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017-2018 SiFive, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2 or later, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
21 | #include "qemu/log.h" | |
22 | #include "cpu.h" | |
23 | #include "qemu/main-loop.h" | |
24 | #include "exec/exec-all.h" | |
25 | #include "exec/helper-proto.h" | |
26 | ||
0c3e702a | 27 | /* Exceptions processing helpers */ |
fb738839 | 28 | void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, |
0c3e702a MC |
29 | uint32_t exception, uintptr_t pc) |
30 | { | |
3109cd98 | 31 | CPUState *cs = env_cpu(env); |
0c3e702a MC |
32 | qemu_log_mask(CPU_LOG_INT, "%s: %d\n", __func__, exception); |
33 | cs->exception_index = exception; | |
34 | cpu_loop_exit_restore(cs, pc); | |
35 | } | |
36 | ||
37 | void helper_raise_exception(CPURISCVState *env, uint32_t exception) | |
38 | { | |
fb738839 | 39 | riscv_raise_exception(env, exception, 0); |
0c3e702a MC |
40 | } |
41 | ||
0c3e702a MC |
42 | target_ulong helper_csrrw(CPURISCVState *env, target_ulong src, |
43 | target_ulong csr) | |
44 | { | |
c7b95171 MC |
45 | target_ulong val = 0; |
46 | if (riscv_csrrw(env, csr, &val, src, -1) < 0) { | |
fb738839 | 47 | riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); |
c7b95171 MC |
48 | } |
49 | return val; | |
0c3e702a MC |
50 | } |
51 | ||
52 | target_ulong helper_csrrs(CPURISCVState *env, target_ulong src, | |
53 | target_ulong csr, target_ulong rs1_pass) | |
54 | { | |
c7b95171 MC |
55 | target_ulong val = 0; |
56 | if (riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0) < 0) { | |
fb738839 | 57 | riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); |
0c3e702a | 58 | } |
c7b95171 | 59 | return val; |
0c3e702a MC |
60 | } |
61 | ||
62 | target_ulong helper_csrrc(CPURISCVState *env, target_ulong src, | |
63 | target_ulong csr, target_ulong rs1_pass) | |
64 | { | |
c7b95171 MC |
65 | target_ulong val = 0; |
66 | if (riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0) < 0) { | |
fb738839 | 67 | riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); |
0c3e702a | 68 | } |
c7b95171 | 69 | return val; |
0c3e702a MC |
70 | } |
71 | ||
72 | #ifndef CONFIG_USER_ONLY | |
73 | ||
0c3e702a MC |
74 | target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb) |
75 | { | |
e3fba4ba AF |
76 | target_ulong prev_priv, prev_virt, mstatus; |
77 | ||
0c3e702a | 78 | if (!(env->priv >= PRV_S)) { |
fb738839 | 79 | riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); |
0c3e702a MC |
80 | } |
81 | ||
82 | target_ulong retpc = env->sepc; | |
83 | if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) { | |
fb738839 | 84 | riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC()); |
0c3e702a MC |
85 | } |
86 | ||
1a9540d1 | 87 | if (get_field(env->mstatus, MSTATUS_TSR) && !(env->priv >= PRV_M)) { |
fb738839 | 88 | riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); |
7f2b5ff1 MC |
89 | } |
90 | ||
e3fba4ba AF |
91 | mstatus = env->mstatus; |
92 | ||
93 | if (riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) { | |
94 | /* We support Hypervisor extensions and virtulisation is disabled */ | |
95 | target_ulong hstatus = env->hstatus; | |
96 | ||
97 | prev_priv = get_field(mstatus, MSTATUS_SPP); | |
98 | prev_virt = get_field(hstatus, HSTATUS_SPV); | |
99 | ||
100 | hstatus = set_field(hstatus, HSTATUS_SPV, | |
101 | get_field(hstatus, HSTATUS_SP2V)); | |
102 | mstatus = set_field(mstatus, MSTATUS_SPP, | |
103 | get_field(hstatus, HSTATUS_SP2P)); | |
104 | hstatus = set_field(hstatus, HSTATUS_SP2V, 0); | |
105 | hstatus = set_field(hstatus, HSTATUS_SP2P, 0); | |
106 | mstatus = set_field(mstatus, SSTATUS_SIE, | |
107 | get_field(mstatus, SSTATUS_SPIE)); | |
108 | mstatus = set_field(mstatus, SSTATUS_SPIE, 1); | |
109 | ||
110 | env->mstatus = mstatus; | |
111 | env->hstatus = hstatus; | |
112 | ||
113 | if (prev_virt) { | |
114 | riscv_cpu_swap_hypervisor_regs(env); | |
115 | } | |
116 | ||
117 | riscv_cpu_set_virt_enabled(env, prev_virt); | |
118 | } else { | |
119 | prev_priv = get_field(mstatus, MSTATUS_SPP); | |
120 | ||
1a9540d1 AF |
121 | mstatus = set_field(mstatus, MSTATUS_SIE, |
122 | get_field(mstatus, MSTATUS_SPIE)); | |
e3fba4ba AF |
123 | mstatus = set_field(mstatus, MSTATUS_SPIE, 1); |
124 | mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U); | |
125 | env->mstatus = mstatus; | |
126 | } | |
127 | ||
fb738839 | 128 | riscv_cpu_set_mode(env, prev_priv); |
0c3e702a MC |
129 | |
130 | return retpc; | |
131 | } | |
132 | ||
133 | target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb) | |
134 | { | |
135 | if (!(env->priv >= PRV_M)) { | |
fb738839 | 136 | riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); |
0c3e702a MC |
137 | } |
138 | ||
139 | target_ulong retpc = env->mepc; | |
140 | if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) { | |
fb738839 | 141 | riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC()); |
0c3e702a MC |
142 | } |
143 | ||
144 | target_ulong mstatus = env->mstatus; | |
145 | target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP); | |
e44b50b5 | 146 | target_ulong prev_virt = MSTATUS_MPV_ISSET(env); |
1a9540d1 AF |
147 | mstatus = set_field(mstatus, MSTATUS_MIE, |
148 | get_field(mstatus, MSTATUS_MPIE)); | |
a37f21c2 | 149 | mstatus = set_field(mstatus, MSTATUS_MPIE, 1); |
0c3e702a | 150 | mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U); |
551fa7e8 AF |
151 | #ifdef TARGET_RISCV32 |
152 | env->mstatush = set_field(env->mstatush, MSTATUS_MPV, 0); | |
153 | #else | |
e3fba4ba | 154 | mstatus = set_field(mstatus, MSTATUS_MPV, 0); |
551fa7e8 | 155 | #endif |
c7b95171 | 156 | env->mstatus = mstatus; |
e3fba4ba AF |
157 | riscv_cpu_set_mode(env, prev_priv); |
158 | ||
159 | if (riscv_has_ext(env, RVH)) { | |
160 | if (prev_virt) { | |
161 | riscv_cpu_swap_hypervisor_regs(env); | |
162 | } | |
163 | ||
164 | riscv_cpu_set_virt_enabled(env, prev_virt); | |
165 | } | |
0c3e702a MC |
166 | |
167 | return retpc; | |
168 | } | |
169 | ||
0c3e702a MC |
170 | void helper_wfi(CPURISCVState *env) |
171 | { | |
3109cd98 | 172 | CPUState *cs = env_cpu(env); |
0c3e702a | 173 | |
9d0d1126 | 174 | if ((env->priv == PRV_S && |
9d0d1126 AF |
175 | get_field(env->mstatus, MSTATUS_TW)) || |
176 | riscv_cpu_virt_enabled(env)) { | |
fb738839 | 177 | riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); |
7f2b5ff1 MC |
178 | } else { |
179 | cs->halted = 1; | |
180 | cs->exception_index = EXCP_HLT; | |
181 | cpu_loop_exit(cs); | |
182 | } | |
0c3e702a MC |
183 | } |
184 | ||
185 | void helper_tlb_flush(CPURISCVState *env) | |
186 | { | |
3109cd98 | 187 | CPUState *cs = env_cpu(env); |
b86f4167 JB |
188 | if (!(env->priv >= PRV_S) || |
189 | (env->priv == PRV_S && | |
b86f4167 | 190 | get_field(env->mstatus, MSTATUS_TVM))) { |
fb738839 | 191 | riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); |
7f2b5ff1 MC |
192 | } else { |
193 | tlb_flush(cs); | |
194 | } | |
0c3e702a MC |
195 | } |
196 | ||
2761db5f AF |
197 | void helper_hyp_tlb_flush(CPURISCVState *env) |
198 | { | |
199 | CPUState *cs = env_cpu(env); | |
200 | ||
201 | if (env->priv == PRV_M || | |
202 | (env->priv == PRV_S && !riscv_cpu_virt_enabled(env))) { | |
203 | tlb_flush(cs); | |
204 | return; | |
205 | } | |
206 | ||
207 | riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); | |
208 | } | |
209 | ||
0c3e702a | 210 | #endif /* !CONFIG_USER_ONLY */ |