]>
Commit | Line | Data |
---|---|---|
65c5b75c MC |
1 | /* |
2 | * QEMU RISC-V PMP (Physical Memory Protection) | |
3 | * | |
4 | * Author: Daire McNamara, daire.mcnamara@emdalo.com | |
5 | * Ivan Griffin, ivan.griffin@emdalo.com | |
6 | * | |
7 | * This provides a RISC-V Physical Memory Protection interface | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms and conditions of the GNU General Public License, | |
11 | * version 2 or later, as published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope it will be useful, but WITHOUT | |
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
16 | * more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along with | |
19 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
a8b991b5 MA |
22 | #ifndef RISCV_PMP_H |
23 | #define RISCV_PMP_H | |
65c5b75c | 24 | |
3cb1a410 PMD |
25 | #include "cpu.h" |
26 | ||
65c5b75c MC |
27 | typedef enum { |
28 | PMP_READ = 1 << 0, | |
29 | PMP_WRITE = 1 << 1, | |
30 | PMP_EXEC = 1 << 2, | |
31 | PMP_LOCK = 1 << 7 | |
32 | } pmp_priv_t; | |
33 | ||
34 | typedef enum { | |
35 | PMP_AMATCH_OFF, /* Null (off) */ | |
36 | PMP_AMATCH_TOR, /* Top of Range */ | |
37 | PMP_AMATCH_NA4, /* Naturally aligned four-byte region */ | |
38 | PMP_AMATCH_NAPOT /* Naturally aligned power-of-two region */ | |
39 | } pmp_am_t; | |
40 | ||
2582a95c | 41 | typedef enum { |
77442380 WL |
42 | MSECCFG_MML = 1 << 0, |
43 | MSECCFG_MMWP = 1 << 1, | |
44 | MSECCFG_RLB = 1 << 2, | |
45 | MSECCFG_USEED = 1 << 8, | |
46 | MSECCFG_SSEED = 1 << 9 | |
2582a95c HW |
47 | } mseccfg_field_t; |
48 | ||
65c5b75c MC |
49 | typedef struct { |
50 | target_ulong addr_reg; | |
51 | uint8_t cfg_reg; | |
52 | } pmp_entry_t; | |
53 | ||
54 | typedef struct { | |
55 | target_ulong sa; | |
56 | target_ulong ea; | |
57 | } pmp_addr_t; | |
58 | ||
59 | typedef struct { | |
60 | pmp_entry_t pmp[MAX_RISCV_PMPS]; | |
61 | pmp_addr_t addr[MAX_RISCV_PMPS]; | |
62 | uint32_t num_rules; | |
63 | } pmp_table_t; | |
64 | ||
65 | void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index, | |
66 | target_ulong val); | |
67 | target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index); | |
2582a95c HW |
68 | |
69 | void mseccfg_csr_write(CPURISCVState *env, target_ulong val); | |
70 | target_ulong mseccfg_csr_read(CPURISCVState *env); | |
71 | ||
65c5b75c MC |
72 | void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index, |
73 | target_ulong val); | |
74 | target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index); | |
824cac68 | 75 | int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, |
b297129a JS |
76 | target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs, |
77 | target_ulong mode); | |
824cac68 LZ |
78 | target_ulong pmp_get_tlb_size(CPURISCVState *env, int pmp_index, |
79 | target_ulong tlb_sa, target_ulong tlb_ea); | |
24beb03e YJ |
80 | void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index); |
81 | void pmp_update_rule_nums(CPURISCVState *env); | |
d102f19a | 82 | uint32_t pmp_get_num_rules(CPURISCVState *env); |
b297129a | 83 | int pmp_priv_to_page_prot(pmp_priv_t pmp_priv); |
65c5b75c | 84 | |
2582a95c HW |
85 | #define MSECCFG_MML_ISSET(env) get_field(env->mseccfg, MSECCFG_MML) |
86 | #define MSECCFG_MMWP_ISSET(env) get_field(env->mseccfg, MSECCFG_MMWP) | |
87 | #define MSECCFG_RLB_ISSET(env) get_field(env->mseccfg, MSECCFG_RLB) | |
88 | ||
65c5b75c | 89 | #endif |