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55c2a12c MC |
1 | /* |
2 | * RISC-V emulation for qemu: main translation routines. | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2 or later, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along with | |
16 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | ||
19 | #include "qemu/osdep.h" | |
20 | #include "qemu/log.h" | |
21 | #include "cpu.h" | |
dcb32f1d | 22 | #include "tcg/tcg-op.h" |
55c2a12c MC |
23 | #include "disas/disas.h" |
24 | #include "exec/cpu_ldst.h" | |
25 | #include "exec/exec-all.h" | |
26 | #include "exec/helper-proto.h" | |
27 | #include "exec/helper-gen.h" | |
28 | ||
b2e32021 | 29 | #include "exec/translator.h" |
55c2a12c MC |
30 | #include "exec/log.h" |
31 | ||
32 | #include "instmap.h" | |
33 | ||
34 | /* global register indices */ | |
35 | static TCGv cpu_gpr[32], cpu_pc; | |
36 | static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ | |
37 | static TCGv load_res; | |
38 | static TCGv load_val; | |
39 | ||
40 | #include "exec/gen-icount.h" | |
41 | ||
42 | typedef struct DisasContext { | |
0114db1c EC |
43 | DisasContextBase base; |
44 | /* pc_succ_insn points to the instruction following base.pc_next */ | |
45 | target_ulong pc_succ_insn; | |
d75377bf | 46 | target_ulong priv_ver; |
83a71719 | 47 | uint32_t mstatus_fs; |
db9f3fd6 | 48 | uint32_t misa; |
55c2a12c | 49 | uint32_t mem_idx; |
55c2a12c MC |
50 | /* Remember the rounding mode encoded in the previous fp instruction, |
51 | which we have already installed into env->fp_status. Or -1 for | |
52 | no previous fp instruction. Note that we exit the TB when writing | |
53 | to any system register, which includes CSR_FRM, so we do not have | |
54 | to reset this known value. */ | |
55 | int frm; | |
50fba816 | 56 | bool ext_ifencei; |
55c2a12c MC |
57 | } DisasContext; |
58 | ||
bce8a342 | 59 | #ifdef TARGET_RISCV64 |
55c2a12c MC |
60 | /* convert riscv funct3 to qemu memop for load/store */ |
61 | static const int tcg_memop_lookup[8] = { | |
62 | [0 ... 7] = -1, | |
63 | [0] = MO_SB, | |
64 | [1] = MO_TESW, | |
65 | [2] = MO_TESL, | |
f480f6e8 | 66 | [3] = MO_TEQ, |
55c2a12c MC |
67 | [4] = MO_UB, |
68 | [5] = MO_TEUW, | |
55c2a12c | 69 | [6] = MO_TEUL, |
55c2a12c | 70 | }; |
bce8a342 | 71 | #endif |
55c2a12c MC |
72 | |
73 | #ifdef TARGET_RISCV64 | |
74 | #define CASE_OP_32_64(X) case X: case glue(X, W) | |
75 | #else | |
76 | #define CASE_OP_32_64(X) case X | |
77 | #endif | |
78 | ||
db9f3fd6 MC |
79 | static inline bool has_ext(DisasContext *ctx, uint32_t ext) |
80 | { | |
81 | return ctx->misa & ext; | |
82 | } | |
83 | ||
55c2a12c MC |
84 | static void generate_exception(DisasContext *ctx, int excp) |
85 | { | |
0114db1c | 86 | tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); |
55c2a12c MC |
87 | TCGv_i32 helper_tmp = tcg_const_i32(excp); |
88 | gen_helper_raise_exception(cpu_env, helper_tmp); | |
89 | tcg_temp_free_i32(helper_tmp); | |
0114db1c | 90 | ctx->base.is_jmp = DISAS_NORETURN; |
55c2a12c MC |
91 | } |
92 | ||
93 | static void generate_exception_mbadaddr(DisasContext *ctx, int excp) | |
94 | { | |
0114db1c | 95 | tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); |
55c2a12c MC |
96 | tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); |
97 | TCGv_i32 helper_tmp = tcg_const_i32(excp); | |
98 | gen_helper_raise_exception(cpu_env, helper_tmp); | |
99 | tcg_temp_free_i32(helper_tmp); | |
0114db1c | 100 | ctx->base.is_jmp = DISAS_NORETURN; |
55c2a12c MC |
101 | } |
102 | ||
103 | static void gen_exception_debug(void) | |
104 | { | |
105 | TCGv_i32 helper_tmp = tcg_const_i32(EXCP_DEBUG); | |
106 | gen_helper_raise_exception(cpu_env, helper_tmp); | |
107 | tcg_temp_free_i32(helper_tmp); | |
108 | } | |
109 | ||
6e2716d8 FC |
110 | /* Wrapper around tcg_gen_exit_tb that handles single stepping */ |
111 | static void exit_tb(DisasContext *ctx) | |
112 | { | |
113 | if (ctx->base.singlestep_enabled) { | |
114 | gen_exception_debug(); | |
115 | } else { | |
116 | tcg_gen_exit_tb(NULL, 0); | |
117 | } | |
118 | } | |
119 | ||
120 | /* Wrapper around tcg_gen_lookup_and_goto_ptr that handles single stepping */ | |
121 | static void lookup_and_goto_ptr(DisasContext *ctx) | |
122 | { | |
123 | if (ctx->base.singlestep_enabled) { | |
124 | gen_exception_debug(); | |
125 | } else { | |
126 | tcg_gen_lookup_and_goto_ptr(); | |
127 | } | |
128 | } | |
129 | ||
55c2a12c MC |
130 | static void gen_exception_illegal(DisasContext *ctx) |
131 | { | |
132 | generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); | |
133 | } | |
134 | ||
135 | static void gen_exception_inst_addr_mis(DisasContext *ctx) | |
136 | { | |
137 | generate_exception_mbadaddr(ctx, RISCV_EXCP_INST_ADDR_MIS); | |
138 | } | |
139 | ||
140 | static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) | |
141 | { | |
0114db1c | 142 | if (unlikely(ctx->base.singlestep_enabled)) { |
55c2a12c MC |
143 | return false; |
144 | } | |
145 | ||
146 | #ifndef CONFIG_USER_ONLY | |
0114db1c | 147 | return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); |
55c2a12c MC |
148 | #else |
149 | return true; | |
150 | #endif | |
151 | } | |
152 | ||
153 | static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) | |
154 | { | |
155 | if (use_goto_tb(ctx, dest)) { | |
156 | /* chaining is only allowed when the jump is to the same page */ | |
157 | tcg_gen_goto_tb(n); | |
158 | tcg_gen_movi_tl(cpu_pc, dest); | |
6e2716d8 FC |
159 | |
160 | /* No need to check for single stepping here as use_goto_tb() will | |
161 | * return false in case of single stepping. | |
162 | */ | |
07ea28b4 | 163 | tcg_gen_exit_tb(ctx->base.tb, n); |
55c2a12c MC |
164 | } else { |
165 | tcg_gen_movi_tl(cpu_pc, dest); | |
6e2716d8 | 166 | lookup_and_goto_ptr(ctx); |
55c2a12c MC |
167 | } |
168 | } | |
169 | ||
170 | /* Wrapper for getting reg values - need to check of reg is zero since | |
171 | * cpu_gpr[0] is not actually allocated | |
172 | */ | |
173 | static inline void gen_get_gpr(TCGv t, int reg_num) | |
174 | { | |
175 | if (reg_num == 0) { | |
176 | tcg_gen_movi_tl(t, 0); | |
177 | } else { | |
178 | tcg_gen_mov_tl(t, cpu_gpr[reg_num]); | |
179 | } | |
180 | } | |
181 | ||
182 | /* Wrapper for setting reg values - need to check of reg is zero since | |
183 | * cpu_gpr[0] is not actually allocated. this is more for safety purposes, | |
184 | * since we usually avoid calling the OP_TYPE_gen function if we see a write to | |
185 | * $zero | |
186 | */ | |
187 | static inline void gen_set_gpr(int reg_num_dst, TCGv t) | |
188 | { | |
189 | if (reg_num_dst != 0) { | |
190 | tcg_gen_mov_tl(cpu_gpr[reg_num_dst], t); | |
191 | } | |
192 | } | |
193 | ||
194 | static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2) | |
195 | { | |
196 | TCGv rl = tcg_temp_new(); | |
197 | TCGv rh = tcg_temp_new(); | |
198 | ||
199 | tcg_gen_mulu2_tl(rl, rh, arg1, arg2); | |
200 | /* fix up for one negative */ | |
201 | tcg_gen_sari_tl(rl, arg1, TARGET_LONG_BITS - 1); | |
202 | tcg_gen_and_tl(rl, rl, arg2); | |
203 | tcg_gen_sub_tl(ret, rh, rl); | |
204 | ||
205 | tcg_temp_free(rl); | |
206 | tcg_temp_free(rh); | |
207 | } | |
208 | ||
12887016 | 209 | static void gen_div(TCGv ret, TCGv source1, TCGv source2) |
55c2a12c | 210 | { |
12887016 BK |
211 | TCGv cond1, cond2, zeroreg, resultopt1; |
212 | /* | |
213 | * Handle by altering args to tcg_gen_div to produce req'd results: | |
214 | * For overflow: want source1 in source1 and 1 in source2 | |
215 | * For div by zero: want -1 in source1 and 1 in source2 -> -1 result | |
216 | */ | |
217 | cond1 = tcg_temp_new(); | |
218 | cond2 = tcg_temp_new(); | |
219 | zeroreg = tcg_const_tl(0); | |
220 | resultopt1 = tcg_temp_new(); | |
221 | ||
222 | tcg_gen_movi_tl(resultopt1, (target_ulong)-1); | |
223 | tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)(~0L)); | |
224 | tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1, | |
225 | ((target_ulong)1) << (TARGET_LONG_BITS - 1)); | |
226 | tcg_gen_and_tl(cond1, cond1, cond2); /* cond1 = overflow */ | |
227 | tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, 0); /* cond2 = div 0 */ | |
228 | /* if div by zero, set source1 to -1, otherwise don't change */ | |
229 | tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond2, zeroreg, source1, | |
230 | resultopt1); | |
231 | /* if overflow or div by zero, set source2 to 1, else don't change */ | |
232 | tcg_gen_or_tl(cond1, cond1, cond2); | |
233 | tcg_gen_movi_tl(resultopt1, (target_ulong)1); | |
234 | tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2, | |
235 | resultopt1); | |
236 | tcg_gen_div_tl(ret, source1, source2); | |
237 | ||
238 | tcg_temp_free(cond1); | |
239 | tcg_temp_free(cond2); | |
240 | tcg_temp_free(zeroreg); | |
241 | tcg_temp_free(resultopt1); | |
242 | } | |
55c2a12c | 243 | |
12887016 BK |
244 | static void gen_divu(TCGv ret, TCGv source1, TCGv source2) |
245 | { | |
246 | TCGv cond1, zeroreg, resultopt1; | |
247 | cond1 = tcg_temp_new(); | |
248 | ||
249 | zeroreg = tcg_const_tl(0); | |
250 | resultopt1 = tcg_temp_new(); | |
251 | ||
252 | tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); | |
253 | tcg_gen_movi_tl(resultopt1, (target_ulong)-1); | |
254 | tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond1, zeroreg, source1, | |
255 | resultopt1); | |
256 | tcg_gen_movi_tl(resultopt1, (target_ulong)1); | |
257 | tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2, | |
258 | resultopt1); | |
259 | tcg_gen_divu_tl(ret, source1, source2); | |
260 | ||
261 | tcg_temp_free(cond1); | |
262 | tcg_temp_free(zeroreg); | |
263 | tcg_temp_free(resultopt1); | |
264 | } | |
55c2a12c | 265 | |
12887016 BK |
266 | static void gen_rem(TCGv ret, TCGv source1, TCGv source2) |
267 | { | |
268 | TCGv cond1, cond2, zeroreg, resultopt1; | |
269 | ||
270 | cond1 = tcg_temp_new(); | |
271 | cond2 = tcg_temp_new(); | |
272 | zeroreg = tcg_const_tl(0); | |
273 | resultopt1 = tcg_temp_new(); | |
274 | ||
275 | tcg_gen_movi_tl(resultopt1, 1L); | |
276 | tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)-1); | |
277 | tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1, | |
278 | (target_ulong)1 << (TARGET_LONG_BITS - 1)); | |
279 | tcg_gen_and_tl(cond2, cond1, cond2); /* cond1 = overflow */ | |
280 | tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); /* cond2 = div 0 */ | |
281 | /* if overflow or div by zero, set source2 to 1, else don't change */ | |
282 | tcg_gen_or_tl(cond2, cond1, cond2); | |
283 | tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond2, zeroreg, source2, | |
284 | resultopt1); | |
285 | tcg_gen_rem_tl(resultopt1, source1, source2); | |
286 | /* if div by zero, just return the original dividend */ | |
287 | tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1, | |
288 | source1); | |
289 | ||
290 | tcg_temp_free(cond1); | |
291 | tcg_temp_free(cond2); | |
292 | tcg_temp_free(zeroreg); | |
293 | tcg_temp_free(resultopt1); | |
294 | } | |
55c2a12c | 295 | |
12887016 BK |
296 | static void gen_remu(TCGv ret, TCGv source1, TCGv source2) |
297 | { | |
298 | TCGv cond1, zeroreg, resultopt1; | |
299 | cond1 = tcg_temp_new(); | |
300 | zeroreg = tcg_const_tl(0); | |
301 | resultopt1 = tcg_temp_new(); | |
302 | ||
303 | tcg_gen_movi_tl(resultopt1, (target_ulong)1); | |
304 | tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); | |
305 | tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2, | |
306 | resultopt1); | |
307 | tcg_gen_remu_tl(resultopt1, source1, source2); | |
308 | /* if div by zero, just return the original dividend */ | |
309 | tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1, | |
310 | source1); | |
311 | ||
312 | tcg_temp_free(cond1); | |
313 | tcg_temp_free(zeroreg); | |
314 | tcg_temp_free(resultopt1); | |
55c2a12c MC |
315 | } |
316 | ||
db9f3fd6 | 317 | static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) |
55c2a12c MC |
318 | { |
319 | target_ulong next_pc; | |
320 | ||
321 | /* check misaligned: */ | |
0114db1c | 322 | next_pc = ctx->base.pc_next + imm; |
db9f3fd6 | 323 | if (!has_ext(ctx, RVC)) { |
55c2a12c MC |
324 | if ((next_pc & 0x3) != 0) { |
325 | gen_exception_inst_addr_mis(ctx); | |
326 | return; | |
327 | } | |
328 | } | |
329 | if (rd != 0) { | |
0114db1c | 330 | tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn); |
55c2a12c MC |
331 | } |
332 | ||
0114db1c EC |
333 | gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */ |
334 | ctx->base.is_jmp = DISAS_NORETURN; | |
55c2a12c MC |
335 | } |
336 | ||
98898b20 BK |
337 | #ifdef TARGET_RISCV64 |
338 | static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1, | |
55c2a12c MC |
339 | target_long imm) |
340 | { | |
341 | TCGv t0 = tcg_temp_new(); | |
342 | TCGv t1 = tcg_temp_new(); | |
343 | gen_get_gpr(t0, rs1); | |
344 | tcg_gen_addi_tl(t0, t0, imm); | |
345 | int memop = tcg_memop_lookup[(opc >> 12) & 0x7]; | |
346 | ||
347 | if (memop < 0) { | |
348 | gen_exception_illegal(ctx); | |
349 | return; | |
350 | } | |
351 | ||
352 | tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop); | |
353 | gen_set_gpr(rd, t1); | |
354 | tcg_temp_free(t0); | |
355 | tcg_temp_free(t1); | |
356 | } | |
357 | ||
bce8a342 | 358 | static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2, |
55c2a12c MC |
359 | target_long imm) |
360 | { | |
361 | TCGv t0 = tcg_temp_new(); | |
362 | TCGv dat = tcg_temp_new(); | |
363 | gen_get_gpr(t0, rs1); | |
364 | tcg_gen_addi_tl(t0, t0, imm); | |
365 | gen_get_gpr(dat, rs2); | |
366 | int memop = tcg_memop_lookup[(opc >> 12) & 0x7]; | |
367 | ||
368 | if (memop < 0) { | |
369 | gen_exception_illegal(ctx); | |
370 | return; | |
371 | } | |
372 | ||
373 | tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop); | |
374 | tcg_temp_free(t0); | |
375 | tcg_temp_free(dat); | |
376 | } | |
bce8a342 | 377 | #endif |
55c2a12c | 378 | |
533b8f88 RH |
379 | #ifndef CONFIG_USER_ONLY |
380 | /* The states of mstatus_fs are: | |
381 | * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty | |
382 | * We will have already diagnosed disabled state, | |
383 | * and need to turn initial/clean into dirty. | |
384 | */ | |
385 | static void mark_fs_dirty(DisasContext *ctx) | |
386 | { | |
387 | TCGv tmp; | |
388 | if (ctx->mstatus_fs == MSTATUS_FS) { | |
389 | return; | |
390 | } | |
391 | /* Remember the state change for the rest of the TB. */ | |
392 | ctx->mstatus_fs = MSTATUS_FS; | |
393 | ||
394 | tmp = tcg_temp_new(); | |
395 | tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); | |
82f01467 | 396 | tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD); |
533b8f88 RH |
397 | tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); |
398 | tcg_temp_free(tmp); | |
399 | } | |
400 | #else | |
401 | static inline void mark_fs_dirty(DisasContext *ctx) { } | |
402 | #endif | |
403 | ||
97b0be81 | 404 | #if !defined(TARGET_RISCV64) |
55c2a12c MC |
405 | static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd, |
406 | int rs1, target_long imm) | |
407 | { | |
408 | TCGv t0; | |
409 | ||
83a71719 | 410 | if (ctx->mstatus_fs == 0) { |
55c2a12c MC |
411 | gen_exception_illegal(ctx); |
412 | return; | |
413 | } | |
414 | ||
415 | t0 = tcg_temp_new(); | |
416 | gen_get_gpr(t0, rs1); | |
417 | tcg_gen_addi_tl(t0, t0, imm); | |
418 | ||
419 | switch (opc) { | |
420 | case OPC_RISC_FLW: | |
d77c3401 MC |
421 | if (!has_ext(ctx, RVF)) { |
422 | goto do_illegal; | |
423 | } | |
55c2a12c MC |
424 | tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEUL); |
425 | /* RISC-V requires NaN-boxing of narrower width floating point values */ | |
426 | tcg_gen_ori_i64(cpu_fpr[rd], cpu_fpr[rd], 0xffffffff00000000ULL); | |
427 | break; | |
428 | case OPC_RISC_FLD: | |
d77c3401 MC |
429 | if (!has_ext(ctx, RVD)) { |
430 | goto do_illegal; | |
431 | } | |
55c2a12c MC |
432 | tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEQ); |
433 | break; | |
d77c3401 | 434 | do_illegal: |
55c2a12c MC |
435 | default: |
436 | gen_exception_illegal(ctx); | |
437 | break; | |
438 | } | |
439 | tcg_temp_free(t0); | |
533b8f88 RH |
440 | |
441 | mark_fs_dirty(ctx); | |
55c2a12c MC |
442 | } |
443 | ||
444 | static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1, | |
445 | int rs2, target_long imm) | |
446 | { | |
447 | TCGv t0; | |
448 | ||
83a71719 | 449 | if (ctx->mstatus_fs == 0) { |
55c2a12c MC |
450 | gen_exception_illegal(ctx); |
451 | return; | |
452 | } | |
453 | ||
454 | t0 = tcg_temp_new(); | |
455 | gen_get_gpr(t0, rs1); | |
456 | tcg_gen_addi_tl(t0, t0, imm); | |
457 | ||
458 | switch (opc) { | |
459 | case OPC_RISC_FSW: | |
d77c3401 MC |
460 | if (!has_ext(ctx, RVF)) { |
461 | goto do_illegal; | |
462 | } | |
55c2a12c MC |
463 | tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEUL); |
464 | break; | |
465 | case OPC_RISC_FSD: | |
d77c3401 MC |
466 | if (!has_ext(ctx, RVD)) { |
467 | goto do_illegal; | |
468 | } | |
55c2a12c MC |
469 | tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEQ); |
470 | break; | |
d77c3401 | 471 | do_illegal: |
55c2a12c MC |
472 | default: |
473 | gen_exception_illegal(ctx); | |
474 | break; | |
475 | } | |
476 | ||
477 | tcg_temp_free(t0); | |
478 | } | |
97b0be81 | 479 | #endif |
55c2a12c | 480 | |
55c2a12c MC |
481 | static void gen_set_rm(DisasContext *ctx, int rm) |
482 | { | |
483 | TCGv_i32 t0; | |
484 | ||
485 | if (ctx->frm == rm) { | |
486 | return; | |
487 | } | |
488 | ctx->frm = rm; | |
489 | t0 = tcg_const_i32(rm); | |
490 | gen_helper_set_rounding_mode(cpu_env, t0); | |
491 | tcg_temp_free_i32(t0); | |
492 | } | |
493 | ||
25139bf7 | 494 | static void decode_RV32_64C0(DisasContext *ctx, uint16_t opcode) |
55c2a12c | 495 | { |
25139bf7 AB |
496 | uint8_t funct3 = extract16(opcode, 13, 3); |
497 | uint8_t rd_rs2 = GET_C_RS2S(opcode); | |
498 | uint8_t rs1s = GET_C_RS1S(opcode); | |
55c2a12c MC |
499 | |
500 | switch (funct3) { | |
55c2a12c MC |
501 | case 3: |
502 | #if defined(TARGET_RISCV64) | |
503 | /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/ | |
98898b20 | 504 | gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s, |
25139bf7 | 505 | GET_C_LD_IMM(opcode)); |
55c2a12c MC |
506 | #else |
507 | /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/ | |
508 | gen_fp_load(ctx, OPC_RISC_FLW, rd_rs2, rs1s, | |
25139bf7 | 509 | GET_C_LW_IMM(opcode)); |
55c2a12c MC |
510 | #endif |
511 | break; | |
55c2a12c MC |
512 | case 7: |
513 | #if defined(TARGET_RISCV64) | |
514 | /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/ | |
bce8a342 | 515 | gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2, |
25139bf7 | 516 | GET_C_LD_IMM(opcode)); |
55c2a12c MC |
517 | #else |
518 | /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/ | |
519 | gen_fp_store(ctx, OPC_RISC_FSW, rs1s, rd_rs2, | |
25139bf7 | 520 | GET_C_LW_IMM(opcode)); |
55c2a12c MC |
521 | #endif |
522 | break; | |
523 | } | |
524 | } | |
525 | ||
25139bf7 | 526 | static void decode_RV32_64C(DisasContext *ctx, uint16_t opcode) |
55c2a12c | 527 | { |
25139bf7 | 528 | uint8_t op = extract16(opcode, 0, 2); |
55c2a12c MC |
529 | |
530 | switch (op) { | |
531 | case 0: | |
25139bf7 | 532 | decode_RV32_64C0(ctx, opcode); |
55c2a12c | 533 | break; |
55c2a12c MC |
534 | } |
535 | } | |
536 | ||
2a53cff4 | 537 | #define EX_SH(amount) \ |
451e4ffd | 538 | static int ex_shift_##amount(DisasContext *ctx, int imm) \ |
2a53cff4 BK |
539 | { \ |
540 | return imm << amount; \ | |
541 | } | |
3cca75a6 | 542 | EX_SH(1) |
e98d9140 BK |
543 | EX_SH(2) |
544 | EX_SH(3) | |
07b001c6 | 545 | EX_SH(4) |
2a53cff4 BK |
546 | EX_SH(12) |
547 | ||
d2e2c1e4 BK |
548 | #define REQUIRE_EXT(ctx, ext) do { \ |
549 | if (!has_ext(ctx, ext)) { \ | |
550 | return false; \ | |
551 | } \ | |
552 | } while (0) | |
553 | ||
451e4ffd | 554 | static int ex_rvc_register(DisasContext *ctx, int reg) |
e98d9140 BK |
555 | { |
556 | return 8 + reg; | |
557 | } | |
558 | ||
6cafec92 RH |
559 | static int ex_rvc_shifti(DisasContext *ctx, int imm) |
560 | { | |
561 | /* For RV128 a shamt of 0 means a shift by 64. */ | |
562 | return imm ? imm : 64; | |
563 | } | |
564 | ||
2a53cff4 BK |
565 | /* Include the auto-generated decoder for 32 bit insn */ |
566 | #include "decode_insn32.inc.c" | |
7a50d3e2 | 567 | |
598aa116 RH |
568 | static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, |
569 | void (*func)(TCGv, TCGv, target_long)) | |
570 | { | |
571 | TCGv source1; | |
572 | source1 = tcg_temp_new(); | |
573 | ||
574 | gen_get_gpr(source1, a->rs1); | |
575 | ||
576 | (*func)(source1, source1, a->imm); | |
577 | ||
578 | gen_set_gpr(a->rd, source1); | |
579 | tcg_temp_free(source1); | |
580 | return true; | |
581 | } | |
582 | ||
583 | static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, | |
584 | void (*func)(TCGv, TCGv, TCGv)) | |
7a50d3e2 BK |
585 | { |
586 | TCGv source1, source2; | |
587 | source1 = tcg_temp_new(); | |
588 | source2 = tcg_temp_new(); | |
589 | ||
590 | gen_get_gpr(source1, a->rs1); | |
591 | tcg_gen_movi_tl(source2, a->imm); | |
592 | ||
593 | (*func)(source1, source1, source2); | |
594 | ||
595 | gen_set_gpr(a->rd, source1); | |
596 | tcg_temp_free(source1); | |
597 | tcg_temp_free(source2); | |
598 | return true; | |
599 | } | |
600 | ||
601 | #ifdef TARGET_RISCV64 | |
602 | static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2) | |
603 | { | |
604 | tcg_gen_add_tl(ret, arg1, arg2); | |
605 | tcg_gen_ext32s_tl(ret, ret); | |
606 | } | |
f2ab1728 BK |
607 | |
608 | static void gen_subw(TCGv ret, TCGv arg1, TCGv arg2) | |
609 | { | |
610 | tcg_gen_sub_tl(ret, arg1, arg2); | |
611 | tcg_gen_ext32s_tl(ret, ret); | |
612 | } | |
613 | ||
12887016 BK |
614 | static void gen_mulw(TCGv ret, TCGv arg1, TCGv arg2) |
615 | { | |
616 | tcg_gen_mul_tl(ret, arg1, arg2); | |
617 | tcg_gen_ext32s_tl(ret, ret); | |
618 | } | |
619 | ||
620 | static bool gen_arith_div_w(DisasContext *ctx, arg_r *a, | |
621 | void(*func)(TCGv, TCGv, TCGv)) | |
622 | { | |
623 | TCGv source1, source2; | |
624 | source1 = tcg_temp_new(); | |
625 | source2 = tcg_temp_new(); | |
626 | ||
627 | gen_get_gpr(source1, a->rs1); | |
628 | gen_get_gpr(source2, a->rs2); | |
629 | tcg_gen_ext32s_tl(source1, source1); | |
630 | tcg_gen_ext32s_tl(source2, source2); | |
631 | ||
632 | (*func)(source1, source1, source2); | |
633 | ||
634 | tcg_gen_ext32s_tl(source1, source1); | |
635 | gen_set_gpr(a->rd, source1); | |
636 | tcg_temp_free(source1); | |
637 | tcg_temp_free(source2); | |
638 | return true; | |
639 | } | |
640 | ||
f17e02cd PD |
641 | static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a, |
642 | void(*func)(TCGv, TCGv, TCGv)) | |
643 | { | |
644 | TCGv source1, source2; | |
645 | source1 = tcg_temp_new(); | |
646 | source2 = tcg_temp_new(); | |
647 | ||
648 | gen_get_gpr(source1, a->rs1); | |
649 | gen_get_gpr(source2, a->rs2); | |
650 | tcg_gen_ext32u_tl(source1, source1); | |
651 | tcg_gen_ext32u_tl(source2, source2); | |
652 | ||
653 | (*func)(source1, source1, source2); | |
654 | ||
655 | tcg_gen_ext32s_tl(source1, source1); | |
656 | gen_set_gpr(a->rd, source1); | |
657 | tcg_temp_free(source1); | |
658 | tcg_temp_free(source2); | |
659 | return true; | |
660 | } | |
661 | ||
7a50d3e2 BK |
662 | #endif |
663 | ||
8dc9e8a8 BK |
664 | static bool gen_arith(DisasContext *ctx, arg_r *a, |
665 | void(*func)(TCGv, TCGv, TCGv)) | |
f2ab1728 BK |
666 | { |
667 | TCGv source1, source2; | |
668 | source1 = tcg_temp_new(); | |
669 | source2 = tcg_temp_new(); | |
670 | ||
671 | gen_get_gpr(source1, a->rs1); | |
672 | gen_get_gpr(source2, a->rs2); | |
673 | ||
674 | (*func)(source1, source1, source2); | |
675 | ||
676 | gen_set_gpr(a->rd, source1); | |
677 | tcg_temp_free(source1); | |
678 | tcg_temp_free(source2); | |
679 | return true; | |
680 | } | |
681 | ||
34446e84 BK |
682 | static bool gen_shift(DisasContext *ctx, arg_r *a, |
683 | void(*func)(TCGv, TCGv, TCGv)) | |
684 | { | |
685 | TCGv source1 = tcg_temp_new(); | |
686 | TCGv source2 = tcg_temp_new(); | |
687 | ||
688 | gen_get_gpr(source1, a->rs1); | |
689 | gen_get_gpr(source2, a->rs2); | |
690 | ||
691 | tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1); | |
692 | (*func)(source1, source1, source2); | |
693 | ||
694 | gen_set_gpr(a->rd, source1); | |
695 | tcg_temp_free(source1); | |
696 | tcg_temp_free(source2); | |
697 | return true; | |
698 | } | |
699 | ||
2a53cff4 BK |
700 | /* Include insn module translation function */ |
701 | #include "insn_trans/trans_rvi.inc.c" | |
d2e2c1e4 | 702 | #include "insn_trans/trans_rvm.inc.c" |
3b77c289 | 703 | #include "insn_trans/trans_rva.inc.c" |
6f0e74ff | 704 | #include "insn_trans/trans_rvf.inc.c" |
97f8b493 | 705 | #include "insn_trans/trans_rvd.inc.c" |
4ba79c47 | 706 | #include "insn_trans/trans_privileged.inc.c" |
2a53cff4 | 707 | |
59a3a1c0 | 708 | /* Include the auto-generated decoder for 16 bit insn */ |
e98d9140 | 709 | #include "decode_insn16.inc.c" |
e98d9140 | 710 | |
25139bf7 | 711 | static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) |
55c2a12c MC |
712 | { |
713 | /* check for compressed insn */ | |
25139bf7 | 714 | if (extract16(opcode, 0, 2) != 3) { |
db9f3fd6 | 715 | if (!has_ext(ctx, RVC)) { |
55c2a12c MC |
716 | gen_exception_illegal(ctx); |
717 | } else { | |
0114db1c | 718 | ctx->pc_succ_insn = ctx->base.pc_next + 2; |
25139bf7 | 719 | if (!decode_insn16(ctx, opcode)) { |
e98d9140 | 720 | /* fall back to old decoder */ |
25139bf7 | 721 | decode_RV32_64C(ctx, opcode); |
e98d9140 | 722 | } |
55c2a12c MC |
723 | } |
724 | } else { | |
25139bf7 AB |
725 | uint32_t opcode32 = opcode; |
726 | opcode32 = deposit32(opcode32, 16, 16, | |
727 | translator_lduw(env, ctx->base.pc_next + 2)); | |
0114db1c | 728 | ctx->pc_succ_insn = ctx->base.pc_next + 4; |
25139bf7 | 729 | if (!decode_insn32(ctx, opcode32)) { |
25e6ca30 | 730 | gen_exception_illegal(ctx); |
2a53cff4 | 731 | } |
55c2a12c MC |
732 | } |
733 | } | |
734 | ||
5b4f1d2d | 735 | static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) |
55c2a12c | 736 | { |
5b4f1d2d | 737 | DisasContext *ctx = container_of(dcbase, DisasContext, base); |
d75377bf | 738 | CPURISCVState *env = cs->env_ptr; |
50fba816 | 739 | RISCVCPU *cpu = RISCV_CPU(cs); |
55c2a12c | 740 | |
5b4f1d2d | 741 | ctx->pc_succ_insn = ctx->base.pc_first; |
5b4f1d2d | 742 | ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK; |
83a71719 | 743 | ctx->mstatus_fs = ctx->base.tb->flags & TB_FLAGS_MSTATUS_FS; |
d75377bf | 744 | ctx->priv_ver = env->priv_ver; |
db9f3fd6 | 745 | ctx->misa = env->misa; |
5b4f1d2d | 746 | ctx->frm = -1; /* unknown rounding mode */ |
50fba816 | 747 | ctx->ext_ifencei = cpu->cfg.ext_ifencei; |
5b4f1d2d | 748 | } |
55c2a12c | 749 | |
5b4f1d2d EC |
750 | static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) |
751 | { | |
752 | } | |
55c2a12c | 753 | |
5b4f1d2d EC |
754 | static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) |
755 | { | |
756 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
757 | ||
758 | tcg_gen_insn_start(ctx->base.pc_next); | |
759 | } | |
760 | ||
761 | static bool riscv_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, | |
762 | const CPUBreakpoint *bp) | |
763 | { | |
764 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
765 | ||
766 | tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); | |
767 | ctx->base.is_jmp = DISAS_NORETURN; | |
768 | gen_exception_debug(); | |
769 | /* The address covered by the breakpoint must be included in | |
770 | [tb->pc, tb->pc + tb->size) in order to for it to be | |
771 | properly cleared -- thus we increment the PC here so that | |
772 | the logic setting tb->size below does the right thing. */ | |
773 | ctx->base.pc_next += 4; | |
774 | return true; | |
775 | } | |
776 | ||
5b4f1d2d EC |
777 | static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) |
778 | { | |
779 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
780 | CPURISCVState *env = cpu->env_ptr; | |
25139bf7 | 781 | uint16_t opcode16 = translator_lduw(env, ctx->base.pc_next); |
55c2a12c | 782 | |
25139bf7 | 783 | decode_opc(env, ctx, opcode16); |
5b4f1d2d EC |
784 | ctx->base.pc_next = ctx->pc_succ_insn; |
785 | ||
786 | if (ctx->base.is_jmp == DISAS_NEXT) { | |
787 | target_ulong page_start; | |
788 | ||
789 | page_start = ctx->base.pc_first & TARGET_PAGE_MASK; | |
790 | if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) { | |
791 | ctx->base.is_jmp = DISAS_TOO_MANY; | |
55c2a12c | 792 | } |
55c2a12c | 793 | } |
5b4f1d2d EC |
794 | } |
795 | ||
796 | static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) | |
797 | { | |
798 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
799 | ||
800 | switch (ctx->base.is_jmp) { | |
b2e32021 | 801 | case DISAS_TOO_MANY: |
ccf08e40 | 802 | gen_goto_tb(ctx, 0, ctx->base.pc_next); |
55c2a12c | 803 | break; |
b2e32021 | 804 | case DISAS_NORETURN: |
55c2a12c | 805 | break; |
b2e32021 EC |
806 | default: |
807 | g_assert_not_reached(); | |
55c2a12c | 808 | } |
5b4f1d2d EC |
809 | } |
810 | ||
811 | static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) | |
812 | { | |
813 | qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); | |
814 | log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); | |
815 | } | |
816 | ||
817 | static const TranslatorOps riscv_tr_ops = { | |
818 | .init_disas_context = riscv_tr_init_disas_context, | |
819 | .tb_start = riscv_tr_tb_start, | |
820 | .insn_start = riscv_tr_insn_start, | |
821 | .breakpoint_check = riscv_tr_breakpoint_check, | |
822 | .translate_insn = riscv_tr_translate_insn, | |
823 | .tb_stop = riscv_tr_tb_stop, | |
824 | .disas_log = riscv_tr_disas_log, | |
825 | }; | |
826 | ||
8b86d6d2 | 827 | void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) |
5b4f1d2d EC |
828 | { |
829 | DisasContext ctx; | |
830 | ||
8b86d6d2 | 831 | translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns); |
55c2a12c MC |
832 | } |
833 | ||
834 | void riscv_translate_init(void) | |
835 | { | |
836 | int i; | |
837 | ||
838 | /* cpu_gpr[0] is a placeholder for the zero register. Do not use it. */ | |
839 | /* Use the gen_set_gpr and gen_get_gpr helper functions when accessing */ | |
840 | /* registers, unless you specifically block reads/writes to reg 0 */ | |
841 | cpu_gpr[0] = NULL; | |
842 | ||
843 | for (i = 1; i < 32; i++) { | |
844 | cpu_gpr[i] = tcg_global_mem_new(cpu_env, | |
845 | offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); | |
846 | } | |
847 | ||
848 | for (i = 0; i < 32; i++) { | |
849 | cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, | |
850 | offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); | |
851 | } | |
852 | ||
853 | cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); | |
854 | load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), | |
855 | "load_res"); | |
856 | load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), | |
857 | "load_val"); | |
858 | } |