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55c2a12c MC |
1 | /* |
2 | * RISC-V emulation for qemu: main translation routines. | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2 or later, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along with | |
16 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | ||
19 | #include "qemu/osdep.h" | |
20 | #include "qemu/log.h" | |
21 | #include "cpu.h" | |
dcb32f1d | 22 | #include "tcg/tcg-op.h" |
55c2a12c MC |
23 | #include "disas/disas.h" |
24 | #include "exec/cpu_ldst.h" | |
25 | #include "exec/exec-all.h" | |
26 | #include "exec/helper-proto.h" | |
27 | #include "exec/helper-gen.h" | |
28 | ||
b2e32021 | 29 | #include "exec/translator.h" |
55c2a12c MC |
30 | #include "exec/log.h" |
31 | ||
32 | #include "instmap.h" | |
33 | ||
34 | /* global register indices */ | |
ad9e5aa2 | 35 | static TCGv cpu_gpr[32], cpu_pc, cpu_vl; |
55c2a12c MC |
36 | static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ |
37 | static TCGv load_res; | |
38 | static TCGv load_val; | |
39 | ||
40 | #include "exec/gen-icount.h" | |
41 | ||
42 | typedef struct DisasContext { | |
0114db1c EC |
43 | DisasContextBase base; |
44 | /* pc_succ_insn points to the instruction following base.pc_next */ | |
45 | target_ulong pc_succ_insn; | |
d75377bf | 46 | target_ulong priv_ver; |
45b4dc8b AF |
47 | bool virt_enabled; |
48 | uint32_t opcode; | |
83a71719 | 49 | uint32_t mstatus_fs; |
db9f3fd6 | 50 | uint32_t misa; |
55c2a12c | 51 | uint32_t mem_idx; |
55c2a12c MC |
52 | /* Remember the rounding mode encoded in the previous fp instruction, |
53 | which we have already installed into env->fp_status. Or -1 for | |
54 | no previous fp instruction. Note that we exit the TB when writing | |
55 | to any system register, which includes CSR_FRM, so we do not have | |
56 | to reset this known value. */ | |
57 | int frm; | |
50fba816 | 58 | bool ext_ifencei; |
743077b3 | 59 | bool hlsx; |
2b7168fc LZ |
60 | /* vector extension */ |
61 | bool vill; | |
62 | uint8_t lmul; | |
63 | uint8_t sew; | |
64 | uint16_t vlen; | |
751538d5 | 65 | uint16_t mlen; |
2b7168fc | 66 | bool vl_eq_vlmax; |
a10b9d93 | 67 | CPUState *cs; |
55c2a12c MC |
68 | } DisasContext; |
69 | ||
db9f3fd6 MC |
70 | static inline bool has_ext(DisasContext *ctx, uint32_t ext) |
71 | { | |
72 | return ctx->misa & ext; | |
d36a86d0 RH |
73 | } |
74 | ||
4fd7455b AF |
75 | #ifdef TARGET_RISCV32 |
76 | # define is_32bit(ctx) true | |
77 | #elif defined(CONFIG_USER_ONLY) | |
78 | # define is_32bit(ctx) false | |
79 | #else | |
80 | static inline bool is_32bit(DisasContext *ctx) | |
81 | { | |
82 | return (ctx->misa & RV32) == RV32; | |
83 | } | |
84 | #endif | |
85 | ||
d36a86d0 RH |
86 | /* |
87 | * RISC-V requires NaN-boxing of narrower width floating point values. | |
88 | * This applies when a 32-bit value is assigned to a 64-bit FP register. | |
89 | * For consistency and simplicity, we nanbox results even when the RVD | |
90 | * extension is not present. | |
91 | */ | |
92 | static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) | |
93 | { | |
94 | tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); | |
ffe70e4d RH |
95 | } |
96 | ||
97 | /* | |
98 | * A narrow n-bit operation, where n < FLEN, checks that input operands | |
99 | * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. | |
100 | * If so, the least-significant bits of the input are used, otherwise the | |
101 | * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). | |
102 | * | |
103 | * Here, the result is always nan-boxed, even the canonical nan. | |
104 | */ | |
105 | static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) | |
106 | { | |
107 | TCGv_i64 t_max = tcg_const_i64(0xffffffff00000000ull); | |
108 | TCGv_i64 t_nan = tcg_const_i64(0xffffffff7fc00000ull); | |
109 | ||
110 | tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); | |
111 | tcg_temp_free_i64(t_max); | |
112 | tcg_temp_free_i64(t_nan); | |
db9f3fd6 MC |
113 | } |
114 | ||
55c2a12c MC |
115 | static void generate_exception(DisasContext *ctx, int excp) |
116 | { | |
0114db1c | 117 | tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); |
55c2a12c MC |
118 | TCGv_i32 helper_tmp = tcg_const_i32(excp); |
119 | gen_helper_raise_exception(cpu_env, helper_tmp); | |
120 | tcg_temp_free_i32(helper_tmp); | |
0114db1c | 121 | ctx->base.is_jmp = DISAS_NORETURN; |
55c2a12c MC |
122 | } |
123 | ||
ac12b601 | 124 | static void generate_exception_mtval(DisasContext *ctx, int excp) |
55c2a12c | 125 | { |
0114db1c | 126 | tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); |
55c2a12c MC |
127 | tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); |
128 | TCGv_i32 helper_tmp = tcg_const_i32(excp); | |
129 | gen_helper_raise_exception(cpu_env, helper_tmp); | |
130 | tcg_temp_free_i32(helper_tmp); | |
0114db1c | 131 | ctx->base.is_jmp = DISAS_NORETURN; |
55c2a12c MC |
132 | } |
133 | ||
134 | static void gen_exception_debug(void) | |
135 | { | |
136 | TCGv_i32 helper_tmp = tcg_const_i32(EXCP_DEBUG); | |
137 | gen_helper_raise_exception(cpu_env, helper_tmp); | |
138 | tcg_temp_free_i32(helper_tmp); | |
139 | } | |
140 | ||
6e2716d8 FC |
141 | /* Wrapper around tcg_gen_exit_tb that handles single stepping */ |
142 | static void exit_tb(DisasContext *ctx) | |
143 | { | |
144 | if (ctx->base.singlestep_enabled) { | |
145 | gen_exception_debug(); | |
146 | } else { | |
147 | tcg_gen_exit_tb(NULL, 0); | |
148 | } | |
149 | } | |
150 | ||
151 | /* Wrapper around tcg_gen_lookup_and_goto_ptr that handles single stepping */ | |
152 | static void lookup_and_goto_ptr(DisasContext *ctx) | |
153 | { | |
154 | if (ctx->base.singlestep_enabled) { | |
155 | gen_exception_debug(); | |
156 | } else { | |
157 | tcg_gen_lookup_and_goto_ptr(); | |
158 | } | |
159 | } | |
160 | ||
55c2a12c MC |
161 | static void gen_exception_illegal(DisasContext *ctx) |
162 | { | |
163 | generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); | |
164 | } | |
165 | ||
166 | static void gen_exception_inst_addr_mis(DisasContext *ctx) | |
167 | { | |
ac12b601 | 168 | generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS); |
55c2a12c MC |
169 | } |
170 | ||
171 | static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) | |
172 | { | |
0114db1c | 173 | if (unlikely(ctx->base.singlestep_enabled)) { |
55c2a12c MC |
174 | return false; |
175 | } | |
176 | ||
177 | #ifndef CONFIG_USER_ONLY | |
0114db1c | 178 | return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); |
55c2a12c MC |
179 | #else |
180 | return true; | |
181 | #endif | |
182 | } | |
183 | ||
184 | static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) | |
185 | { | |
186 | if (use_goto_tb(ctx, dest)) { | |
187 | /* chaining is only allowed when the jump is to the same page */ | |
188 | tcg_gen_goto_tb(n); | |
189 | tcg_gen_movi_tl(cpu_pc, dest); | |
6e2716d8 FC |
190 | |
191 | /* No need to check for single stepping here as use_goto_tb() will | |
192 | * return false in case of single stepping. | |
193 | */ | |
07ea28b4 | 194 | tcg_gen_exit_tb(ctx->base.tb, n); |
55c2a12c MC |
195 | } else { |
196 | tcg_gen_movi_tl(cpu_pc, dest); | |
6e2716d8 | 197 | lookup_and_goto_ptr(ctx); |
55c2a12c MC |
198 | } |
199 | } | |
200 | ||
201 | /* Wrapper for getting reg values - need to check of reg is zero since | |
202 | * cpu_gpr[0] is not actually allocated | |
203 | */ | |
204 | static inline void gen_get_gpr(TCGv t, int reg_num) | |
205 | { | |
206 | if (reg_num == 0) { | |
207 | tcg_gen_movi_tl(t, 0); | |
208 | } else { | |
209 | tcg_gen_mov_tl(t, cpu_gpr[reg_num]); | |
210 | } | |
211 | } | |
212 | ||
213 | /* Wrapper for setting reg values - need to check of reg is zero since | |
214 | * cpu_gpr[0] is not actually allocated. this is more for safety purposes, | |
215 | * since we usually avoid calling the OP_TYPE_gen function if we see a write to | |
216 | * $zero | |
217 | */ | |
218 | static inline void gen_set_gpr(int reg_num_dst, TCGv t) | |
219 | { | |
220 | if (reg_num_dst != 0) { | |
221 | tcg_gen_mov_tl(cpu_gpr[reg_num_dst], t); | |
222 | } | |
223 | } | |
224 | ||
225 | static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2) | |
226 | { | |
227 | TCGv rl = tcg_temp_new(); | |
228 | TCGv rh = tcg_temp_new(); | |
229 | ||
230 | tcg_gen_mulu2_tl(rl, rh, arg1, arg2); | |
231 | /* fix up for one negative */ | |
232 | tcg_gen_sari_tl(rl, arg1, TARGET_LONG_BITS - 1); | |
233 | tcg_gen_and_tl(rl, rl, arg2); | |
234 | tcg_gen_sub_tl(ret, rh, rl); | |
235 | ||
236 | tcg_temp_free(rl); | |
237 | tcg_temp_free(rh); | |
238 | } | |
239 | ||
12887016 | 240 | static void gen_div(TCGv ret, TCGv source1, TCGv source2) |
55c2a12c | 241 | { |
12887016 BK |
242 | TCGv cond1, cond2, zeroreg, resultopt1; |
243 | /* | |
244 | * Handle by altering args to tcg_gen_div to produce req'd results: | |
245 | * For overflow: want source1 in source1 and 1 in source2 | |
246 | * For div by zero: want -1 in source1 and 1 in source2 -> -1 result | |
247 | */ | |
248 | cond1 = tcg_temp_new(); | |
249 | cond2 = tcg_temp_new(); | |
250 | zeroreg = tcg_const_tl(0); | |
251 | resultopt1 = tcg_temp_new(); | |
252 | ||
253 | tcg_gen_movi_tl(resultopt1, (target_ulong)-1); | |
254 | tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)(~0L)); | |
255 | tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1, | |
256 | ((target_ulong)1) << (TARGET_LONG_BITS - 1)); | |
257 | tcg_gen_and_tl(cond1, cond1, cond2); /* cond1 = overflow */ | |
258 | tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, 0); /* cond2 = div 0 */ | |
259 | /* if div by zero, set source1 to -1, otherwise don't change */ | |
260 | tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond2, zeroreg, source1, | |
261 | resultopt1); | |
262 | /* if overflow or div by zero, set source2 to 1, else don't change */ | |
263 | tcg_gen_or_tl(cond1, cond1, cond2); | |
264 | tcg_gen_movi_tl(resultopt1, (target_ulong)1); | |
265 | tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2, | |
266 | resultopt1); | |
267 | tcg_gen_div_tl(ret, source1, source2); | |
268 | ||
269 | tcg_temp_free(cond1); | |
270 | tcg_temp_free(cond2); | |
271 | tcg_temp_free(zeroreg); | |
272 | tcg_temp_free(resultopt1); | |
273 | } | |
55c2a12c | 274 | |
12887016 BK |
275 | static void gen_divu(TCGv ret, TCGv source1, TCGv source2) |
276 | { | |
277 | TCGv cond1, zeroreg, resultopt1; | |
278 | cond1 = tcg_temp_new(); | |
279 | ||
280 | zeroreg = tcg_const_tl(0); | |
281 | resultopt1 = tcg_temp_new(); | |
282 | ||
283 | tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); | |
284 | tcg_gen_movi_tl(resultopt1, (target_ulong)-1); | |
285 | tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond1, zeroreg, source1, | |
286 | resultopt1); | |
287 | tcg_gen_movi_tl(resultopt1, (target_ulong)1); | |
288 | tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2, | |
289 | resultopt1); | |
290 | tcg_gen_divu_tl(ret, source1, source2); | |
291 | ||
292 | tcg_temp_free(cond1); | |
293 | tcg_temp_free(zeroreg); | |
294 | tcg_temp_free(resultopt1); | |
295 | } | |
55c2a12c | 296 | |
12887016 BK |
297 | static void gen_rem(TCGv ret, TCGv source1, TCGv source2) |
298 | { | |
299 | TCGv cond1, cond2, zeroreg, resultopt1; | |
300 | ||
301 | cond1 = tcg_temp_new(); | |
302 | cond2 = tcg_temp_new(); | |
303 | zeroreg = tcg_const_tl(0); | |
304 | resultopt1 = tcg_temp_new(); | |
305 | ||
306 | tcg_gen_movi_tl(resultopt1, 1L); | |
307 | tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)-1); | |
308 | tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1, | |
309 | (target_ulong)1 << (TARGET_LONG_BITS - 1)); | |
310 | tcg_gen_and_tl(cond2, cond1, cond2); /* cond1 = overflow */ | |
311 | tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); /* cond2 = div 0 */ | |
312 | /* if overflow or div by zero, set source2 to 1, else don't change */ | |
313 | tcg_gen_or_tl(cond2, cond1, cond2); | |
314 | tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond2, zeroreg, source2, | |
315 | resultopt1); | |
316 | tcg_gen_rem_tl(resultopt1, source1, source2); | |
317 | /* if div by zero, just return the original dividend */ | |
318 | tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1, | |
319 | source1); | |
320 | ||
321 | tcg_temp_free(cond1); | |
322 | tcg_temp_free(cond2); | |
323 | tcg_temp_free(zeroreg); | |
324 | tcg_temp_free(resultopt1); | |
325 | } | |
55c2a12c | 326 | |
12887016 BK |
327 | static void gen_remu(TCGv ret, TCGv source1, TCGv source2) |
328 | { | |
329 | TCGv cond1, zeroreg, resultopt1; | |
330 | cond1 = tcg_temp_new(); | |
331 | zeroreg = tcg_const_tl(0); | |
332 | resultopt1 = tcg_temp_new(); | |
333 | ||
334 | tcg_gen_movi_tl(resultopt1, (target_ulong)1); | |
335 | tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); | |
336 | tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2, | |
337 | resultopt1); | |
338 | tcg_gen_remu_tl(resultopt1, source1, source2); | |
339 | /* if div by zero, just return the original dividend */ | |
340 | tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1, | |
341 | source1); | |
342 | ||
343 | tcg_temp_free(cond1); | |
344 | tcg_temp_free(zeroreg); | |
345 | tcg_temp_free(resultopt1); | |
55c2a12c MC |
346 | } |
347 | ||
db9f3fd6 | 348 | static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) |
55c2a12c MC |
349 | { |
350 | target_ulong next_pc; | |
351 | ||
352 | /* check misaligned: */ | |
0114db1c | 353 | next_pc = ctx->base.pc_next + imm; |
db9f3fd6 | 354 | if (!has_ext(ctx, RVC)) { |
55c2a12c MC |
355 | if ((next_pc & 0x3) != 0) { |
356 | gen_exception_inst_addr_mis(ctx); | |
357 | return; | |
358 | } | |
359 | } | |
360 | if (rd != 0) { | |
0114db1c | 361 | tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn); |
55c2a12c MC |
362 | } |
363 | ||
0114db1c EC |
364 | gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */ |
365 | ctx->base.is_jmp = DISAS_NORETURN; | |
55c2a12c MC |
366 | } |
367 | ||
533b8f88 RH |
368 | #ifndef CONFIG_USER_ONLY |
369 | /* The states of mstatus_fs are: | |
370 | * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty | |
371 | * We will have already diagnosed disabled state, | |
372 | * and need to turn initial/clean into dirty. | |
373 | */ | |
374 | static void mark_fs_dirty(DisasContext *ctx) | |
375 | { | |
376 | TCGv tmp; | |
4fd7455b AF |
377 | target_ulong sd; |
378 | ||
533b8f88 RH |
379 | if (ctx->mstatus_fs == MSTATUS_FS) { |
380 | return; | |
381 | } | |
382 | /* Remember the state change for the rest of the TB. */ | |
383 | ctx->mstatus_fs = MSTATUS_FS; | |
384 | ||
385 | tmp = tcg_temp_new(); | |
4fd7455b AF |
386 | sd = is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD; |
387 | ||
533b8f88 | 388 | tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); |
4fd7455b | 389 | tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd); |
533b8f88 | 390 | tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); |
45b4dc8b AF |
391 | |
392 | if (ctx->virt_enabled) { | |
393 | tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); | |
4fd7455b | 394 | tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd); |
45b4dc8b AF |
395 | tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); |
396 | } | |
533b8f88 RH |
397 | tcg_temp_free(tmp); |
398 | } | |
399 | #else | |
400 | static inline void mark_fs_dirty(DisasContext *ctx) { } | |
401 | #endif | |
402 | ||
55c2a12c MC |
403 | static void gen_set_rm(DisasContext *ctx, int rm) |
404 | { | |
405 | TCGv_i32 t0; | |
406 | ||
407 | if (ctx->frm == rm) { | |
408 | return; | |
409 | } | |
410 | ctx->frm = rm; | |
411 | t0 = tcg_const_i32(rm); | |
412 | gen_helper_set_rounding_mode(cpu_env, t0); | |
413 | tcg_temp_free_i32(t0); | |
414 | } | |
415 | ||
751538d5 LZ |
416 | static int ex_plus_1(DisasContext *ctx, int nf) |
417 | { | |
418 | return nf + 1; | |
419 | } | |
420 | ||
2a53cff4 | 421 | #define EX_SH(amount) \ |
451e4ffd | 422 | static int ex_shift_##amount(DisasContext *ctx, int imm) \ |
2a53cff4 BK |
423 | { \ |
424 | return imm << amount; \ | |
425 | } | |
3cca75a6 | 426 | EX_SH(1) |
e98d9140 BK |
427 | EX_SH(2) |
428 | EX_SH(3) | |
07b001c6 | 429 | EX_SH(4) |
2a53cff4 BK |
430 | EX_SH(12) |
431 | ||
d2e2c1e4 BK |
432 | #define REQUIRE_EXT(ctx, ext) do { \ |
433 | if (!has_ext(ctx, ext)) { \ | |
434 | return false; \ | |
435 | } \ | |
436 | } while (0) | |
437 | ||
daf866b6 AF |
438 | #define REQUIRE_64BIT(ctx) do { \ |
439 | if (is_32bit(ctx)) { \ | |
440 | return false; \ | |
441 | } \ | |
442 | } while (0) | |
443 | ||
451e4ffd | 444 | static int ex_rvc_register(DisasContext *ctx, int reg) |
e98d9140 BK |
445 | { |
446 | return 8 + reg; | |
447 | } | |
448 | ||
6cafec92 RH |
449 | static int ex_rvc_shifti(DisasContext *ctx, int imm) |
450 | { | |
451 | /* For RV128 a shamt of 0 means a shift by 64. */ | |
452 | return imm ? imm : 64; | |
453 | } | |
454 | ||
2a53cff4 | 455 | /* Include the auto-generated decoder for 32 bit insn */ |
abff1abf | 456 | #include "decode-insn32.c.inc" |
7a50d3e2 | 457 | |
598aa116 RH |
458 | static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, |
459 | void (*func)(TCGv, TCGv, target_long)) | |
460 | { | |
461 | TCGv source1; | |
462 | source1 = tcg_temp_new(); | |
463 | ||
464 | gen_get_gpr(source1, a->rs1); | |
465 | ||
466 | (*func)(source1, source1, a->imm); | |
467 | ||
468 | gen_set_gpr(a->rd, source1); | |
469 | tcg_temp_free(source1); | |
470 | return true; | |
471 | } | |
472 | ||
473 | static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, | |
474 | void (*func)(TCGv, TCGv, TCGv)) | |
7a50d3e2 BK |
475 | { |
476 | TCGv source1, source2; | |
477 | source1 = tcg_temp_new(); | |
478 | source2 = tcg_temp_new(); | |
479 | ||
480 | gen_get_gpr(source1, a->rs1); | |
481 | tcg_gen_movi_tl(source2, a->imm); | |
482 | ||
483 | (*func)(source1, source1, source2); | |
484 | ||
485 | gen_set_gpr(a->rd, source1); | |
486 | tcg_temp_free(source1); | |
487 | tcg_temp_free(source2); | |
488 | return true; | |
489 | } | |
490 | ||
7a50d3e2 BK |
491 | static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2) |
492 | { | |
493 | tcg_gen_add_tl(ret, arg1, arg2); | |
494 | tcg_gen_ext32s_tl(ret, ret); | |
495 | } | |
f2ab1728 BK |
496 | |
497 | static void gen_subw(TCGv ret, TCGv arg1, TCGv arg2) | |
498 | { | |
499 | tcg_gen_sub_tl(ret, arg1, arg2); | |
500 | tcg_gen_ext32s_tl(ret, ret); | |
501 | } | |
502 | ||
12887016 BK |
503 | static void gen_mulw(TCGv ret, TCGv arg1, TCGv arg2) |
504 | { | |
505 | tcg_gen_mul_tl(ret, arg1, arg2); | |
506 | tcg_gen_ext32s_tl(ret, ret); | |
507 | } | |
508 | ||
509 | static bool gen_arith_div_w(DisasContext *ctx, arg_r *a, | |
510 | void(*func)(TCGv, TCGv, TCGv)) | |
511 | { | |
512 | TCGv source1, source2; | |
513 | source1 = tcg_temp_new(); | |
514 | source2 = tcg_temp_new(); | |
515 | ||
516 | gen_get_gpr(source1, a->rs1); | |
517 | gen_get_gpr(source2, a->rs2); | |
518 | tcg_gen_ext32s_tl(source1, source1); | |
519 | tcg_gen_ext32s_tl(source2, source2); | |
520 | ||
521 | (*func)(source1, source1, source2); | |
522 | ||
523 | tcg_gen_ext32s_tl(source1, source1); | |
524 | gen_set_gpr(a->rd, source1); | |
525 | tcg_temp_free(source1); | |
526 | tcg_temp_free(source2); | |
527 | return true; | |
528 | } | |
529 | ||
f17e02cd PD |
530 | static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a, |
531 | void(*func)(TCGv, TCGv, TCGv)) | |
532 | { | |
533 | TCGv source1, source2; | |
534 | source1 = tcg_temp_new(); | |
535 | source2 = tcg_temp_new(); | |
536 | ||
537 | gen_get_gpr(source1, a->rs1); | |
538 | gen_get_gpr(source2, a->rs2); | |
539 | tcg_gen_ext32u_tl(source1, source1); | |
540 | tcg_gen_ext32u_tl(source2, source2); | |
541 | ||
542 | (*func)(source1, source1, source2); | |
543 | ||
544 | tcg_gen_ext32s_tl(source1, source1); | |
545 | gen_set_gpr(a->rd, source1); | |
546 | tcg_temp_free(source1); | |
547 | tcg_temp_free(source2); | |
548 | return true; | |
549 | } | |
550 | ||
43824018 KC |
551 | static void gen_ctzw(TCGv ret, TCGv arg1) |
552 | { | |
553 | tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32)); | |
554 | tcg_gen_ctzi_tl(ret, ret, 64); | |
555 | } | |
556 | ||
557 | static void gen_clzw(TCGv ret, TCGv arg1) | |
558 | { | |
559 | tcg_gen_ext32u_tl(ret, arg1); | |
560 | tcg_gen_clzi_tl(ret, ret, 64); | |
561 | tcg_gen_subi_tl(ret, ret, 32); | |
562 | } | |
563 | ||
8dc9e8a8 BK |
564 | static bool gen_arith(DisasContext *ctx, arg_r *a, |
565 | void(*func)(TCGv, TCGv, TCGv)) | |
f2ab1728 BK |
566 | { |
567 | TCGv source1, source2; | |
568 | source1 = tcg_temp_new(); | |
569 | source2 = tcg_temp_new(); | |
570 | ||
571 | gen_get_gpr(source1, a->rs1); | |
572 | gen_get_gpr(source2, a->rs2); | |
573 | ||
574 | (*func)(source1, source1, source2); | |
575 | ||
576 | gen_set_gpr(a->rd, source1); | |
577 | tcg_temp_free(source1); | |
578 | tcg_temp_free(source2); | |
579 | return true; | |
580 | } | |
581 | ||
34446e84 BK |
582 | static bool gen_shift(DisasContext *ctx, arg_r *a, |
583 | void(*func)(TCGv, TCGv, TCGv)) | |
584 | { | |
585 | TCGv source1 = tcg_temp_new(); | |
586 | TCGv source2 = tcg_temp_new(); | |
587 | ||
588 | gen_get_gpr(source1, a->rs1); | |
589 | gen_get_gpr(source2, a->rs2); | |
590 | ||
591 | tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1); | |
592 | (*func)(source1, source1, source2); | |
593 | ||
594 | gen_set_gpr(a->rd, source1); | |
595 | tcg_temp_free(source1); | |
596 | tcg_temp_free(source2); | |
597 | return true; | |
598 | } | |
599 | ||
a10b9d93 KP |
600 | static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) |
601 | { | |
602 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
603 | CPUState *cpu = ctx->cs; | |
604 | CPURISCVState *env = cpu->env_ptr; | |
605 | ||
606 | return cpu_ldl_code(env, pc); | |
607 | } | |
608 | ||
43824018 KC |
609 | static void gen_ctz(TCGv ret, TCGv arg1) |
610 | { | |
611 | tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS); | |
612 | } | |
613 | ||
614 | static void gen_clz(TCGv ret, TCGv arg1) | |
615 | { | |
616 | tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS); | |
617 | } | |
618 | ||
619 | static bool gen_unary(DisasContext *ctx, arg_r2 *a, | |
620 | void(*func)(TCGv, TCGv)) | |
621 | { | |
622 | TCGv source = tcg_temp_new(); | |
623 | ||
624 | gen_get_gpr(source, a->rs1); | |
625 | ||
626 | (*func)(source, source); | |
627 | ||
628 | gen_set_gpr(a->rd, source); | |
629 | tcg_temp_free(source); | |
630 | return true; | |
631 | } | |
632 | ||
2a53cff4 | 633 | /* Include insn module translation function */ |
139c1837 PB |
634 | #include "insn_trans/trans_rvi.c.inc" |
635 | #include "insn_trans/trans_rvm.c.inc" | |
636 | #include "insn_trans/trans_rva.c.inc" | |
637 | #include "insn_trans/trans_rvf.c.inc" | |
638 | #include "insn_trans/trans_rvd.c.inc" | |
639 | #include "insn_trans/trans_rvh.c.inc" | |
640 | #include "insn_trans/trans_rvv.c.inc" | |
43824018 | 641 | #include "insn_trans/trans_rvb.c.inc" |
139c1837 | 642 | #include "insn_trans/trans_privileged.c.inc" |
2a53cff4 | 643 | |
59a3a1c0 | 644 | /* Include the auto-generated decoder for 16 bit insn */ |
abff1abf | 645 | #include "decode-insn16.c.inc" |
e98d9140 | 646 | |
25139bf7 | 647 | static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) |
55c2a12c MC |
648 | { |
649 | /* check for compressed insn */ | |
25139bf7 | 650 | if (extract16(opcode, 0, 2) != 3) { |
db9f3fd6 | 651 | if (!has_ext(ctx, RVC)) { |
55c2a12c MC |
652 | gen_exception_illegal(ctx); |
653 | } else { | |
0114db1c | 654 | ctx->pc_succ_insn = ctx->base.pc_next + 2; |
25139bf7 | 655 | if (!decode_insn16(ctx, opcode)) { |
9a27f69b | 656 | gen_exception_illegal(ctx); |
e98d9140 | 657 | } |
55c2a12c MC |
658 | } |
659 | } else { | |
25139bf7 AB |
660 | uint32_t opcode32 = opcode; |
661 | opcode32 = deposit32(opcode32, 16, 16, | |
662 | translator_lduw(env, ctx->base.pc_next + 2)); | |
0114db1c | 663 | ctx->pc_succ_insn = ctx->base.pc_next + 4; |
25139bf7 | 664 | if (!decode_insn32(ctx, opcode32)) { |
25e6ca30 | 665 | gen_exception_illegal(ctx); |
2a53cff4 | 666 | } |
55c2a12c MC |
667 | } |
668 | } | |
669 | ||
5b4f1d2d | 670 | static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) |
55c2a12c | 671 | { |
5b4f1d2d | 672 | DisasContext *ctx = container_of(dcbase, DisasContext, base); |
d75377bf | 673 | CPURISCVState *env = cs->env_ptr; |
50fba816 | 674 | RISCVCPU *cpu = RISCV_CPU(cs); |
2b7168fc | 675 | uint32_t tb_flags = ctx->base.tb->flags; |
55c2a12c | 676 | |
5b4f1d2d | 677 | ctx->pc_succ_insn = ctx->base.pc_first; |
2b7168fc LZ |
678 | ctx->mem_idx = tb_flags & TB_FLAGS_MMU_MASK; |
679 | ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS; | |
d75377bf | 680 | ctx->priv_ver = env->priv_ver; |
45b4dc8b | 681 | #if !defined(CONFIG_USER_ONLY) |
ae84dd0a AF |
682 | if (riscv_has_ext(env, RVH)) { |
683 | ctx->virt_enabled = riscv_cpu_virt_enabled(env); | |
ae84dd0a AF |
684 | } else { |
685 | ctx->virt_enabled = false; | |
686 | } | |
45b4dc8b AF |
687 | #else |
688 | ctx->virt_enabled = false; | |
689 | #endif | |
db9f3fd6 | 690 | ctx->misa = env->misa; |
5b4f1d2d | 691 | ctx->frm = -1; /* unknown rounding mode */ |
50fba816 | 692 | ctx->ext_ifencei = cpu->cfg.ext_ifencei; |
2b7168fc | 693 | ctx->vlen = cpu->cfg.vlen; |
743077b3 | 694 | ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); |
2b7168fc LZ |
695 | ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); |
696 | ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); | |
697 | ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL); | |
751538d5 | 698 | ctx->mlen = 1 << (ctx->sew + 3 - ctx->lmul); |
2b7168fc | 699 | ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); |
a10b9d93 | 700 | ctx->cs = cs; |
5b4f1d2d | 701 | } |
55c2a12c | 702 | |
5b4f1d2d EC |
703 | static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) |
704 | { | |
705 | } | |
55c2a12c | 706 | |
5b4f1d2d EC |
707 | static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) |
708 | { | |
709 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
710 | ||
711 | tcg_gen_insn_start(ctx->base.pc_next); | |
712 | } | |
713 | ||
714 | static bool riscv_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, | |
715 | const CPUBreakpoint *bp) | |
716 | { | |
717 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
718 | ||
719 | tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); | |
720 | ctx->base.is_jmp = DISAS_NORETURN; | |
721 | gen_exception_debug(); | |
722 | /* The address covered by the breakpoint must be included in | |
723 | [tb->pc, tb->pc + tb->size) in order to for it to be | |
724 | properly cleared -- thus we increment the PC here so that | |
725 | the logic setting tb->size below does the right thing. */ | |
726 | ctx->base.pc_next += 4; | |
727 | return true; | |
728 | } | |
729 | ||
5b4f1d2d EC |
730 | static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) |
731 | { | |
732 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
733 | CPURISCVState *env = cpu->env_ptr; | |
25139bf7 | 734 | uint16_t opcode16 = translator_lduw(env, ctx->base.pc_next); |
55c2a12c | 735 | |
25139bf7 | 736 | decode_opc(env, ctx, opcode16); |
5b4f1d2d EC |
737 | ctx->base.pc_next = ctx->pc_succ_insn; |
738 | ||
739 | if (ctx->base.is_jmp == DISAS_NEXT) { | |
740 | target_ulong page_start; | |
741 | ||
742 | page_start = ctx->base.pc_first & TARGET_PAGE_MASK; | |
743 | if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) { | |
744 | ctx->base.is_jmp = DISAS_TOO_MANY; | |
55c2a12c | 745 | } |
55c2a12c | 746 | } |
5b4f1d2d EC |
747 | } |
748 | ||
749 | static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) | |
750 | { | |
751 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
752 | ||
753 | switch (ctx->base.is_jmp) { | |
b2e32021 | 754 | case DISAS_TOO_MANY: |
ccf08e40 | 755 | gen_goto_tb(ctx, 0, ctx->base.pc_next); |
55c2a12c | 756 | break; |
b2e32021 | 757 | case DISAS_NORETURN: |
55c2a12c | 758 | break; |
b2e32021 EC |
759 | default: |
760 | g_assert_not_reached(); | |
55c2a12c | 761 | } |
5b4f1d2d EC |
762 | } |
763 | ||
764 | static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) | |
765 | { | |
35f69039 AF |
766 | #ifndef CONFIG_USER_ONLY |
767 | RISCVCPU *rvcpu = RISCV_CPU(cpu); | |
768 | CPURISCVState *env = &rvcpu->env; | |
769 | #endif | |
770 | ||
5b4f1d2d | 771 | qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); |
35f69039 AF |
772 | #ifndef CONFIG_USER_ONLY |
773 | qemu_log("Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", env->priv, env->virt); | |
774 | #endif | |
5b4f1d2d EC |
775 | log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); |
776 | } | |
777 | ||
778 | static const TranslatorOps riscv_tr_ops = { | |
779 | .init_disas_context = riscv_tr_init_disas_context, | |
780 | .tb_start = riscv_tr_tb_start, | |
781 | .insn_start = riscv_tr_insn_start, | |
782 | .breakpoint_check = riscv_tr_breakpoint_check, | |
783 | .translate_insn = riscv_tr_translate_insn, | |
784 | .tb_stop = riscv_tr_tb_stop, | |
785 | .disas_log = riscv_tr_disas_log, | |
786 | }; | |
787 | ||
8b86d6d2 | 788 | void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) |
5b4f1d2d EC |
789 | { |
790 | DisasContext ctx; | |
791 | ||
8b86d6d2 | 792 | translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns); |
55c2a12c MC |
793 | } |
794 | ||
795 | void riscv_translate_init(void) | |
796 | { | |
797 | int i; | |
798 | ||
799 | /* cpu_gpr[0] is a placeholder for the zero register. Do not use it. */ | |
800 | /* Use the gen_set_gpr and gen_get_gpr helper functions when accessing */ | |
801 | /* registers, unless you specifically block reads/writes to reg 0 */ | |
802 | cpu_gpr[0] = NULL; | |
803 | ||
804 | for (i = 1; i < 32; i++) { | |
805 | cpu_gpr[i] = tcg_global_mem_new(cpu_env, | |
806 | offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); | |
807 | } | |
808 | ||
809 | for (i = 0; i < 32; i++) { | |
810 | cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, | |
811 | offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); | |
812 | } | |
813 | ||
814 | cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); | |
ad9e5aa2 | 815 | cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl"); |
55c2a12c MC |
816 | load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), |
817 | "load_res"); | |
818 | load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), | |
819 | "load_val"); | |
820 | } |