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55c2a12c MC |
1 | /* |
2 | * RISC-V emulation for qemu: main translation routines. | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2 or later, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along with | |
16 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | ||
19 | #include "qemu/osdep.h" | |
20 | #include "qemu/log.h" | |
21 | #include "cpu.h" | |
22 | #include "tcg-op.h" | |
23 | #include "disas/disas.h" | |
24 | #include "exec/cpu_ldst.h" | |
25 | #include "exec/exec-all.h" | |
26 | #include "exec/helper-proto.h" | |
27 | #include "exec/helper-gen.h" | |
28 | ||
b2e32021 | 29 | #include "exec/translator.h" |
55c2a12c MC |
30 | #include "exec/log.h" |
31 | ||
32 | #include "instmap.h" | |
33 | ||
34 | /* global register indices */ | |
35 | static TCGv cpu_gpr[32], cpu_pc; | |
36 | static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ | |
37 | static TCGv load_res; | |
38 | static TCGv load_val; | |
39 | ||
40 | #include "exec/gen-icount.h" | |
41 | ||
42 | typedef struct DisasContext { | |
0114db1c EC |
43 | DisasContextBase base; |
44 | /* pc_succ_insn points to the instruction following base.pc_next */ | |
45 | target_ulong pc_succ_insn; | |
d75377bf | 46 | target_ulong priv_ver; |
55c2a12c | 47 | uint32_t opcode; |
83a71719 | 48 | uint32_t mstatus_fs; |
db9f3fd6 | 49 | uint32_t misa; |
55c2a12c | 50 | uint32_t mem_idx; |
55c2a12c MC |
51 | /* Remember the rounding mode encoded in the previous fp instruction, |
52 | which we have already installed into env->fp_status. Or -1 for | |
53 | no previous fp instruction. Note that we exit the TB when writing | |
54 | to any system register, which includes CSR_FRM, so we do not have | |
55 | to reset this known value. */ | |
56 | int frm; | |
57 | } DisasContext; | |
58 | ||
bce8a342 | 59 | #ifdef TARGET_RISCV64 |
55c2a12c MC |
60 | /* convert riscv funct3 to qemu memop for load/store */ |
61 | static const int tcg_memop_lookup[8] = { | |
62 | [0 ... 7] = -1, | |
63 | [0] = MO_SB, | |
64 | [1] = MO_TESW, | |
65 | [2] = MO_TESL, | |
66 | [4] = MO_UB, | |
67 | [5] = MO_TEUW, | |
68 | #ifdef TARGET_RISCV64 | |
69 | [3] = MO_TEQ, | |
70 | [6] = MO_TEUL, | |
71 | #endif | |
72 | }; | |
bce8a342 | 73 | #endif |
55c2a12c MC |
74 | |
75 | #ifdef TARGET_RISCV64 | |
76 | #define CASE_OP_32_64(X) case X: case glue(X, W) | |
77 | #else | |
78 | #define CASE_OP_32_64(X) case X | |
79 | #endif | |
80 | ||
db9f3fd6 MC |
81 | static inline bool has_ext(DisasContext *ctx, uint32_t ext) |
82 | { | |
83 | return ctx->misa & ext; | |
84 | } | |
85 | ||
55c2a12c MC |
86 | static void generate_exception(DisasContext *ctx, int excp) |
87 | { | |
0114db1c | 88 | tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); |
55c2a12c MC |
89 | TCGv_i32 helper_tmp = tcg_const_i32(excp); |
90 | gen_helper_raise_exception(cpu_env, helper_tmp); | |
91 | tcg_temp_free_i32(helper_tmp); | |
0114db1c | 92 | ctx->base.is_jmp = DISAS_NORETURN; |
55c2a12c MC |
93 | } |
94 | ||
95 | static void generate_exception_mbadaddr(DisasContext *ctx, int excp) | |
96 | { | |
0114db1c | 97 | tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); |
55c2a12c MC |
98 | tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); |
99 | TCGv_i32 helper_tmp = tcg_const_i32(excp); | |
100 | gen_helper_raise_exception(cpu_env, helper_tmp); | |
101 | tcg_temp_free_i32(helper_tmp); | |
0114db1c | 102 | ctx->base.is_jmp = DISAS_NORETURN; |
55c2a12c MC |
103 | } |
104 | ||
105 | static void gen_exception_debug(void) | |
106 | { | |
107 | TCGv_i32 helper_tmp = tcg_const_i32(EXCP_DEBUG); | |
108 | gen_helper_raise_exception(cpu_env, helper_tmp); | |
109 | tcg_temp_free_i32(helper_tmp); | |
110 | } | |
111 | ||
112 | static void gen_exception_illegal(DisasContext *ctx) | |
113 | { | |
114 | generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); | |
115 | } | |
116 | ||
117 | static void gen_exception_inst_addr_mis(DisasContext *ctx) | |
118 | { | |
119 | generate_exception_mbadaddr(ctx, RISCV_EXCP_INST_ADDR_MIS); | |
120 | } | |
121 | ||
122 | static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) | |
123 | { | |
0114db1c | 124 | if (unlikely(ctx->base.singlestep_enabled)) { |
55c2a12c MC |
125 | return false; |
126 | } | |
127 | ||
128 | #ifndef CONFIG_USER_ONLY | |
0114db1c | 129 | return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); |
55c2a12c MC |
130 | #else |
131 | return true; | |
132 | #endif | |
133 | } | |
134 | ||
135 | static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) | |
136 | { | |
137 | if (use_goto_tb(ctx, dest)) { | |
138 | /* chaining is only allowed when the jump is to the same page */ | |
139 | tcg_gen_goto_tb(n); | |
140 | tcg_gen_movi_tl(cpu_pc, dest); | |
07ea28b4 | 141 | tcg_gen_exit_tb(ctx->base.tb, n); |
55c2a12c MC |
142 | } else { |
143 | tcg_gen_movi_tl(cpu_pc, dest); | |
0114db1c | 144 | if (ctx->base.singlestep_enabled) { |
55c2a12c MC |
145 | gen_exception_debug(); |
146 | } else { | |
6dbebd55 | 147 | tcg_gen_lookup_and_goto_ptr(); |
55c2a12c MC |
148 | } |
149 | } | |
150 | } | |
151 | ||
152 | /* Wrapper for getting reg values - need to check of reg is zero since | |
153 | * cpu_gpr[0] is not actually allocated | |
154 | */ | |
155 | static inline void gen_get_gpr(TCGv t, int reg_num) | |
156 | { | |
157 | if (reg_num == 0) { | |
158 | tcg_gen_movi_tl(t, 0); | |
159 | } else { | |
160 | tcg_gen_mov_tl(t, cpu_gpr[reg_num]); | |
161 | } | |
162 | } | |
163 | ||
164 | /* Wrapper for setting reg values - need to check of reg is zero since | |
165 | * cpu_gpr[0] is not actually allocated. this is more for safety purposes, | |
166 | * since we usually avoid calling the OP_TYPE_gen function if we see a write to | |
167 | * $zero | |
168 | */ | |
169 | static inline void gen_set_gpr(int reg_num_dst, TCGv t) | |
170 | { | |
171 | if (reg_num_dst != 0) { | |
172 | tcg_gen_mov_tl(cpu_gpr[reg_num_dst], t); | |
173 | } | |
174 | } | |
175 | ||
176 | static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2) | |
177 | { | |
178 | TCGv rl = tcg_temp_new(); | |
179 | TCGv rh = tcg_temp_new(); | |
180 | ||
181 | tcg_gen_mulu2_tl(rl, rh, arg1, arg2); | |
182 | /* fix up for one negative */ | |
183 | tcg_gen_sari_tl(rl, arg1, TARGET_LONG_BITS - 1); | |
184 | tcg_gen_and_tl(rl, rl, arg2); | |
185 | tcg_gen_sub_tl(ret, rh, rl); | |
186 | ||
187 | tcg_temp_free(rl); | |
188 | tcg_temp_free(rh); | |
189 | } | |
190 | ||
12887016 | 191 | static void gen_div(TCGv ret, TCGv source1, TCGv source2) |
55c2a12c | 192 | { |
12887016 BK |
193 | TCGv cond1, cond2, zeroreg, resultopt1; |
194 | /* | |
195 | * Handle by altering args to tcg_gen_div to produce req'd results: | |
196 | * For overflow: want source1 in source1 and 1 in source2 | |
197 | * For div by zero: want -1 in source1 and 1 in source2 -> -1 result | |
198 | */ | |
199 | cond1 = tcg_temp_new(); | |
200 | cond2 = tcg_temp_new(); | |
201 | zeroreg = tcg_const_tl(0); | |
202 | resultopt1 = tcg_temp_new(); | |
203 | ||
204 | tcg_gen_movi_tl(resultopt1, (target_ulong)-1); | |
205 | tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)(~0L)); | |
206 | tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1, | |
207 | ((target_ulong)1) << (TARGET_LONG_BITS - 1)); | |
208 | tcg_gen_and_tl(cond1, cond1, cond2); /* cond1 = overflow */ | |
209 | tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, 0); /* cond2 = div 0 */ | |
210 | /* if div by zero, set source1 to -1, otherwise don't change */ | |
211 | tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond2, zeroreg, source1, | |
212 | resultopt1); | |
213 | /* if overflow or div by zero, set source2 to 1, else don't change */ | |
214 | tcg_gen_or_tl(cond1, cond1, cond2); | |
215 | tcg_gen_movi_tl(resultopt1, (target_ulong)1); | |
216 | tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2, | |
217 | resultopt1); | |
218 | tcg_gen_div_tl(ret, source1, source2); | |
219 | ||
220 | tcg_temp_free(cond1); | |
221 | tcg_temp_free(cond2); | |
222 | tcg_temp_free(zeroreg); | |
223 | tcg_temp_free(resultopt1); | |
224 | } | |
55c2a12c | 225 | |
12887016 BK |
226 | static void gen_divu(TCGv ret, TCGv source1, TCGv source2) |
227 | { | |
228 | TCGv cond1, zeroreg, resultopt1; | |
229 | cond1 = tcg_temp_new(); | |
230 | ||
231 | zeroreg = tcg_const_tl(0); | |
232 | resultopt1 = tcg_temp_new(); | |
233 | ||
234 | tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); | |
235 | tcg_gen_movi_tl(resultopt1, (target_ulong)-1); | |
236 | tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond1, zeroreg, source1, | |
237 | resultopt1); | |
238 | tcg_gen_movi_tl(resultopt1, (target_ulong)1); | |
239 | tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2, | |
240 | resultopt1); | |
241 | tcg_gen_divu_tl(ret, source1, source2); | |
242 | ||
243 | tcg_temp_free(cond1); | |
244 | tcg_temp_free(zeroreg); | |
245 | tcg_temp_free(resultopt1); | |
246 | } | |
55c2a12c | 247 | |
12887016 BK |
248 | static void gen_rem(TCGv ret, TCGv source1, TCGv source2) |
249 | { | |
250 | TCGv cond1, cond2, zeroreg, resultopt1; | |
251 | ||
252 | cond1 = tcg_temp_new(); | |
253 | cond2 = tcg_temp_new(); | |
254 | zeroreg = tcg_const_tl(0); | |
255 | resultopt1 = tcg_temp_new(); | |
256 | ||
257 | tcg_gen_movi_tl(resultopt1, 1L); | |
258 | tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)-1); | |
259 | tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1, | |
260 | (target_ulong)1 << (TARGET_LONG_BITS - 1)); | |
261 | tcg_gen_and_tl(cond2, cond1, cond2); /* cond1 = overflow */ | |
262 | tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); /* cond2 = div 0 */ | |
263 | /* if overflow or div by zero, set source2 to 1, else don't change */ | |
264 | tcg_gen_or_tl(cond2, cond1, cond2); | |
265 | tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond2, zeroreg, source2, | |
266 | resultopt1); | |
267 | tcg_gen_rem_tl(resultopt1, source1, source2); | |
268 | /* if div by zero, just return the original dividend */ | |
269 | tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1, | |
270 | source1); | |
271 | ||
272 | tcg_temp_free(cond1); | |
273 | tcg_temp_free(cond2); | |
274 | tcg_temp_free(zeroreg); | |
275 | tcg_temp_free(resultopt1); | |
276 | } | |
55c2a12c | 277 | |
12887016 BK |
278 | static void gen_remu(TCGv ret, TCGv source1, TCGv source2) |
279 | { | |
280 | TCGv cond1, zeroreg, resultopt1; | |
281 | cond1 = tcg_temp_new(); | |
282 | zeroreg = tcg_const_tl(0); | |
283 | resultopt1 = tcg_temp_new(); | |
284 | ||
285 | tcg_gen_movi_tl(resultopt1, (target_ulong)1); | |
286 | tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); | |
287 | tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2, | |
288 | resultopt1); | |
289 | tcg_gen_remu_tl(resultopt1, source1, source2); | |
290 | /* if div by zero, just return the original dividend */ | |
291 | tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1, | |
292 | source1); | |
293 | ||
294 | tcg_temp_free(cond1); | |
295 | tcg_temp_free(zeroreg); | |
296 | tcg_temp_free(resultopt1); | |
55c2a12c MC |
297 | } |
298 | ||
db9f3fd6 | 299 | static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) |
55c2a12c MC |
300 | { |
301 | target_ulong next_pc; | |
302 | ||
303 | /* check misaligned: */ | |
0114db1c | 304 | next_pc = ctx->base.pc_next + imm; |
db9f3fd6 | 305 | if (!has_ext(ctx, RVC)) { |
55c2a12c MC |
306 | if ((next_pc & 0x3) != 0) { |
307 | gen_exception_inst_addr_mis(ctx); | |
308 | return; | |
309 | } | |
310 | } | |
311 | if (rd != 0) { | |
0114db1c | 312 | tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn); |
55c2a12c MC |
313 | } |
314 | ||
0114db1c EC |
315 | gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */ |
316 | ctx->base.is_jmp = DISAS_NORETURN; | |
55c2a12c MC |
317 | } |
318 | ||
98898b20 BK |
319 | #ifdef TARGET_RISCV64 |
320 | static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1, | |
55c2a12c MC |
321 | target_long imm) |
322 | { | |
323 | TCGv t0 = tcg_temp_new(); | |
324 | TCGv t1 = tcg_temp_new(); | |
325 | gen_get_gpr(t0, rs1); | |
326 | tcg_gen_addi_tl(t0, t0, imm); | |
327 | int memop = tcg_memop_lookup[(opc >> 12) & 0x7]; | |
328 | ||
329 | if (memop < 0) { | |
330 | gen_exception_illegal(ctx); | |
331 | return; | |
332 | } | |
333 | ||
334 | tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop); | |
335 | gen_set_gpr(rd, t1); | |
336 | tcg_temp_free(t0); | |
337 | tcg_temp_free(t1); | |
338 | } | |
339 | ||
bce8a342 | 340 | static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2, |
55c2a12c MC |
341 | target_long imm) |
342 | { | |
343 | TCGv t0 = tcg_temp_new(); | |
344 | TCGv dat = tcg_temp_new(); | |
345 | gen_get_gpr(t0, rs1); | |
346 | tcg_gen_addi_tl(t0, t0, imm); | |
347 | gen_get_gpr(dat, rs2); | |
348 | int memop = tcg_memop_lookup[(opc >> 12) & 0x7]; | |
349 | ||
350 | if (memop < 0) { | |
351 | gen_exception_illegal(ctx); | |
352 | return; | |
353 | } | |
354 | ||
355 | tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop); | |
356 | tcg_temp_free(t0); | |
357 | tcg_temp_free(dat); | |
358 | } | |
bce8a342 | 359 | #endif |
55c2a12c | 360 | |
533b8f88 RH |
361 | #ifndef CONFIG_USER_ONLY |
362 | /* The states of mstatus_fs are: | |
363 | * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty | |
364 | * We will have already diagnosed disabled state, | |
365 | * and need to turn initial/clean into dirty. | |
366 | */ | |
367 | static void mark_fs_dirty(DisasContext *ctx) | |
368 | { | |
369 | TCGv tmp; | |
370 | if (ctx->mstatus_fs == MSTATUS_FS) { | |
371 | return; | |
372 | } | |
373 | /* Remember the state change for the rest of the TB. */ | |
374 | ctx->mstatus_fs = MSTATUS_FS; | |
375 | ||
376 | tmp = tcg_temp_new(); | |
377 | tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); | |
378 | tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); | |
379 | tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); | |
380 | tcg_temp_free(tmp); | |
381 | } | |
382 | #else | |
383 | static inline void mark_fs_dirty(DisasContext *ctx) { } | |
384 | #endif | |
385 | ||
97b0be81 | 386 | #if !defined(TARGET_RISCV64) |
55c2a12c MC |
387 | static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd, |
388 | int rs1, target_long imm) | |
389 | { | |
390 | TCGv t0; | |
391 | ||
83a71719 | 392 | if (ctx->mstatus_fs == 0) { |
55c2a12c MC |
393 | gen_exception_illegal(ctx); |
394 | return; | |
395 | } | |
396 | ||
397 | t0 = tcg_temp_new(); | |
398 | gen_get_gpr(t0, rs1); | |
399 | tcg_gen_addi_tl(t0, t0, imm); | |
400 | ||
401 | switch (opc) { | |
402 | case OPC_RISC_FLW: | |
d77c3401 MC |
403 | if (!has_ext(ctx, RVF)) { |
404 | goto do_illegal; | |
405 | } | |
55c2a12c MC |
406 | tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEUL); |
407 | /* RISC-V requires NaN-boxing of narrower width floating point values */ | |
408 | tcg_gen_ori_i64(cpu_fpr[rd], cpu_fpr[rd], 0xffffffff00000000ULL); | |
409 | break; | |
410 | case OPC_RISC_FLD: | |
d77c3401 MC |
411 | if (!has_ext(ctx, RVD)) { |
412 | goto do_illegal; | |
413 | } | |
55c2a12c MC |
414 | tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEQ); |
415 | break; | |
d77c3401 | 416 | do_illegal: |
55c2a12c MC |
417 | default: |
418 | gen_exception_illegal(ctx); | |
419 | break; | |
420 | } | |
421 | tcg_temp_free(t0); | |
533b8f88 RH |
422 | |
423 | mark_fs_dirty(ctx); | |
55c2a12c MC |
424 | } |
425 | ||
426 | static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1, | |
427 | int rs2, target_long imm) | |
428 | { | |
429 | TCGv t0; | |
430 | ||
83a71719 | 431 | if (ctx->mstatus_fs == 0) { |
55c2a12c MC |
432 | gen_exception_illegal(ctx); |
433 | return; | |
434 | } | |
435 | ||
436 | t0 = tcg_temp_new(); | |
437 | gen_get_gpr(t0, rs1); | |
438 | tcg_gen_addi_tl(t0, t0, imm); | |
439 | ||
440 | switch (opc) { | |
441 | case OPC_RISC_FSW: | |
d77c3401 MC |
442 | if (!has_ext(ctx, RVF)) { |
443 | goto do_illegal; | |
444 | } | |
55c2a12c MC |
445 | tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEUL); |
446 | break; | |
447 | case OPC_RISC_FSD: | |
d77c3401 MC |
448 | if (!has_ext(ctx, RVD)) { |
449 | goto do_illegal; | |
450 | } | |
55c2a12c MC |
451 | tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEQ); |
452 | break; | |
d77c3401 | 453 | do_illegal: |
55c2a12c MC |
454 | default: |
455 | gen_exception_illegal(ctx); | |
456 | break; | |
457 | } | |
458 | ||
459 | tcg_temp_free(t0); | |
460 | } | |
97b0be81 | 461 | #endif |
55c2a12c | 462 | |
55c2a12c MC |
463 | static void gen_set_rm(DisasContext *ctx, int rm) |
464 | { | |
465 | TCGv_i32 t0; | |
466 | ||
467 | if (ctx->frm == rm) { | |
468 | return; | |
469 | } | |
470 | ctx->frm = rm; | |
471 | t0 = tcg_const_i32(rm); | |
472 | gen_helper_set_rounding_mode(cpu_env, t0); | |
473 | tcg_temp_free_i32(t0); | |
474 | } | |
475 | ||
55c2a12c MC |
476 | static void decode_RV32_64C0(DisasContext *ctx) |
477 | { | |
478 | uint8_t funct3 = extract32(ctx->opcode, 13, 3); | |
479 | uint8_t rd_rs2 = GET_C_RS2S(ctx->opcode); | |
480 | uint8_t rs1s = GET_C_RS1S(ctx->opcode); | |
481 | ||
482 | switch (funct3) { | |
55c2a12c MC |
483 | case 3: |
484 | #if defined(TARGET_RISCV64) | |
485 | /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/ | |
98898b20 | 486 | gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s, |
55c2a12c MC |
487 | GET_C_LD_IMM(ctx->opcode)); |
488 | #else | |
489 | /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/ | |
490 | gen_fp_load(ctx, OPC_RISC_FLW, rd_rs2, rs1s, | |
491 | GET_C_LW_IMM(ctx->opcode)); | |
492 | #endif | |
493 | break; | |
55c2a12c MC |
494 | case 7: |
495 | #if defined(TARGET_RISCV64) | |
496 | /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/ | |
bce8a342 | 497 | gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2, |
55c2a12c MC |
498 | GET_C_LD_IMM(ctx->opcode)); |
499 | #else | |
500 | /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/ | |
501 | gen_fp_store(ctx, OPC_RISC_FSW, rs1s, rd_rs2, | |
502 | GET_C_LW_IMM(ctx->opcode)); | |
503 | #endif | |
504 | break; | |
505 | } | |
506 | } | |
507 | ||
db9f3fd6 | 508 | static void decode_RV32_64C(DisasContext *ctx) |
55c2a12c MC |
509 | { |
510 | uint8_t op = extract32(ctx->opcode, 0, 2); | |
511 | ||
512 | switch (op) { | |
513 | case 0: | |
514 | decode_RV32_64C0(ctx); | |
515 | break; | |
55c2a12c MC |
516 | } |
517 | } | |
518 | ||
2a53cff4 BK |
519 | #define EX_SH(amount) \ |
520 | static int ex_shift_##amount(int imm) \ | |
521 | { \ | |
522 | return imm << amount; \ | |
523 | } | |
3cca75a6 | 524 | EX_SH(1) |
e98d9140 BK |
525 | EX_SH(2) |
526 | EX_SH(3) | |
07b001c6 | 527 | EX_SH(4) |
2a53cff4 BK |
528 | EX_SH(12) |
529 | ||
d2e2c1e4 BK |
530 | #define REQUIRE_EXT(ctx, ext) do { \ |
531 | if (!has_ext(ctx, ext)) { \ | |
532 | return false; \ | |
533 | } \ | |
534 | } while (0) | |
535 | ||
e98d9140 BK |
536 | static int ex_rvc_register(int reg) |
537 | { | |
538 | return 8 + reg; | |
539 | } | |
540 | ||
2a53cff4 BK |
541 | bool decode_insn32(DisasContext *ctx, uint32_t insn); |
542 | /* Include the auto-generated decoder for 32 bit insn */ | |
543 | #include "decode_insn32.inc.c" | |
7a50d3e2 BK |
544 | |
545 | static bool gen_arith_imm(DisasContext *ctx, arg_i *a, | |
546 | void(*func)(TCGv, TCGv, TCGv)) | |
547 | { | |
548 | TCGv source1, source2; | |
549 | source1 = tcg_temp_new(); | |
550 | source2 = tcg_temp_new(); | |
551 | ||
552 | gen_get_gpr(source1, a->rs1); | |
553 | tcg_gen_movi_tl(source2, a->imm); | |
554 | ||
555 | (*func)(source1, source1, source2); | |
556 | ||
557 | gen_set_gpr(a->rd, source1); | |
558 | tcg_temp_free(source1); | |
559 | tcg_temp_free(source2); | |
560 | return true; | |
561 | } | |
562 | ||
563 | #ifdef TARGET_RISCV64 | |
564 | static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2) | |
565 | { | |
566 | tcg_gen_add_tl(ret, arg1, arg2); | |
567 | tcg_gen_ext32s_tl(ret, ret); | |
568 | } | |
f2ab1728 BK |
569 | |
570 | static void gen_subw(TCGv ret, TCGv arg1, TCGv arg2) | |
571 | { | |
572 | tcg_gen_sub_tl(ret, arg1, arg2); | |
573 | tcg_gen_ext32s_tl(ret, ret); | |
574 | } | |
575 | ||
12887016 BK |
576 | static void gen_mulw(TCGv ret, TCGv arg1, TCGv arg2) |
577 | { | |
578 | tcg_gen_mul_tl(ret, arg1, arg2); | |
579 | tcg_gen_ext32s_tl(ret, ret); | |
580 | } | |
581 | ||
582 | static bool gen_arith_div_w(DisasContext *ctx, arg_r *a, | |
583 | void(*func)(TCGv, TCGv, TCGv)) | |
584 | { | |
585 | TCGv source1, source2; | |
586 | source1 = tcg_temp_new(); | |
587 | source2 = tcg_temp_new(); | |
588 | ||
589 | gen_get_gpr(source1, a->rs1); | |
590 | gen_get_gpr(source2, a->rs2); | |
591 | tcg_gen_ext32s_tl(source1, source1); | |
592 | tcg_gen_ext32s_tl(source2, source2); | |
593 | ||
594 | (*func)(source1, source1, source2); | |
595 | ||
596 | tcg_gen_ext32s_tl(source1, source1); | |
597 | gen_set_gpr(a->rd, source1); | |
598 | tcg_temp_free(source1); | |
599 | tcg_temp_free(source2); | |
600 | return true; | |
601 | } | |
602 | ||
f17e02cd PD |
603 | static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a, |
604 | void(*func)(TCGv, TCGv, TCGv)) | |
605 | { | |
606 | TCGv source1, source2; | |
607 | source1 = tcg_temp_new(); | |
608 | source2 = tcg_temp_new(); | |
609 | ||
610 | gen_get_gpr(source1, a->rs1); | |
611 | gen_get_gpr(source2, a->rs2); | |
612 | tcg_gen_ext32u_tl(source1, source1); | |
613 | tcg_gen_ext32u_tl(source2, source2); | |
614 | ||
615 | (*func)(source1, source1, source2); | |
616 | ||
617 | tcg_gen_ext32s_tl(source1, source1); | |
618 | gen_set_gpr(a->rd, source1); | |
619 | tcg_temp_free(source1); | |
620 | tcg_temp_free(source2); | |
621 | return true; | |
622 | } | |
623 | ||
7a50d3e2 BK |
624 | #endif |
625 | ||
8dc9e8a8 BK |
626 | static bool gen_arith(DisasContext *ctx, arg_r *a, |
627 | void(*func)(TCGv, TCGv, TCGv)) | |
f2ab1728 BK |
628 | { |
629 | TCGv source1, source2; | |
630 | source1 = tcg_temp_new(); | |
631 | source2 = tcg_temp_new(); | |
632 | ||
633 | gen_get_gpr(source1, a->rs1); | |
634 | gen_get_gpr(source2, a->rs2); | |
635 | ||
636 | (*func)(source1, source1, source2); | |
637 | ||
638 | gen_set_gpr(a->rd, source1); | |
639 | tcg_temp_free(source1); | |
640 | tcg_temp_free(source2); | |
641 | return true; | |
642 | } | |
643 | ||
34446e84 BK |
644 | static bool gen_shift(DisasContext *ctx, arg_r *a, |
645 | void(*func)(TCGv, TCGv, TCGv)) | |
646 | { | |
647 | TCGv source1 = tcg_temp_new(); | |
648 | TCGv source2 = tcg_temp_new(); | |
649 | ||
650 | gen_get_gpr(source1, a->rs1); | |
651 | gen_get_gpr(source2, a->rs2); | |
652 | ||
653 | tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1); | |
654 | (*func)(source1, source1, source2); | |
655 | ||
656 | gen_set_gpr(a->rd, source1); | |
657 | tcg_temp_free(source1); | |
658 | tcg_temp_free(source2); | |
659 | return true; | |
660 | } | |
661 | ||
2a53cff4 BK |
662 | /* Include insn module translation function */ |
663 | #include "insn_trans/trans_rvi.inc.c" | |
d2e2c1e4 | 664 | #include "insn_trans/trans_rvm.inc.c" |
3b77c289 | 665 | #include "insn_trans/trans_rva.inc.c" |
6f0e74ff | 666 | #include "insn_trans/trans_rvf.inc.c" |
97f8b493 | 667 | #include "insn_trans/trans_rvd.inc.c" |
4ba79c47 | 668 | #include "insn_trans/trans_privileged.inc.c" |
2a53cff4 | 669 | |
e98d9140 BK |
670 | bool decode_insn16(DisasContext *ctx, uint16_t insn); |
671 | /* auto-generated decoder*/ | |
672 | #include "decode_insn16.inc.c" | |
673 | #include "insn_trans/trans_rvc.inc.c" | |
674 | ||
db9f3fd6 | 675 | static void decode_opc(DisasContext *ctx) |
55c2a12c MC |
676 | { |
677 | /* check for compressed insn */ | |
678 | if (extract32(ctx->opcode, 0, 2) != 3) { | |
db9f3fd6 | 679 | if (!has_ext(ctx, RVC)) { |
55c2a12c MC |
680 | gen_exception_illegal(ctx); |
681 | } else { | |
0114db1c | 682 | ctx->pc_succ_insn = ctx->base.pc_next + 2; |
e98d9140 BK |
683 | if (!decode_insn16(ctx, ctx->opcode)) { |
684 | /* fall back to old decoder */ | |
685 | decode_RV32_64C(ctx); | |
686 | } | |
55c2a12c MC |
687 | } |
688 | } else { | |
0114db1c | 689 | ctx->pc_succ_insn = ctx->base.pc_next + 4; |
2a53cff4 | 690 | if (!decode_insn32(ctx, ctx->opcode)) { |
25e6ca30 | 691 | gen_exception_illegal(ctx); |
2a53cff4 | 692 | } |
55c2a12c MC |
693 | } |
694 | } | |
695 | ||
5b4f1d2d | 696 | static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) |
55c2a12c | 697 | { |
5b4f1d2d | 698 | DisasContext *ctx = container_of(dcbase, DisasContext, base); |
d75377bf | 699 | CPURISCVState *env = cs->env_ptr; |
55c2a12c | 700 | |
5b4f1d2d | 701 | ctx->pc_succ_insn = ctx->base.pc_first; |
5b4f1d2d | 702 | ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK; |
83a71719 | 703 | ctx->mstatus_fs = ctx->base.tb->flags & TB_FLAGS_MSTATUS_FS; |
d75377bf | 704 | ctx->priv_ver = env->priv_ver; |
db9f3fd6 | 705 | ctx->misa = env->misa; |
5b4f1d2d EC |
706 | ctx->frm = -1; /* unknown rounding mode */ |
707 | } | |
55c2a12c | 708 | |
5b4f1d2d EC |
709 | static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) |
710 | { | |
711 | } | |
55c2a12c | 712 | |
5b4f1d2d EC |
713 | static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) |
714 | { | |
715 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
716 | ||
717 | tcg_gen_insn_start(ctx->base.pc_next); | |
718 | } | |
719 | ||
720 | static bool riscv_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, | |
721 | const CPUBreakpoint *bp) | |
722 | { | |
723 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
724 | ||
725 | tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); | |
726 | ctx->base.is_jmp = DISAS_NORETURN; | |
727 | gen_exception_debug(); | |
728 | /* The address covered by the breakpoint must be included in | |
729 | [tb->pc, tb->pc + tb->size) in order to for it to be | |
730 | properly cleared -- thus we increment the PC here so that | |
731 | the logic setting tb->size below does the right thing. */ | |
732 | ctx->base.pc_next += 4; | |
733 | return true; | |
734 | } | |
735 | ||
5b4f1d2d EC |
736 | static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) |
737 | { | |
738 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
739 | CPURISCVState *env = cpu->env_ptr; | |
55c2a12c | 740 | |
5b4f1d2d | 741 | ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next); |
db9f3fd6 | 742 | decode_opc(ctx); |
5b4f1d2d EC |
743 | ctx->base.pc_next = ctx->pc_succ_insn; |
744 | ||
745 | if (ctx->base.is_jmp == DISAS_NEXT) { | |
746 | target_ulong page_start; | |
747 | ||
748 | page_start = ctx->base.pc_first & TARGET_PAGE_MASK; | |
749 | if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) { | |
750 | ctx->base.is_jmp = DISAS_TOO_MANY; | |
55c2a12c | 751 | } |
55c2a12c | 752 | } |
5b4f1d2d EC |
753 | } |
754 | ||
755 | static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) | |
756 | { | |
757 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
758 | ||
759 | switch (ctx->base.is_jmp) { | |
b2e32021 | 760 | case DISAS_TOO_MANY: |
ccf08e40 | 761 | gen_goto_tb(ctx, 0, ctx->base.pc_next); |
55c2a12c | 762 | break; |
b2e32021 | 763 | case DISAS_NORETURN: |
55c2a12c | 764 | break; |
b2e32021 EC |
765 | default: |
766 | g_assert_not_reached(); | |
55c2a12c | 767 | } |
5b4f1d2d EC |
768 | } |
769 | ||
770 | static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) | |
771 | { | |
772 | qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); | |
773 | log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); | |
774 | } | |
775 | ||
776 | static const TranslatorOps riscv_tr_ops = { | |
777 | .init_disas_context = riscv_tr_init_disas_context, | |
778 | .tb_start = riscv_tr_tb_start, | |
779 | .insn_start = riscv_tr_insn_start, | |
780 | .breakpoint_check = riscv_tr_breakpoint_check, | |
781 | .translate_insn = riscv_tr_translate_insn, | |
782 | .tb_stop = riscv_tr_tb_stop, | |
783 | .disas_log = riscv_tr_disas_log, | |
784 | }; | |
785 | ||
786 | void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) | |
787 | { | |
788 | DisasContext ctx; | |
789 | ||
790 | translator_loop(&riscv_tr_ops, &ctx.base, cs, tb); | |
55c2a12c MC |
791 | } |
792 | ||
793 | void riscv_translate_init(void) | |
794 | { | |
795 | int i; | |
796 | ||
797 | /* cpu_gpr[0] is a placeholder for the zero register. Do not use it. */ | |
798 | /* Use the gen_set_gpr and gen_get_gpr helper functions when accessing */ | |
799 | /* registers, unless you specifically block reads/writes to reg 0 */ | |
800 | cpu_gpr[0] = NULL; | |
801 | ||
802 | for (i = 1; i < 32; i++) { | |
803 | cpu_gpr[i] = tcg_global_mem_new(cpu_env, | |
804 | offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); | |
805 | } | |
806 | ||
807 | for (i = 0; i < 32; i++) { | |
808 | cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, | |
809 | offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); | |
810 | } | |
811 | ||
812 | cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); | |
813 | load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), | |
814 | "load_res"); | |
815 | load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), | |
816 | "load_val"); | |
817 | } |