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Commit | Line | Data |
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55c2a12c MC |
1 | /* |
2 | * RISC-V emulation for qemu: main translation routines. | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2 or later, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along with | |
16 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | ||
19 | #include "qemu/osdep.h" | |
20 | #include "qemu/log.h" | |
21 | #include "cpu.h" | |
dcb32f1d | 22 | #include "tcg/tcg-op.h" |
55c2a12c MC |
23 | #include "disas/disas.h" |
24 | #include "exec/cpu_ldst.h" | |
25 | #include "exec/exec-all.h" | |
26 | #include "exec/helper-proto.h" | |
27 | #include "exec/helper-gen.h" | |
28 | ||
b2e32021 | 29 | #include "exec/translator.h" |
55c2a12c MC |
30 | #include "exec/log.h" |
31 | ||
32 | #include "instmap.h" | |
33 | ||
34 | /* global register indices */ | |
ad9e5aa2 | 35 | static TCGv cpu_gpr[32], cpu_pc, cpu_vl; |
55c2a12c MC |
36 | static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ |
37 | static TCGv load_res; | |
38 | static TCGv load_val; | |
39 | ||
40 | #include "exec/gen-icount.h" | |
41 | ||
ecda15d1 RH |
42 | /* |
43 | * If an operation is being performed on less than TARGET_LONG_BITS, | |
44 | * it may require the inputs to be sign- or zero-extended; which will | |
45 | * depend on the exact operation being performed. | |
46 | */ | |
47 | typedef enum { | |
48 | EXT_NONE, | |
49 | EXT_SIGN, | |
50 | EXT_ZERO, | |
51 | } DisasExtend; | |
52 | ||
55c2a12c | 53 | typedef struct DisasContext { |
0114db1c EC |
54 | DisasContextBase base; |
55 | /* pc_succ_insn points to the instruction following base.pc_next */ | |
56 | target_ulong pc_succ_insn; | |
d75377bf | 57 | target_ulong priv_ver; |
ecda15d1 | 58 | target_ulong misa; |
45b4dc8b | 59 | uint32_t opcode; |
83a71719 | 60 | uint32_t mstatus_fs; |
a88f0402 | 61 | uint32_t mstatus_hs_fs; |
55c2a12c | 62 | uint32_t mem_idx; |
55c2a12c MC |
63 | /* Remember the rounding mode encoded in the previous fp instruction, |
64 | which we have already installed into env->fp_status. Or -1 for | |
65 | no previous fp instruction. Note that we exit the TB when writing | |
66 | to any system register, which includes CSR_FRM, so we do not have | |
67 | to reset this known value. */ | |
68 | int frm; | |
ecda15d1 RH |
69 | bool w; |
70 | bool virt_enabled; | |
50fba816 | 71 | bool ext_ifencei; |
743077b3 | 72 | bool hlsx; |
2b7168fc LZ |
73 | /* vector extension */ |
74 | bool vill; | |
75 | uint8_t lmul; | |
76 | uint8_t sew; | |
77 | uint16_t vlen; | |
751538d5 | 78 | uint16_t mlen; |
2b7168fc | 79 | bool vl_eq_vlmax; |
ecda15d1 | 80 | uint8_t ntemp; |
a10b9d93 | 81 | CPUState *cs; |
ecda15d1 RH |
82 | TCGv zero; |
83 | /* Space for 3 operands plus 1 extra for address computation. */ | |
84 | TCGv temp[4]; | |
55c2a12c MC |
85 | } DisasContext; |
86 | ||
db9f3fd6 MC |
87 | static inline bool has_ext(DisasContext *ctx, uint32_t ext) |
88 | { | |
89 | return ctx->misa & ext; | |
d36a86d0 RH |
90 | } |
91 | ||
4fd7455b AF |
92 | #ifdef TARGET_RISCV32 |
93 | # define is_32bit(ctx) true | |
94 | #elif defined(CONFIG_USER_ONLY) | |
95 | # define is_32bit(ctx) false | |
96 | #else | |
97 | static inline bool is_32bit(DisasContext *ctx) | |
98 | { | |
99 | return (ctx->misa & RV32) == RV32; | |
100 | } | |
101 | #endif | |
102 | ||
89c88309 RH |
103 | /* The word size for this operation. */ |
104 | static inline int oper_len(DisasContext *ctx) | |
105 | { | |
106 | return ctx->w ? 32 : TARGET_LONG_BITS; | |
107 | } | |
108 | ||
109 | ||
d36a86d0 RH |
110 | /* |
111 | * RISC-V requires NaN-boxing of narrower width floating point values. | |
112 | * This applies when a 32-bit value is assigned to a 64-bit FP register. | |
113 | * For consistency and simplicity, we nanbox results even when the RVD | |
114 | * extension is not present. | |
115 | */ | |
116 | static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) | |
117 | { | |
118 | tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); | |
ffe70e4d RH |
119 | } |
120 | ||
121 | /* | |
122 | * A narrow n-bit operation, where n < FLEN, checks that input operands | |
123 | * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. | |
124 | * If so, the least-significant bits of the input are used, otherwise the | |
125 | * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). | |
126 | * | |
127 | * Here, the result is always nan-boxed, even the canonical nan. | |
128 | */ | |
129 | static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) | |
130 | { | |
05b80ed0 RH |
131 | TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); |
132 | TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull); | |
ffe70e4d RH |
133 | |
134 | tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); | |
db9f3fd6 MC |
135 | } |
136 | ||
55c2a12c MC |
137 | static void generate_exception(DisasContext *ctx, int excp) |
138 | { | |
0114db1c | 139 | tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); |
05b80ed0 | 140 | gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); |
0114db1c | 141 | ctx->base.is_jmp = DISAS_NORETURN; |
55c2a12c MC |
142 | } |
143 | ||
ac12b601 | 144 | static void generate_exception_mtval(DisasContext *ctx, int excp) |
55c2a12c | 145 | { |
0114db1c | 146 | tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); |
55c2a12c | 147 | tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); |
05b80ed0 | 148 | gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); |
0114db1c | 149 | ctx->base.is_jmp = DISAS_NORETURN; |
55c2a12c MC |
150 | } |
151 | ||
55c2a12c MC |
152 | static void gen_exception_illegal(DisasContext *ctx) |
153 | { | |
154 | generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); | |
155 | } | |
156 | ||
157 | static void gen_exception_inst_addr_mis(DisasContext *ctx) | |
158 | { | |
ac12b601 | 159 | generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS); |
55c2a12c MC |
160 | } |
161 | ||
55c2a12c MC |
162 | static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) |
163 | { | |
c54d50c1 | 164 | if (translator_use_goto_tb(&ctx->base, dest)) { |
55c2a12c MC |
165 | tcg_gen_goto_tb(n); |
166 | tcg_gen_movi_tl(cpu_pc, dest); | |
07ea28b4 | 167 | tcg_gen_exit_tb(ctx->base.tb, n); |
55c2a12c MC |
168 | } else { |
169 | tcg_gen_movi_tl(cpu_pc, dest); | |
273b68b1 | 170 | tcg_gen_lookup_and_goto_ptr(); |
55c2a12c MC |
171 | } |
172 | } | |
173 | ||
ecda15d1 RH |
174 | /* |
175 | * Wrappers for getting reg values. | |
176 | * | |
177 | * The $zero register does not have cpu_gpr[0] allocated -- we supply the | |
178 | * constant zero as a source, and an uninitialized sink as destination. | |
179 | * | |
180 | * Further, we may provide an extension for word operations. | |
55c2a12c | 181 | */ |
ecda15d1 RH |
182 | static TCGv temp_new(DisasContext *ctx) |
183 | { | |
184 | assert(ctx->ntemp < ARRAY_SIZE(ctx->temp)); | |
185 | return ctx->temp[ctx->ntemp++] = tcg_temp_new(); | |
186 | } | |
187 | ||
188 | static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) | |
55c2a12c | 189 | { |
ecda15d1 RH |
190 | TCGv t; |
191 | ||
55c2a12c | 192 | if (reg_num == 0) { |
ecda15d1 | 193 | return ctx->zero; |
55c2a12c | 194 | } |
ecda15d1 RH |
195 | |
196 | switch (ctx->w ? ext : EXT_NONE) { | |
197 | case EXT_NONE: | |
198 | return cpu_gpr[reg_num]; | |
199 | case EXT_SIGN: | |
200 | t = temp_new(ctx); | |
201 | tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); | |
202 | return t; | |
203 | case EXT_ZERO: | |
204 | t = temp_new(ctx); | |
205 | tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); | |
206 | return t; | |
207 | } | |
208 | g_assert_not_reached(); | |
55c2a12c MC |
209 | } |
210 | ||
191d1daf | 211 | static TCGv dest_gpr(DisasContext *ctx, int reg_num) |
ecda15d1 RH |
212 | { |
213 | if (reg_num == 0 || ctx->w) { | |
214 | return temp_new(ctx); | |
215 | } | |
216 | return cpu_gpr[reg_num]; | |
217 | } | |
218 | ||
219 | static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) | |
55c2a12c | 220 | { |
ecda15d1 RH |
221 | if (reg_num != 0) { |
222 | if (ctx->w) { | |
223 | tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); | |
224 | } else { | |
225 | tcg_gen_mov_tl(cpu_gpr[reg_num], t); | |
226 | } | |
55c2a12c MC |
227 | } |
228 | } | |
229 | ||
db9f3fd6 | 230 | static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) |
55c2a12c MC |
231 | { |
232 | target_ulong next_pc; | |
233 | ||
234 | /* check misaligned: */ | |
0114db1c | 235 | next_pc = ctx->base.pc_next + imm; |
db9f3fd6 | 236 | if (!has_ext(ctx, RVC)) { |
55c2a12c MC |
237 | if ((next_pc & 0x3) != 0) { |
238 | gen_exception_inst_addr_mis(ctx); | |
239 | return; | |
240 | } | |
241 | } | |
242 | if (rd != 0) { | |
0114db1c | 243 | tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn); |
55c2a12c MC |
244 | } |
245 | ||
0114db1c EC |
246 | gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */ |
247 | ctx->base.is_jmp = DISAS_NORETURN; | |
55c2a12c MC |
248 | } |
249 | ||
533b8f88 RH |
250 | #ifndef CONFIG_USER_ONLY |
251 | /* The states of mstatus_fs are: | |
252 | * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty | |
253 | * We will have already diagnosed disabled state, | |
254 | * and need to turn initial/clean into dirty. | |
255 | */ | |
256 | static void mark_fs_dirty(DisasContext *ctx) | |
257 | { | |
258 | TCGv tmp; | |
a88f0402 | 259 | target_ulong sd = is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD; |
4fd7455b | 260 | |
a88f0402 FC |
261 | if (ctx->mstatus_fs != MSTATUS_FS) { |
262 | /* Remember the state change for the rest of the TB. */ | |
263 | ctx->mstatus_fs = MSTATUS_FS; | |
533b8f88 | 264 | |
a88f0402 FC |
265 | tmp = tcg_temp_new(); |
266 | tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); | |
267 | tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd); | |
268 | tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); | |
269 | tcg_temp_free(tmp); | |
270 | } | |
4fd7455b | 271 | |
a88f0402 FC |
272 | if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) { |
273 | /* Remember the stage change for the rest of the TB. */ | |
274 | ctx->mstatus_hs_fs = MSTATUS_FS; | |
45b4dc8b | 275 | |
a88f0402 | 276 | tmp = tcg_temp_new(); |
45b4dc8b | 277 | tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); |
4fd7455b | 278 | tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd); |
45b4dc8b | 279 | tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); |
a88f0402 | 280 | tcg_temp_free(tmp); |
45b4dc8b | 281 | } |
533b8f88 RH |
282 | } |
283 | #else | |
284 | static inline void mark_fs_dirty(DisasContext *ctx) { } | |
285 | #endif | |
286 | ||
55c2a12c MC |
287 | static void gen_set_rm(DisasContext *ctx, int rm) |
288 | { | |
55c2a12c MC |
289 | if (ctx->frm == rm) { |
290 | return; | |
291 | } | |
292 | ctx->frm = rm; | |
05b80ed0 | 293 | gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); |
55c2a12c MC |
294 | } |
295 | ||
751538d5 LZ |
296 | static int ex_plus_1(DisasContext *ctx, int nf) |
297 | { | |
298 | return nf + 1; | |
299 | } | |
300 | ||
2a53cff4 | 301 | #define EX_SH(amount) \ |
451e4ffd | 302 | static int ex_shift_##amount(DisasContext *ctx, int imm) \ |
2a53cff4 BK |
303 | { \ |
304 | return imm << amount; \ | |
305 | } | |
3cca75a6 | 306 | EX_SH(1) |
e98d9140 BK |
307 | EX_SH(2) |
308 | EX_SH(3) | |
07b001c6 | 309 | EX_SH(4) |
2a53cff4 BK |
310 | EX_SH(12) |
311 | ||
d2e2c1e4 BK |
312 | #define REQUIRE_EXT(ctx, ext) do { \ |
313 | if (!has_ext(ctx, ext)) { \ | |
314 | return false; \ | |
315 | } \ | |
316 | } while (0) | |
7e68e6c7 PT |
317 | |
318 | #define REQUIRE_32BIT(ctx) do { \ | |
319 | if (!is_32bit(ctx)) { \ | |
320 | return false; \ | |
321 | } \ | |
322 | } while (0) | |
d2e2c1e4 | 323 | |
daf866b6 AF |
324 | #define REQUIRE_64BIT(ctx) do { \ |
325 | if (is_32bit(ctx)) { \ | |
326 | return false; \ | |
327 | } \ | |
328 | } while (0) | |
329 | ||
451e4ffd | 330 | static int ex_rvc_register(DisasContext *ctx, int reg) |
e98d9140 BK |
331 | { |
332 | return 8 + reg; | |
333 | } | |
334 | ||
6cafec92 RH |
335 | static int ex_rvc_shifti(DisasContext *ctx, int imm) |
336 | { | |
337 | /* For RV128 a shamt of 0 means a shift by 64. */ | |
338 | return imm ? imm : 64; | |
339 | } | |
340 | ||
2a53cff4 | 341 | /* Include the auto-generated decoder for 32 bit insn */ |
abff1abf | 342 | #include "decode-insn32.c.inc" |
7a50d3e2 | 343 | |
191d1daf | 344 | static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, |
598aa116 RH |
345 | void (*func)(TCGv, TCGv, target_long)) |
346 | { | |
191d1daf RH |
347 | TCGv dest = dest_gpr(ctx, a->rd); |
348 | TCGv src1 = get_gpr(ctx, a->rs1, ext); | |
598aa116 | 349 | |
191d1daf | 350 | func(dest, src1, a->imm); |
598aa116 | 351 | |
191d1daf | 352 | gen_set_gpr(ctx, a->rd, dest); |
598aa116 RH |
353 | return true; |
354 | } | |
355 | ||
191d1daf | 356 | static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, |
598aa116 | 357 | void (*func)(TCGv, TCGv, TCGv)) |
7a50d3e2 | 358 | { |
191d1daf RH |
359 | TCGv dest = dest_gpr(ctx, a->rd); |
360 | TCGv src1 = get_gpr(ctx, a->rs1, ext); | |
361 | TCGv src2 = tcg_constant_tl(a->imm); | |
7a50d3e2 | 362 | |
191d1daf | 363 | func(dest, src1, src2); |
7a50d3e2 | 364 | |
191d1daf | 365 | gen_set_gpr(ctx, a->rd, dest); |
7a50d3e2 BK |
366 | return true; |
367 | } | |
368 | ||
191d1daf RH |
369 | static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, |
370 | void (*func)(TCGv, TCGv, TCGv)) | |
f2ab1728 | 371 | { |
191d1daf RH |
372 | TCGv dest = dest_gpr(ctx, a->rd); |
373 | TCGv src1 = get_gpr(ctx, a->rs1, ext); | |
374 | TCGv src2 = get_gpr(ctx, a->rs2, ext); | |
f2ab1728 | 375 | |
191d1daf | 376 | func(dest, src1, src2); |
f2ab1728 | 377 | |
191d1daf | 378 | gen_set_gpr(ctx, a->rd, dest); |
f2ab1728 BK |
379 | return true; |
380 | } | |
381 | ||
89c88309 RH |
382 | static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, |
383 | void (*func)(TCGv, TCGv, target_long)) | |
a10b9d93 | 384 | { |
89c88309 RH |
385 | TCGv dest, src1; |
386 | int max_len = oper_len(ctx); | |
a10b9d93 | 387 | |
89c88309 | 388 | if (a->shamt >= max_len) { |
981d3568 FC |
389 | return false; |
390 | } | |
391 | ||
89c88309 RH |
392 | dest = dest_gpr(ctx, a->rd); |
393 | src1 = get_gpr(ctx, a->rs1, ext); | |
981d3568 | 394 | |
89c88309 | 395 | func(dest, src1, a->shamt); |
981d3568 | 396 | |
89c88309 | 397 | gen_set_gpr(ctx, a->rd, dest); |
981d3568 FC |
398 | return true; |
399 | } | |
400 | ||
89c88309 RH |
401 | static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, |
402 | void (*func)(TCGv, TCGv, TCGv)) | |
23cd1777 | 403 | { |
89c88309 RH |
404 | TCGv dest, src1, src2; |
405 | int max_len = oper_len(ctx); | |
406 | ||
407 | if (a->shamt >= max_len) { | |
408 | return false; | |
409 | } | |
23cd1777 | 410 | |
89c88309 RH |
411 | dest = dest_gpr(ctx, a->rd); |
412 | src1 = get_gpr(ctx, a->rs1, ext); | |
413 | src2 = tcg_constant_tl(a->shamt); | |
23cd1777 | 414 | |
89c88309 | 415 | func(dest, src1, src2); |
23cd1777 | 416 | |
89c88309 | 417 | gen_set_gpr(ctx, a->rd, dest); |
23cd1777 FC |
418 | return true; |
419 | } | |
420 | ||
89c88309 RH |
421 | static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, |
422 | void (*func)(TCGv, TCGv, TCGv)) | |
981d3568 | 423 | { |
89c88309 RH |
424 | TCGv dest = dest_gpr(ctx, a->rd); |
425 | TCGv src1 = get_gpr(ctx, a->rs1, ext); | |
426 | TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); | |
427 | TCGv ext2 = tcg_temp_new(); | |
981d3568 | 428 | |
89c88309 RH |
429 | tcg_gen_andi_tl(ext2, src2, oper_len(ctx) - 1); |
430 | func(dest, src1, ext2); | |
981d3568 | 431 | |
89c88309 RH |
432 | gen_set_gpr(ctx, a->rd, dest); |
433 | tcg_temp_free(ext2); | |
981d3568 FC |
434 | return true; |
435 | } | |
436 | ||
60903915 RH |
437 | static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, |
438 | void (*func)(TCGv, TCGv)) | |
43824018 | 439 | { |
60903915 RH |
440 | TCGv dest = dest_gpr(ctx, a->rd); |
441 | TCGv src1 = get_gpr(ctx, a->rs1, ext); | |
43824018 | 442 | |
60903915 | 443 | func(dest, src1); |
43824018 | 444 | |
60903915 | 445 | gen_set_gpr(ctx, a->rd, dest); |
43824018 KC |
446 | return true; |
447 | } | |
448 | ||
89c88309 RH |
449 | static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) |
450 | { | |
451 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
452 | CPUState *cpu = ctx->cs; | |
453 | CPURISCVState *env = cpu->env_ptr; | |
454 | ||
455 | return cpu_ldl_code(env, pc); | |
456 | } | |
457 | ||
2a53cff4 | 458 | /* Include insn module translation function */ |
139c1837 PB |
459 | #include "insn_trans/trans_rvi.c.inc" |
460 | #include "insn_trans/trans_rvm.c.inc" | |
461 | #include "insn_trans/trans_rva.c.inc" | |
462 | #include "insn_trans/trans_rvf.c.inc" | |
463 | #include "insn_trans/trans_rvd.c.inc" | |
464 | #include "insn_trans/trans_rvh.c.inc" | |
465 | #include "insn_trans/trans_rvv.c.inc" | |
43824018 | 466 | #include "insn_trans/trans_rvb.c.inc" |
139c1837 | 467 | #include "insn_trans/trans_privileged.c.inc" |
2a53cff4 | 468 | |
59a3a1c0 | 469 | /* Include the auto-generated decoder for 16 bit insn */ |
abff1abf | 470 | #include "decode-insn16.c.inc" |
e98d9140 | 471 | |
25139bf7 | 472 | static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) |
55c2a12c MC |
473 | { |
474 | /* check for compressed insn */ | |
25139bf7 | 475 | if (extract16(opcode, 0, 2) != 3) { |
db9f3fd6 | 476 | if (!has_ext(ctx, RVC)) { |
55c2a12c MC |
477 | gen_exception_illegal(ctx); |
478 | } else { | |
0114db1c | 479 | ctx->pc_succ_insn = ctx->base.pc_next + 2; |
25139bf7 | 480 | if (!decode_insn16(ctx, opcode)) { |
9a27f69b | 481 | gen_exception_illegal(ctx); |
e98d9140 | 482 | } |
55c2a12c MC |
483 | } |
484 | } else { | |
25139bf7 AB |
485 | uint32_t opcode32 = opcode; |
486 | opcode32 = deposit32(opcode32, 16, 16, | |
4e116893 IL |
487 | translator_lduw(env, &ctx->base, |
488 | ctx->base.pc_next + 2)); | |
0114db1c | 489 | ctx->pc_succ_insn = ctx->base.pc_next + 4; |
25139bf7 | 490 | if (!decode_insn32(ctx, opcode32)) { |
25e6ca30 | 491 | gen_exception_illegal(ctx); |
2a53cff4 | 492 | } |
55c2a12c MC |
493 | } |
494 | } | |
495 | ||
5b4f1d2d | 496 | static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) |
55c2a12c | 497 | { |
5b4f1d2d | 498 | DisasContext *ctx = container_of(dcbase, DisasContext, base); |
d75377bf | 499 | CPURISCVState *env = cs->env_ptr; |
50fba816 | 500 | RISCVCPU *cpu = RISCV_CPU(cs); |
2b7168fc | 501 | uint32_t tb_flags = ctx->base.tb->flags; |
55c2a12c | 502 | |
5b4f1d2d | 503 | ctx->pc_succ_insn = ctx->base.pc_first; |
61d56494 | 504 | ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); |
2b7168fc | 505 | ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS; |
d75377bf | 506 | ctx->priv_ver = env->priv_ver; |
45b4dc8b | 507 | #if !defined(CONFIG_USER_ONLY) |
ae84dd0a AF |
508 | if (riscv_has_ext(env, RVH)) { |
509 | ctx->virt_enabled = riscv_cpu_virt_enabled(env); | |
ae84dd0a AF |
510 | } else { |
511 | ctx->virt_enabled = false; | |
512 | } | |
45b4dc8b AF |
513 | #else |
514 | ctx->virt_enabled = false; | |
515 | #endif | |
db9f3fd6 | 516 | ctx->misa = env->misa; |
5b4f1d2d | 517 | ctx->frm = -1; /* unknown rounding mode */ |
50fba816 | 518 | ctx->ext_ifencei = cpu->cfg.ext_ifencei; |
2b7168fc | 519 | ctx->vlen = cpu->cfg.vlen; |
a88f0402 | 520 | ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS); |
743077b3 | 521 | ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); |
2b7168fc LZ |
522 | ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); |
523 | ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); | |
524 | ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL); | |
751538d5 | 525 | ctx->mlen = 1 << (ctx->sew + 3 - ctx->lmul); |
2b7168fc | 526 | ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); |
a10b9d93 | 527 | ctx->cs = cs; |
ecda15d1 RH |
528 | ctx->w = false; |
529 | ctx->ntemp = 0; | |
530 | memset(ctx->temp, 0, sizeof(ctx->temp)); | |
531 | ||
532 | ctx->zero = tcg_constant_tl(0); | |
5b4f1d2d | 533 | } |
55c2a12c | 534 | |
5b4f1d2d EC |
535 | static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) |
536 | { | |
537 | } | |
55c2a12c | 538 | |
5b4f1d2d EC |
539 | static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) |
540 | { | |
541 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
542 | ||
543 | tcg_gen_insn_start(ctx->base.pc_next); | |
544 | } | |
545 | ||
5b4f1d2d EC |
546 | static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) |
547 | { | |
548 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
549 | CPURISCVState *env = cpu->env_ptr; | |
4e116893 | 550 | uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); |
55c2a12c | 551 | |
25139bf7 | 552 | decode_opc(env, ctx, opcode16); |
5b4f1d2d | 553 | ctx->base.pc_next = ctx->pc_succ_insn; |
ecda15d1 RH |
554 | ctx->w = false; |
555 | ||
556 | for (int i = ctx->ntemp - 1; i >= 0; --i) { | |
557 | tcg_temp_free(ctx->temp[i]); | |
558 | ctx->temp[i] = NULL; | |
559 | } | |
560 | ctx->ntemp = 0; | |
5b4f1d2d EC |
561 | |
562 | if (ctx->base.is_jmp == DISAS_NEXT) { | |
563 | target_ulong page_start; | |
564 | ||
565 | page_start = ctx->base.pc_first & TARGET_PAGE_MASK; | |
566 | if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) { | |
567 | ctx->base.is_jmp = DISAS_TOO_MANY; | |
55c2a12c | 568 | } |
55c2a12c | 569 | } |
5b4f1d2d EC |
570 | } |
571 | ||
572 | static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) | |
573 | { | |
574 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
575 | ||
576 | switch (ctx->base.is_jmp) { | |
b2e32021 | 577 | case DISAS_TOO_MANY: |
ccf08e40 | 578 | gen_goto_tb(ctx, 0, ctx->base.pc_next); |
55c2a12c | 579 | break; |
b2e32021 | 580 | case DISAS_NORETURN: |
55c2a12c | 581 | break; |
b2e32021 EC |
582 | default: |
583 | g_assert_not_reached(); | |
55c2a12c | 584 | } |
5b4f1d2d EC |
585 | } |
586 | ||
587 | static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) | |
588 | { | |
35f69039 AF |
589 | #ifndef CONFIG_USER_ONLY |
590 | RISCVCPU *rvcpu = RISCV_CPU(cpu); | |
591 | CPURISCVState *env = &rvcpu->env; | |
592 | #endif | |
593 | ||
5b4f1d2d | 594 | qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); |
35f69039 AF |
595 | #ifndef CONFIG_USER_ONLY |
596 | qemu_log("Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", env->priv, env->virt); | |
597 | #endif | |
5b4f1d2d EC |
598 | log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); |
599 | } | |
600 | ||
601 | static const TranslatorOps riscv_tr_ops = { | |
602 | .init_disas_context = riscv_tr_init_disas_context, | |
603 | .tb_start = riscv_tr_tb_start, | |
604 | .insn_start = riscv_tr_insn_start, | |
5b4f1d2d EC |
605 | .translate_insn = riscv_tr_translate_insn, |
606 | .tb_stop = riscv_tr_tb_stop, | |
607 | .disas_log = riscv_tr_disas_log, | |
608 | }; | |
609 | ||
8b86d6d2 | 610 | void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) |
5b4f1d2d EC |
611 | { |
612 | DisasContext ctx; | |
613 | ||
8b86d6d2 | 614 | translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns); |
55c2a12c MC |
615 | } |
616 | ||
617 | void riscv_translate_init(void) | |
618 | { | |
619 | int i; | |
620 | ||
8e034ae4 RH |
621 | /* |
622 | * cpu_gpr[0] is a placeholder for the zero register. Do not use it. | |
623 | * Use the gen_set_gpr and get_gpr helper functions when accessing regs, | |
624 | * unless you specifically block reads/writes to reg 0. | |
625 | */ | |
55c2a12c MC |
626 | cpu_gpr[0] = NULL; |
627 | ||
628 | for (i = 1; i < 32; i++) { | |
629 | cpu_gpr[i] = tcg_global_mem_new(cpu_env, | |
630 | offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); | |
631 | } | |
632 | ||
633 | for (i = 0; i < 32; i++) { | |
634 | cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, | |
635 | offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); | |
636 | } | |
637 | ||
638 | cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); | |
ad9e5aa2 | 639 | cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl"); |
55c2a12c MC |
640 | load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), |
641 | "load_res"); | |
642 | load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), | |
643 | "load_val"); | |
644 | } |