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55c2a12c MC |
1 | /* |
2 | * RISC-V emulation for qemu: main translation routines. | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2 or later, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along with | |
16 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | ||
19 | #include "qemu/osdep.h" | |
20 | #include "qemu/log.h" | |
21 | #include "cpu.h" | |
dcb32f1d | 22 | #include "tcg/tcg-op.h" |
55c2a12c MC |
23 | #include "disas/disas.h" |
24 | #include "exec/cpu_ldst.h" | |
25 | #include "exec/exec-all.h" | |
26 | #include "exec/helper-proto.h" | |
27 | #include "exec/helper-gen.h" | |
28 | ||
b2e32021 | 29 | #include "exec/translator.h" |
55c2a12c MC |
30 | #include "exec/log.h" |
31 | ||
32 | #include "instmap.h" | |
33 | ||
34 | /* global register indices */ | |
ad9e5aa2 | 35 | static TCGv cpu_gpr[32], cpu_pc, cpu_vl; |
55c2a12c MC |
36 | static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ |
37 | static TCGv load_res; | |
38 | static TCGv load_val; | |
39 | ||
40 | #include "exec/gen-icount.h" | |
41 | ||
42 | typedef struct DisasContext { | |
0114db1c EC |
43 | DisasContextBase base; |
44 | /* pc_succ_insn points to the instruction following base.pc_next */ | |
45 | target_ulong pc_succ_insn; | |
d75377bf | 46 | target_ulong priv_ver; |
45b4dc8b AF |
47 | bool virt_enabled; |
48 | uint32_t opcode; | |
83a71719 | 49 | uint32_t mstatus_fs; |
65d1a2bd | 50 | target_ulong misa; |
55c2a12c | 51 | uint32_t mem_idx; |
55c2a12c MC |
52 | /* Remember the rounding mode encoded in the previous fp instruction, |
53 | which we have already installed into env->fp_status. Or -1 for | |
54 | no previous fp instruction. Note that we exit the TB when writing | |
55 | to any system register, which includes CSR_FRM, so we do not have | |
56 | to reset this known value. */ | |
57 | int frm; | |
50fba816 | 58 | bool ext_ifencei; |
743077b3 | 59 | bool hlsx; |
2b7168fc LZ |
60 | /* vector extension */ |
61 | bool vill; | |
62 | uint8_t lmul; | |
63 | uint8_t sew; | |
64 | uint16_t vlen; | |
751538d5 | 65 | uint16_t mlen; |
2b7168fc | 66 | bool vl_eq_vlmax; |
a10b9d93 | 67 | CPUState *cs; |
55c2a12c MC |
68 | } DisasContext; |
69 | ||
db9f3fd6 MC |
70 | static inline bool has_ext(DisasContext *ctx, uint32_t ext) |
71 | { | |
72 | return ctx->misa & ext; | |
d36a86d0 RH |
73 | } |
74 | ||
4fd7455b AF |
75 | #ifdef TARGET_RISCV32 |
76 | # define is_32bit(ctx) true | |
77 | #elif defined(CONFIG_USER_ONLY) | |
78 | # define is_32bit(ctx) false | |
79 | #else | |
80 | static inline bool is_32bit(DisasContext *ctx) | |
81 | { | |
82 | return (ctx->misa & RV32) == RV32; | |
83 | } | |
84 | #endif | |
85 | ||
d36a86d0 RH |
86 | /* |
87 | * RISC-V requires NaN-boxing of narrower width floating point values. | |
88 | * This applies when a 32-bit value is assigned to a 64-bit FP register. | |
89 | * For consistency and simplicity, we nanbox results even when the RVD | |
90 | * extension is not present. | |
91 | */ | |
92 | static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) | |
93 | { | |
94 | tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); | |
ffe70e4d RH |
95 | } |
96 | ||
97 | /* | |
98 | * A narrow n-bit operation, where n < FLEN, checks that input operands | |
99 | * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. | |
100 | * If so, the least-significant bits of the input are used, otherwise the | |
101 | * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). | |
102 | * | |
103 | * Here, the result is always nan-boxed, even the canonical nan. | |
104 | */ | |
105 | static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) | |
106 | { | |
05b80ed0 RH |
107 | TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); |
108 | TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull); | |
ffe70e4d RH |
109 | |
110 | tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); | |
db9f3fd6 MC |
111 | } |
112 | ||
55c2a12c MC |
113 | static void generate_exception(DisasContext *ctx, int excp) |
114 | { | |
0114db1c | 115 | tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); |
05b80ed0 | 116 | gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); |
0114db1c | 117 | ctx->base.is_jmp = DISAS_NORETURN; |
55c2a12c MC |
118 | } |
119 | ||
ac12b601 | 120 | static void generate_exception_mtval(DisasContext *ctx, int excp) |
55c2a12c | 121 | { |
0114db1c | 122 | tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); |
55c2a12c | 123 | tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); |
05b80ed0 | 124 | gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); |
0114db1c | 125 | ctx->base.is_jmp = DISAS_NORETURN; |
55c2a12c MC |
126 | } |
127 | ||
128 | static void gen_exception_debug(void) | |
129 | { | |
05b80ed0 | 130 | gen_helper_raise_exception(cpu_env, tcg_constant_i32(EXCP_DEBUG)); |
55c2a12c MC |
131 | } |
132 | ||
6e2716d8 FC |
133 | /* Wrapper around tcg_gen_exit_tb that handles single stepping */ |
134 | static void exit_tb(DisasContext *ctx) | |
135 | { | |
136 | if (ctx->base.singlestep_enabled) { | |
137 | gen_exception_debug(); | |
138 | } else { | |
139 | tcg_gen_exit_tb(NULL, 0); | |
140 | } | |
141 | } | |
142 | ||
143 | /* Wrapper around tcg_gen_lookup_and_goto_ptr that handles single stepping */ | |
144 | static void lookup_and_goto_ptr(DisasContext *ctx) | |
145 | { | |
146 | if (ctx->base.singlestep_enabled) { | |
147 | gen_exception_debug(); | |
148 | } else { | |
149 | tcg_gen_lookup_and_goto_ptr(); | |
150 | } | |
151 | } | |
152 | ||
55c2a12c MC |
153 | static void gen_exception_illegal(DisasContext *ctx) |
154 | { | |
155 | generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); | |
156 | } | |
157 | ||
158 | static void gen_exception_inst_addr_mis(DisasContext *ctx) | |
159 | { | |
ac12b601 | 160 | generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS); |
55c2a12c MC |
161 | } |
162 | ||
55c2a12c MC |
163 | static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) |
164 | { | |
c54d50c1 | 165 | if (translator_use_goto_tb(&ctx->base, dest)) { |
55c2a12c MC |
166 | tcg_gen_goto_tb(n); |
167 | tcg_gen_movi_tl(cpu_pc, dest); | |
07ea28b4 | 168 | tcg_gen_exit_tb(ctx->base.tb, n); |
55c2a12c MC |
169 | } else { |
170 | tcg_gen_movi_tl(cpu_pc, dest); | |
6e2716d8 | 171 | lookup_and_goto_ptr(ctx); |
55c2a12c MC |
172 | } |
173 | } | |
174 | ||
175 | /* Wrapper for getting reg values - need to check of reg is zero since | |
176 | * cpu_gpr[0] is not actually allocated | |
177 | */ | |
867c8196 | 178 | static void gen_get_gpr(DisasContext *ctx, TCGv t, int reg_num) |
55c2a12c MC |
179 | { |
180 | if (reg_num == 0) { | |
181 | tcg_gen_movi_tl(t, 0); | |
182 | } else { | |
183 | tcg_gen_mov_tl(t, cpu_gpr[reg_num]); | |
184 | } | |
185 | } | |
186 | ||
187 | /* Wrapper for setting reg values - need to check of reg is zero since | |
188 | * cpu_gpr[0] is not actually allocated. this is more for safety purposes, | |
189 | * since we usually avoid calling the OP_TYPE_gen function if we see a write to | |
190 | * $zero | |
191 | */ | |
867c8196 | 192 | static void gen_set_gpr(DisasContext *ctx, int reg_num_dst, TCGv t) |
55c2a12c MC |
193 | { |
194 | if (reg_num_dst != 0) { | |
195 | tcg_gen_mov_tl(cpu_gpr[reg_num_dst], t); | |
196 | } | |
197 | } | |
198 | ||
199 | static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2) | |
200 | { | |
201 | TCGv rl = tcg_temp_new(); | |
202 | TCGv rh = tcg_temp_new(); | |
203 | ||
204 | tcg_gen_mulu2_tl(rl, rh, arg1, arg2); | |
205 | /* fix up for one negative */ | |
206 | tcg_gen_sari_tl(rl, arg1, TARGET_LONG_BITS - 1); | |
207 | tcg_gen_and_tl(rl, rl, arg2); | |
208 | tcg_gen_sub_tl(ret, rh, rl); | |
209 | ||
210 | tcg_temp_free(rl); | |
211 | tcg_temp_free(rh); | |
212 | } | |
213 | ||
12887016 | 214 | static void gen_div(TCGv ret, TCGv source1, TCGv source2) |
55c2a12c | 215 | { |
4a083b56 RH |
216 | TCGv temp1, temp2, zero, one, mone, min; |
217 | ||
218 | temp1 = tcg_temp_new(); | |
219 | temp2 = tcg_temp_new(); | |
220 | zero = tcg_constant_tl(0); | |
221 | one = tcg_constant_tl(1); | |
222 | mone = tcg_constant_tl(-1); | |
223 | min = tcg_constant_tl(1ull << (TARGET_LONG_BITS - 1)); | |
224 | ||
225 | /* | |
226 | * If overflow, set temp2 to 1, else source2. | |
227 | * This produces the required result of min. | |
228 | */ | |
229 | tcg_gen_setcond_tl(TCG_COND_EQ, temp1, source1, min); | |
230 | tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, mone); | |
231 | tcg_gen_and_tl(temp1, temp1, temp2); | |
232 | tcg_gen_movcond_tl(TCG_COND_NE, temp2, temp1, zero, one, source2); | |
233 | ||
12887016 | 234 | /* |
4a083b56 RH |
235 | * If div by zero, set temp1 to -1 and temp2 to 1 to |
236 | * produce the required result of -1. | |
12887016 | 237 | */ |
4a083b56 RH |
238 | tcg_gen_movcond_tl(TCG_COND_EQ, temp1, source2, zero, mone, source1); |
239 | tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, temp2); | |
240 | ||
241 | tcg_gen_div_tl(ret, temp1, temp2); | |
242 | ||
243 | tcg_temp_free(temp1); | |
244 | tcg_temp_free(temp2); | |
12887016 | 245 | } |
55c2a12c | 246 | |
12887016 BK |
247 | static void gen_divu(TCGv ret, TCGv source1, TCGv source2) |
248 | { | |
4a083b56 RH |
249 | TCGv temp1, temp2, zero, one, max; |
250 | ||
251 | temp1 = tcg_temp_new(); | |
252 | temp2 = tcg_temp_new(); | |
253 | zero = tcg_constant_tl(0); | |
254 | one = tcg_constant_tl(1); | |
255 | max = tcg_constant_tl(~0); | |
256 | ||
257 | /* | |
258 | * If div by zero, set temp1 to max and temp2 to 1 to | |
259 | * produce the required result of max. | |
260 | */ | |
261 | tcg_gen_movcond_tl(TCG_COND_EQ, temp1, source2, zero, max, source1); | |
262 | tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, source2); | |
263 | tcg_gen_divu_tl(ret, temp1, temp2); | |
264 | ||
265 | tcg_temp_free(temp1); | |
266 | tcg_temp_free(temp2); | |
12887016 | 267 | } |
55c2a12c | 268 | |
12887016 BK |
269 | static void gen_rem(TCGv ret, TCGv source1, TCGv source2) |
270 | { | |
4a083b56 RH |
271 | TCGv temp1, temp2, zero, one, mone, min; |
272 | ||
273 | temp1 = tcg_temp_new(); | |
274 | temp2 = tcg_temp_new(); | |
275 | zero = tcg_constant_tl(0); | |
276 | one = tcg_constant_tl(1); | |
277 | mone = tcg_constant_tl(-1); | |
278 | min = tcg_constant_tl(1ull << (TARGET_LONG_BITS - 1)); | |
279 | ||
280 | /* | |
281 | * If overflow, set temp1 to 0, else source1. | |
282 | * This avoids a possible host trap, and produces the required result of 0. | |
283 | */ | |
284 | tcg_gen_setcond_tl(TCG_COND_EQ, temp1, source1, min); | |
285 | tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, mone); | |
286 | tcg_gen_and_tl(temp1, temp1, temp2); | |
287 | tcg_gen_movcond_tl(TCG_COND_NE, temp1, temp1, zero, zero, source1); | |
288 | ||
289 | /* | |
290 | * If div by zero, set temp2 to 1, else source2. | |
291 | * This avoids a possible host trap, but produces an incorrect result. | |
292 | */ | |
293 | tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, source2); | |
294 | ||
295 | tcg_gen_rem_tl(temp1, temp1, temp2); | |
296 | ||
297 | /* If div by zero, the required result is the original dividend. */ | |
298 | tcg_gen_movcond_tl(TCG_COND_EQ, ret, source2, zero, source1, temp1); | |
299 | ||
300 | tcg_temp_free(temp1); | |
301 | tcg_temp_free(temp2); | |
12887016 | 302 | } |
55c2a12c | 303 | |
12887016 BK |
304 | static void gen_remu(TCGv ret, TCGv source1, TCGv source2) |
305 | { | |
4a083b56 RH |
306 | TCGv temp, zero, one; |
307 | ||
308 | temp = tcg_temp_new(); | |
309 | zero = tcg_constant_tl(0); | |
310 | one = tcg_constant_tl(1); | |
311 | ||
312 | /* | |
313 | * If div by zero, set temp to 1, else source2. | |
314 | * This avoids a possible host trap, but produces an incorrect result. | |
315 | */ | |
316 | tcg_gen_movcond_tl(TCG_COND_EQ, temp, source2, zero, one, source2); | |
317 | ||
318 | tcg_gen_remu_tl(temp, source1, temp); | |
319 | ||
320 | /* If div by zero, the required result is the original dividend. */ | |
321 | tcg_gen_movcond_tl(TCG_COND_EQ, ret, source2, zero, source1, temp); | |
322 | ||
323 | tcg_temp_free(temp); | |
55c2a12c MC |
324 | } |
325 | ||
db9f3fd6 | 326 | static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) |
55c2a12c MC |
327 | { |
328 | target_ulong next_pc; | |
329 | ||
330 | /* check misaligned: */ | |
0114db1c | 331 | next_pc = ctx->base.pc_next + imm; |
db9f3fd6 | 332 | if (!has_ext(ctx, RVC)) { |
55c2a12c MC |
333 | if ((next_pc & 0x3) != 0) { |
334 | gen_exception_inst_addr_mis(ctx); | |
335 | return; | |
336 | } | |
337 | } | |
338 | if (rd != 0) { | |
0114db1c | 339 | tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn); |
55c2a12c MC |
340 | } |
341 | ||
0114db1c EC |
342 | gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */ |
343 | ctx->base.is_jmp = DISAS_NORETURN; | |
55c2a12c MC |
344 | } |
345 | ||
533b8f88 RH |
346 | #ifndef CONFIG_USER_ONLY |
347 | /* The states of mstatus_fs are: | |
348 | * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty | |
349 | * We will have already diagnosed disabled state, | |
350 | * and need to turn initial/clean into dirty. | |
351 | */ | |
352 | static void mark_fs_dirty(DisasContext *ctx) | |
353 | { | |
354 | TCGv tmp; | |
4fd7455b AF |
355 | target_ulong sd; |
356 | ||
533b8f88 RH |
357 | if (ctx->mstatus_fs == MSTATUS_FS) { |
358 | return; | |
359 | } | |
360 | /* Remember the state change for the rest of the TB. */ | |
361 | ctx->mstatus_fs = MSTATUS_FS; | |
362 | ||
363 | tmp = tcg_temp_new(); | |
4fd7455b AF |
364 | sd = is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD; |
365 | ||
533b8f88 | 366 | tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); |
4fd7455b | 367 | tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd); |
533b8f88 | 368 | tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); |
45b4dc8b AF |
369 | |
370 | if (ctx->virt_enabled) { | |
371 | tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); | |
4fd7455b | 372 | tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd); |
45b4dc8b AF |
373 | tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); |
374 | } | |
533b8f88 RH |
375 | tcg_temp_free(tmp); |
376 | } | |
377 | #else | |
378 | static inline void mark_fs_dirty(DisasContext *ctx) { } | |
379 | #endif | |
380 | ||
55c2a12c MC |
381 | static void gen_set_rm(DisasContext *ctx, int rm) |
382 | { | |
55c2a12c MC |
383 | if (ctx->frm == rm) { |
384 | return; | |
385 | } | |
386 | ctx->frm = rm; | |
05b80ed0 | 387 | gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); |
55c2a12c MC |
388 | } |
389 | ||
751538d5 LZ |
390 | static int ex_plus_1(DisasContext *ctx, int nf) |
391 | { | |
392 | return nf + 1; | |
393 | } | |
394 | ||
2a53cff4 | 395 | #define EX_SH(amount) \ |
451e4ffd | 396 | static int ex_shift_##amount(DisasContext *ctx, int imm) \ |
2a53cff4 BK |
397 | { \ |
398 | return imm << amount; \ | |
399 | } | |
3cca75a6 | 400 | EX_SH(1) |
e98d9140 BK |
401 | EX_SH(2) |
402 | EX_SH(3) | |
07b001c6 | 403 | EX_SH(4) |
2a53cff4 BK |
404 | EX_SH(12) |
405 | ||
d2e2c1e4 BK |
406 | #define REQUIRE_EXT(ctx, ext) do { \ |
407 | if (!has_ext(ctx, ext)) { \ | |
408 | return false; \ | |
409 | } \ | |
410 | } while (0) | |
411 | ||
daf866b6 AF |
412 | #define REQUIRE_64BIT(ctx) do { \ |
413 | if (is_32bit(ctx)) { \ | |
414 | return false; \ | |
415 | } \ | |
416 | } while (0) | |
417 | ||
451e4ffd | 418 | static int ex_rvc_register(DisasContext *ctx, int reg) |
e98d9140 BK |
419 | { |
420 | return 8 + reg; | |
421 | } | |
422 | ||
6cafec92 RH |
423 | static int ex_rvc_shifti(DisasContext *ctx, int imm) |
424 | { | |
425 | /* For RV128 a shamt of 0 means a shift by 64. */ | |
426 | return imm ? imm : 64; | |
427 | } | |
428 | ||
2a53cff4 | 429 | /* Include the auto-generated decoder for 32 bit insn */ |
abff1abf | 430 | #include "decode-insn32.c.inc" |
7a50d3e2 | 431 | |
598aa116 RH |
432 | static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, |
433 | void (*func)(TCGv, TCGv, target_long)) | |
434 | { | |
435 | TCGv source1; | |
436 | source1 = tcg_temp_new(); | |
437 | ||
867c8196 | 438 | gen_get_gpr(ctx, source1, a->rs1); |
598aa116 RH |
439 | |
440 | (*func)(source1, source1, a->imm); | |
441 | ||
867c8196 | 442 | gen_set_gpr(ctx, a->rd, source1); |
598aa116 RH |
443 | tcg_temp_free(source1); |
444 | return true; | |
445 | } | |
446 | ||
447 | static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, | |
448 | void (*func)(TCGv, TCGv, TCGv)) | |
7a50d3e2 BK |
449 | { |
450 | TCGv source1, source2; | |
451 | source1 = tcg_temp_new(); | |
452 | source2 = tcg_temp_new(); | |
453 | ||
867c8196 | 454 | gen_get_gpr(ctx, source1, a->rs1); |
7a50d3e2 BK |
455 | tcg_gen_movi_tl(source2, a->imm); |
456 | ||
457 | (*func)(source1, source1, source2); | |
458 | ||
867c8196 | 459 | gen_set_gpr(ctx, a->rd, source1); |
7a50d3e2 BK |
460 | tcg_temp_free(source1); |
461 | tcg_temp_free(source2); | |
462 | return true; | |
463 | } | |
464 | ||
7a50d3e2 BK |
465 | static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2) |
466 | { | |
467 | tcg_gen_add_tl(ret, arg1, arg2); | |
468 | tcg_gen_ext32s_tl(ret, ret); | |
469 | } | |
f2ab1728 BK |
470 | |
471 | static void gen_subw(TCGv ret, TCGv arg1, TCGv arg2) | |
472 | { | |
473 | tcg_gen_sub_tl(ret, arg1, arg2); | |
474 | tcg_gen_ext32s_tl(ret, ret); | |
475 | } | |
476 | ||
12887016 BK |
477 | static void gen_mulw(TCGv ret, TCGv arg1, TCGv arg2) |
478 | { | |
479 | tcg_gen_mul_tl(ret, arg1, arg2); | |
480 | tcg_gen_ext32s_tl(ret, ret); | |
481 | } | |
482 | ||
483 | static bool gen_arith_div_w(DisasContext *ctx, arg_r *a, | |
484 | void(*func)(TCGv, TCGv, TCGv)) | |
485 | { | |
486 | TCGv source1, source2; | |
487 | source1 = tcg_temp_new(); | |
488 | source2 = tcg_temp_new(); | |
489 | ||
867c8196 RH |
490 | gen_get_gpr(ctx, source1, a->rs1); |
491 | gen_get_gpr(ctx, source2, a->rs2); | |
12887016 BK |
492 | tcg_gen_ext32s_tl(source1, source1); |
493 | tcg_gen_ext32s_tl(source2, source2); | |
494 | ||
495 | (*func)(source1, source1, source2); | |
496 | ||
497 | tcg_gen_ext32s_tl(source1, source1); | |
867c8196 | 498 | gen_set_gpr(ctx, a->rd, source1); |
12887016 BK |
499 | tcg_temp_free(source1); |
500 | tcg_temp_free(source2); | |
501 | return true; | |
502 | } | |
503 | ||
f17e02cd PD |
504 | static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a, |
505 | void(*func)(TCGv, TCGv, TCGv)) | |
506 | { | |
507 | TCGv source1, source2; | |
508 | source1 = tcg_temp_new(); | |
509 | source2 = tcg_temp_new(); | |
510 | ||
867c8196 RH |
511 | gen_get_gpr(ctx, source1, a->rs1); |
512 | gen_get_gpr(ctx, source2, a->rs2); | |
f17e02cd PD |
513 | tcg_gen_ext32u_tl(source1, source1); |
514 | tcg_gen_ext32u_tl(source2, source2); | |
515 | ||
516 | (*func)(source1, source1, source2); | |
517 | ||
518 | tcg_gen_ext32s_tl(source1, source1); | |
867c8196 | 519 | gen_set_gpr(ctx, a->rd, source1); |
f17e02cd PD |
520 | tcg_temp_free(source1); |
521 | tcg_temp_free(source2); | |
522 | return true; | |
523 | } | |
524 | ||
6ef58431 KC |
525 | static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2) |
526 | { | |
527 | tcg_gen_deposit_tl(ret, arg1, arg2, | |
528 | TARGET_LONG_BITS / 2, | |
529 | TARGET_LONG_BITS / 2); | |
530 | } | |
531 | ||
532 | static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2) | |
533 | { | |
534 | TCGv t = tcg_temp_new(); | |
535 | tcg_gen_shri_tl(t, arg1, TARGET_LONG_BITS / 2); | |
536 | tcg_gen_deposit_tl(ret, arg2, t, 0, TARGET_LONG_BITS / 2); | |
537 | tcg_temp_free(t); | |
538 | } | |
539 | ||
540 | static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2) | |
541 | { | |
542 | TCGv t = tcg_temp_new(); | |
543 | tcg_gen_ext8u_tl(t, arg2); | |
544 | tcg_gen_deposit_tl(ret, arg1, t, 8, TARGET_LONG_BITS - 8); | |
545 | tcg_temp_free(t); | |
546 | } | |
547 | ||
23cd1777 FC |
548 | static void gen_sbop_mask(TCGv ret, TCGv shamt) |
549 | { | |
550 | tcg_gen_movi_tl(ret, 1); | |
551 | tcg_gen_shl_tl(ret, ret, shamt); | |
552 | } | |
553 | ||
554 | static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt) | |
555 | { | |
556 | TCGv t = tcg_temp_new(); | |
557 | ||
558 | gen_sbop_mask(t, shamt); | |
559 | tcg_gen_or_tl(ret, arg1, t); | |
560 | ||
561 | tcg_temp_free(t); | |
562 | } | |
563 | ||
564 | static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt) | |
565 | { | |
566 | TCGv t = tcg_temp_new(); | |
567 | ||
568 | gen_sbop_mask(t, shamt); | |
569 | tcg_gen_andc_tl(ret, arg1, t); | |
570 | ||
571 | tcg_temp_free(t); | |
572 | } | |
573 | ||
574 | static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt) | |
575 | { | |
576 | TCGv t = tcg_temp_new(); | |
577 | ||
578 | gen_sbop_mask(t, shamt); | |
579 | tcg_gen_xor_tl(ret, arg1, t); | |
580 | ||
581 | tcg_temp_free(t); | |
582 | } | |
583 | ||
584 | static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt) | |
585 | { | |
586 | tcg_gen_shr_tl(ret, arg1, shamt); | |
587 | tcg_gen_andi_tl(ret, ret, 1); | |
588 | } | |
589 | ||
91d8fc67 KC |
590 | static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2) |
591 | { | |
592 | tcg_gen_not_tl(ret, arg1); | |
593 | tcg_gen_shl_tl(ret, ret, arg2); | |
594 | tcg_gen_not_tl(ret, ret); | |
595 | } | |
596 | ||
597 | static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2) | |
598 | { | |
599 | tcg_gen_not_tl(ret, arg1); | |
600 | tcg_gen_shr_tl(ret, ret, arg2); | |
601 | tcg_gen_not_tl(ret, ret); | |
602 | } | |
603 | ||
831ec7f3 FC |
604 | static bool gen_grevi(DisasContext *ctx, arg_grevi *a) |
605 | { | |
606 | TCGv source1 = tcg_temp_new(); | |
607 | TCGv source2; | |
608 | ||
867c8196 | 609 | gen_get_gpr(ctx, source1, a->rs1); |
831ec7f3 FC |
610 | |
611 | if (a->shamt == (TARGET_LONG_BITS - 8)) { | |
612 | /* rev8, byte swaps */ | |
613 | tcg_gen_bswap_tl(source1, source1); | |
614 | } else { | |
615 | source2 = tcg_temp_new(); | |
616 | tcg_gen_movi_tl(source2, a->shamt); | |
617 | gen_helper_grev(source1, source1, source2); | |
618 | tcg_temp_free(source2); | |
619 | } | |
620 | ||
867c8196 | 621 | gen_set_gpr(ctx, a->rd, source1); |
831ec7f3 FC |
622 | tcg_temp_free(source1); |
623 | return true; | |
624 | } | |
625 | ||
920a1f99 KC |
626 | #define GEN_SHADD(SHAMT) \ |
627 | static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \ | |
628 | { \ | |
629 | TCGv t = tcg_temp_new(); \ | |
630 | \ | |
631 | tcg_gen_shli_tl(t, arg1, SHAMT); \ | |
632 | tcg_gen_add_tl(ret, t, arg2); \ | |
633 | \ | |
634 | tcg_temp_free(t); \ | |
635 | } | |
636 | ||
637 | GEN_SHADD(1) | |
638 | GEN_SHADD(2) | |
639 | GEN_SHADD(3) | |
640 | ||
43824018 KC |
641 | static void gen_ctzw(TCGv ret, TCGv arg1) |
642 | { | |
643 | tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32)); | |
644 | tcg_gen_ctzi_tl(ret, ret, 64); | |
645 | } | |
646 | ||
647 | static void gen_clzw(TCGv ret, TCGv arg1) | |
648 | { | |
649 | tcg_gen_ext32u_tl(ret, arg1); | |
650 | tcg_gen_clzi_tl(ret, ret, 64); | |
651 | tcg_gen_subi_tl(ret, ret, 32); | |
652 | } | |
653 | ||
1e16310c FC |
654 | static void gen_cpopw(TCGv ret, TCGv arg1) |
655 | { | |
656 | tcg_gen_ext32u_tl(arg1, arg1); | |
657 | tcg_gen_ctpop_tl(ret, arg1); | |
658 | } | |
659 | ||
6ef58431 KC |
660 | static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2) |
661 | { | |
662 | TCGv t = tcg_temp_new(); | |
663 | tcg_gen_ext16s_tl(t, arg2); | |
664 | tcg_gen_deposit_tl(ret, arg1, t, 16, 48); | |
665 | tcg_temp_free(t); | |
666 | } | |
667 | ||
668 | static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2) | |
669 | { | |
670 | TCGv t = tcg_temp_new(); | |
671 | tcg_gen_shri_tl(t, arg1, 16); | |
672 | tcg_gen_deposit_tl(ret, arg2, t, 0, 16); | |
673 | tcg_gen_ext32s_tl(ret, ret); | |
674 | tcg_temp_free(t); | |
675 | } | |
676 | ||
e58529a8 KC |
677 | static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2) |
678 | { | |
679 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
680 | TCGv_i32 t2 = tcg_temp_new_i32(); | |
681 | ||
682 | /* truncate to 32-bits */ | |
683 | tcg_gen_trunc_tl_i32(t1, arg1); | |
684 | tcg_gen_trunc_tl_i32(t2, arg2); | |
685 | ||
686 | tcg_gen_rotr_i32(t1, t1, t2); | |
687 | ||
688 | /* sign-extend 64-bits */ | |
689 | tcg_gen_ext_i32_tl(ret, t1); | |
690 | ||
691 | tcg_temp_free_i32(t1); | |
692 | tcg_temp_free_i32(t2); | |
693 | } | |
694 | ||
695 | static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2) | |
696 | { | |
697 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
698 | TCGv_i32 t2 = tcg_temp_new_i32(); | |
699 | ||
700 | /* truncate to 32-bits */ | |
701 | tcg_gen_trunc_tl_i32(t1, arg1); | |
702 | tcg_gen_trunc_tl_i32(t2, arg2); | |
703 | ||
704 | tcg_gen_rotl_i32(t1, t1, t2); | |
705 | ||
706 | /* sign-extend 64-bits */ | |
707 | tcg_gen_ext_i32_tl(ret, t1); | |
708 | ||
709 | tcg_temp_free_i32(t1); | |
710 | tcg_temp_free_i32(t2); | |
711 | } | |
712 | ||
831ec7f3 FC |
713 | static void gen_grevw(TCGv ret, TCGv arg1, TCGv arg2) |
714 | { | |
715 | tcg_gen_ext32u_tl(arg1, arg1); | |
716 | gen_helper_grev(ret, arg1, arg2); | |
717 | } | |
718 | ||
c24f0422 FC |
719 | static void gen_gorcw(TCGv ret, TCGv arg1, TCGv arg2) |
720 | { | |
721 | tcg_gen_ext32u_tl(arg1, arg1); | |
722 | gen_helper_gorcw(ret, arg1, arg2); | |
723 | } | |
724 | ||
920a1f99 KC |
725 | #define GEN_SHADD_UW(SHAMT) \ |
726 | static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \ | |
727 | { \ | |
728 | TCGv t = tcg_temp_new(); \ | |
729 | \ | |
730 | tcg_gen_ext32u_tl(t, arg1); \ | |
731 | \ | |
732 | tcg_gen_shli_tl(t, t, SHAMT); \ | |
733 | tcg_gen_add_tl(ret, t, arg2); \ | |
734 | \ | |
735 | tcg_temp_free(t); \ | |
736 | } | |
737 | ||
738 | GEN_SHADD_UW(1) | |
739 | GEN_SHADD_UW(2) | |
740 | GEN_SHADD_UW(3) | |
741 | ||
3a4a43e4 KC |
742 | static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2) |
743 | { | |
744 | tcg_gen_ext32u_tl(arg1, arg1); | |
745 | tcg_gen_add_tl(ret, arg1, arg2); | |
746 | } | |
747 | ||
8dc9e8a8 BK |
748 | static bool gen_arith(DisasContext *ctx, arg_r *a, |
749 | void(*func)(TCGv, TCGv, TCGv)) | |
f2ab1728 BK |
750 | { |
751 | TCGv source1, source2; | |
752 | source1 = tcg_temp_new(); | |
753 | source2 = tcg_temp_new(); | |
754 | ||
867c8196 RH |
755 | gen_get_gpr(ctx, source1, a->rs1); |
756 | gen_get_gpr(ctx, source2, a->rs2); | |
f2ab1728 BK |
757 | |
758 | (*func)(source1, source1, source2); | |
759 | ||
867c8196 | 760 | gen_set_gpr(ctx, a->rd, source1); |
f2ab1728 BK |
761 | tcg_temp_free(source1); |
762 | tcg_temp_free(source2); | |
763 | return true; | |
764 | } | |
765 | ||
34446e84 BK |
766 | static bool gen_shift(DisasContext *ctx, arg_r *a, |
767 | void(*func)(TCGv, TCGv, TCGv)) | |
768 | { | |
769 | TCGv source1 = tcg_temp_new(); | |
770 | TCGv source2 = tcg_temp_new(); | |
771 | ||
867c8196 RH |
772 | gen_get_gpr(ctx, source1, a->rs1); |
773 | gen_get_gpr(ctx, source2, a->rs2); | |
34446e84 BK |
774 | |
775 | tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1); | |
776 | (*func)(source1, source1, source2); | |
777 | ||
867c8196 | 778 | gen_set_gpr(ctx, a->rd, source1); |
34446e84 BK |
779 | tcg_temp_free(source1); |
780 | tcg_temp_free(source2); | |
781 | return true; | |
782 | } | |
783 | ||
a10b9d93 KP |
784 | static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) |
785 | { | |
786 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
787 | CPUState *cpu = ctx->cs; | |
788 | CPURISCVState *env = cpu->env_ptr; | |
789 | ||
790 | return cpu_ldl_code(env, pc); | |
791 | } | |
792 | ||
981d3568 FC |
793 | static bool gen_shifti(DisasContext *ctx, arg_shift *a, |
794 | void(*func)(TCGv, TCGv, TCGv)) | |
795 | { | |
796 | if (a->shamt >= TARGET_LONG_BITS) { | |
797 | return false; | |
798 | } | |
799 | ||
800 | TCGv source1 = tcg_temp_new(); | |
801 | TCGv source2 = tcg_temp_new(); | |
802 | ||
867c8196 | 803 | gen_get_gpr(ctx, source1, a->rs1); |
981d3568 FC |
804 | |
805 | tcg_gen_movi_tl(source2, a->shamt); | |
806 | (*func)(source1, source1, source2); | |
807 | ||
867c8196 | 808 | gen_set_gpr(ctx, a->rd, source1); |
981d3568 FC |
809 | tcg_temp_free(source1); |
810 | tcg_temp_free(source2); | |
811 | return true; | |
812 | } | |
813 | ||
23cd1777 FC |
814 | static bool gen_shiftw(DisasContext *ctx, arg_r *a, |
815 | void(*func)(TCGv, TCGv, TCGv)) | |
816 | { | |
817 | TCGv source1 = tcg_temp_new(); | |
818 | TCGv source2 = tcg_temp_new(); | |
819 | ||
867c8196 RH |
820 | gen_get_gpr(ctx, source1, a->rs1); |
821 | gen_get_gpr(ctx, source2, a->rs2); | |
23cd1777 FC |
822 | |
823 | tcg_gen_andi_tl(source2, source2, 31); | |
824 | (*func)(source1, source1, source2); | |
825 | tcg_gen_ext32s_tl(source1, source1); | |
826 | ||
867c8196 | 827 | gen_set_gpr(ctx, a->rd, source1); |
23cd1777 FC |
828 | tcg_temp_free(source1); |
829 | tcg_temp_free(source2); | |
830 | return true; | |
831 | } | |
832 | ||
981d3568 FC |
833 | static bool gen_shiftiw(DisasContext *ctx, arg_shift *a, |
834 | void(*func)(TCGv, TCGv, TCGv)) | |
835 | { | |
836 | TCGv source1 = tcg_temp_new(); | |
837 | TCGv source2 = tcg_temp_new(); | |
838 | ||
867c8196 | 839 | gen_get_gpr(ctx, source1, a->rs1); |
981d3568 FC |
840 | tcg_gen_movi_tl(source2, a->shamt); |
841 | ||
842 | (*func)(source1, source1, source2); | |
843 | tcg_gen_ext32s_tl(source1, source1); | |
844 | ||
867c8196 | 845 | gen_set_gpr(ctx, a->rd, source1); |
981d3568 FC |
846 | tcg_temp_free(source1); |
847 | tcg_temp_free(source2); | |
848 | return true; | |
849 | } | |
850 | ||
43824018 KC |
851 | static void gen_ctz(TCGv ret, TCGv arg1) |
852 | { | |
853 | tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS); | |
854 | } | |
855 | ||
856 | static void gen_clz(TCGv ret, TCGv arg1) | |
857 | { | |
858 | tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS); | |
859 | } | |
860 | ||
861 | static bool gen_unary(DisasContext *ctx, arg_r2 *a, | |
862 | void(*func)(TCGv, TCGv)) | |
863 | { | |
864 | TCGv source = tcg_temp_new(); | |
865 | ||
867c8196 | 866 | gen_get_gpr(ctx, source, a->rs1); |
43824018 KC |
867 | |
868 | (*func)(source, source); | |
869 | ||
867c8196 | 870 | gen_set_gpr(ctx, a->rd, source); |
43824018 KC |
871 | tcg_temp_free(source); |
872 | return true; | |
873 | } | |
874 | ||
2a53cff4 | 875 | /* Include insn module translation function */ |
139c1837 PB |
876 | #include "insn_trans/trans_rvi.c.inc" |
877 | #include "insn_trans/trans_rvm.c.inc" | |
878 | #include "insn_trans/trans_rva.c.inc" | |
879 | #include "insn_trans/trans_rvf.c.inc" | |
880 | #include "insn_trans/trans_rvd.c.inc" | |
881 | #include "insn_trans/trans_rvh.c.inc" | |
882 | #include "insn_trans/trans_rvv.c.inc" | |
43824018 | 883 | #include "insn_trans/trans_rvb.c.inc" |
139c1837 | 884 | #include "insn_trans/trans_privileged.c.inc" |
2a53cff4 | 885 | |
59a3a1c0 | 886 | /* Include the auto-generated decoder for 16 bit insn */ |
abff1abf | 887 | #include "decode-insn16.c.inc" |
e98d9140 | 888 | |
25139bf7 | 889 | static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) |
55c2a12c MC |
890 | { |
891 | /* check for compressed insn */ | |
25139bf7 | 892 | if (extract16(opcode, 0, 2) != 3) { |
db9f3fd6 | 893 | if (!has_ext(ctx, RVC)) { |
55c2a12c MC |
894 | gen_exception_illegal(ctx); |
895 | } else { | |
0114db1c | 896 | ctx->pc_succ_insn = ctx->base.pc_next + 2; |
25139bf7 | 897 | if (!decode_insn16(ctx, opcode)) { |
9a27f69b | 898 | gen_exception_illegal(ctx); |
e98d9140 | 899 | } |
55c2a12c MC |
900 | } |
901 | } else { | |
25139bf7 AB |
902 | uint32_t opcode32 = opcode; |
903 | opcode32 = deposit32(opcode32, 16, 16, | |
904 | translator_lduw(env, ctx->base.pc_next + 2)); | |
0114db1c | 905 | ctx->pc_succ_insn = ctx->base.pc_next + 4; |
25139bf7 | 906 | if (!decode_insn32(ctx, opcode32)) { |
25e6ca30 | 907 | gen_exception_illegal(ctx); |
2a53cff4 | 908 | } |
55c2a12c MC |
909 | } |
910 | } | |
911 | ||
5b4f1d2d | 912 | static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) |
55c2a12c | 913 | { |
5b4f1d2d | 914 | DisasContext *ctx = container_of(dcbase, DisasContext, base); |
d75377bf | 915 | CPURISCVState *env = cs->env_ptr; |
50fba816 | 916 | RISCVCPU *cpu = RISCV_CPU(cs); |
2b7168fc | 917 | uint32_t tb_flags = ctx->base.tb->flags; |
55c2a12c | 918 | |
5b4f1d2d | 919 | ctx->pc_succ_insn = ctx->base.pc_first; |
2b7168fc LZ |
920 | ctx->mem_idx = tb_flags & TB_FLAGS_MMU_MASK; |
921 | ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS; | |
d75377bf | 922 | ctx->priv_ver = env->priv_ver; |
45b4dc8b | 923 | #if !defined(CONFIG_USER_ONLY) |
ae84dd0a AF |
924 | if (riscv_has_ext(env, RVH)) { |
925 | ctx->virt_enabled = riscv_cpu_virt_enabled(env); | |
ae84dd0a AF |
926 | } else { |
927 | ctx->virt_enabled = false; | |
928 | } | |
45b4dc8b AF |
929 | #else |
930 | ctx->virt_enabled = false; | |
931 | #endif | |
db9f3fd6 | 932 | ctx->misa = env->misa; |
5b4f1d2d | 933 | ctx->frm = -1; /* unknown rounding mode */ |
50fba816 | 934 | ctx->ext_ifencei = cpu->cfg.ext_ifencei; |
2b7168fc | 935 | ctx->vlen = cpu->cfg.vlen; |
743077b3 | 936 | ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); |
2b7168fc LZ |
937 | ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); |
938 | ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); | |
939 | ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL); | |
751538d5 | 940 | ctx->mlen = 1 << (ctx->sew + 3 - ctx->lmul); |
2b7168fc | 941 | ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); |
a10b9d93 | 942 | ctx->cs = cs; |
5b4f1d2d | 943 | } |
55c2a12c | 944 | |
5b4f1d2d EC |
945 | static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) |
946 | { | |
947 | } | |
55c2a12c | 948 | |
5b4f1d2d EC |
949 | static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) |
950 | { | |
951 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
952 | ||
953 | tcg_gen_insn_start(ctx->base.pc_next); | |
954 | } | |
955 | ||
5b4f1d2d EC |
956 | static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) |
957 | { | |
958 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
959 | CPURISCVState *env = cpu->env_ptr; | |
25139bf7 | 960 | uint16_t opcode16 = translator_lduw(env, ctx->base.pc_next); |
55c2a12c | 961 | |
25139bf7 | 962 | decode_opc(env, ctx, opcode16); |
5b4f1d2d EC |
963 | ctx->base.pc_next = ctx->pc_succ_insn; |
964 | ||
965 | if (ctx->base.is_jmp == DISAS_NEXT) { | |
966 | target_ulong page_start; | |
967 | ||
968 | page_start = ctx->base.pc_first & TARGET_PAGE_MASK; | |
969 | if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) { | |
970 | ctx->base.is_jmp = DISAS_TOO_MANY; | |
55c2a12c | 971 | } |
55c2a12c | 972 | } |
5b4f1d2d EC |
973 | } |
974 | ||
975 | static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) | |
976 | { | |
977 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
978 | ||
979 | switch (ctx->base.is_jmp) { | |
b2e32021 | 980 | case DISAS_TOO_MANY: |
ccf08e40 | 981 | gen_goto_tb(ctx, 0, ctx->base.pc_next); |
55c2a12c | 982 | break; |
b2e32021 | 983 | case DISAS_NORETURN: |
55c2a12c | 984 | break; |
b2e32021 EC |
985 | default: |
986 | g_assert_not_reached(); | |
55c2a12c | 987 | } |
5b4f1d2d EC |
988 | } |
989 | ||
990 | static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) | |
991 | { | |
35f69039 AF |
992 | #ifndef CONFIG_USER_ONLY |
993 | RISCVCPU *rvcpu = RISCV_CPU(cpu); | |
994 | CPURISCVState *env = &rvcpu->env; | |
995 | #endif | |
996 | ||
5b4f1d2d | 997 | qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); |
35f69039 AF |
998 | #ifndef CONFIG_USER_ONLY |
999 | qemu_log("Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", env->priv, env->virt); | |
1000 | #endif | |
5b4f1d2d EC |
1001 | log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); |
1002 | } | |
1003 | ||
1004 | static const TranslatorOps riscv_tr_ops = { | |
1005 | .init_disas_context = riscv_tr_init_disas_context, | |
1006 | .tb_start = riscv_tr_tb_start, | |
1007 | .insn_start = riscv_tr_insn_start, | |
5b4f1d2d EC |
1008 | .translate_insn = riscv_tr_translate_insn, |
1009 | .tb_stop = riscv_tr_tb_stop, | |
1010 | .disas_log = riscv_tr_disas_log, | |
1011 | }; | |
1012 | ||
8b86d6d2 | 1013 | void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) |
5b4f1d2d EC |
1014 | { |
1015 | DisasContext ctx; | |
1016 | ||
8b86d6d2 | 1017 | translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns); |
55c2a12c MC |
1018 | } |
1019 | ||
1020 | void riscv_translate_init(void) | |
1021 | { | |
1022 | int i; | |
1023 | ||
1024 | /* cpu_gpr[0] is a placeholder for the zero register. Do not use it. */ | |
1025 | /* Use the gen_set_gpr and gen_get_gpr helper functions when accessing */ | |
1026 | /* registers, unless you specifically block reads/writes to reg 0 */ | |
1027 | cpu_gpr[0] = NULL; | |
1028 | ||
1029 | for (i = 1; i < 32; i++) { | |
1030 | cpu_gpr[i] = tcg_global_mem_new(cpu_env, | |
1031 | offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); | |
1032 | } | |
1033 | ||
1034 | for (i = 0; i < 32; i++) { | |
1035 | cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, | |
1036 | offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); | |
1037 | } | |
1038 | ||
1039 | cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); | |
ad9e5aa2 | 1040 | cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl"); |
55c2a12c MC |
1041 | load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), |
1042 | "load_res"); | |
1043 | load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), | |
1044 | "load_val"); | |
1045 | } |