]>
Commit | Line | Data |
---|---|---|
55c2a12c MC |
1 | /* |
2 | * RISC-V emulation for qemu: main translation routines. | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2 or later, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along with | |
16 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | ||
19 | #include "qemu/osdep.h" | |
20 | #include "qemu/log.h" | |
21 | #include "cpu.h" | |
dcb32f1d | 22 | #include "tcg/tcg-op.h" |
55c2a12c MC |
23 | #include "disas/disas.h" |
24 | #include "exec/cpu_ldst.h" | |
25 | #include "exec/exec-all.h" | |
26 | #include "exec/helper-proto.h" | |
27 | #include "exec/helper-gen.h" | |
28 | ||
b2e32021 | 29 | #include "exec/translator.h" |
55c2a12c MC |
30 | #include "exec/log.h" |
31 | ||
32 | #include "instmap.h" | |
33 | ||
34 | /* global register indices */ | |
ad9e5aa2 | 35 | static TCGv cpu_gpr[32], cpu_pc, cpu_vl; |
55c2a12c MC |
36 | static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ |
37 | static TCGv load_res; | |
38 | static TCGv load_val; | |
39 | ||
40 | #include "exec/gen-icount.h" | |
41 | ||
42 | typedef struct DisasContext { | |
0114db1c EC |
43 | DisasContextBase base; |
44 | /* pc_succ_insn points to the instruction following base.pc_next */ | |
45 | target_ulong pc_succ_insn; | |
d75377bf | 46 | target_ulong priv_ver; |
45b4dc8b AF |
47 | bool virt_enabled; |
48 | uint32_t opcode; | |
83a71719 | 49 | uint32_t mstatus_fs; |
db9f3fd6 | 50 | uint32_t misa; |
55c2a12c | 51 | uint32_t mem_idx; |
55c2a12c MC |
52 | /* Remember the rounding mode encoded in the previous fp instruction, |
53 | which we have already installed into env->fp_status. Or -1 for | |
54 | no previous fp instruction. Note that we exit the TB when writing | |
55 | to any system register, which includes CSR_FRM, so we do not have | |
56 | to reset this known value. */ | |
57 | int frm; | |
50fba816 | 58 | bool ext_ifencei; |
743077b3 | 59 | bool hlsx; |
2b7168fc LZ |
60 | /* vector extension */ |
61 | bool vill; | |
62 | uint8_t lmul; | |
63 | uint8_t sew; | |
64 | uint16_t vlen; | |
751538d5 | 65 | uint16_t mlen; |
2b7168fc | 66 | bool vl_eq_vlmax; |
a10b9d93 | 67 | CPUState *cs; |
55c2a12c MC |
68 | } DisasContext; |
69 | ||
55c2a12c MC |
70 | #ifdef TARGET_RISCV64 |
71 | #define CASE_OP_32_64(X) case X: case glue(X, W) | |
72 | #else | |
73 | #define CASE_OP_32_64(X) case X | |
74 | #endif | |
75 | ||
db9f3fd6 MC |
76 | static inline bool has_ext(DisasContext *ctx, uint32_t ext) |
77 | { | |
78 | return ctx->misa & ext; | |
d36a86d0 RH |
79 | } |
80 | ||
81 | /* | |
82 | * RISC-V requires NaN-boxing of narrower width floating point values. | |
83 | * This applies when a 32-bit value is assigned to a 64-bit FP register. | |
84 | * For consistency and simplicity, we nanbox results even when the RVD | |
85 | * extension is not present. | |
86 | */ | |
87 | static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) | |
88 | { | |
89 | tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); | |
ffe70e4d RH |
90 | } |
91 | ||
92 | /* | |
93 | * A narrow n-bit operation, where n < FLEN, checks that input operands | |
94 | * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. | |
95 | * If so, the least-significant bits of the input are used, otherwise the | |
96 | * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). | |
97 | * | |
98 | * Here, the result is always nan-boxed, even the canonical nan. | |
99 | */ | |
100 | static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) | |
101 | { | |
102 | TCGv_i64 t_max = tcg_const_i64(0xffffffff00000000ull); | |
103 | TCGv_i64 t_nan = tcg_const_i64(0xffffffff7fc00000ull); | |
104 | ||
105 | tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); | |
106 | tcg_temp_free_i64(t_max); | |
107 | tcg_temp_free_i64(t_nan); | |
db9f3fd6 MC |
108 | } |
109 | ||
55c2a12c MC |
110 | static void generate_exception(DisasContext *ctx, int excp) |
111 | { | |
0114db1c | 112 | tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); |
55c2a12c MC |
113 | TCGv_i32 helper_tmp = tcg_const_i32(excp); |
114 | gen_helper_raise_exception(cpu_env, helper_tmp); | |
115 | tcg_temp_free_i32(helper_tmp); | |
0114db1c | 116 | ctx->base.is_jmp = DISAS_NORETURN; |
55c2a12c MC |
117 | } |
118 | ||
119 | static void generate_exception_mbadaddr(DisasContext *ctx, int excp) | |
120 | { | |
0114db1c | 121 | tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); |
55c2a12c MC |
122 | tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); |
123 | TCGv_i32 helper_tmp = tcg_const_i32(excp); | |
124 | gen_helper_raise_exception(cpu_env, helper_tmp); | |
125 | tcg_temp_free_i32(helper_tmp); | |
0114db1c | 126 | ctx->base.is_jmp = DISAS_NORETURN; |
55c2a12c MC |
127 | } |
128 | ||
129 | static void gen_exception_debug(void) | |
130 | { | |
131 | TCGv_i32 helper_tmp = tcg_const_i32(EXCP_DEBUG); | |
132 | gen_helper_raise_exception(cpu_env, helper_tmp); | |
133 | tcg_temp_free_i32(helper_tmp); | |
134 | } | |
135 | ||
6e2716d8 FC |
136 | /* Wrapper around tcg_gen_exit_tb that handles single stepping */ |
137 | static void exit_tb(DisasContext *ctx) | |
138 | { | |
139 | if (ctx->base.singlestep_enabled) { | |
140 | gen_exception_debug(); | |
141 | } else { | |
142 | tcg_gen_exit_tb(NULL, 0); | |
143 | } | |
144 | } | |
145 | ||
146 | /* Wrapper around tcg_gen_lookup_and_goto_ptr that handles single stepping */ | |
147 | static void lookup_and_goto_ptr(DisasContext *ctx) | |
148 | { | |
149 | if (ctx->base.singlestep_enabled) { | |
150 | gen_exception_debug(); | |
151 | } else { | |
152 | tcg_gen_lookup_and_goto_ptr(); | |
153 | } | |
154 | } | |
155 | ||
55c2a12c MC |
156 | static void gen_exception_illegal(DisasContext *ctx) |
157 | { | |
158 | generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); | |
159 | } | |
160 | ||
161 | static void gen_exception_inst_addr_mis(DisasContext *ctx) | |
162 | { | |
163 | generate_exception_mbadaddr(ctx, RISCV_EXCP_INST_ADDR_MIS); | |
164 | } | |
165 | ||
166 | static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) | |
167 | { | |
0114db1c | 168 | if (unlikely(ctx->base.singlestep_enabled)) { |
55c2a12c MC |
169 | return false; |
170 | } | |
171 | ||
172 | #ifndef CONFIG_USER_ONLY | |
0114db1c | 173 | return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); |
55c2a12c MC |
174 | #else |
175 | return true; | |
176 | #endif | |
177 | } | |
178 | ||
179 | static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) | |
180 | { | |
181 | if (use_goto_tb(ctx, dest)) { | |
182 | /* chaining is only allowed when the jump is to the same page */ | |
183 | tcg_gen_goto_tb(n); | |
184 | tcg_gen_movi_tl(cpu_pc, dest); | |
6e2716d8 FC |
185 | |
186 | /* No need to check for single stepping here as use_goto_tb() will | |
187 | * return false in case of single stepping. | |
188 | */ | |
07ea28b4 | 189 | tcg_gen_exit_tb(ctx->base.tb, n); |
55c2a12c MC |
190 | } else { |
191 | tcg_gen_movi_tl(cpu_pc, dest); | |
6e2716d8 | 192 | lookup_and_goto_ptr(ctx); |
55c2a12c MC |
193 | } |
194 | } | |
195 | ||
196 | /* Wrapper for getting reg values - need to check of reg is zero since | |
197 | * cpu_gpr[0] is not actually allocated | |
198 | */ | |
199 | static inline void gen_get_gpr(TCGv t, int reg_num) | |
200 | { | |
201 | if (reg_num == 0) { | |
202 | tcg_gen_movi_tl(t, 0); | |
203 | } else { | |
204 | tcg_gen_mov_tl(t, cpu_gpr[reg_num]); | |
205 | } | |
206 | } | |
207 | ||
208 | /* Wrapper for setting reg values - need to check of reg is zero since | |
209 | * cpu_gpr[0] is not actually allocated. this is more for safety purposes, | |
210 | * since we usually avoid calling the OP_TYPE_gen function if we see a write to | |
211 | * $zero | |
212 | */ | |
213 | static inline void gen_set_gpr(int reg_num_dst, TCGv t) | |
214 | { | |
215 | if (reg_num_dst != 0) { | |
216 | tcg_gen_mov_tl(cpu_gpr[reg_num_dst], t); | |
217 | } | |
218 | } | |
219 | ||
220 | static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2) | |
221 | { | |
222 | TCGv rl = tcg_temp_new(); | |
223 | TCGv rh = tcg_temp_new(); | |
224 | ||
225 | tcg_gen_mulu2_tl(rl, rh, arg1, arg2); | |
226 | /* fix up for one negative */ | |
227 | tcg_gen_sari_tl(rl, arg1, TARGET_LONG_BITS - 1); | |
228 | tcg_gen_and_tl(rl, rl, arg2); | |
229 | tcg_gen_sub_tl(ret, rh, rl); | |
230 | ||
231 | tcg_temp_free(rl); | |
232 | tcg_temp_free(rh); | |
233 | } | |
234 | ||
12887016 | 235 | static void gen_div(TCGv ret, TCGv source1, TCGv source2) |
55c2a12c | 236 | { |
12887016 BK |
237 | TCGv cond1, cond2, zeroreg, resultopt1; |
238 | /* | |
239 | * Handle by altering args to tcg_gen_div to produce req'd results: | |
240 | * For overflow: want source1 in source1 and 1 in source2 | |
241 | * For div by zero: want -1 in source1 and 1 in source2 -> -1 result | |
242 | */ | |
243 | cond1 = tcg_temp_new(); | |
244 | cond2 = tcg_temp_new(); | |
245 | zeroreg = tcg_const_tl(0); | |
246 | resultopt1 = tcg_temp_new(); | |
247 | ||
248 | tcg_gen_movi_tl(resultopt1, (target_ulong)-1); | |
249 | tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)(~0L)); | |
250 | tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1, | |
251 | ((target_ulong)1) << (TARGET_LONG_BITS - 1)); | |
252 | tcg_gen_and_tl(cond1, cond1, cond2); /* cond1 = overflow */ | |
253 | tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, 0); /* cond2 = div 0 */ | |
254 | /* if div by zero, set source1 to -1, otherwise don't change */ | |
255 | tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond2, zeroreg, source1, | |
256 | resultopt1); | |
257 | /* if overflow or div by zero, set source2 to 1, else don't change */ | |
258 | tcg_gen_or_tl(cond1, cond1, cond2); | |
259 | tcg_gen_movi_tl(resultopt1, (target_ulong)1); | |
260 | tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2, | |
261 | resultopt1); | |
262 | tcg_gen_div_tl(ret, source1, source2); | |
263 | ||
264 | tcg_temp_free(cond1); | |
265 | tcg_temp_free(cond2); | |
266 | tcg_temp_free(zeroreg); | |
267 | tcg_temp_free(resultopt1); | |
268 | } | |
55c2a12c | 269 | |
12887016 BK |
270 | static void gen_divu(TCGv ret, TCGv source1, TCGv source2) |
271 | { | |
272 | TCGv cond1, zeroreg, resultopt1; | |
273 | cond1 = tcg_temp_new(); | |
274 | ||
275 | zeroreg = tcg_const_tl(0); | |
276 | resultopt1 = tcg_temp_new(); | |
277 | ||
278 | tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); | |
279 | tcg_gen_movi_tl(resultopt1, (target_ulong)-1); | |
280 | tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond1, zeroreg, source1, | |
281 | resultopt1); | |
282 | tcg_gen_movi_tl(resultopt1, (target_ulong)1); | |
283 | tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2, | |
284 | resultopt1); | |
285 | tcg_gen_divu_tl(ret, source1, source2); | |
286 | ||
287 | tcg_temp_free(cond1); | |
288 | tcg_temp_free(zeroreg); | |
289 | tcg_temp_free(resultopt1); | |
290 | } | |
55c2a12c | 291 | |
12887016 BK |
292 | static void gen_rem(TCGv ret, TCGv source1, TCGv source2) |
293 | { | |
294 | TCGv cond1, cond2, zeroreg, resultopt1; | |
295 | ||
296 | cond1 = tcg_temp_new(); | |
297 | cond2 = tcg_temp_new(); | |
298 | zeroreg = tcg_const_tl(0); | |
299 | resultopt1 = tcg_temp_new(); | |
300 | ||
301 | tcg_gen_movi_tl(resultopt1, 1L); | |
302 | tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)-1); | |
303 | tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1, | |
304 | (target_ulong)1 << (TARGET_LONG_BITS - 1)); | |
305 | tcg_gen_and_tl(cond2, cond1, cond2); /* cond1 = overflow */ | |
306 | tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); /* cond2 = div 0 */ | |
307 | /* if overflow or div by zero, set source2 to 1, else don't change */ | |
308 | tcg_gen_or_tl(cond2, cond1, cond2); | |
309 | tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond2, zeroreg, source2, | |
310 | resultopt1); | |
311 | tcg_gen_rem_tl(resultopt1, source1, source2); | |
312 | /* if div by zero, just return the original dividend */ | |
313 | tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1, | |
314 | source1); | |
315 | ||
316 | tcg_temp_free(cond1); | |
317 | tcg_temp_free(cond2); | |
318 | tcg_temp_free(zeroreg); | |
319 | tcg_temp_free(resultopt1); | |
320 | } | |
55c2a12c | 321 | |
12887016 BK |
322 | static void gen_remu(TCGv ret, TCGv source1, TCGv source2) |
323 | { | |
324 | TCGv cond1, zeroreg, resultopt1; | |
325 | cond1 = tcg_temp_new(); | |
326 | zeroreg = tcg_const_tl(0); | |
327 | resultopt1 = tcg_temp_new(); | |
328 | ||
329 | tcg_gen_movi_tl(resultopt1, (target_ulong)1); | |
330 | tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); | |
331 | tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2, | |
332 | resultopt1); | |
333 | tcg_gen_remu_tl(resultopt1, source1, source2); | |
334 | /* if div by zero, just return the original dividend */ | |
335 | tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1, | |
336 | source1); | |
337 | ||
338 | tcg_temp_free(cond1); | |
339 | tcg_temp_free(zeroreg); | |
340 | tcg_temp_free(resultopt1); | |
55c2a12c MC |
341 | } |
342 | ||
db9f3fd6 | 343 | static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) |
55c2a12c MC |
344 | { |
345 | target_ulong next_pc; | |
346 | ||
347 | /* check misaligned: */ | |
0114db1c | 348 | next_pc = ctx->base.pc_next + imm; |
db9f3fd6 | 349 | if (!has_ext(ctx, RVC)) { |
55c2a12c MC |
350 | if ((next_pc & 0x3) != 0) { |
351 | gen_exception_inst_addr_mis(ctx); | |
352 | return; | |
353 | } | |
354 | } | |
355 | if (rd != 0) { | |
0114db1c | 356 | tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn); |
55c2a12c MC |
357 | } |
358 | ||
0114db1c EC |
359 | gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */ |
360 | ctx->base.is_jmp = DISAS_NORETURN; | |
55c2a12c MC |
361 | } |
362 | ||
533b8f88 RH |
363 | #ifndef CONFIG_USER_ONLY |
364 | /* The states of mstatus_fs are: | |
365 | * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty | |
366 | * We will have already diagnosed disabled state, | |
367 | * and need to turn initial/clean into dirty. | |
368 | */ | |
369 | static void mark_fs_dirty(DisasContext *ctx) | |
370 | { | |
371 | TCGv tmp; | |
372 | if (ctx->mstatus_fs == MSTATUS_FS) { | |
373 | return; | |
374 | } | |
375 | /* Remember the state change for the rest of the TB. */ | |
376 | ctx->mstatus_fs = MSTATUS_FS; | |
377 | ||
378 | tmp = tcg_temp_new(); | |
379 | tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); | |
82f01467 | 380 | tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD); |
533b8f88 | 381 | tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); |
45b4dc8b AF |
382 | |
383 | if (ctx->virt_enabled) { | |
384 | tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); | |
385 | tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD); | |
386 | tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); | |
387 | } | |
533b8f88 RH |
388 | tcg_temp_free(tmp); |
389 | } | |
390 | #else | |
391 | static inline void mark_fs_dirty(DisasContext *ctx) { } | |
392 | #endif | |
393 | ||
55c2a12c MC |
394 | static void gen_set_rm(DisasContext *ctx, int rm) |
395 | { | |
396 | TCGv_i32 t0; | |
397 | ||
398 | if (ctx->frm == rm) { | |
399 | return; | |
400 | } | |
401 | ctx->frm = rm; | |
402 | t0 = tcg_const_i32(rm); | |
403 | gen_helper_set_rounding_mode(cpu_env, t0); | |
404 | tcg_temp_free_i32(t0); | |
405 | } | |
406 | ||
751538d5 LZ |
407 | static int ex_plus_1(DisasContext *ctx, int nf) |
408 | { | |
409 | return nf + 1; | |
410 | } | |
411 | ||
2a53cff4 | 412 | #define EX_SH(amount) \ |
451e4ffd | 413 | static int ex_shift_##amount(DisasContext *ctx, int imm) \ |
2a53cff4 BK |
414 | { \ |
415 | return imm << amount; \ | |
416 | } | |
3cca75a6 | 417 | EX_SH(1) |
e98d9140 BK |
418 | EX_SH(2) |
419 | EX_SH(3) | |
07b001c6 | 420 | EX_SH(4) |
2a53cff4 BK |
421 | EX_SH(12) |
422 | ||
d2e2c1e4 BK |
423 | #define REQUIRE_EXT(ctx, ext) do { \ |
424 | if (!has_ext(ctx, ext)) { \ | |
425 | return false; \ | |
426 | } \ | |
427 | } while (0) | |
428 | ||
451e4ffd | 429 | static int ex_rvc_register(DisasContext *ctx, int reg) |
e98d9140 BK |
430 | { |
431 | return 8 + reg; | |
432 | } | |
433 | ||
6cafec92 RH |
434 | static int ex_rvc_shifti(DisasContext *ctx, int imm) |
435 | { | |
436 | /* For RV128 a shamt of 0 means a shift by 64. */ | |
437 | return imm ? imm : 64; | |
438 | } | |
439 | ||
2a53cff4 | 440 | /* Include the auto-generated decoder for 32 bit insn */ |
abff1abf | 441 | #include "decode-insn32.c.inc" |
7a50d3e2 | 442 | |
598aa116 RH |
443 | static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, |
444 | void (*func)(TCGv, TCGv, target_long)) | |
445 | { | |
446 | TCGv source1; | |
447 | source1 = tcg_temp_new(); | |
448 | ||
449 | gen_get_gpr(source1, a->rs1); | |
450 | ||
451 | (*func)(source1, source1, a->imm); | |
452 | ||
453 | gen_set_gpr(a->rd, source1); | |
454 | tcg_temp_free(source1); | |
455 | return true; | |
456 | } | |
457 | ||
458 | static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, | |
459 | void (*func)(TCGv, TCGv, TCGv)) | |
7a50d3e2 BK |
460 | { |
461 | TCGv source1, source2; | |
462 | source1 = tcg_temp_new(); | |
463 | source2 = tcg_temp_new(); | |
464 | ||
465 | gen_get_gpr(source1, a->rs1); | |
466 | tcg_gen_movi_tl(source2, a->imm); | |
467 | ||
468 | (*func)(source1, source1, source2); | |
469 | ||
470 | gen_set_gpr(a->rd, source1); | |
471 | tcg_temp_free(source1); | |
472 | tcg_temp_free(source2); | |
473 | return true; | |
474 | } | |
475 | ||
476 | #ifdef TARGET_RISCV64 | |
477 | static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2) | |
478 | { | |
479 | tcg_gen_add_tl(ret, arg1, arg2); | |
480 | tcg_gen_ext32s_tl(ret, ret); | |
481 | } | |
f2ab1728 BK |
482 | |
483 | static void gen_subw(TCGv ret, TCGv arg1, TCGv arg2) | |
484 | { | |
485 | tcg_gen_sub_tl(ret, arg1, arg2); | |
486 | tcg_gen_ext32s_tl(ret, ret); | |
487 | } | |
488 | ||
12887016 BK |
489 | static void gen_mulw(TCGv ret, TCGv arg1, TCGv arg2) |
490 | { | |
491 | tcg_gen_mul_tl(ret, arg1, arg2); | |
492 | tcg_gen_ext32s_tl(ret, ret); | |
493 | } | |
494 | ||
495 | static bool gen_arith_div_w(DisasContext *ctx, arg_r *a, | |
496 | void(*func)(TCGv, TCGv, TCGv)) | |
497 | { | |
498 | TCGv source1, source2; | |
499 | source1 = tcg_temp_new(); | |
500 | source2 = tcg_temp_new(); | |
501 | ||
502 | gen_get_gpr(source1, a->rs1); | |
503 | gen_get_gpr(source2, a->rs2); | |
504 | tcg_gen_ext32s_tl(source1, source1); | |
505 | tcg_gen_ext32s_tl(source2, source2); | |
506 | ||
507 | (*func)(source1, source1, source2); | |
508 | ||
509 | tcg_gen_ext32s_tl(source1, source1); | |
510 | gen_set_gpr(a->rd, source1); | |
511 | tcg_temp_free(source1); | |
512 | tcg_temp_free(source2); | |
513 | return true; | |
514 | } | |
515 | ||
f17e02cd PD |
516 | static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a, |
517 | void(*func)(TCGv, TCGv, TCGv)) | |
518 | { | |
519 | TCGv source1, source2; | |
520 | source1 = tcg_temp_new(); | |
521 | source2 = tcg_temp_new(); | |
522 | ||
523 | gen_get_gpr(source1, a->rs1); | |
524 | gen_get_gpr(source2, a->rs2); | |
525 | tcg_gen_ext32u_tl(source1, source1); | |
526 | tcg_gen_ext32u_tl(source2, source2); | |
527 | ||
528 | (*func)(source1, source1, source2); | |
529 | ||
530 | tcg_gen_ext32s_tl(source1, source1); | |
531 | gen_set_gpr(a->rd, source1); | |
532 | tcg_temp_free(source1); | |
533 | tcg_temp_free(source2); | |
534 | return true; | |
535 | } | |
536 | ||
7a50d3e2 BK |
537 | #endif |
538 | ||
8dc9e8a8 BK |
539 | static bool gen_arith(DisasContext *ctx, arg_r *a, |
540 | void(*func)(TCGv, TCGv, TCGv)) | |
f2ab1728 BK |
541 | { |
542 | TCGv source1, source2; | |
543 | source1 = tcg_temp_new(); | |
544 | source2 = tcg_temp_new(); | |
545 | ||
546 | gen_get_gpr(source1, a->rs1); | |
547 | gen_get_gpr(source2, a->rs2); | |
548 | ||
549 | (*func)(source1, source1, source2); | |
550 | ||
551 | gen_set_gpr(a->rd, source1); | |
552 | tcg_temp_free(source1); | |
553 | tcg_temp_free(source2); | |
554 | return true; | |
555 | } | |
556 | ||
34446e84 BK |
557 | static bool gen_shift(DisasContext *ctx, arg_r *a, |
558 | void(*func)(TCGv, TCGv, TCGv)) | |
559 | { | |
560 | TCGv source1 = tcg_temp_new(); | |
561 | TCGv source2 = tcg_temp_new(); | |
562 | ||
563 | gen_get_gpr(source1, a->rs1); | |
564 | gen_get_gpr(source2, a->rs2); | |
565 | ||
566 | tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1); | |
567 | (*func)(source1, source1, source2); | |
568 | ||
569 | gen_set_gpr(a->rd, source1); | |
570 | tcg_temp_free(source1); | |
571 | tcg_temp_free(source2); | |
572 | return true; | |
573 | } | |
574 | ||
a10b9d93 KP |
575 | static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) |
576 | { | |
577 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
578 | CPUState *cpu = ctx->cs; | |
579 | CPURISCVState *env = cpu->env_ptr; | |
580 | ||
581 | return cpu_ldl_code(env, pc); | |
582 | } | |
583 | ||
2a53cff4 | 584 | /* Include insn module translation function */ |
139c1837 PB |
585 | #include "insn_trans/trans_rvi.c.inc" |
586 | #include "insn_trans/trans_rvm.c.inc" | |
587 | #include "insn_trans/trans_rva.c.inc" | |
588 | #include "insn_trans/trans_rvf.c.inc" | |
589 | #include "insn_trans/trans_rvd.c.inc" | |
590 | #include "insn_trans/trans_rvh.c.inc" | |
591 | #include "insn_trans/trans_rvv.c.inc" | |
592 | #include "insn_trans/trans_privileged.c.inc" | |
2a53cff4 | 593 | |
59a3a1c0 | 594 | /* Include the auto-generated decoder for 16 bit insn */ |
abff1abf | 595 | #include "decode-insn16.c.inc" |
e98d9140 | 596 | |
25139bf7 | 597 | static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) |
55c2a12c MC |
598 | { |
599 | /* check for compressed insn */ | |
25139bf7 | 600 | if (extract16(opcode, 0, 2) != 3) { |
db9f3fd6 | 601 | if (!has_ext(ctx, RVC)) { |
55c2a12c MC |
602 | gen_exception_illegal(ctx); |
603 | } else { | |
0114db1c | 604 | ctx->pc_succ_insn = ctx->base.pc_next + 2; |
25139bf7 | 605 | if (!decode_insn16(ctx, opcode)) { |
9a27f69b | 606 | gen_exception_illegal(ctx); |
e98d9140 | 607 | } |
55c2a12c MC |
608 | } |
609 | } else { | |
25139bf7 AB |
610 | uint32_t opcode32 = opcode; |
611 | opcode32 = deposit32(opcode32, 16, 16, | |
612 | translator_lduw(env, ctx->base.pc_next + 2)); | |
0114db1c | 613 | ctx->pc_succ_insn = ctx->base.pc_next + 4; |
25139bf7 | 614 | if (!decode_insn32(ctx, opcode32)) { |
25e6ca30 | 615 | gen_exception_illegal(ctx); |
2a53cff4 | 616 | } |
55c2a12c MC |
617 | } |
618 | } | |
619 | ||
5b4f1d2d | 620 | static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) |
55c2a12c | 621 | { |
5b4f1d2d | 622 | DisasContext *ctx = container_of(dcbase, DisasContext, base); |
d75377bf | 623 | CPURISCVState *env = cs->env_ptr; |
50fba816 | 624 | RISCVCPU *cpu = RISCV_CPU(cs); |
2b7168fc | 625 | uint32_t tb_flags = ctx->base.tb->flags; |
55c2a12c | 626 | |
5b4f1d2d | 627 | ctx->pc_succ_insn = ctx->base.pc_first; |
2b7168fc LZ |
628 | ctx->mem_idx = tb_flags & TB_FLAGS_MMU_MASK; |
629 | ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS; | |
d75377bf | 630 | ctx->priv_ver = env->priv_ver; |
45b4dc8b | 631 | #if !defined(CONFIG_USER_ONLY) |
ae84dd0a AF |
632 | if (riscv_has_ext(env, RVH)) { |
633 | ctx->virt_enabled = riscv_cpu_virt_enabled(env); | |
ae84dd0a AF |
634 | } else { |
635 | ctx->virt_enabled = false; | |
636 | } | |
45b4dc8b AF |
637 | #else |
638 | ctx->virt_enabled = false; | |
639 | #endif | |
db9f3fd6 | 640 | ctx->misa = env->misa; |
5b4f1d2d | 641 | ctx->frm = -1; /* unknown rounding mode */ |
50fba816 | 642 | ctx->ext_ifencei = cpu->cfg.ext_ifencei; |
2b7168fc | 643 | ctx->vlen = cpu->cfg.vlen; |
743077b3 | 644 | ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); |
2b7168fc LZ |
645 | ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); |
646 | ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); | |
647 | ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL); | |
751538d5 | 648 | ctx->mlen = 1 << (ctx->sew + 3 - ctx->lmul); |
2b7168fc | 649 | ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); |
a10b9d93 | 650 | ctx->cs = cs; |
5b4f1d2d | 651 | } |
55c2a12c | 652 | |
5b4f1d2d EC |
653 | static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) |
654 | { | |
655 | } | |
55c2a12c | 656 | |
5b4f1d2d EC |
657 | static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) |
658 | { | |
659 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
660 | ||
661 | tcg_gen_insn_start(ctx->base.pc_next); | |
662 | } | |
663 | ||
664 | static bool riscv_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, | |
665 | const CPUBreakpoint *bp) | |
666 | { | |
667 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
668 | ||
669 | tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); | |
670 | ctx->base.is_jmp = DISAS_NORETURN; | |
671 | gen_exception_debug(); | |
672 | /* The address covered by the breakpoint must be included in | |
673 | [tb->pc, tb->pc + tb->size) in order to for it to be | |
674 | properly cleared -- thus we increment the PC here so that | |
675 | the logic setting tb->size below does the right thing. */ | |
676 | ctx->base.pc_next += 4; | |
677 | return true; | |
678 | } | |
679 | ||
5b4f1d2d EC |
680 | static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) |
681 | { | |
682 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
683 | CPURISCVState *env = cpu->env_ptr; | |
25139bf7 | 684 | uint16_t opcode16 = translator_lduw(env, ctx->base.pc_next); |
55c2a12c | 685 | |
25139bf7 | 686 | decode_opc(env, ctx, opcode16); |
5b4f1d2d EC |
687 | ctx->base.pc_next = ctx->pc_succ_insn; |
688 | ||
689 | if (ctx->base.is_jmp == DISAS_NEXT) { | |
690 | target_ulong page_start; | |
691 | ||
692 | page_start = ctx->base.pc_first & TARGET_PAGE_MASK; | |
693 | if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) { | |
694 | ctx->base.is_jmp = DISAS_TOO_MANY; | |
55c2a12c | 695 | } |
55c2a12c | 696 | } |
5b4f1d2d EC |
697 | } |
698 | ||
699 | static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) | |
700 | { | |
701 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
702 | ||
703 | switch (ctx->base.is_jmp) { | |
b2e32021 | 704 | case DISAS_TOO_MANY: |
ccf08e40 | 705 | gen_goto_tb(ctx, 0, ctx->base.pc_next); |
55c2a12c | 706 | break; |
b2e32021 | 707 | case DISAS_NORETURN: |
55c2a12c | 708 | break; |
b2e32021 EC |
709 | default: |
710 | g_assert_not_reached(); | |
55c2a12c | 711 | } |
5b4f1d2d EC |
712 | } |
713 | ||
714 | static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) | |
715 | { | |
35f69039 AF |
716 | #ifndef CONFIG_USER_ONLY |
717 | RISCVCPU *rvcpu = RISCV_CPU(cpu); | |
718 | CPURISCVState *env = &rvcpu->env; | |
719 | #endif | |
720 | ||
5b4f1d2d | 721 | qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); |
35f69039 AF |
722 | #ifndef CONFIG_USER_ONLY |
723 | qemu_log("Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", env->priv, env->virt); | |
724 | #endif | |
5b4f1d2d EC |
725 | log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); |
726 | } | |
727 | ||
728 | static const TranslatorOps riscv_tr_ops = { | |
729 | .init_disas_context = riscv_tr_init_disas_context, | |
730 | .tb_start = riscv_tr_tb_start, | |
731 | .insn_start = riscv_tr_insn_start, | |
732 | .breakpoint_check = riscv_tr_breakpoint_check, | |
733 | .translate_insn = riscv_tr_translate_insn, | |
734 | .tb_stop = riscv_tr_tb_stop, | |
735 | .disas_log = riscv_tr_disas_log, | |
736 | }; | |
737 | ||
8b86d6d2 | 738 | void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) |
5b4f1d2d EC |
739 | { |
740 | DisasContext ctx; | |
741 | ||
8b86d6d2 | 742 | translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns); |
55c2a12c MC |
743 | } |
744 | ||
745 | void riscv_translate_init(void) | |
746 | { | |
747 | int i; | |
748 | ||
749 | /* cpu_gpr[0] is a placeholder for the zero register. Do not use it. */ | |
750 | /* Use the gen_set_gpr and gen_get_gpr helper functions when accessing */ | |
751 | /* registers, unless you specifically block reads/writes to reg 0 */ | |
752 | cpu_gpr[0] = NULL; | |
753 | ||
754 | for (i = 1; i < 32; i++) { | |
755 | cpu_gpr[i] = tcg_global_mem_new(cpu_env, | |
756 | offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); | |
757 | } | |
758 | ||
759 | for (i = 0; i < 32; i++) { | |
760 | cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, | |
761 | offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); | |
762 | } | |
763 | ||
764 | cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); | |
ad9e5aa2 | 765 | cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl"); |
55c2a12c MC |
766 | load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), |
767 | "load_res"); | |
768 | load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), | |
769 | "load_val"); | |
770 | } |