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target/riscv: vector single-width averaging add and subtract
[mirror_qemu.git] / target / riscv / vector_helper.c
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2b7168fc
LZ		 1/*
2 * RISC-V Vector Extension Helpers for QEMU.
3 *
4 * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include "qemu/osdep.h"
20#include "cpu.h"
751538d5 21#include "exec/memop.h"
2b7168fc
LZ		 22#include "exec/exec-all.h"
23#include "exec/helper-proto.h"
751538d5
LZ		 24#include "tcg/tcg-gvec-desc.h"
25#include "internals.h"
2b7168fc
LZ		 26#include <math.h>
27
28target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
29 target_ulong s2)
30{
31 int vlmax, vl;
32 RISCVCPU *cpu = env_archcpu(env);
33 uint16_t sew = 8 << FIELD_EX64(s2, VTYPE, VSEW);
34 uint8_t ediv = FIELD_EX64(s2, VTYPE, VEDIV);
35 bool vill = FIELD_EX64(s2, VTYPE, VILL);
36 target_ulong reserved = FIELD_EX64(s2, VTYPE, RESERVED);
37
38 if ((sew > cpu->cfg.elen) || vill || (ediv != 0) || (reserved != 0)) {
39 /* only set vill bit. */
40 env->vtype = FIELD_DP64(0, VTYPE, VILL, 1);
41 env->vl = 0;
42 env->vstart = 0;
43 return 0;
44 }
45
46 vlmax = vext_get_vlmax(cpu, s2);
47 if (s1 <= vlmax) {
48 vl = s1;
49 } else {
50 vl = vlmax;
51 }
52 env->vl = vl;
53 env->vtype = s2;
54 env->vstart = 0;
55 return vl;
56}
751538d5
LZ		 57
58/*
59 * Note that vector data is stored in host-endian 64-bit chunks,
60 * so addressing units smaller than that needs a host-endian fixup.
61 */
62#ifdef HOST_WORDS_BIGENDIAN
63#define H1(x) ((x) ^ 7)
64#define H1_2(x) ((x) ^ 6)
65#define H1_4(x) ((x) ^ 4)
66#define H2(x) ((x) ^ 3)
67#define H4(x) ((x) ^ 1)
68#define H8(x) ((x))
69#else
70#define H1(x) (x)
71#define H1_2(x) (x)
72#define H1_4(x) (x)
73#define H2(x) (x)
74#define H4(x) (x)
75#define H8(x) (x)
76#endif
77
78static inline uint32_t vext_nf(uint32_t desc)
79{
80 return FIELD_EX32(simd_data(desc), VDATA, NF);
81}
82
83static inline uint32_t vext_mlen(uint32_t desc)
84{
85 return FIELD_EX32(simd_data(desc), VDATA, MLEN);
86}
87
88static inline uint32_t vext_vm(uint32_t desc)
89{
90 return FIELD_EX32(simd_data(desc), VDATA, VM);
91}
92
93static inline uint32_t vext_lmul(uint32_t desc)
94{
95 return FIELD_EX32(simd_data(desc), VDATA, LMUL);
96}
97
268fcca6
LZ		 98static uint32_t vext_wd(uint32_t desc)
99{
100 return (simd_data(desc) >> 11) & 0x1;
101}
102
751538d5
LZ		 103/*
104 * Get vector group length in bytes. Its range is [64, 2048].
105 *
106 * As simd_desc support at most 256, the max vlen is 512 bits.
107 * So vlen in bytes is encoded as maxsz.
108 */
109static inline uint32_t vext_maxsz(uint32_t desc)
110{
111 return simd_maxsz(desc) << vext_lmul(desc);
112}
113
114/*
115 * This function checks watchpoint before real load operation.
116 *
117 * In softmmu mode, the TLB API probe_access is enough for watchpoint check.
118 * In user mode, there is no watchpoint support now.
119 *
120 * It will trigger an exception if there is no mapping in TLB
121 * and page table walk can't fill the TLB entry. Then the guest
122 * software can return here after process the exception or never return.
123 */
124static void probe_pages(CPURISCVState *env, target_ulong addr,
125 target_ulong len, uintptr_t ra,
126 MMUAccessType access_type)
127{
128 target_ulong pagelen = -(addr | TARGET_PAGE_MASK);
129 target_ulong curlen = MIN(pagelen, len);
130
131 probe_access(env, addr, curlen, access_type,
132 cpu_mmu_index(env, false), ra);
133 if (len > curlen) {
134 addr += curlen;
135 curlen = len - curlen;
136 probe_access(env, addr, curlen, access_type,
137 cpu_mmu_index(env, false), ra);
138 }
139}
140
141#ifdef HOST_WORDS_BIGENDIAN
142static void vext_clear(void *tail, uint32_t cnt, uint32_t tot)
143{
144 /*
145 * Split the remaining range to two parts.
146 * The first part is in the last uint64_t unit.
147 * The second part start from the next uint64_t unit.
148 */
149 int part1 = 0, part2 = tot - cnt;
150 if (cnt % 8) {
151 part1 = 8 - (cnt % 8);
152 part2 = tot - cnt - part1;
153 memset((void *)((uintptr_t)tail & ~(7ULL)), 0, part1);
154 memset((void *)(((uintptr_t)tail + 8) & ~(7ULL)), 0, part2);
155 } else {
156 memset(tail, 0, part2);
157 }
158}
159#else
160static void vext_clear(void *tail, uint32_t cnt, uint32_t tot)
161{
162 memset(tail, 0, tot - cnt);
163}
164#endif
165
166static void clearb(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot)
167{
168 int8_t *cur = ((int8_t *)vd + H1(idx));
169 vext_clear(cur, cnt, tot);
170}
171
172static void clearh(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot)
173{
174 int16_t *cur = ((int16_t *)vd + H2(idx));
175 vext_clear(cur, cnt, tot);
176}
177
178static void clearl(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot)
179{
180 int32_t *cur = ((int32_t *)vd + H4(idx));
181 vext_clear(cur, cnt, tot);
182}
183
184static void clearq(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot)
185{
186 int64_t *cur = (int64_t *)vd + idx;
187 vext_clear(cur, cnt, tot);
188}
189
3a6f8f68
LZ		 190static inline void vext_set_elem_mask(void *v0, int mlen, int index,
191 uint8_t value)
192{
193 int idx = (index * mlen) / 64;
194 int pos = (index * mlen) % 64;
195 uint64_t old = ((uint64_t *)v0)[idx];
196 ((uint64_t *)v0)[idx] = deposit64(old, pos, mlen, value);
197}
751538d5
LZ		 198
199static inline int vext_elem_mask(void *v0, int mlen, int index)
200{
201 int idx = (index * mlen) / 64;
202 int pos = (index * mlen) % 64;
203 return (((uint64_t *)v0)[idx] >> pos) & 1;
204}
205
206/* elements operations for load and store */
207typedef void vext_ldst_elem_fn(CPURISCVState *env, target_ulong addr,
208 uint32_t idx, void *vd, uintptr_t retaddr);
209typedef void clear_fn(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot);
210
211#define GEN_VEXT_LD_ELEM(NAME, MTYPE, ETYPE, H, LDSUF) \
212static void NAME(CPURISCVState *env, abi_ptr addr, \
213 uint32_t idx, void *vd, uintptr_t retaddr)\
214{ \
215 MTYPE data; \
216 ETYPE *cur = ((ETYPE *)vd + H(idx)); \
217 data = cpu_##LDSUF##_data_ra(env, addr, retaddr); \
218 *cur = data; \
219} \
220
221GEN_VEXT_LD_ELEM(ldb_b, int8_t, int8_t, H1, ldsb)
222GEN_VEXT_LD_ELEM(ldb_h, int8_t, int16_t, H2, ldsb)
223GEN_VEXT_LD_ELEM(ldb_w, int8_t, int32_t, H4, ldsb)
224GEN_VEXT_LD_ELEM(ldb_d, int8_t, int64_t, H8, ldsb)
225GEN_VEXT_LD_ELEM(ldh_h, int16_t, int16_t, H2, ldsw)
226GEN_VEXT_LD_ELEM(ldh_w, int16_t, int32_t, H4, ldsw)
227GEN_VEXT_LD_ELEM(ldh_d, int16_t, int64_t, H8, ldsw)
228GEN_VEXT_LD_ELEM(ldw_w, int32_t, int32_t, H4, ldl)
229GEN_VEXT_LD_ELEM(ldw_d, int32_t, int64_t, H8, ldl)
230GEN_VEXT_LD_ELEM(lde_b, int8_t, int8_t, H1, ldsb)
231GEN_VEXT_LD_ELEM(lde_h, int16_t, int16_t, H2, ldsw)
232GEN_VEXT_LD_ELEM(lde_w, int32_t, int32_t, H4, ldl)
233GEN_VEXT_LD_ELEM(lde_d, int64_t, int64_t, H8, ldq)
234GEN_VEXT_LD_ELEM(ldbu_b, uint8_t, uint8_t, H1, ldub)
235GEN_VEXT_LD_ELEM(ldbu_h, uint8_t, uint16_t, H2, ldub)
236GEN_VEXT_LD_ELEM(ldbu_w, uint8_t, uint32_t, H4, ldub)
237GEN_VEXT_LD_ELEM(ldbu_d, uint8_t, uint64_t, H8, ldub)
238GEN_VEXT_LD_ELEM(ldhu_h, uint16_t, uint16_t, H2, lduw)
239GEN_VEXT_LD_ELEM(ldhu_w, uint16_t, uint32_t, H4, lduw)
240GEN_VEXT_LD_ELEM(ldhu_d, uint16_t, uint64_t, H8, lduw)
241GEN_VEXT_LD_ELEM(ldwu_w, uint32_t, uint32_t, H4, ldl)
242GEN_VEXT_LD_ELEM(ldwu_d, uint32_t, uint64_t, H8, ldl)
243
244#define GEN_VEXT_ST_ELEM(NAME, ETYPE, H, STSUF) \
245static void NAME(CPURISCVState *env, abi_ptr addr, \
246 uint32_t idx, void *vd, uintptr_t retaddr)\
247{ \
248 ETYPE data = *((ETYPE *)vd + H(idx)); \
249 cpu_##STSUF##_data_ra(env, addr, data, retaddr); \
250}
251
252GEN_VEXT_ST_ELEM(stb_b, int8_t, H1, stb)
253GEN_VEXT_ST_ELEM(stb_h, int16_t, H2, stb)
254GEN_VEXT_ST_ELEM(stb_w, int32_t, H4, stb)
255GEN_VEXT_ST_ELEM(stb_d, int64_t, H8, stb)
256GEN_VEXT_ST_ELEM(sth_h, int16_t, H2, stw)
257GEN_VEXT_ST_ELEM(sth_w, int32_t, H4, stw)
258GEN_VEXT_ST_ELEM(sth_d, int64_t, H8, stw)
259GEN_VEXT_ST_ELEM(stw_w, int32_t, H4, stl)
260GEN_VEXT_ST_ELEM(stw_d, int64_t, H8, stl)
261GEN_VEXT_ST_ELEM(ste_b, int8_t, H1, stb)
262GEN_VEXT_ST_ELEM(ste_h, int16_t, H2, stw)
263GEN_VEXT_ST_ELEM(ste_w, int32_t, H4, stl)
264GEN_VEXT_ST_ELEM(ste_d, int64_t, H8, stq)
265
266/*
267 *** stride: access vector element from strided memory
268 */
269static void
270vext_ldst_stride(void *vd, void *v0, target_ulong base,
271 target_ulong stride, CPURISCVState *env,
272 uint32_t desc, uint32_t vm,
273 vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem,
274 uint32_t esz, uint32_t msz, uintptr_t ra,
275 MMUAccessType access_type)
276{
277 uint32_t i, k;
278 uint32_t nf = vext_nf(desc);
279 uint32_t mlen = vext_mlen(desc);
280 uint32_t vlmax = vext_maxsz(desc) / esz;
281
282 /* probe every access*/
283 for (i = 0; i < env->vl; i++) {
284 if (!vm && !vext_elem_mask(v0, mlen, i)) {
285 continue;
286 }
287 probe_pages(env, base + stride * i, nf * msz, ra, access_type);
288 }
289 /* do real access */
290 for (i = 0; i < env->vl; i++) {
291 k = 0;
292 if (!vm && !vext_elem_mask(v0, mlen, i)) {
293 continue;
294 }
295 while (k < nf) {
296 target_ulong addr = base + stride * i + k * msz;
297 ldst_elem(env, addr, i + k * vlmax, vd, ra);
298 k++;
299 }
300 }
301 /* clear tail elements */
302 if (clear_elem) {
303 for (k = 0; k < nf; k++) {
304 clear_elem(vd, env->vl + k * vlmax, env->vl * esz, vlmax * esz);
305 }
306 }
307}
308
309#define GEN_VEXT_LD_STRIDE(NAME, MTYPE, ETYPE, LOAD_FN, CLEAR_FN) \
310void HELPER(NAME)(void *vd, void * v0, target_ulong base, \
311 target_ulong stride, CPURISCVState *env, \
312 uint32_t desc) \
313{ \
314 uint32_t vm = vext_vm(desc); \
315 vext_ldst_stride(vd, v0, base, stride, env, desc, vm, LOAD_FN, \
316 CLEAR_FN, sizeof(ETYPE), sizeof(MTYPE), \
317 GETPC(), MMU_DATA_LOAD); \
318}
319
320GEN_VEXT_LD_STRIDE(vlsb_v_b, int8_t, int8_t, ldb_b, clearb)
321GEN_VEXT_LD_STRIDE(vlsb_v_h, int8_t, int16_t, ldb_h, clearh)
322GEN_VEXT_LD_STRIDE(vlsb_v_w, int8_t, int32_t, ldb_w, clearl)
323GEN_VEXT_LD_STRIDE(vlsb_v_d, int8_t, int64_t, ldb_d, clearq)
324GEN_VEXT_LD_STRIDE(vlsh_v_h, int16_t, int16_t, ldh_h, clearh)
325GEN_VEXT_LD_STRIDE(vlsh_v_w, int16_t, int32_t, ldh_w, clearl)
326GEN_VEXT_LD_STRIDE(vlsh_v_d, int16_t, int64_t, ldh_d, clearq)
327GEN_VEXT_LD_STRIDE(vlsw_v_w, int32_t, int32_t, ldw_w, clearl)
328GEN_VEXT_LD_STRIDE(vlsw_v_d, int32_t, int64_t, ldw_d, clearq)
329GEN_VEXT_LD_STRIDE(vlse_v_b, int8_t, int8_t, lde_b, clearb)
330GEN_VEXT_LD_STRIDE(vlse_v_h, int16_t, int16_t, lde_h, clearh)
331GEN_VEXT_LD_STRIDE(vlse_v_w, int32_t, int32_t, lde_w, clearl)
332GEN_VEXT_LD_STRIDE(vlse_v_d, int64_t, int64_t, lde_d, clearq)
333GEN_VEXT_LD_STRIDE(vlsbu_v_b, uint8_t, uint8_t, ldbu_b, clearb)
334GEN_VEXT_LD_STRIDE(vlsbu_v_h, uint8_t, uint16_t, ldbu_h, clearh)
335GEN_VEXT_LD_STRIDE(vlsbu_v_w, uint8_t, uint32_t, ldbu_w, clearl)
336GEN_VEXT_LD_STRIDE(vlsbu_v_d, uint8_t, uint64_t, ldbu_d, clearq)
337GEN_VEXT_LD_STRIDE(vlshu_v_h, uint16_t, uint16_t, ldhu_h, clearh)
338GEN_VEXT_LD_STRIDE(vlshu_v_w, uint16_t, uint32_t, ldhu_w, clearl)
339GEN_VEXT_LD_STRIDE(vlshu_v_d, uint16_t, uint64_t, ldhu_d, clearq)
340GEN_VEXT_LD_STRIDE(vlswu_v_w, uint32_t, uint32_t, ldwu_w, clearl)
341GEN_VEXT_LD_STRIDE(vlswu_v_d, uint32_t, uint64_t, ldwu_d, clearq)
342
343#define GEN_VEXT_ST_STRIDE(NAME, MTYPE, ETYPE, STORE_FN) \
344void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
345 target_ulong stride, CPURISCVState *env, \
346 uint32_t desc) \
347{ \
348 uint32_t vm = vext_vm(desc); \
349 vext_ldst_stride(vd, v0, base, stride, env, desc, vm, STORE_FN, \
350 NULL, sizeof(ETYPE), sizeof(MTYPE), \
351 GETPC(), MMU_DATA_STORE); \
352}
353
354GEN_VEXT_ST_STRIDE(vssb_v_b, int8_t, int8_t, stb_b)
355GEN_VEXT_ST_STRIDE(vssb_v_h, int8_t, int16_t, stb_h)
356GEN_VEXT_ST_STRIDE(vssb_v_w, int8_t, int32_t, stb_w)
357GEN_VEXT_ST_STRIDE(vssb_v_d, int8_t, int64_t, stb_d)
358GEN_VEXT_ST_STRIDE(vssh_v_h, int16_t, int16_t, sth_h)
359GEN_VEXT_ST_STRIDE(vssh_v_w, int16_t, int32_t, sth_w)
360GEN_VEXT_ST_STRIDE(vssh_v_d, int16_t, int64_t, sth_d)
361GEN_VEXT_ST_STRIDE(vssw_v_w, int32_t, int32_t, stw_w)
362GEN_VEXT_ST_STRIDE(vssw_v_d, int32_t, int64_t, stw_d)
363GEN_VEXT_ST_STRIDE(vsse_v_b, int8_t, int8_t, ste_b)
364GEN_VEXT_ST_STRIDE(vsse_v_h, int16_t, int16_t, ste_h)
365GEN_VEXT_ST_STRIDE(vsse_v_w, int32_t, int32_t, ste_w)
366GEN_VEXT_ST_STRIDE(vsse_v_d, int64_t, int64_t, ste_d)
367
368/*
369 *** unit-stride: access elements stored contiguously in memory
370 */
371
372/* unmasked unit-stride load and store operation*/
373static void
374vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
375 vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem,
376 uint32_t esz, uint32_t msz, uintptr_t ra,
377 MMUAccessType access_type)
378{
379 uint32_t i, k;
380 uint32_t nf = vext_nf(desc);
381 uint32_t vlmax = vext_maxsz(desc) / esz;
382
383 /* probe every access */
384 probe_pages(env, base, env->vl * nf * msz, ra, access_type);
385 /* load bytes from guest memory */
386 for (i = 0; i < env->vl; i++) {
387 k = 0;
388 while (k < nf) {
389 target_ulong addr = base + (i * nf + k) * msz;
390 ldst_elem(env, addr, i + k * vlmax, vd, ra);
391 k++;
392 }
393 }
394 /* clear tail elements */
395 if (clear_elem) {
396 for (k = 0; k < nf; k++) {
397 clear_elem(vd, env->vl + k * vlmax, env->vl * esz, vlmax * esz);
398 }
399 }
400}
401
402/*
403 * masked unit-stride load and store operation will be a special case of stride,
404 * stride = NF * sizeof (MTYPE)
405 */
406
407#define GEN_VEXT_LD_US(NAME, MTYPE, ETYPE, LOAD_FN, CLEAR_FN) \
408void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \
409 CPURISCVState *env, uint32_t desc) \
410{ \
411 uint32_t stride = vext_nf(desc) * sizeof(MTYPE); \
412 vext_ldst_stride(vd, v0, base, stride, env, desc, false, LOAD_FN, \
413 CLEAR_FN, sizeof(ETYPE), sizeof(MTYPE), \
414 GETPC(), MMU_DATA_LOAD); \
415} \
416 \
417void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
418 CPURISCVState *env, uint32_t desc) \
419{ \
420 vext_ldst_us(vd, base, env, desc, LOAD_FN, CLEAR_FN, \
421 sizeof(ETYPE), sizeof(MTYPE), GETPC(), MMU_DATA_LOAD); \
422}
423
424GEN_VEXT_LD_US(vlb_v_b, int8_t, int8_t, ldb_b, clearb)
425GEN_VEXT_LD_US(vlb_v_h, int8_t, int16_t, ldb_h, clearh)
426GEN_VEXT_LD_US(vlb_v_w, int8_t, int32_t, ldb_w, clearl)
427GEN_VEXT_LD_US(vlb_v_d, int8_t, int64_t, ldb_d, clearq)
428GEN_VEXT_LD_US(vlh_v_h, int16_t, int16_t, ldh_h, clearh)
429GEN_VEXT_LD_US(vlh_v_w, int16_t, int32_t, ldh_w, clearl)
430GEN_VEXT_LD_US(vlh_v_d, int16_t, int64_t, ldh_d, clearq)
431GEN_VEXT_LD_US(vlw_v_w, int32_t, int32_t, ldw_w, clearl)
432GEN_VEXT_LD_US(vlw_v_d, int32_t, int64_t, ldw_d, clearq)
433GEN_VEXT_LD_US(vle_v_b, int8_t, int8_t, lde_b, clearb)
434GEN_VEXT_LD_US(vle_v_h, int16_t, int16_t, lde_h, clearh)
435GEN_VEXT_LD_US(vle_v_w, int32_t, int32_t, lde_w, clearl)
436GEN_VEXT_LD_US(vle_v_d, int64_t, int64_t, lde_d, clearq)
437GEN_VEXT_LD_US(vlbu_v_b, uint8_t, uint8_t, ldbu_b, clearb)
438GEN_VEXT_LD_US(vlbu_v_h, uint8_t, uint16_t, ldbu_h, clearh)
439GEN_VEXT_LD_US(vlbu_v_w, uint8_t, uint32_t, ldbu_w, clearl)
440GEN_VEXT_LD_US(vlbu_v_d, uint8_t, uint64_t, ldbu_d, clearq)
441GEN_VEXT_LD_US(vlhu_v_h, uint16_t, uint16_t, ldhu_h, clearh)
442GEN_VEXT_LD_US(vlhu_v_w, uint16_t, uint32_t, ldhu_w, clearl)
443GEN_VEXT_LD_US(vlhu_v_d, uint16_t, uint64_t, ldhu_d, clearq)
444GEN_VEXT_LD_US(vlwu_v_w, uint32_t, uint32_t, ldwu_w, clearl)
445GEN_VEXT_LD_US(vlwu_v_d, uint32_t, uint64_t, ldwu_d, clearq)
446
447#define GEN_VEXT_ST_US(NAME, MTYPE, ETYPE, STORE_FN) \
448void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \
449 CPURISCVState *env, uint32_t desc) \
450{ \
451 uint32_t stride = vext_nf(desc) * sizeof(MTYPE); \
452 vext_ldst_stride(vd, v0, base, stride, env, desc, false, STORE_FN, \
453 NULL, sizeof(ETYPE), sizeof(MTYPE), \
454 GETPC(), MMU_DATA_STORE); \
455} \
456 \
457void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
458 CPURISCVState *env, uint32_t desc) \
459{ \
460 vext_ldst_us(vd, base, env, desc, STORE_FN, NULL, \
461 sizeof(ETYPE), sizeof(MTYPE), GETPC(), MMU_DATA_STORE);\
462}
463
464GEN_VEXT_ST_US(vsb_v_b, int8_t, int8_t , stb_b)
465GEN_VEXT_ST_US(vsb_v_h, int8_t, int16_t, stb_h)
466GEN_VEXT_ST_US(vsb_v_w, int8_t, int32_t, stb_w)
467GEN_VEXT_ST_US(vsb_v_d, int8_t, int64_t, stb_d)
468GEN_VEXT_ST_US(vsh_v_h, int16_t, int16_t, sth_h)
469GEN_VEXT_ST_US(vsh_v_w, int16_t, int32_t, sth_w)
470GEN_VEXT_ST_US(vsh_v_d, int16_t, int64_t, sth_d)
471GEN_VEXT_ST_US(vsw_v_w, int32_t, int32_t, stw_w)
472GEN_VEXT_ST_US(vsw_v_d, int32_t, int64_t, stw_d)
473GEN_VEXT_ST_US(vse_v_b, int8_t, int8_t , ste_b)
474GEN_VEXT_ST_US(vse_v_h, int16_t, int16_t, ste_h)
475GEN_VEXT_ST_US(vse_v_w, int32_t, int32_t, ste_w)
476GEN_VEXT_ST_US(vse_v_d, int64_t, int64_t, ste_d)
f732560e
LZ		 477
478/*
479 *** index: access vector element from indexed memory
480 */
481typedef target_ulong vext_get_index_addr(target_ulong base,
482 uint32_t idx, void *vs2);
483
484#define GEN_VEXT_GET_INDEX_ADDR(NAME, ETYPE, H) \
485static target_ulong NAME(target_ulong base, \
486 uint32_t idx, void *vs2) \
487{ \
488 return (base + *((ETYPE *)vs2 + H(idx))); \
489}
490
491GEN_VEXT_GET_INDEX_ADDR(idx_b, int8_t, H1)
492GEN_VEXT_GET_INDEX_ADDR(idx_h, int16_t, H2)
493GEN_VEXT_GET_INDEX_ADDR(idx_w, int32_t, H4)
494GEN_VEXT_GET_INDEX_ADDR(idx_d, int64_t, H8)
495
496static inline void
497vext_ldst_index(void *vd, void *v0, target_ulong base,
498 void *vs2, CPURISCVState *env, uint32_t desc,
499 vext_get_index_addr get_index_addr,
500 vext_ldst_elem_fn *ldst_elem,
501 clear_fn *clear_elem,
502 uint32_t esz, uint32_t msz, uintptr_t ra,
503 MMUAccessType access_type)
504{
505 uint32_t i, k;
506 uint32_t nf = vext_nf(desc);
507 uint32_t vm = vext_vm(desc);
508 uint32_t mlen = vext_mlen(desc);
509 uint32_t vlmax = vext_maxsz(desc) / esz;
510
511 /* probe every access*/
512 for (i = 0; i < env->vl; i++) {
513 if (!vm && !vext_elem_mask(v0, mlen, i)) {
514 continue;
515 }
516 probe_pages(env, get_index_addr(base, i, vs2), nf * msz, ra,
517 access_type);
518 }
519 /* load bytes from guest memory */
520 for (i = 0; i < env->vl; i++) {
521 k = 0;
522 if (!vm && !vext_elem_mask(v0, mlen, i)) {
523 continue;
524 }
525 while (k < nf) {
526 abi_ptr addr = get_index_addr(base, i, vs2) + k * msz;
527 ldst_elem(env, addr, i + k * vlmax, vd, ra);
528 k++;
529 }
530 }
531 /* clear tail elements */
532 if (clear_elem) {
533 for (k = 0; k < nf; k++) {
534 clear_elem(vd, env->vl + k * vlmax, env->vl * esz, vlmax * esz);
535 }
536 }
537}
538
539#define GEN_VEXT_LD_INDEX(NAME, MTYPE, ETYPE, INDEX_FN, LOAD_FN, CLEAR_FN) \
540void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
541 void *vs2, CPURISCVState *env, uint32_t desc) \
542{ \
543 vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \
544 LOAD_FN, CLEAR_FN, sizeof(ETYPE), sizeof(MTYPE), \
545 GETPC(), MMU_DATA_LOAD); \
546}
547
548GEN_VEXT_LD_INDEX(vlxb_v_b, int8_t, int8_t, idx_b, ldb_b, clearb)
549GEN_VEXT_LD_INDEX(vlxb_v_h, int8_t, int16_t, idx_h, ldb_h, clearh)
550GEN_VEXT_LD_INDEX(vlxb_v_w, int8_t, int32_t, idx_w, ldb_w, clearl)
551GEN_VEXT_LD_INDEX(vlxb_v_d, int8_t, int64_t, idx_d, ldb_d, clearq)
552GEN_VEXT_LD_INDEX(vlxh_v_h, int16_t, int16_t, idx_h, ldh_h, clearh)
553GEN_VEXT_LD_INDEX(vlxh_v_w, int16_t, int32_t, idx_w, ldh_w, clearl)
554GEN_VEXT_LD_INDEX(vlxh_v_d, int16_t, int64_t, idx_d, ldh_d, clearq)
555GEN_VEXT_LD_INDEX(vlxw_v_w, int32_t, int32_t, idx_w, ldw_w, clearl)
556GEN_VEXT_LD_INDEX(vlxw_v_d, int32_t, int64_t, idx_d, ldw_d, clearq)
557GEN_VEXT_LD_INDEX(vlxe_v_b, int8_t, int8_t, idx_b, lde_b, clearb)
558GEN_VEXT_LD_INDEX(vlxe_v_h, int16_t, int16_t, idx_h, lde_h, clearh)
559GEN_VEXT_LD_INDEX(vlxe_v_w, int32_t, int32_t, idx_w, lde_w, clearl)
560GEN_VEXT_LD_INDEX(vlxe_v_d, int64_t, int64_t, idx_d, lde_d, clearq)
561GEN_VEXT_LD_INDEX(vlxbu_v_b, uint8_t, uint8_t, idx_b, ldbu_b, clearb)
562GEN_VEXT_LD_INDEX(vlxbu_v_h, uint8_t, uint16_t, idx_h, ldbu_h, clearh)
563GEN_VEXT_LD_INDEX(vlxbu_v_w, uint8_t, uint32_t, idx_w, ldbu_w, clearl)
564GEN_VEXT_LD_INDEX(vlxbu_v_d, uint8_t, uint64_t, idx_d, ldbu_d, clearq)
565GEN_VEXT_LD_INDEX(vlxhu_v_h, uint16_t, uint16_t, idx_h, ldhu_h, clearh)
566GEN_VEXT_LD_INDEX(vlxhu_v_w, uint16_t, uint32_t, idx_w, ldhu_w, clearl)
567GEN_VEXT_LD_INDEX(vlxhu_v_d, uint16_t, uint64_t, idx_d, ldhu_d, clearq)
568GEN_VEXT_LD_INDEX(vlxwu_v_w, uint32_t, uint32_t, idx_w, ldwu_w, clearl)
569GEN_VEXT_LD_INDEX(vlxwu_v_d, uint32_t, uint64_t, idx_d, ldwu_d, clearq)
570
571#define GEN_VEXT_ST_INDEX(NAME, MTYPE, ETYPE, INDEX_FN, STORE_FN)\
572void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
573 void *vs2, CPURISCVState *env, uint32_t desc) \
574{ \
575 vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \
576 STORE_FN, NULL, sizeof(ETYPE), sizeof(MTYPE),\
577 GETPC(), MMU_DATA_STORE); \
578}
579
580GEN_VEXT_ST_INDEX(vsxb_v_b, int8_t, int8_t, idx_b, stb_b)
581GEN_VEXT_ST_INDEX(vsxb_v_h, int8_t, int16_t, idx_h, stb_h)
582GEN_VEXT_ST_INDEX(vsxb_v_w, int8_t, int32_t, idx_w, stb_w)
583GEN_VEXT_ST_INDEX(vsxb_v_d, int8_t, int64_t, idx_d, stb_d)
584GEN_VEXT_ST_INDEX(vsxh_v_h, int16_t, int16_t, idx_h, sth_h)
585GEN_VEXT_ST_INDEX(vsxh_v_w, int16_t, int32_t, idx_w, sth_w)
586GEN_VEXT_ST_INDEX(vsxh_v_d, int16_t, int64_t, idx_d, sth_d)
587GEN_VEXT_ST_INDEX(vsxw_v_w, int32_t, int32_t, idx_w, stw_w)
588GEN_VEXT_ST_INDEX(vsxw_v_d, int32_t, int64_t, idx_d, stw_d)
589GEN_VEXT_ST_INDEX(vsxe_v_b, int8_t, int8_t, idx_b, ste_b)
590GEN_VEXT_ST_INDEX(vsxe_v_h, int16_t, int16_t, idx_h, ste_h)
591GEN_VEXT_ST_INDEX(vsxe_v_w, int32_t, int32_t, idx_w, ste_w)
592GEN_VEXT_ST_INDEX(vsxe_v_d, int64_t, int64_t, idx_d, ste_d)
022b4ecf
LZ		 593
594/*
595 *** unit-stride fault-only-fisrt load instructions
596 */
597static inline void
598vext_ldff(void *vd, void *v0, target_ulong base,
599 CPURISCVState *env, uint32_t desc,
600 vext_ldst_elem_fn *ldst_elem,
601 clear_fn *clear_elem,
602 uint32_t esz, uint32_t msz, uintptr_t ra)
603{
604 void *host;
605 uint32_t i, k, vl = 0;
606 uint32_t mlen = vext_mlen(desc);
607 uint32_t nf = vext_nf(desc);
608 uint32_t vm = vext_vm(desc);
609 uint32_t vlmax = vext_maxsz(desc) / esz;
610 target_ulong addr, offset, remain;
611
612 /* probe every access*/
613 for (i = 0; i < env->vl; i++) {
614 if (!vm && !vext_elem_mask(v0, mlen, i)) {
615 continue;
616 }
617 addr = base + nf * i * msz;
618 if (i == 0) {
619 probe_pages(env, addr, nf * msz, ra, MMU_DATA_LOAD);
620 } else {
621 /* if it triggers an exception, no need to check watchpoint */
622 remain = nf * msz;
623 while (remain > 0) {
624 offset = -(addr | TARGET_PAGE_MASK);
625 host = tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD,
626 cpu_mmu_index(env, false));
627 if (host) {
628#ifdef CONFIG_USER_ONLY
629 if (page_check_range(addr, nf * msz, PAGE_READ) < 0) {
630 vl = i;
631 goto ProbeSuccess;
632 }
633#else
634 probe_pages(env, addr, nf * msz, ra, MMU_DATA_LOAD);
635#endif
636 } else {
637 vl = i;
638 goto ProbeSuccess;
639 }
640 if (remain <= offset) {
641 break;
642 }
643 remain -= offset;
644 addr += offset;
645 }
646 }
647 }
648ProbeSuccess:
649 /* load bytes from guest memory */
650 if (vl != 0) {
651 env->vl = vl;
652 }
653 for (i = 0; i < env->vl; i++) {
654 k = 0;
655 if (!vm && !vext_elem_mask(v0, mlen, i)) {
656 continue;
657 }
658 while (k < nf) {
659 target_ulong addr = base + (i * nf + k) * msz;
660 ldst_elem(env, addr, i + k * vlmax, vd, ra);
661 k++;
662 }
663 }
664 /* clear tail elements */
665 if (vl != 0) {
666 return;
667 }
668 for (k = 0; k < nf; k++) {
669 clear_elem(vd, env->vl + k * vlmax, env->vl * esz, vlmax * esz);
670 }
671}
672
673#define GEN_VEXT_LDFF(NAME, MTYPE, ETYPE, LOAD_FN, CLEAR_FN) \
674void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
675 CPURISCVState *env, uint32_t desc) \
676{ \
677 vext_ldff(vd, v0, base, env, desc, LOAD_FN, CLEAR_FN, \
678 sizeof(ETYPE), sizeof(MTYPE), GETPC()); \
679}
680
681GEN_VEXT_LDFF(vlbff_v_b, int8_t, int8_t, ldb_b, clearb)
682GEN_VEXT_LDFF(vlbff_v_h, int8_t, int16_t, ldb_h, clearh)
683GEN_VEXT_LDFF(vlbff_v_w, int8_t, int32_t, ldb_w, clearl)
684GEN_VEXT_LDFF(vlbff_v_d, int8_t, int64_t, ldb_d, clearq)
685GEN_VEXT_LDFF(vlhff_v_h, int16_t, int16_t, ldh_h, clearh)
686GEN_VEXT_LDFF(vlhff_v_w, int16_t, int32_t, ldh_w, clearl)
687GEN_VEXT_LDFF(vlhff_v_d, int16_t, int64_t, ldh_d, clearq)
688GEN_VEXT_LDFF(vlwff_v_w, int32_t, int32_t, ldw_w, clearl)
689GEN_VEXT_LDFF(vlwff_v_d, int32_t, int64_t, ldw_d, clearq)
690GEN_VEXT_LDFF(vleff_v_b, int8_t, int8_t, lde_b, clearb)
691GEN_VEXT_LDFF(vleff_v_h, int16_t, int16_t, lde_h, clearh)
692GEN_VEXT_LDFF(vleff_v_w, int32_t, int32_t, lde_w, clearl)
693GEN_VEXT_LDFF(vleff_v_d, int64_t, int64_t, lde_d, clearq)
694GEN_VEXT_LDFF(vlbuff_v_b, uint8_t, uint8_t, ldbu_b, clearb)
695GEN_VEXT_LDFF(vlbuff_v_h, uint8_t, uint16_t, ldbu_h, clearh)
696GEN_VEXT_LDFF(vlbuff_v_w, uint8_t, uint32_t, ldbu_w, clearl)
697GEN_VEXT_LDFF(vlbuff_v_d, uint8_t, uint64_t, ldbu_d, clearq)
698GEN_VEXT_LDFF(vlhuff_v_h, uint16_t, uint16_t, ldhu_h, clearh)
699GEN_VEXT_LDFF(vlhuff_v_w, uint16_t, uint32_t, ldhu_w, clearl)
700GEN_VEXT_LDFF(vlhuff_v_d, uint16_t, uint64_t, ldhu_d, clearq)
701GEN_VEXT_LDFF(vlwuff_v_w, uint32_t, uint32_t, ldwu_w, clearl)
702GEN_VEXT_LDFF(vlwuff_v_d, uint32_t, uint64_t, ldwu_d, clearq)
268fcca6
LZ		 703
704/*
705 *** Vector AMO Operations (Zvamo)
706 */
707typedef void vext_amo_noatomic_fn(void *vs3, target_ulong addr,
708 uint32_t wd, uint32_t idx, CPURISCVState *env,
709 uintptr_t retaddr);
710
711/* no atomic opreation for vector atomic insructions */
712#define DO_SWAP(N, M) (M)
713#define DO_AND(N, M) (N & M)
714#define DO_XOR(N, M) (N ^ M)
715#define DO_OR(N, M) (N | M)
716#define DO_ADD(N, M) (N + M)
717
718#define GEN_VEXT_AMO_NOATOMIC_OP(NAME, ESZ, MSZ, H, DO_OP, SUF) \
719static void \
720vext_##NAME##_noatomic_op(void *vs3, target_ulong addr, \
721 uint32_t wd, uint32_t idx, \
722 CPURISCVState *env, uintptr_t retaddr)\
723{ \
724 typedef int##ESZ##_t ETYPE; \
725 typedef int##MSZ##_t MTYPE; \
726 typedef uint##MSZ##_t UMTYPE __attribute__((unused)); \
727 ETYPE *pe3 = (ETYPE *)vs3 + H(idx); \
728 MTYPE a = cpu_ld##SUF##_data(env, addr), b = *pe3; \
729 \
730 cpu_st##SUF##_data(env, addr, DO_OP(a, b)); \
731 if (wd) { \
732 *pe3 = a; \
733 } \
734}
735
736/* Signed min/max */
737#define DO_MAX(N, M) ((N) >= (M) ? (N) : (M))
738#define DO_MIN(N, M) ((N) >= (M) ? (M) : (N))
739
740/* Unsigned min/max */
741#define DO_MAXU(N, M) DO_MAX((UMTYPE)N, (UMTYPE)M)
742#define DO_MINU(N, M) DO_MIN((UMTYPE)N, (UMTYPE)M)
743
744GEN_VEXT_AMO_NOATOMIC_OP(vamoswapw_v_w, 32, 32, H4, DO_SWAP, l)
745GEN_VEXT_AMO_NOATOMIC_OP(vamoaddw_v_w, 32, 32, H4, DO_ADD, l)
746GEN_VEXT_AMO_NOATOMIC_OP(vamoxorw_v_w, 32, 32, H4, DO_XOR, l)
747GEN_VEXT_AMO_NOATOMIC_OP(vamoandw_v_w, 32, 32, H4, DO_AND, l)
748GEN_VEXT_AMO_NOATOMIC_OP(vamoorw_v_w, 32, 32, H4, DO_OR, l)
749GEN_VEXT_AMO_NOATOMIC_OP(vamominw_v_w, 32, 32, H4, DO_MIN, l)
750GEN_VEXT_AMO_NOATOMIC_OP(vamomaxw_v_w, 32, 32, H4, DO_MAX, l)
751GEN_VEXT_AMO_NOATOMIC_OP(vamominuw_v_w, 32, 32, H4, DO_MINU, l)
752GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuw_v_w, 32, 32, H4, DO_MAXU, l)
753#ifdef TARGET_RISCV64
754GEN_VEXT_AMO_NOATOMIC_OP(vamoswapw_v_d, 64, 32, H8, DO_SWAP, l)
755GEN_VEXT_AMO_NOATOMIC_OP(vamoswapd_v_d, 64, 64, H8, DO_SWAP, q)
756GEN_VEXT_AMO_NOATOMIC_OP(vamoaddw_v_d, 64, 32, H8, DO_ADD, l)
757GEN_VEXT_AMO_NOATOMIC_OP(vamoaddd_v_d, 64, 64, H8, DO_ADD, q)
758GEN_VEXT_AMO_NOATOMIC_OP(vamoxorw_v_d, 64, 32, H8, DO_XOR, l)
759GEN_VEXT_AMO_NOATOMIC_OP(vamoxord_v_d, 64, 64, H8, DO_XOR, q)
760GEN_VEXT_AMO_NOATOMIC_OP(vamoandw_v_d, 64, 32, H8, DO_AND, l)
761GEN_VEXT_AMO_NOATOMIC_OP(vamoandd_v_d, 64, 64, H8, DO_AND, q)
762GEN_VEXT_AMO_NOATOMIC_OP(vamoorw_v_d, 64, 32, H8, DO_OR, l)
763GEN_VEXT_AMO_NOATOMIC_OP(vamoord_v_d, 64, 64, H8, DO_OR, q)
764GEN_VEXT_AMO_NOATOMIC_OP(vamominw_v_d, 64, 32, H8, DO_MIN, l)
765GEN_VEXT_AMO_NOATOMIC_OP(vamomind_v_d, 64, 64, H8, DO_MIN, q)
766GEN_VEXT_AMO_NOATOMIC_OP(vamomaxw_v_d, 64, 32, H8, DO_MAX, l)
767GEN_VEXT_AMO_NOATOMIC_OP(vamomaxd_v_d, 64, 64, H8, DO_MAX, q)
768GEN_VEXT_AMO_NOATOMIC_OP(vamominuw_v_d, 64, 32, H8, DO_MINU, l)
769GEN_VEXT_AMO_NOATOMIC_OP(vamominud_v_d, 64, 64, H8, DO_MINU, q)
770GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuw_v_d, 64, 32, H8, DO_MAXU, l)
771GEN_VEXT_AMO_NOATOMIC_OP(vamomaxud_v_d, 64, 64, H8, DO_MAXU, q)
772#endif
773
774static inline void
775vext_amo_noatomic(void *vs3, void *v0, target_ulong base,
776 void *vs2, CPURISCVState *env, uint32_t desc,
777 vext_get_index_addr get_index_addr,
778 vext_amo_noatomic_fn *noatomic_op,
779 clear_fn *clear_elem,
780 uint32_t esz, uint32_t msz, uintptr_t ra)
781{
782 uint32_t i;
783 target_long addr;
784 uint32_t wd = vext_wd(desc);
785 uint32_t vm = vext_vm(desc);
786 uint32_t mlen = vext_mlen(desc);
787 uint32_t vlmax = vext_maxsz(desc) / esz;
788
789 for (i = 0; i < env->vl; i++) {
790 if (!vm && !vext_elem_mask(v0, mlen, i)) {
791 continue;
792 }
793 probe_pages(env, get_index_addr(base, i, vs2), msz, ra, MMU_DATA_LOAD);
794 probe_pages(env, get_index_addr(base, i, vs2), msz, ra, MMU_DATA_STORE);
795 }
796 for (i = 0; i < env->vl; i++) {
797 if (!vm && !vext_elem_mask(v0, mlen, i)) {
798 continue;
799 }
800 addr = get_index_addr(base, i, vs2);
801 noatomic_op(vs3, addr, wd, i, env, ra);
802 }
803 clear_elem(vs3, env->vl, env->vl * esz, vlmax * esz);
804}
805
806#define GEN_VEXT_AMO(NAME, MTYPE, ETYPE, INDEX_FN, CLEAR_FN) \
807void HELPER(NAME)(void *vs3, void *v0, target_ulong base, \
808 void *vs2, CPURISCVState *env, uint32_t desc) \
809{ \
810 vext_amo_noatomic(vs3, v0, base, vs2, env, desc, \
811 INDEX_FN, vext_##NAME##_noatomic_op, \
812 CLEAR_FN, sizeof(ETYPE), sizeof(MTYPE), \
813 GETPC()); \
814}
815
816#ifdef TARGET_RISCV64
817GEN_VEXT_AMO(vamoswapw_v_d, int32_t, int64_t, idx_d, clearq)
818GEN_VEXT_AMO(vamoswapd_v_d, int64_t, int64_t, idx_d, clearq)
819GEN_VEXT_AMO(vamoaddw_v_d, int32_t, int64_t, idx_d, clearq)
820GEN_VEXT_AMO(vamoaddd_v_d, int64_t, int64_t, idx_d, clearq)
821GEN_VEXT_AMO(vamoxorw_v_d, int32_t, int64_t, idx_d, clearq)
822GEN_VEXT_AMO(vamoxord_v_d, int64_t, int64_t, idx_d, clearq)
823GEN_VEXT_AMO(vamoandw_v_d, int32_t, int64_t, idx_d, clearq)
824GEN_VEXT_AMO(vamoandd_v_d, int64_t, int64_t, idx_d, clearq)
825GEN_VEXT_AMO(vamoorw_v_d, int32_t, int64_t, idx_d, clearq)
826GEN_VEXT_AMO(vamoord_v_d, int64_t, int64_t, idx_d, clearq)
827GEN_VEXT_AMO(vamominw_v_d, int32_t, int64_t, idx_d, clearq)
828GEN_VEXT_AMO(vamomind_v_d, int64_t, int64_t, idx_d, clearq)
829GEN_VEXT_AMO(vamomaxw_v_d, int32_t, int64_t, idx_d, clearq)
830GEN_VEXT_AMO(vamomaxd_v_d, int64_t, int64_t, idx_d, clearq)
831GEN_VEXT_AMO(vamominuw_v_d, uint32_t, uint64_t, idx_d, clearq)
832GEN_VEXT_AMO(vamominud_v_d, uint64_t, uint64_t, idx_d, clearq)
833GEN_VEXT_AMO(vamomaxuw_v_d, uint32_t, uint64_t, idx_d, clearq)
834GEN_VEXT_AMO(vamomaxud_v_d, uint64_t, uint64_t, idx_d, clearq)
835#endif
836GEN_VEXT_AMO(vamoswapw_v_w, int32_t, int32_t, idx_w, clearl)
837GEN_VEXT_AMO(vamoaddw_v_w, int32_t, int32_t, idx_w, clearl)
838GEN_VEXT_AMO(vamoxorw_v_w, int32_t, int32_t, idx_w, clearl)
839GEN_VEXT_AMO(vamoandw_v_w, int32_t, int32_t, idx_w, clearl)
840GEN_VEXT_AMO(vamoorw_v_w, int32_t, int32_t, idx_w, clearl)
841GEN_VEXT_AMO(vamominw_v_w, int32_t, int32_t, idx_w, clearl)
842GEN_VEXT_AMO(vamomaxw_v_w, int32_t, int32_t, idx_w, clearl)
843GEN_VEXT_AMO(vamominuw_v_w, uint32_t, uint32_t, idx_w, clearl)
844GEN_VEXT_AMO(vamomaxuw_v_w, uint32_t, uint32_t, idx_w, clearl)
43740e3a
LZ		 845
846/*
847 *** Vector Integer Arithmetic Instructions
848 */
849
850/* expand macro args before macro */
851#define RVVCALL(macro, ...) macro(__VA_ARGS__)
852
853/* (TD, T1, T2, TX1, TX2) */
854#define OP_SSS_B int8_t, int8_t, int8_t, int8_t, int8_t
855#define OP_SSS_H int16_t, int16_t, int16_t, int16_t, int16_t
856#define OP_SSS_W int32_t, int32_t, int32_t, int32_t, int32_t
857#define OP_SSS_D int64_t, int64_t, int64_t, int64_t, int64_t
558fa779
LZ		 858#define OP_UUU_B uint8_t, uint8_t, uint8_t, uint8_t, uint8_t
859#define OP_UUU_H uint16_t, uint16_t, uint16_t, uint16_t, uint16_t
860#define OP_UUU_W uint32_t, uint32_t, uint32_t, uint32_t, uint32_t
861#define OP_UUU_D uint64_t, uint64_t, uint64_t, uint64_t, uint64_t
958b85f3
LZ		 862#define OP_SUS_B int8_t, uint8_t, int8_t, uint8_t, int8_t
863#define OP_SUS_H int16_t, uint16_t, int16_t, uint16_t, int16_t
864#define OP_SUS_W int32_t, uint32_t, int32_t, uint32_t, int32_t
865#define OP_SUS_D int64_t, uint64_t, int64_t, uint64_t, int64_t
97b1cba3
LZ		 866#define WOP_UUU_B uint16_t, uint8_t, uint8_t, uint16_t, uint16_t
867#define WOP_UUU_H uint32_t, uint16_t, uint16_t, uint32_t, uint32_t
868#define WOP_UUU_W uint64_t, uint32_t, uint32_t, uint64_t, uint64_t
869#define WOP_SSS_B int16_t, int8_t, int8_t, int16_t, int16_t
870#define WOP_SSS_H int32_t, int16_t, int16_t, int32_t, int32_t
871#define WOP_SSS_W int64_t, int32_t, int32_t, int64_t, int64_t
872#define WOP_SUS_B int16_t, uint8_t, int8_t, uint16_t, int16_t
873#define WOP_SUS_H int32_t, uint16_t, int16_t, uint32_t, int32_t
874#define WOP_SUS_W int64_t, uint32_t, int32_t, uint64_t, int64_t
875#define WOP_SSU_B int16_t, int8_t, uint8_t, int16_t, uint16_t
876#define WOP_SSU_H int32_t, int16_t, uint16_t, int32_t, uint32_t
877#define WOP_SSU_W int64_t, int32_t, uint32_t, int64_t, uint64_t
43740e3a
LZ		 878
879/* operation of two vector elements */
880typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i);
881
882#define OPIVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \
883static void do_##NAME(void *vd, void *vs1, void *vs2, int i) \
884{ \
885 TX1 s1 = *((T1 *)vs1 + HS1(i)); \
886 TX2 s2 = *((T2 *)vs2 + HS2(i)); \
887 *((TD *)vd + HD(i)) = OP(s2, s1); \
888}
889#define DO_SUB(N, M) (N - M)
890#define DO_RSUB(N, M) (M - N)
891
892RVVCALL(OPIVV2, vadd_vv_b, OP_SSS_B, H1, H1, H1, DO_ADD)
893RVVCALL(OPIVV2, vadd_vv_h, OP_SSS_H, H2, H2, H2, DO_ADD)
894RVVCALL(OPIVV2, vadd_vv_w, OP_SSS_W, H4, H4, H4, DO_ADD)
895RVVCALL(OPIVV2, vadd_vv_d, OP_SSS_D, H8, H8, H8, DO_ADD)
896RVVCALL(OPIVV2, vsub_vv_b, OP_SSS_B, H1, H1, H1, DO_SUB)
897RVVCALL(OPIVV2, vsub_vv_h, OP_SSS_H, H2, H2, H2, DO_SUB)
898RVVCALL(OPIVV2, vsub_vv_w, OP_SSS_W, H4, H4, H4, DO_SUB)
899RVVCALL(OPIVV2, vsub_vv_d, OP_SSS_D, H8, H8, H8, DO_SUB)
900
901static void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2,
902 CPURISCVState *env, uint32_t desc,
903 uint32_t esz, uint32_t dsz,
904 opivv2_fn *fn, clear_fn *clearfn)
905{
906 uint32_t vlmax = vext_maxsz(desc) / esz;
907 uint32_t mlen = vext_mlen(desc);
908 uint32_t vm = vext_vm(desc);
909 uint32_t vl = env->vl;
910 uint32_t i;
911
912 for (i = 0; i < vl; i++) {
913 if (!vm && !vext_elem_mask(v0, mlen, i)) {
914 continue;
915 }
916 fn(vd, vs1, vs2, i);
917 }
918 clearfn(vd, vl, vl * dsz, vlmax * dsz);
919}
920
921/* generate the helpers for OPIVV */
922#define GEN_VEXT_VV(NAME, ESZ, DSZ, CLEAR_FN) \
923void HELPER(NAME)(void *vd, void *v0, void *vs1, \
924 void *vs2, CPURISCVState *env, \
925 uint32_t desc) \
926{ \
927 do_vext_vv(vd, v0, vs1, vs2, env, desc, ESZ, DSZ, \
928 do_##NAME, CLEAR_FN); \
929}
930
931GEN_VEXT_VV(vadd_vv_b, 1, 1, clearb)
932GEN_VEXT_VV(vadd_vv_h, 2, 2, clearh)
933GEN_VEXT_VV(vadd_vv_w, 4, 4, clearl)
934GEN_VEXT_VV(vadd_vv_d, 8, 8, clearq)
935GEN_VEXT_VV(vsub_vv_b, 1, 1, clearb)
936GEN_VEXT_VV(vsub_vv_h, 2, 2, clearh)
937GEN_VEXT_VV(vsub_vv_w, 4, 4, clearl)
938GEN_VEXT_VV(vsub_vv_d, 8, 8, clearq)
939
940typedef void opivx2_fn(void *vd, target_long s1, void *vs2, int i);
941
942/*
943 * (T1)s1 gives the real operator type.
944 * (TX1)(T1)s1 expands the operator type of widen or narrow operations.
945 */
946#define OPIVX2(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \
947static void do_##NAME(void *vd, target_long s1, void *vs2, int i) \
948{ \
949 TX2 s2 = *((T2 *)vs2 + HS2(i)); \
950 *((TD *)vd + HD(i)) = OP(s2, (TX1)(T1)s1); \
951}
952
953RVVCALL(OPIVX2, vadd_vx_b, OP_SSS_B, H1, H1, DO_ADD)
954RVVCALL(OPIVX2, vadd_vx_h, OP_SSS_H, H2, H2, DO_ADD)
955RVVCALL(OPIVX2, vadd_vx_w, OP_SSS_W, H4, H4, DO_ADD)
956RVVCALL(OPIVX2, vadd_vx_d, OP_SSS_D, H8, H8, DO_ADD)
957RVVCALL(OPIVX2, vsub_vx_b, OP_SSS_B, H1, H1, DO_SUB)
958RVVCALL(OPIVX2, vsub_vx_h, OP_SSS_H, H2, H2, DO_SUB)
959RVVCALL(OPIVX2, vsub_vx_w, OP_SSS_W, H4, H4, DO_SUB)
960RVVCALL(OPIVX2, vsub_vx_d, OP_SSS_D, H8, H8, DO_SUB)
961RVVCALL(OPIVX2, vrsub_vx_b, OP_SSS_B, H1, H1, DO_RSUB)
962RVVCALL(OPIVX2, vrsub_vx_h, OP_SSS_H, H2, H2, DO_RSUB)
963RVVCALL(OPIVX2, vrsub_vx_w, OP_SSS_W, H4, H4, DO_RSUB)
964RVVCALL(OPIVX2, vrsub_vx_d, OP_SSS_D, H8, H8, DO_RSUB)
965
966static void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2,
967 CPURISCVState *env, uint32_t desc,
968 uint32_t esz, uint32_t dsz,
969 opivx2_fn fn, clear_fn *clearfn)
970{
971 uint32_t vlmax = vext_maxsz(desc) / esz;
972 uint32_t mlen = vext_mlen(desc);
973 uint32_t vm = vext_vm(desc);
974 uint32_t vl = env->vl;
975 uint32_t i;
976
977 for (i = 0; i < vl; i++) {
978 if (!vm && !vext_elem_mask(v0, mlen, i)) {
979 continue;
980 }
981 fn(vd, s1, vs2, i);
982 }
983 clearfn(vd, vl, vl * dsz, vlmax * dsz);
984}
985
986/* generate the helpers for OPIVX */
987#define GEN_VEXT_VX(NAME, ESZ, DSZ, CLEAR_FN) \
988void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
989 void *vs2, CPURISCVState *env, \
990 uint32_t desc) \
991{ \
992 do_vext_vx(vd, v0, s1, vs2, env, desc, ESZ, DSZ, \
993 do_##NAME, CLEAR_FN); \
994}
995
996GEN_VEXT_VX(vadd_vx_b, 1, 1, clearb)
997GEN_VEXT_VX(vadd_vx_h, 2, 2, clearh)
998GEN_VEXT_VX(vadd_vx_w, 4, 4, clearl)
999GEN_VEXT_VX(vadd_vx_d, 8, 8, clearq)
1000GEN_VEXT_VX(vsub_vx_b, 1, 1, clearb)
1001GEN_VEXT_VX(vsub_vx_h, 2, 2, clearh)
1002GEN_VEXT_VX(vsub_vx_w, 4, 4, clearl)
1003GEN_VEXT_VX(vsub_vx_d, 8, 8, clearq)
1004GEN_VEXT_VX(vrsub_vx_b, 1, 1, clearb)
1005GEN_VEXT_VX(vrsub_vx_h, 2, 2, clearh)
1006GEN_VEXT_VX(vrsub_vx_w, 4, 4, clearl)
1007GEN_VEXT_VX(vrsub_vx_d, 8, 8, clearq)
1008
1009void HELPER(vec_rsubs8)(void *d, void *a, uint64_t b, uint32_t desc)
1010{
1011 intptr_t oprsz = simd_oprsz(desc);
1012 intptr_t i;
1013
1014 for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
1015 *(uint8_t *)(d + i) = (uint8_t)b - *(uint8_t *)(a + i);
1016 }
1017}
1018
1019void HELPER(vec_rsubs16)(void *d, void *a, uint64_t b, uint32_t desc)
1020{
1021 intptr_t oprsz = simd_oprsz(desc);
1022 intptr_t i;
1023
1024 for (i = 0; i < oprsz; i += sizeof(uint16_t)) {
1025 *(uint16_t *)(d + i) = (uint16_t)b - *(uint16_t *)(a + i);
1026 }
1027}
1028
1029void HELPER(vec_rsubs32)(void *d, void *a, uint64_t b, uint32_t desc)
1030{
1031 intptr_t oprsz = simd_oprsz(desc);
1032 intptr_t i;
1033
1034 for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
1035 *(uint32_t *)(d + i) = (uint32_t)b - *(uint32_t *)(a + i);
1036 }
1037}
1038
1039void HELPER(vec_rsubs64)(void *d, void *a, uint64_t b, uint32_t desc)
1040{
1041 intptr_t oprsz = simd_oprsz(desc);
1042 intptr_t i;
1043
1044 for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
1045 *(uint64_t *)(d + i) = b - *(uint64_t *)(a + i);
1046 }
1047}
8fcdf776
LZ		 1048
1049/* Vector Widening Integer Add/Subtract */
1050#define WOP_UUU_B uint16_t, uint8_t, uint8_t, uint16_t, uint16_t
1051#define WOP_UUU_H uint32_t, uint16_t, uint16_t, uint32_t, uint32_t
1052#define WOP_UUU_W uint64_t, uint32_t, uint32_t, uint64_t, uint64_t
1053#define WOP_SSS_B int16_t, int8_t, int8_t, int16_t, int16_t
1054#define WOP_SSS_H int32_t, int16_t, int16_t, int32_t, int32_t
1055#define WOP_SSS_W int64_t, int32_t, int32_t, int64_t, int64_t
1056#define WOP_WUUU_B uint16_t, uint8_t, uint16_t, uint16_t, uint16_t
1057#define WOP_WUUU_H uint32_t, uint16_t, uint32_t, uint32_t, uint32_t
1058#define WOP_WUUU_W uint64_t, uint32_t, uint64_t, uint64_t, uint64_t
1059#define WOP_WSSS_B int16_t, int8_t, int16_t, int16_t, int16_t
1060#define WOP_WSSS_H int32_t, int16_t, int32_t, int32_t, int32_t
1061#define WOP_WSSS_W int64_t, int32_t, int64_t, int64_t, int64_t
1062RVVCALL(OPIVV2, vwaddu_vv_b, WOP_UUU_B, H2, H1, H1, DO_ADD)
1063RVVCALL(OPIVV2, vwaddu_vv_h, WOP_UUU_H, H4, H2, H2, DO_ADD)
1064RVVCALL(OPIVV2, vwaddu_vv_w, WOP_UUU_W, H8, H4, H4, DO_ADD)
1065RVVCALL(OPIVV2, vwsubu_vv_b, WOP_UUU_B, H2, H1, H1, DO_SUB)
1066RVVCALL(OPIVV2, vwsubu_vv_h, WOP_UUU_H, H4, H2, H2, DO_SUB)
1067RVVCALL(OPIVV2, vwsubu_vv_w, WOP_UUU_W, H8, H4, H4, DO_SUB)
1068RVVCALL(OPIVV2, vwadd_vv_b, WOP_SSS_B, H2, H1, H1, DO_ADD)
1069RVVCALL(OPIVV2, vwadd_vv_h, WOP_SSS_H, H4, H2, H2, DO_ADD)
1070RVVCALL(OPIVV2, vwadd_vv_w, WOP_SSS_W, H8, H4, H4, DO_ADD)
1071RVVCALL(OPIVV2, vwsub_vv_b, WOP_SSS_B, H2, H1, H1, DO_SUB)
1072RVVCALL(OPIVV2, vwsub_vv_h, WOP_SSS_H, H4, H2, H2, DO_SUB)
1073RVVCALL(OPIVV2, vwsub_vv_w, WOP_SSS_W, H8, H4, H4, DO_SUB)
1074RVVCALL(OPIVV2, vwaddu_wv_b, WOP_WUUU_B, H2, H1, H1, DO_ADD)
1075RVVCALL(OPIVV2, vwaddu_wv_h, WOP_WUUU_H, H4, H2, H2, DO_ADD)
1076RVVCALL(OPIVV2, vwaddu_wv_w, WOP_WUUU_W, H8, H4, H4, DO_ADD)
1077RVVCALL(OPIVV2, vwsubu_wv_b, WOP_WUUU_B, H2, H1, H1, DO_SUB)
1078RVVCALL(OPIVV2, vwsubu_wv_h, WOP_WUUU_H, H4, H2, H2, DO_SUB)
1079RVVCALL(OPIVV2, vwsubu_wv_w, WOP_WUUU_W, H8, H4, H4, DO_SUB)
1080RVVCALL(OPIVV2, vwadd_wv_b, WOP_WSSS_B, H2, H1, H1, DO_ADD)
1081RVVCALL(OPIVV2, vwadd_wv_h, WOP_WSSS_H, H4, H2, H2, DO_ADD)
1082RVVCALL(OPIVV2, vwadd_wv_w, WOP_WSSS_W, H8, H4, H4, DO_ADD)
1083RVVCALL(OPIVV2, vwsub_wv_b, WOP_WSSS_B, H2, H1, H1, DO_SUB)
1084RVVCALL(OPIVV2, vwsub_wv_h, WOP_WSSS_H, H4, H2, H2, DO_SUB)
1085RVVCALL(OPIVV2, vwsub_wv_w, WOP_WSSS_W, H8, H4, H4, DO_SUB)
1086GEN_VEXT_VV(vwaddu_vv_b, 1, 2, clearh)
1087GEN_VEXT_VV(vwaddu_vv_h, 2, 4, clearl)
1088GEN_VEXT_VV(vwaddu_vv_w, 4, 8, clearq)
1089GEN_VEXT_VV(vwsubu_vv_b, 1, 2, clearh)
1090GEN_VEXT_VV(vwsubu_vv_h, 2, 4, clearl)
1091GEN_VEXT_VV(vwsubu_vv_w, 4, 8, clearq)
1092GEN_VEXT_VV(vwadd_vv_b, 1, 2, clearh)
1093GEN_VEXT_VV(vwadd_vv_h, 2, 4, clearl)
1094GEN_VEXT_VV(vwadd_vv_w, 4, 8, clearq)
1095GEN_VEXT_VV(vwsub_vv_b, 1, 2, clearh)
1096GEN_VEXT_VV(vwsub_vv_h, 2, 4, clearl)
1097GEN_VEXT_VV(vwsub_vv_w, 4, 8, clearq)
1098GEN_VEXT_VV(vwaddu_wv_b, 1, 2, clearh)
1099GEN_VEXT_VV(vwaddu_wv_h, 2, 4, clearl)
1100GEN_VEXT_VV(vwaddu_wv_w, 4, 8, clearq)
1101GEN_VEXT_VV(vwsubu_wv_b, 1, 2, clearh)
1102GEN_VEXT_VV(vwsubu_wv_h, 2, 4, clearl)
1103GEN_VEXT_VV(vwsubu_wv_w, 4, 8, clearq)
1104GEN_VEXT_VV(vwadd_wv_b, 1, 2, clearh)
1105GEN_VEXT_VV(vwadd_wv_h, 2, 4, clearl)
1106GEN_VEXT_VV(vwadd_wv_w, 4, 8, clearq)
1107GEN_VEXT_VV(vwsub_wv_b, 1, 2, clearh)
1108GEN_VEXT_VV(vwsub_wv_h, 2, 4, clearl)
1109GEN_VEXT_VV(vwsub_wv_w, 4, 8, clearq)
1110
1111RVVCALL(OPIVX2, vwaddu_vx_b, WOP_UUU_B, H2, H1, DO_ADD)
1112RVVCALL(OPIVX2, vwaddu_vx_h, WOP_UUU_H, H4, H2, DO_ADD)
1113RVVCALL(OPIVX2, vwaddu_vx_w, WOP_UUU_W, H8, H4, DO_ADD)
1114RVVCALL(OPIVX2, vwsubu_vx_b, WOP_UUU_B, H2, H1, DO_SUB)
1115RVVCALL(OPIVX2, vwsubu_vx_h, WOP_UUU_H, H4, H2, DO_SUB)
1116RVVCALL(OPIVX2, vwsubu_vx_w, WOP_UUU_W, H8, H4, DO_SUB)
1117RVVCALL(OPIVX2, vwadd_vx_b, WOP_SSS_B, H2, H1, DO_ADD)
1118RVVCALL(OPIVX2, vwadd_vx_h, WOP_SSS_H, H4, H2, DO_ADD)
1119RVVCALL(OPIVX2, vwadd_vx_w, WOP_SSS_W, H8, H4, DO_ADD)
1120RVVCALL(OPIVX2, vwsub_vx_b, WOP_SSS_B, H2, H1, DO_SUB)
1121RVVCALL(OPIVX2, vwsub_vx_h, WOP_SSS_H, H4, H2, DO_SUB)
1122RVVCALL(OPIVX2, vwsub_vx_w, WOP_SSS_W, H8, H4, DO_SUB)
1123RVVCALL(OPIVX2, vwaddu_wx_b, WOP_WUUU_B, H2, H1, DO_ADD)
1124RVVCALL(OPIVX2, vwaddu_wx_h, WOP_WUUU_H, H4, H2, DO_ADD)
1125RVVCALL(OPIVX2, vwaddu_wx_w, WOP_WUUU_W, H8, H4, DO_ADD)
1126RVVCALL(OPIVX2, vwsubu_wx_b, WOP_WUUU_B, H2, H1, DO_SUB)
1127RVVCALL(OPIVX2, vwsubu_wx_h, WOP_WUUU_H, H4, H2, DO_SUB)
1128RVVCALL(OPIVX2, vwsubu_wx_w, WOP_WUUU_W, H8, H4, DO_SUB)
1129RVVCALL(OPIVX2, vwadd_wx_b, WOP_WSSS_B, H2, H1, DO_ADD)
1130RVVCALL(OPIVX2, vwadd_wx_h, WOP_WSSS_H, H4, H2, DO_ADD)
1131RVVCALL(OPIVX2, vwadd_wx_w, WOP_WSSS_W, H8, H4, DO_ADD)
1132RVVCALL(OPIVX2, vwsub_wx_b, WOP_WSSS_B, H2, H1, DO_SUB)
1133RVVCALL(OPIVX2, vwsub_wx_h, WOP_WSSS_H, H4, H2, DO_SUB)
1134RVVCALL(OPIVX2, vwsub_wx_w, WOP_WSSS_W, H8, H4, DO_SUB)
1135GEN_VEXT_VX(vwaddu_vx_b, 1, 2, clearh)
1136GEN_VEXT_VX(vwaddu_vx_h, 2, 4, clearl)
1137GEN_VEXT_VX(vwaddu_vx_w, 4, 8, clearq)
1138GEN_VEXT_VX(vwsubu_vx_b, 1, 2, clearh)
1139GEN_VEXT_VX(vwsubu_vx_h, 2, 4, clearl)
1140GEN_VEXT_VX(vwsubu_vx_w, 4, 8, clearq)
1141GEN_VEXT_VX(vwadd_vx_b, 1, 2, clearh)
1142GEN_VEXT_VX(vwadd_vx_h, 2, 4, clearl)
1143GEN_VEXT_VX(vwadd_vx_w, 4, 8, clearq)
1144GEN_VEXT_VX(vwsub_vx_b, 1, 2, clearh)
1145GEN_VEXT_VX(vwsub_vx_h, 2, 4, clearl)
1146GEN_VEXT_VX(vwsub_vx_w, 4, 8, clearq)
1147GEN_VEXT_VX(vwaddu_wx_b, 1, 2, clearh)
1148GEN_VEXT_VX(vwaddu_wx_h, 2, 4, clearl)
1149GEN_VEXT_VX(vwaddu_wx_w, 4, 8, clearq)
1150GEN_VEXT_VX(vwsubu_wx_b, 1, 2, clearh)
1151GEN_VEXT_VX(vwsubu_wx_h, 2, 4, clearl)
1152GEN_VEXT_VX(vwsubu_wx_w, 4, 8, clearq)
1153GEN_VEXT_VX(vwadd_wx_b, 1, 2, clearh)
1154GEN_VEXT_VX(vwadd_wx_h, 2, 4, clearl)
1155GEN_VEXT_VX(vwadd_wx_w, 4, 8, clearq)
1156GEN_VEXT_VX(vwsub_wx_b, 1, 2, clearh)
1157GEN_VEXT_VX(vwsub_wx_h, 2, 4, clearl)
1158GEN_VEXT_VX(vwsub_wx_w, 4, 8, clearq)
3a6f8f68
LZ		 1159
1160/* Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions */
1161#define DO_VADC(N, M, C) (N + M + C)
1162#define DO_VSBC(N, M, C) (N - M - C)
1163
1164#define GEN_VEXT_VADC_VVM(NAME, ETYPE, H, DO_OP, CLEAR_FN) \
1165void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
1166 CPURISCVState *env, uint32_t desc) \
1167{ \
1168 uint32_t mlen = vext_mlen(desc); \
1169 uint32_t vl = env->vl; \
1170 uint32_t esz = sizeof(ETYPE); \
1171 uint32_t vlmax = vext_maxsz(desc) / esz; \
1172 uint32_t i; \
1173 \
1174 for (i = 0; i < vl; i++) { \
1175 ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
1176 ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
1177 uint8_t carry = vext_elem_mask(v0, mlen, i); \
1178 \
1179 *((ETYPE *)vd + H(i)) = DO_OP(s2, s1, carry); \
1180 } \
1181 CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
1182}
1183
1184GEN_VEXT_VADC_VVM(vadc_vvm_b, uint8_t, H1, DO_VADC, clearb)
1185GEN_VEXT_VADC_VVM(vadc_vvm_h, uint16_t, H2, DO_VADC, clearh)
1186GEN_VEXT_VADC_VVM(vadc_vvm_w, uint32_t, H4, DO_VADC, clearl)
1187GEN_VEXT_VADC_VVM(vadc_vvm_d, uint64_t, H8, DO_VADC, clearq)
1188
1189GEN_VEXT_VADC_VVM(vsbc_vvm_b, uint8_t, H1, DO_VSBC, clearb)
1190GEN_VEXT_VADC_VVM(vsbc_vvm_h, uint16_t, H2, DO_VSBC, clearh)
1191GEN_VEXT_VADC_VVM(vsbc_vvm_w, uint32_t, H4, DO_VSBC, clearl)
1192GEN_VEXT_VADC_VVM(vsbc_vvm_d, uint64_t, H8, DO_VSBC, clearq)
1193
1194#define GEN_VEXT_VADC_VXM(NAME, ETYPE, H, DO_OP, CLEAR_FN) \
1195void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
1196 CPURISCVState *env, uint32_t desc) \
1197{ \
1198 uint32_t mlen = vext_mlen(desc); \
1199 uint32_t vl = env->vl; \
1200 uint32_t esz = sizeof(ETYPE); \
1201 uint32_t vlmax = vext_maxsz(desc) / esz; \
1202 uint32_t i; \
1203 \
1204 for (i = 0; i < vl; i++) { \
1205 ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
1206 uint8_t carry = vext_elem_mask(v0, mlen, i); \
1207 \
1208 *((ETYPE *)vd + H(i)) = DO_OP(s2, (ETYPE)(target_long)s1, carry);\
1209 } \
1210 CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
1211}
1212
1213GEN_VEXT_VADC_VXM(vadc_vxm_b, uint8_t, H1, DO_VADC, clearb)
1214GEN_VEXT_VADC_VXM(vadc_vxm_h, uint16_t, H2, DO_VADC, clearh)
1215GEN_VEXT_VADC_VXM(vadc_vxm_w, uint32_t, H4, DO_VADC, clearl)
1216GEN_VEXT_VADC_VXM(vadc_vxm_d, uint64_t, H8, DO_VADC, clearq)
1217
1218GEN_VEXT_VADC_VXM(vsbc_vxm_b, uint8_t, H1, DO_VSBC, clearb)
1219GEN_VEXT_VADC_VXM(vsbc_vxm_h, uint16_t, H2, DO_VSBC, clearh)
1220GEN_VEXT_VADC_VXM(vsbc_vxm_w, uint32_t, H4, DO_VSBC, clearl)
1221GEN_VEXT_VADC_VXM(vsbc_vxm_d, uint64_t, H8, DO_VSBC, clearq)
1222
1223#define DO_MADC(N, M, C) (C ? (__typeof(N))(N + M + 1) <= N : \
1224 (__typeof(N))(N + M) < N)
1225#define DO_MSBC(N, M, C) (C ? N <= M : N < M)
1226
1227#define GEN_VEXT_VMADC_VVM(NAME, ETYPE, H, DO_OP) \
1228void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
1229 CPURISCVState *env, uint32_t desc) \
1230{ \
1231 uint32_t mlen = vext_mlen(desc); \
1232 uint32_t vl = env->vl; \
1233 uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
1234 uint32_t i; \
1235 \
1236 for (i = 0; i < vl; i++) { \
1237 ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
1238 ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
1239 uint8_t carry = vext_elem_mask(v0, mlen, i); \
1240 \
1241 vext_set_elem_mask(vd, mlen, i, DO_OP(s2, s1, carry));\
1242 } \
1243 for (; i < vlmax; i++) { \
1244 vext_set_elem_mask(vd, mlen, i, 0); \
1245 } \
1246}
1247
1248GEN_VEXT_VMADC_VVM(vmadc_vvm_b, uint8_t, H1, DO_MADC)
1249GEN_VEXT_VMADC_VVM(vmadc_vvm_h, uint16_t, H2, DO_MADC)
1250GEN_VEXT_VMADC_VVM(vmadc_vvm_w, uint32_t, H4, DO_MADC)
1251GEN_VEXT_VMADC_VVM(vmadc_vvm_d, uint64_t, H8, DO_MADC)
1252
1253GEN_VEXT_VMADC_VVM(vmsbc_vvm_b, uint8_t, H1, DO_MSBC)
1254GEN_VEXT_VMADC_VVM(vmsbc_vvm_h, uint16_t, H2, DO_MSBC)
1255GEN_VEXT_VMADC_VVM(vmsbc_vvm_w, uint32_t, H4, DO_MSBC)
1256GEN_VEXT_VMADC_VVM(vmsbc_vvm_d, uint64_t, H8, DO_MSBC)
1257
1258#define GEN_VEXT_VMADC_VXM(NAME, ETYPE, H, DO_OP) \
1259void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
1260 void *vs2, CPURISCVState *env, uint32_t desc) \
1261{ \
1262 uint32_t mlen = vext_mlen(desc); \
1263 uint32_t vl = env->vl; \
1264 uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
1265 uint32_t i; \
1266 \
1267 for (i = 0; i < vl; i++) { \
1268 ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
1269 uint8_t carry = vext_elem_mask(v0, mlen, i); \
1270 \
1271 vext_set_elem_mask(vd, mlen, i, \
1272 DO_OP(s2, (ETYPE)(target_long)s1, carry)); \
1273 } \
1274 for (; i < vlmax; i++) { \
1275 vext_set_elem_mask(vd, mlen, i, 0); \
1276 } \
1277}
1278
1279GEN_VEXT_VMADC_VXM(vmadc_vxm_b, uint8_t, H1, DO_MADC)
1280GEN_VEXT_VMADC_VXM(vmadc_vxm_h, uint16_t, H2, DO_MADC)
1281GEN_VEXT_VMADC_VXM(vmadc_vxm_w, uint32_t, H4, DO_MADC)
1282GEN_VEXT_VMADC_VXM(vmadc_vxm_d, uint64_t, H8, DO_MADC)
1283
1284GEN_VEXT_VMADC_VXM(vmsbc_vxm_b, uint8_t, H1, DO_MSBC)
1285GEN_VEXT_VMADC_VXM(vmsbc_vxm_h, uint16_t, H2, DO_MSBC)
1286GEN_VEXT_VMADC_VXM(vmsbc_vxm_w, uint32_t, H4, DO_MSBC)
1287GEN_VEXT_VMADC_VXM(vmsbc_vxm_d, uint64_t, H8, DO_MSBC)
d3842924
LZ		 1288
1289/* Vector Bitwise Logical Instructions */
1290RVVCALL(OPIVV2, vand_vv_b, OP_SSS_B, H1, H1, H1, DO_AND)
1291RVVCALL(OPIVV2, vand_vv_h, OP_SSS_H, H2, H2, H2, DO_AND)
1292RVVCALL(OPIVV2, vand_vv_w, OP_SSS_W, H4, H4, H4, DO_AND)
1293RVVCALL(OPIVV2, vand_vv_d, OP_SSS_D, H8, H8, H8, DO_AND)
1294RVVCALL(OPIVV2, vor_vv_b, OP_SSS_B, H1, H1, H1, DO_OR)
1295RVVCALL(OPIVV2, vor_vv_h, OP_SSS_H, H2, H2, H2, DO_OR)
1296RVVCALL(OPIVV2, vor_vv_w, OP_SSS_W, H4, H4, H4, DO_OR)
1297RVVCALL(OPIVV2, vor_vv_d, OP_SSS_D, H8, H8, H8, DO_OR)
1298RVVCALL(OPIVV2, vxor_vv_b, OP_SSS_B, H1, H1, H1, DO_XOR)
1299RVVCALL(OPIVV2, vxor_vv_h, OP_SSS_H, H2, H2, H2, DO_XOR)
1300RVVCALL(OPIVV2, vxor_vv_w, OP_SSS_W, H4, H4, H4, DO_XOR)
1301RVVCALL(OPIVV2, vxor_vv_d, OP_SSS_D, H8, H8, H8, DO_XOR)
1302GEN_VEXT_VV(vand_vv_b, 1, 1, clearb)
1303GEN_VEXT_VV(vand_vv_h, 2, 2, clearh)
1304GEN_VEXT_VV(vand_vv_w, 4, 4, clearl)
1305GEN_VEXT_VV(vand_vv_d, 8, 8, clearq)
1306GEN_VEXT_VV(vor_vv_b, 1, 1, clearb)
1307GEN_VEXT_VV(vor_vv_h, 2, 2, clearh)
1308GEN_VEXT_VV(vor_vv_w, 4, 4, clearl)
1309GEN_VEXT_VV(vor_vv_d, 8, 8, clearq)
1310GEN_VEXT_VV(vxor_vv_b, 1, 1, clearb)
1311GEN_VEXT_VV(vxor_vv_h, 2, 2, clearh)
1312GEN_VEXT_VV(vxor_vv_w, 4, 4, clearl)
1313GEN_VEXT_VV(vxor_vv_d, 8, 8, clearq)
1314
1315RVVCALL(OPIVX2, vand_vx_b, OP_SSS_B, H1, H1, DO_AND)
1316RVVCALL(OPIVX2, vand_vx_h, OP_SSS_H, H2, H2, DO_AND)
1317RVVCALL(OPIVX2, vand_vx_w, OP_SSS_W, H4, H4, DO_AND)
1318RVVCALL(OPIVX2, vand_vx_d, OP_SSS_D, H8, H8, DO_AND)
1319RVVCALL(OPIVX2, vor_vx_b, OP_SSS_B, H1, H1, DO_OR)
1320RVVCALL(OPIVX2, vor_vx_h, OP_SSS_H, H2, H2, DO_OR)
1321RVVCALL(OPIVX2, vor_vx_w, OP_SSS_W, H4, H4, DO_OR)
1322RVVCALL(OPIVX2, vor_vx_d, OP_SSS_D, H8, H8, DO_OR)
1323RVVCALL(OPIVX2, vxor_vx_b, OP_SSS_B, H1, H1, DO_XOR)
1324RVVCALL(OPIVX2, vxor_vx_h, OP_SSS_H, H2, H2, DO_XOR)
1325RVVCALL(OPIVX2, vxor_vx_w, OP_SSS_W, H4, H4, DO_XOR)
1326RVVCALL(OPIVX2, vxor_vx_d, OP_SSS_D, H8, H8, DO_XOR)
1327GEN_VEXT_VX(vand_vx_b, 1, 1, clearb)
1328GEN_VEXT_VX(vand_vx_h, 2, 2, clearh)
1329GEN_VEXT_VX(vand_vx_w, 4, 4, clearl)
1330GEN_VEXT_VX(vand_vx_d, 8, 8, clearq)
1331GEN_VEXT_VX(vor_vx_b, 1, 1, clearb)
1332GEN_VEXT_VX(vor_vx_h, 2, 2, clearh)
1333GEN_VEXT_VX(vor_vx_w, 4, 4, clearl)
1334GEN_VEXT_VX(vor_vx_d, 8, 8, clearq)
1335GEN_VEXT_VX(vxor_vx_b, 1, 1, clearb)
1336GEN_VEXT_VX(vxor_vx_h, 2, 2, clearh)
1337GEN_VEXT_VX(vxor_vx_w, 4, 4, clearl)
1338GEN_VEXT_VX(vxor_vx_d, 8, 8, clearq)
3277d955
LZ		 1339
1340/* Vector Single-Width Bit Shift Instructions */
1341#define DO_SLL(N, M) (N << (M))
1342#define DO_SRL(N, M) (N >> (M))
1343
1344/* generate the helpers for shift instructions with two vector operators */
1345#define GEN_VEXT_SHIFT_VV(NAME, TS1, TS2, HS1, HS2, OP, MASK, CLEAR_FN) \
1346void HELPER(NAME)(void *vd, void *v0, void *vs1, \
1347 void *vs2, CPURISCVState *env, uint32_t desc) \
1348{ \
1349 uint32_t mlen = vext_mlen(desc); \
1350 uint32_t vm = vext_vm(desc); \
1351 uint32_t vl = env->vl; \
1352 uint32_t esz = sizeof(TS1); \
1353 uint32_t vlmax = vext_maxsz(desc) / esz; \
1354 uint32_t i; \
1355 \
1356 for (i = 0; i < vl; i++) { \
1357 if (!vm && !vext_elem_mask(v0, mlen, i)) { \
1358 continue; \
1359 } \
1360 TS1 s1 = *((TS1 *)vs1 + HS1(i)); \
1361 TS2 s2 = *((TS2 *)vs2 + HS2(i)); \
1362 *((TS1 *)vd + HS1(i)) = OP(s2, s1 & MASK); \
1363 } \
1364 CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
1365}
1366
1367GEN_VEXT_SHIFT_VV(vsll_vv_b, uint8_t, uint8_t, H1, H1, DO_SLL, 0x7, clearb)
1368GEN_VEXT_SHIFT_VV(vsll_vv_h, uint16_t, uint16_t, H2, H2, DO_SLL, 0xf, clearh)
1369GEN_VEXT_SHIFT_VV(vsll_vv_w, uint32_t, uint32_t, H4, H4, DO_SLL, 0x1f, clearl)
1370GEN_VEXT_SHIFT_VV(vsll_vv_d, uint64_t, uint64_t, H8, H8, DO_SLL, 0x3f, clearq)
1371
1372GEN_VEXT_SHIFT_VV(vsrl_vv_b, uint8_t, uint8_t, H1, H1, DO_SRL, 0x7, clearb)
1373GEN_VEXT_SHIFT_VV(vsrl_vv_h, uint16_t, uint16_t, H2, H2, DO_SRL, 0xf, clearh)
1374GEN_VEXT_SHIFT_VV(vsrl_vv_w, uint32_t, uint32_t, H4, H4, DO_SRL, 0x1f, clearl)
1375GEN_VEXT_SHIFT_VV(vsrl_vv_d, uint64_t, uint64_t, H8, H8, DO_SRL, 0x3f, clearq)
1376
1377GEN_VEXT_SHIFT_VV(vsra_vv_b, uint8_t, int8_t, H1, H1, DO_SRL, 0x7, clearb)
1378GEN_VEXT_SHIFT_VV(vsra_vv_h, uint16_t, int16_t, H2, H2, DO_SRL, 0xf, clearh)
1379GEN_VEXT_SHIFT_VV(vsra_vv_w, uint32_t, int32_t, H4, H4, DO_SRL, 0x1f, clearl)
1380GEN_VEXT_SHIFT_VV(vsra_vv_d, uint64_t, int64_t, H8, H8, DO_SRL, 0x3f, clearq)
1381
1382/* generate the helpers for shift instructions with one vector and one scalar */
1383#define GEN_VEXT_SHIFT_VX(NAME, TD, TS2, HD, HS2, OP, MASK, CLEAR_FN) \
1384void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
1385 void *vs2, CPURISCVState *env, uint32_t desc) \
1386{ \
1387 uint32_t mlen = vext_mlen(desc); \
1388 uint32_t vm = vext_vm(desc); \
1389 uint32_t vl = env->vl; \
1390 uint32_t esz = sizeof(TD); \
1391 uint32_t vlmax = vext_maxsz(desc) / esz; \
1392 uint32_t i; \
1393 \
1394 for (i = 0; i < vl; i++) { \
1395 if (!vm && !vext_elem_mask(v0, mlen, i)) { \
1396 continue; \
1397 } \
1398 TS2 s2 = *((TS2 *)vs2 + HS2(i)); \
1399 *((TD *)vd + HD(i)) = OP(s2, s1 & MASK); \
1400 } \
1401 CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
1402}
1403
1404GEN_VEXT_SHIFT_VX(vsll_vx_b, uint8_t, int8_t, H1, H1, DO_SLL, 0x7, clearb)
1405GEN_VEXT_SHIFT_VX(vsll_vx_h, uint16_t, int16_t, H2, H2, DO_SLL, 0xf, clearh)
1406GEN_VEXT_SHIFT_VX(vsll_vx_w, uint32_t, int32_t, H4, H4, DO_SLL, 0x1f, clearl)
1407GEN_VEXT_SHIFT_VX(vsll_vx_d, uint64_t, int64_t, H8, H8, DO_SLL, 0x3f, clearq)
1408
1409GEN_VEXT_SHIFT_VX(vsrl_vx_b, uint8_t, uint8_t, H1, H1, DO_SRL, 0x7, clearb)
1410GEN_VEXT_SHIFT_VX(vsrl_vx_h, uint16_t, uint16_t, H2, H2, DO_SRL, 0xf, clearh)
1411GEN_VEXT_SHIFT_VX(vsrl_vx_w, uint32_t, uint32_t, H4, H4, DO_SRL, 0x1f, clearl)
1412GEN_VEXT_SHIFT_VX(vsrl_vx_d, uint64_t, uint64_t, H8, H8, DO_SRL, 0x3f, clearq)
1413
1414GEN_VEXT_SHIFT_VX(vsra_vx_b, int8_t, int8_t, H1, H1, DO_SRL, 0x7, clearb)
1415GEN_VEXT_SHIFT_VX(vsra_vx_h, int16_t, int16_t, H2, H2, DO_SRL, 0xf, clearh)
1416GEN_VEXT_SHIFT_VX(vsra_vx_w, int32_t, int32_t, H4, H4, DO_SRL, 0x1f, clearl)
1417GEN_VEXT_SHIFT_VX(vsra_vx_d, int64_t, int64_t, H8, H8, DO_SRL, 0x3f, clearq)
7689b028
LZ		 1418
1419/* Vector Narrowing Integer Right Shift Instructions */
1420GEN_VEXT_SHIFT_VV(vnsrl_vv_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf, clearb)
1421GEN_VEXT_SHIFT_VV(vnsrl_vv_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f, clearh)
1422GEN_VEXT_SHIFT_VV(vnsrl_vv_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f, clearl)
1423GEN_VEXT_SHIFT_VV(vnsra_vv_b, uint8_t, int16_t, H1, H2, DO_SRL, 0xf, clearb)
1424GEN_VEXT_SHIFT_VV(vnsra_vv_h, uint16_t, int32_t, H2, H4, DO_SRL, 0x1f, clearh)
1425GEN_VEXT_SHIFT_VV(vnsra_vv_w, uint32_t, int64_t, H4, H8, DO_SRL, 0x3f, clearl)
1426GEN_VEXT_SHIFT_VX(vnsrl_vx_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf, clearb)
1427GEN_VEXT_SHIFT_VX(vnsrl_vx_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f, clearh)
1428GEN_VEXT_SHIFT_VX(vnsrl_vx_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f, clearl)
1429GEN_VEXT_SHIFT_VX(vnsra_vx_b, int8_t, int16_t, H1, H2, DO_SRL, 0xf, clearb)
1430GEN_VEXT_SHIFT_VX(vnsra_vx_h, int16_t, int32_t, H2, H4, DO_SRL, 0x1f, clearh)
1431GEN_VEXT_SHIFT_VX(vnsra_vx_w, int32_t, int64_t, H4, H8, DO_SRL, 0x3f, clearl)
1366fc79
LZ		 1432
1433/* Vector Integer Comparison Instructions */
1434#define DO_MSEQ(N, M) (N == M)
1435#define DO_MSNE(N, M) (N != M)
1436#define DO_MSLT(N, M) (N < M)
1437#define DO_MSLE(N, M) (N <= M)
1438#define DO_MSGT(N, M) (N > M)
1439
1440#define GEN_VEXT_CMP_VV(NAME, ETYPE, H, DO_OP) \
1441void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
1442 CPURISCVState *env, uint32_t desc) \
1443{ \
1444 uint32_t mlen = vext_mlen(desc); \
1445 uint32_t vm = vext_vm(desc); \
1446 uint32_t vl = env->vl; \
1447 uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
1448 uint32_t i; \
1449 \
1450 for (i = 0; i < vl; i++) { \
1451 ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
1452 ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
1453 if (!vm && !vext_elem_mask(v0, mlen, i)) { \
1454 continue; \
1455 } \
1456 vext_set_elem_mask(vd, mlen, i, DO_OP(s2, s1)); \
1457 } \
1458 for (; i < vlmax; i++) { \
1459 vext_set_elem_mask(vd, mlen, i, 0); \
1460 } \
1461}
1462
1463GEN_VEXT_CMP_VV(vmseq_vv_b, uint8_t, H1, DO_MSEQ)
1464GEN_VEXT_CMP_VV(vmseq_vv_h, uint16_t, H2, DO_MSEQ)
1465GEN_VEXT_CMP_VV(vmseq_vv_w, uint32_t, H4, DO_MSEQ)
1466GEN_VEXT_CMP_VV(vmseq_vv_d, uint64_t, H8, DO_MSEQ)
1467
1468GEN_VEXT_CMP_VV(vmsne_vv_b, uint8_t, H1, DO_MSNE)
1469GEN_VEXT_CMP_VV(vmsne_vv_h, uint16_t, H2, DO_MSNE)
1470GEN_VEXT_CMP_VV(vmsne_vv_w, uint32_t, H4, DO_MSNE)
1471GEN_VEXT_CMP_VV(vmsne_vv_d, uint64_t, H8, DO_MSNE)
1472
1473GEN_VEXT_CMP_VV(vmsltu_vv_b, uint8_t, H1, DO_MSLT)
1474GEN_VEXT_CMP_VV(vmsltu_vv_h, uint16_t, H2, DO_MSLT)
1475GEN_VEXT_CMP_VV(vmsltu_vv_w, uint32_t, H4, DO_MSLT)
1476GEN_VEXT_CMP_VV(vmsltu_vv_d, uint64_t, H8, DO_MSLT)
1477
1478GEN_VEXT_CMP_VV(vmslt_vv_b, int8_t, H1, DO_MSLT)
1479GEN_VEXT_CMP_VV(vmslt_vv_h, int16_t, H2, DO_MSLT)
1480GEN_VEXT_CMP_VV(vmslt_vv_w, int32_t, H4, DO_MSLT)
1481GEN_VEXT_CMP_VV(vmslt_vv_d, int64_t, H8, DO_MSLT)
1482
1483GEN_VEXT_CMP_VV(vmsleu_vv_b, uint8_t, H1, DO_MSLE)
1484GEN_VEXT_CMP_VV(vmsleu_vv_h, uint16_t, H2, DO_MSLE)
1485GEN_VEXT_CMP_VV(vmsleu_vv_w, uint32_t, H4, DO_MSLE)
1486GEN_VEXT_CMP_VV(vmsleu_vv_d, uint64_t, H8, DO_MSLE)
1487
1488GEN_VEXT_CMP_VV(vmsle_vv_b, int8_t, H1, DO_MSLE)
1489GEN_VEXT_CMP_VV(vmsle_vv_h, int16_t, H2, DO_MSLE)
1490GEN_VEXT_CMP_VV(vmsle_vv_w, int32_t, H4, DO_MSLE)
1491GEN_VEXT_CMP_VV(vmsle_vv_d, int64_t, H8, DO_MSLE)
1492
1493#define GEN_VEXT_CMP_VX(NAME, ETYPE, H, DO_OP) \
1494void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
1495 CPURISCVState *env, uint32_t desc) \
1496{ \
1497 uint32_t mlen = vext_mlen(desc); \
1498 uint32_t vm = vext_vm(desc); \
1499 uint32_t vl = env->vl; \
1500 uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
1501 uint32_t i; \
1502 \
1503 for (i = 0; i < vl; i++) { \
1504 ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
1505 if (!vm && !vext_elem_mask(v0, mlen, i)) { \
1506 continue; \
1507 } \
1508 vext_set_elem_mask(vd, mlen, i, \
1509 DO_OP(s2, (ETYPE)(target_long)s1)); \
1510 } \
1511 for (; i < vlmax; i++) { \
1512 vext_set_elem_mask(vd, mlen, i, 0); \
1513 } \
1514}
1515
1516GEN_VEXT_CMP_VX(vmseq_vx_b, uint8_t, H1, DO_MSEQ)
1517GEN_VEXT_CMP_VX(vmseq_vx_h, uint16_t, H2, DO_MSEQ)
1518GEN_VEXT_CMP_VX(vmseq_vx_w, uint32_t, H4, DO_MSEQ)
1519GEN_VEXT_CMP_VX(vmseq_vx_d, uint64_t, H8, DO_MSEQ)
1520
1521GEN_VEXT_CMP_VX(vmsne_vx_b, uint8_t, H1, DO_MSNE)
1522GEN_VEXT_CMP_VX(vmsne_vx_h, uint16_t, H2, DO_MSNE)
1523GEN_VEXT_CMP_VX(vmsne_vx_w, uint32_t, H4, DO_MSNE)
1524GEN_VEXT_CMP_VX(vmsne_vx_d, uint64_t, H8, DO_MSNE)
1525
1526GEN_VEXT_CMP_VX(vmsltu_vx_b, uint8_t, H1, DO_MSLT)
1527GEN_VEXT_CMP_VX(vmsltu_vx_h, uint16_t, H2, DO_MSLT)
1528GEN_VEXT_CMP_VX(vmsltu_vx_w, uint32_t, H4, DO_MSLT)
1529GEN_VEXT_CMP_VX(vmsltu_vx_d, uint64_t, H8, DO_MSLT)
1530
1531GEN_VEXT_CMP_VX(vmslt_vx_b, int8_t, H1, DO_MSLT)
1532GEN_VEXT_CMP_VX(vmslt_vx_h, int16_t, H2, DO_MSLT)
1533GEN_VEXT_CMP_VX(vmslt_vx_w, int32_t, H4, DO_MSLT)
1534GEN_VEXT_CMP_VX(vmslt_vx_d, int64_t, H8, DO_MSLT)
1535
1536GEN_VEXT_CMP_VX(vmsleu_vx_b, uint8_t, H1, DO_MSLE)
1537GEN_VEXT_CMP_VX(vmsleu_vx_h, uint16_t, H2, DO_MSLE)
1538GEN_VEXT_CMP_VX(vmsleu_vx_w, uint32_t, H4, DO_MSLE)
1539GEN_VEXT_CMP_VX(vmsleu_vx_d, uint64_t, H8, DO_MSLE)
1540
1541GEN_VEXT_CMP_VX(vmsle_vx_b, int8_t, H1, DO_MSLE)
1542GEN_VEXT_CMP_VX(vmsle_vx_h, int16_t, H2, DO_MSLE)
1543GEN_VEXT_CMP_VX(vmsle_vx_w, int32_t, H4, DO_MSLE)
1544GEN_VEXT_CMP_VX(vmsle_vx_d, int64_t, H8, DO_MSLE)
1545
1546GEN_VEXT_CMP_VX(vmsgtu_vx_b, uint8_t, H1, DO_MSGT)
1547GEN_VEXT_CMP_VX(vmsgtu_vx_h, uint16_t, H2, DO_MSGT)
1548GEN_VEXT_CMP_VX(vmsgtu_vx_w, uint32_t, H4, DO_MSGT)
1549GEN_VEXT_CMP_VX(vmsgtu_vx_d, uint64_t, H8, DO_MSGT)
1550
1551GEN_VEXT_CMP_VX(vmsgt_vx_b, int8_t, H1, DO_MSGT)
1552GEN_VEXT_CMP_VX(vmsgt_vx_h, int16_t, H2, DO_MSGT)
1553GEN_VEXT_CMP_VX(vmsgt_vx_w, int32_t, H4, DO_MSGT)
1554GEN_VEXT_CMP_VX(vmsgt_vx_d, int64_t, H8, DO_MSGT)
558fa779
LZ		 1555
1556/* Vector Integer Min/Max Instructions */
1557RVVCALL(OPIVV2, vminu_vv_b, OP_UUU_B, H1, H1, H1, DO_MIN)
1558RVVCALL(OPIVV2, vminu_vv_h, OP_UUU_H, H2, H2, H2, DO_MIN)
1559RVVCALL(OPIVV2, vminu_vv_w, OP_UUU_W, H4, H4, H4, DO_MIN)
1560RVVCALL(OPIVV2, vminu_vv_d, OP_UUU_D, H8, H8, H8, DO_MIN)
1561RVVCALL(OPIVV2, vmin_vv_b, OP_SSS_B, H1, H1, H1, DO_MIN)
1562RVVCALL(OPIVV2, vmin_vv_h, OP_SSS_H, H2, H2, H2, DO_MIN)
1563RVVCALL(OPIVV2, vmin_vv_w, OP_SSS_W, H4, H4, H4, DO_MIN)
1564RVVCALL(OPIVV2, vmin_vv_d, OP_SSS_D, H8, H8, H8, DO_MIN)
1565RVVCALL(OPIVV2, vmaxu_vv_b, OP_UUU_B, H1, H1, H1, DO_MAX)
1566RVVCALL(OPIVV2, vmaxu_vv_h, OP_UUU_H, H2, H2, H2, DO_MAX)
1567RVVCALL(OPIVV2, vmaxu_vv_w, OP_UUU_W, H4, H4, H4, DO_MAX)
1568RVVCALL(OPIVV2, vmaxu_vv_d, OP_UUU_D, H8, H8, H8, DO_MAX)
1569RVVCALL(OPIVV2, vmax_vv_b, OP_SSS_B, H1, H1, H1, DO_MAX)
1570RVVCALL(OPIVV2, vmax_vv_h, OP_SSS_H, H2, H2, H2, DO_MAX)
1571RVVCALL(OPIVV2, vmax_vv_w, OP_SSS_W, H4, H4, H4, DO_MAX)
1572RVVCALL(OPIVV2, vmax_vv_d, OP_SSS_D, H8, H8, H8, DO_MAX)
1573GEN_VEXT_VV(vminu_vv_b, 1, 1, clearb)
1574GEN_VEXT_VV(vminu_vv_h, 2, 2, clearh)
1575GEN_VEXT_VV(vminu_vv_w, 4, 4, clearl)
1576GEN_VEXT_VV(vminu_vv_d, 8, 8, clearq)
1577GEN_VEXT_VV(vmin_vv_b, 1, 1, clearb)
1578GEN_VEXT_VV(vmin_vv_h, 2, 2, clearh)
1579GEN_VEXT_VV(vmin_vv_w, 4, 4, clearl)
1580GEN_VEXT_VV(vmin_vv_d, 8, 8, clearq)
1581GEN_VEXT_VV(vmaxu_vv_b, 1, 1, clearb)
1582GEN_VEXT_VV(vmaxu_vv_h, 2, 2, clearh)
1583GEN_VEXT_VV(vmaxu_vv_w, 4, 4, clearl)
1584GEN_VEXT_VV(vmaxu_vv_d, 8, 8, clearq)
1585GEN_VEXT_VV(vmax_vv_b, 1, 1, clearb)
1586GEN_VEXT_VV(vmax_vv_h, 2, 2, clearh)
1587GEN_VEXT_VV(vmax_vv_w, 4, 4, clearl)
1588GEN_VEXT_VV(vmax_vv_d, 8, 8, clearq)
1589
1590RVVCALL(OPIVX2, vminu_vx_b, OP_UUU_B, H1, H1, DO_MIN)
1591RVVCALL(OPIVX2, vminu_vx_h, OP_UUU_H, H2, H2, DO_MIN)
1592RVVCALL(OPIVX2, vminu_vx_w, OP_UUU_W, H4, H4, DO_MIN)
1593RVVCALL(OPIVX2, vminu_vx_d, OP_UUU_D, H8, H8, DO_MIN)
1594RVVCALL(OPIVX2, vmin_vx_b, OP_SSS_B, H1, H1, DO_MIN)
1595RVVCALL(OPIVX2, vmin_vx_h, OP_SSS_H, H2, H2, DO_MIN)
1596RVVCALL(OPIVX2, vmin_vx_w, OP_SSS_W, H4, H4, DO_MIN)
1597RVVCALL(OPIVX2, vmin_vx_d, OP_SSS_D, H8, H8, DO_MIN)
1598RVVCALL(OPIVX2, vmaxu_vx_b, OP_UUU_B, H1, H1, DO_MAX)
1599RVVCALL(OPIVX2, vmaxu_vx_h, OP_UUU_H, H2, H2, DO_MAX)
1600RVVCALL(OPIVX2, vmaxu_vx_w, OP_UUU_W, H4, H4, DO_MAX)
1601RVVCALL(OPIVX2, vmaxu_vx_d, OP_UUU_D, H8, H8, DO_MAX)
1602RVVCALL(OPIVX2, vmax_vx_b, OP_SSS_B, H1, H1, DO_MAX)
1603RVVCALL(OPIVX2, vmax_vx_h, OP_SSS_H, H2, H2, DO_MAX)
1604RVVCALL(OPIVX2, vmax_vx_w, OP_SSS_W, H4, H4, DO_MAX)
1605RVVCALL(OPIVX2, vmax_vx_d, OP_SSS_D, H8, H8, DO_MAX)
1606GEN_VEXT_VX(vminu_vx_b, 1, 1, clearb)
1607GEN_VEXT_VX(vminu_vx_h, 2, 2, clearh)
1608GEN_VEXT_VX(vminu_vx_w, 4, 4, clearl)
1609GEN_VEXT_VX(vminu_vx_d, 8, 8, clearq)
1610GEN_VEXT_VX(vmin_vx_b, 1, 1, clearb)
1611GEN_VEXT_VX(vmin_vx_h, 2, 2, clearh)
1612GEN_VEXT_VX(vmin_vx_w, 4, 4, clearl)
1613GEN_VEXT_VX(vmin_vx_d, 8, 8, clearq)
1614GEN_VEXT_VX(vmaxu_vx_b, 1, 1, clearb)
1615GEN_VEXT_VX(vmaxu_vx_h, 2, 2, clearh)
1616GEN_VEXT_VX(vmaxu_vx_w, 4, 4, clearl)
1617GEN_VEXT_VX(vmaxu_vx_d, 8, 8, clearq)
1618GEN_VEXT_VX(vmax_vx_b, 1, 1, clearb)
1619GEN_VEXT_VX(vmax_vx_h, 2, 2, clearh)
1620GEN_VEXT_VX(vmax_vx_w, 4, 4, clearl)
1621GEN_VEXT_VX(vmax_vx_d, 8, 8, clearq)
958b85f3
LZ		 1622
1623/* Vector Single-Width Integer Multiply Instructions */
1624#define DO_MUL(N, M) (N * M)
1625RVVCALL(OPIVV2, vmul_vv_b, OP_SSS_B, H1, H1, H1, DO_MUL)
1626RVVCALL(OPIVV2, vmul_vv_h, OP_SSS_H, H2, H2, H2, DO_MUL)
1627RVVCALL(OPIVV2, vmul_vv_w, OP_SSS_W, H4, H4, H4, DO_MUL)
1628RVVCALL(OPIVV2, vmul_vv_d, OP_SSS_D, H8, H8, H8, DO_MUL)
1629GEN_VEXT_VV(vmul_vv_b, 1, 1, clearb)
1630GEN_VEXT_VV(vmul_vv_h, 2, 2, clearh)
1631GEN_VEXT_VV(vmul_vv_w, 4, 4, clearl)
1632GEN_VEXT_VV(vmul_vv_d, 8, 8, clearq)
1633
1634static int8_t do_mulh_b(int8_t s2, int8_t s1)
1635{
1636 return (int16_t)s2 * (int16_t)s1 >> 8;
1637}
1638
1639static int16_t do_mulh_h(int16_t s2, int16_t s1)
1640{
1641 return (int32_t)s2 * (int32_t)s1 >> 16;
1642}
1643
1644static int32_t do_mulh_w(int32_t s2, int32_t s1)
1645{
1646 return (int64_t)s2 * (int64_t)s1 >> 32;
1647}
1648
1649static int64_t do_mulh_d(int64_t s2, int64_t s1)
1650{
1651 uint64_t hi_64, lo_64;
1652
1653 muls64(&lo_64, &hi_64, s1, s2);
1654 return hi_64;
1655}
1656
1657static uint8_t do_mulhu_b(uint8_t s2, uint8_t s1)
1658{
1659 return (uint16_t)s2 * (uint16_t)s1 >> 8;
1660}
1661
1662static uint16_t do_mulhu_h(uint16_t s2, uint16_t s1)
1663{
1664 return (uint32_t)s2 * (uint32_t)s1 >> 16;
1665}
1666
1667static uint32_t do_mulhu_w(uint32_t s2, uint32_t s1)
1668{
1669 return (uint64_t)s2 * (uint64_t)s1 >> 32;
1670}
1671
1672static uint64_t do_mulhu_d(uint64_t s2, uint64_t s1)
1673{
1674 uint64_t hi_64, lo_64;
1675
1676 mulu64(&lo_64, &hi_64, s2, s1);
1677 return hi_64;
1678}
1679
1680static int8_t do_mulhsu_b(int8_t s2, uint8_t s1)
1681{
1682 return (int16_t)s2 * (uint16_t)s1 >> 8;
1683}
1684
1685static int16_t do_mulhsu_h(int16_t s2, uint16_t s1)
1686{
1687 return (int32_t)s2 * (uint32_t)s1 >> 16;
1688}
1689
1690static int32_t do_mulhsu_w(int32_t s2, uint32_t s1)
1691{
1692 return (int64_t)s2 * (uint64_t)s1 >> 32;
1693}
1694
1695/*
1696 * Let A = signed operand,
1697 * B = unsigned operand
1698 * P = mulu64(A, B), unsigned product
1699 *
1700 * LET X = 2 ** 64 - A, 2's complement of A
1701 * SP = signed product
1702 * THEN
1703 * IF A < 0
1704 * SP = -X * B
1705 * = -(2 ** 64 - A) * B
1706 * = A * B - 2 ** 64 * B
1707 * = P - 2 ** 64 * B
1708 * ELSE
1709 * SP = P
1710 * THEN
1711 * HI_P -= (A < 0 ? B : 0)
1712 */
1713
1714static int64_t do_mulhsu_d(int64_t s2, uint64_t s1)
1715{
1716 uint64_t hi_64, lo_64;
1717
1718 mulu64(&lo_64, &hi_64, s2, s1);
1719
1720 hi_64 -= s2 < 0 ? s1 : 0;
1721 return hi_64;
1722}
1723
1724RVVCALL(OPIVV2, vmulh_vv_b, OP_SSS_B, H1, H1, H1, do_mulh_b)
1725RVVCALL(OPIVV2, vmulh_vv_h, OP_SSS_H, H2, H2, H2, do_mulh_h)
1726RVVCALL(OPIVV2, vmulh_vv_w, OP_SSS_W, H4, H4, H4, do_mulh_w)
1727RVVCALL(OPIVV2, vmulh_vv_d, OP_SSS_D, H8, H8, H8, do_mulh_d)
1728RVVCALL(OPIVV2, vmulhu_vv_b, OP_UUU_B, H1, H1, H1, do_mulhu_b)
1729RVVCALL(OPIVV2, vmulhu_vv_h, OP_UUU_H, H2, H2, H2, do_mulhu_h)
1730RVVCALL(OPIVV2, vmulhu_vv_w, OP_UUU_W, H4, H4, H4, do_mulhu_w)
1731RVVCALL(OPIVV2, vmulhu_vv_d, OP_UUU_D, H8, H8, H8, do_mulhu_d)
1732RVVCALL(OPIVV2, vmulhsu_vv_b, OP_SUS_B, H1, H1, H1, do_mulhsu_b)
1733RVVCALL(OPIVV2, vmulhsu_vv_h, OP_SUS_H, H2, H2, H2, do_mulhsu_h)
1734RVVCALL(OPIVV2, vmulhsu_vv_w, OP_SUS_W, H4, H4, H4, do_mulhsu_w)
1735RVVCALL(OPIVV2, vmulhsu_vv_d, OP_SUS_D, H8, H8, H8, do_mulhsu_d)
1736GEN_VEXT_VV(vmulh_vv_b, 1, 1, clearb)
1737GEN_VEXT_VV(vmulh_vv_h, 2, 2, clearh)
1738GEN_VEXT_VV(vmulh_vv_w, 4, 4, clearl)
1739GEN_VEXT_VV(vmulh_vv_d, 8, 8, clearq)
1740GEN_VEXT_VV(vmulhu_vv_b, 1, 1, clearb)
1741GEN_VEXT_VV(vmulhu_vv_h, 2, 2, clearh)
1742GEN_VEXT_VV(vmulhu_vv_w, 4, 4, clearl)
1743GEN_VEXT_VV(vmulhu_vv_d, 8, 8, clearq)
1744GEN_VEXT_VV(vmulhsu_vv_b, 1, 1, clearb)
1745GEN_VEXT_VV(vmulhsu_vv_h, 2, 2, clearh)
1746GEN_VEXT_VV(vmulhsu_vv_w, 4, 4, clearl)
1747GEN_VEXT_VV(vmulhsu_vv_d, 8, 8, clearq)
1748
1749RVVCALL(OPIVX2, vmul_vx_b, OP_SSS_B, H1, H1, DO_MUL)
1750RVVCALL(OPIVX2, vmul_vx_h, OP_SSS_H, H2, H2, DO_MUL)
1751RVVCALL(OPIVX2, vmul_vx_w, OP_SSS_W, H4, H4, DO_MUL)
1752RVVCALL(OPIVX2, vmul_vx_d, OP_SSS_D, H8, H8, DO_MUL)
1753RVVCALL(OPIVX2, vmulh_vx_b, OP_SSS_B, H1, H1, do_mulh_b)
1754RVVCALL(OPIVX2, vmulh_vx_h, OP_SSS_H, H2, H2, do_mulh_h)
1755RVVCALL(OPIVX2, vmulh_vx_w, OP_SSS_W, H4, H4, do_mulh_w)
1756RVVCALL(OPIVX2, vmulh_vx_d, OP_SSS_D, H8, H8, do_mulh_d)
1757RVVCALL(OPIVX2, vmulhu_vx_b, OP_UUU_B, H1, H1, do_mulhu_b)
1758RVVCALL(OPIVX2, vmulhu_vx_h, OP_UUU_H, H2, H2, do_mulhu_h)
1759RVVCALL(OPIVX2, vmulhu_vx_w, OP_UUU_W, H4, H4, do_mulhu_w)
1760RVVCALL(OPIVX2, vmulhu_vx_d, OP_UUU_D, H8, H8, do_mulhu_d)
1761RVVCALL(OPIVX2, vmulhsu_vx_b, OP_SUS_B, H1, H1, do_mulhsu_b)
1762RVVCALL(OPIVX2, vmulhsu_vx_h, OP_SUS_H, H2, H2, do_mulhsu_h)
1763RVVCALL(OPIVX2, vmulhsu_vx_w, OP_SUS_W, H4, H4, do_mulhsu_w)
1764RVVCALL(OPIVX2, vmulhsu_vx_d, OP_SUS_D, H8, H8, do_mulhsu_d)
1765GEN_VEXT_VX(vmul_vx_b, 1, 1, clearb)
1766GEN_VEXT_VX(vmul_vx_h, 2, 2, clearh)
1767GEN_VEXT_VX(vmul_vx_w, 4, 4, clearl)
1768GEN_VEXT_VX(vmul_vx_d, 8, 8, clearq)
1769GEN_VEXT_VX(vmulh_vx_b, 1, 1, clearb)
1770GEN_VEXT_VX(vmulh_vx_h, 2, 2, clearh)
1771GEN_VEXT_VX(vmulh_vx_w, 4, 4, clearl)
1772GEN_VEXT_VX(vmulh_vx_d, 8, 8, clearq)
1773GEN_VEXT_VX(vmulhu_vx_b, 1, 1, clearb)
1774GEN_VEXT_VX(vmulhu_vx_h, 2, 2, clearh)
1775GEN_VEXT_VX(vmulhu_vx_w, 4, 4, clearl)
1776GEN_VEXT_VX(vmulhu_vx_d, 8, 8, clearq)
1777GEN_VEXT_VX(vmulhsu_vx_b, 1, 1, clearb)
1778GEN_VEXT_VX(vmulhsu_vx_h, 2, 2, clearh)
1779GEN_VEXT_VX(vmulhsu_vx_w, 4, 4, clearl)
1780GEN_VEXT_VX(vmulhsu_vx_d, 8, 8, clearq)
85e6658c
LZ		 1781
1782/* Vector Integer Divide Instructions */
1783#define DO_DIVU(N, M) (unlikely(M == 0) ? (__typeof(N))(-1) : N / M)
1784#define DO_REMU(N, M) (unlikely(M == 0) ? N : N % M)
1785#define DO_DIV(N, M) (unlikely(M == 0) ? (__typeof(N))(-1) :\
1786 unlikely((N == -N) && (M == (__typeof(N))(-1))) ? N : N / M)
1787#define DO_REM(N, M) (unlikely(M == 0) ? N :\
1788 unlikely((N == -N) && (M == (__typeof(N))(-1))) ? 0 : N % M)
1789
1790RVVCALL(OPIVV2, vdivu_vv_b, OP_UUU_B, H1, H1, H1, DO_DIVU)
1791RVVCALL(OPIVV2, vdivu_vv_h, OP_UUU_H, H2, H2, H2, DO_DIVU)
1792RVVCALL(OPIVV2, vdivu_vv_w, OP_UUU_W, H4, H4, H4, DO_DIVU)
1793RVVCALL(OPIVV2, vdivu_vv_d, OP_UUU_D, H8, H8, H8, DO_DIVU)
1794RVVCALL(OPIVV2, vdiv_vv_b, OP_SSS_B, H1, H1, H1, DO_DIV)
1795RVVCALL(OPIVV2, vdiv_vv_h, OP_SSS_H, H2, H2, H2, DO_DIV)
1796RVVCALL(OPIVV2, vdiv_vv_w, OP_SSS_W, H4, H4, H4, DO_DIV)
1797RVVCALL(OPIVV2, vdiv_vv_d, OP_SSS_D, H8, H8, H8, DO_DIV)
1798RVVCALL(OPIVV2, vremu_vv_b, OP_UUU_B, H1, H1, H1, DO_REMU)
1799RVVCALL(OPIVV2, vremu_vv_h, OP_UUU_H, H2, H2, H2, DO_REMU)
1800RVVCALL(OPIVV2, vremu_vv_w, OP_UUU_W, H4, H4, H4, DO_REMU)
1801RVVCALL(OPIVV2, vremu_vv_d, OP_UUU_D, H8, H8, H8, DO_REMU)
1802RVVCALL(OPIVV2, vrem_vv_b, OP_SSS_B, H1, H1, H1, DO_REM)
1803RVVCALL(OPIVV2, vrem_vv_h, OP_SSS_H, H2, H2, H2, DO_REM)
1804RVVCALL(OPIVV2, vrem_vv_w, OP_SSS_W, H4, H4, H4, DO_REM)
1805RVVCALL(OPIVV2, vrem_vv_d, OP_SSS_D, H8, H8, H8, DO_REM)
1806GEN_VEXT_VV(vdivu_vv_b, 1, 1, clearb)
1807GEN_VEXT_VV(vdivu_vv_h, 2, 2, clearh)
1808GEN_VEXT_VV(vdivu_vv_w, 4, 4, clearl)
1809GEN_VEXT_VV(vdivu_vv_d, 8, 8, clearq)
1810GEN_VEXT_VV(vdiv_vv_b, 1, 1, clearb)
1811GEN_VEXT_VV(vdiv_vv_h, 2, 2, clearh)
1812GEN_VEXT_VV(vdiv_vv_w, 4, 4, clearl)
1813GEN_VEXT_VV(vdiv_vv_d, 8, 8, clearq)
1814GEN_VEXT_VV(vremu_vv_b, 1, 1, clearb)
1815GEN_VEXT_VV(vremu_vv_h, 2, 2, clearh)
1816GEN_VEXT_VV(vremu_vv_w, 4, 4, clearl)
1817GEN_VEXT_VV(vremu_vv_d, 8, 8, clearq)
1818GEN_VEXT_VV(vrem_vv_b, 1, 1, clearb)
1819GEN_VEXT_VV(vrem_vv_h, 2, 2, clearh)
1820GEN_VEXT_VV(vrem_vv_w, 4, 4, clearl)
1821GEN_VEXT_VV(vrem_vv_d, 8, 8, clearq)
1822
1823RVVCALL(OPIVX2, vdivu_vx_b, OP_UUU_B, H1, H1, DO_DIVU)
1824RVVCALL(OPIVX2, vdivu_vx_h, OP_UUU_H, H2, H2, DO_DIVU)
1825RVVCALL(OPIVX2, vdivu_vx_w, OP_UUU_W, H4, H4, DO_DIVU)
1826RVVCALL(OPIVX2, vdivu_vx_d, OP_UUU_D, H8, H8, DO_DIVU)
1827RVVCALL(OPIVX2, vdiv_vx_b, OP_SSS_B, H1, H1, DO_DIV)
1828RVVCALL(OPIVX2, vdiv_vx_h, OP_SSS_H, H2, H2, DO_DIV)
1829RVVCALL(OPIVX2, vdiv_vx_w, OP_SSS_W, H4, H4, DO_DIV)
1830RVVCALL(OPIVX2, vdiv_vx_d, OP_SSS_D, H8, H8, DO_DIV)
1831RVVCALL(OPIVX2, vremu_vx_b, OP_UUU_B, H1, H1, DO_REMU)
1832RVVCALL(OPIVX2, vremu_vx_h, OP_UUU_H, H2, H2, DO_REMU)
1833RVVCALL(OPIVX2, vremu_vx_w, OP_UUU_W, H4, H4, DO_REMU)
1834RVVCALL(OPIVX2, vremu_vx_d, OP_UUU_D, H8, H8, DO_REMU)
1835RVVCALL(OPIVX2, vrem_vx_b, OP_SSS_B, H1, H1, DO_REM)
1836RVVCALL(OPIVX2, vrem_vx_h, OP_SSS_H, H2, H2, DO_REM)
1837RVVCALL(OPIVX2, vrem_vx_w, OP_SSS_W, H4, H4, DO_REM)
1838RVVCALL(OPIVX2, vrem_vx_d, OP_SSS_D, H8, H8, DO_REM)
1839GEN_VEXT_VX(vdivu_vx_b, 1, 1, clearb)
1840GEN_VEXT_VX(vdivu_vx_h, 2, 2, clearh)
1841GEN_VEXT_VX(vdivu_vx_w, 4, 4, clearl)
1842GEN_VEXT_VX(vdivu_vx_d, 8, 8, clearq)
1843GEN_VEXT_VX(vdiv_vx_b, 1, 1, clearb)
1844GEN_VEXT_VX(vdiv_vx_h, 2, 2, clearh)
1845GEN_VEXT_VX(vdiv_vx_w, 4, 4, clearl)
1846GEN_VEXT_VX(vdiv_vx_d, 8, 8, clearq)
1847GEN_VEXT_VX(vremu_vx_b, 1, 1, clearb)
1848GEN_VEXT_VX(vremu_vx_h, 2, 2, clearh)
1849GEN_VEXT_VX(vremu_vx_w, 4, 4, clearl)
1850GEN_VEXT_VX(vremu_vx_d, 8, 8, clearq)
1851GEN_VEXT_VX(vrem_vx_b, 1, 1, clearb)
1852GEN_VEXT_VX(vrem_vx_h, 2, 2, clearh)
1853GEN_VEXT_VX(vrem_vx_w, 4, 4, clearl)
1854GEN_VEXT_VX(vrem_vx_d, 8, 8, clearq)
97b1cba3
LZ		 1855
1856/* Vector Widening Integer Multiply Instructions */
1857RVVCALL(OPIVV2, vwmul_vv_b, WOP_SSS_B, H2, H1, H1, DO_MUL)
1858RVVCALL(OPIVV2, vwmul_vv_h, WOP_SSS_H, H4, H2, H2, DO_MUL)
1859RVVCALL(OPIVV2, vwmul_vv_w, WOP_SSS_W, H8, H4, H4, DO_MUL)
1860RVVCALL(OPIVV2, vwmulu_vv_b, WOP_UUU_B, H2, H1, H1, DO_MUL)
1861RVVCALL(OPIVV2, vwmulu_vv_h, WOP_UUU_H, H4, H2, H2, DO_MUL)
1862RVVCALL(OPIVV2, vwmulu_vv_w, WOP_UUU_W, H8, H4, H4, DO_MUL)
1863RVVCALL(OPIVV2, vwmulsu_vv_b, WOP_SUS_B, H2, H1, H1, DO_MUL)
1864RVVCALL(OPIVV2, vwmulsu_vv_h, WOP_SUS_H, H4, H2, H2, DO_MUL)
1865RVVCALL(OPIVV2, vwmulsu_vv_w, WOP_SUS_W, H8, H4, H4, DO_MUL)
1866GEN_VEXT_VV(vwmul_vv_b, 1, 2, clearh)
1867GEN_VEXT_VV(vwmul_vv_h, 2, 4, clearl)
1868GEN_VEXT_VV(vwmul_vv_w, 4, 8, clearq)
1869GEN_VEXT_VV(vwmulu_vv_b, 1, 2, clearh)
1870GEN_VEXT_VV(vwmulu_vv_h, 2, 4, clearl)
1871GEN_VEXT_VV(vwmulu_vv_w, 4, 8, clearq)
1872GEN_VEXT_VV(vwmulsu_vv_b, 1, 2, clearh)
1873GEN_VEXT_VV(vwmulsu_vv_h, 2, 4, clearl)
1874GEN_VEXT_VV(vwmulsu_vv_w, 4, 8, clearq)
1875
1876RVVCALL(OPIVX2, vwmul_vx_b, WOP_SSS_B, H2, H1, DO_MUL)
1877RVVCALL(OPIVX2, vwmul_vx_h, WOP_SSS_H, H4, H2, DO_MUL)
1878RVVCALL(OPIVX2, vwmul_vx_w, WOP_SSS_W, H8, H4, DO_MUL)
1879RVVCALL(OPIVX2, vwmulu_vx_b, WOP_UUU_B, H2, H1, DO_MUL)
1880RVVCALL(OPIVX2, vwmulu_vx_h, WOP_UUU_H, H4, H2, DO_MUL)
1881RVVCALL(OPIVX2, vwmulu_vx_w, WOP_UUU_W, H8, H4, DO_MUL)
1882RVVCALL(OPIVX2, vwmulsu_vx_b, WOP_SUS_B, H2, H1, DO_MUL)
1883RVVCALL(OPIVX2, vwmulsu_vx_h, WOP_SUS_H, H4, H2, DO_MUL)
1884RVVCALL(OPIVX2, vwmulsu_vx_w, WOP_SUS_W, H8, H4, DO_MUL)
1885GEN_VEXT_VX(vwmul_vx_b, 1, 2, clearh)
1886GEN_VEXT_VX(vwmul_vx_h, 2, 4, clearl)
1887GEN_VEXT_VX(vwmul_vx_w, 4, 8, clearq)
1888GEN_VEXT_VX(vwmulu_vx_b, 1, 2, clearh)
1889GEN_VEXT_VX(vwmulu_vx_h, 2, 4, clearl)
1890GEN_VEXT_VX(vwmulu_vx_w, 4, 8, clearq)
1891GEN_VEXT_VX(vwmulsu_vx_b, 1, 2, clearh)
1892GEN_VEXT_VX(vwmulsu_vx_h, 2, 4, clearl)
1893GEN_VEXT_VX(vwmulsu_vx_w, 4, 8, clearq)
54df813a
LZ		 1894
1895/* Vector Single-Width Integer Multiply-Add Instructions */
1896#define OPIVV3(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \
1897static void do_##NAME(void *vd, void *vs1, void *vs2, int i) \
1898{ \
1899 TX1 s1 = *((T1 *)vs1 + HS1(i)); \
1900 TX2 s2 = *((T2 *)vs2 + HS2(i)); \
1901 TD d = *((TD *)vd + HD(i)); \
1902 *((TD *)vd + HD(i)) = OP(s2, s1, d); \
1903}
1904
1905#define DO_MACC(N, M, D) (M * N + D)
1906#define DO_NMSAC(N, M, D) (-(M * N) + D)
1907#define DO_MADD(N, M, D) (M * D + N)
1908#define DO_NMSUB(N, M, D) (-(M * D) + N)
1909RVVCALL(OPIVV3, vmacc_vv_b, OP_SSS_B, H1, H1, H1, DO_MACC)
1910RVVCALL(OPIVV3, vmacc_vv_h, OP_SSS_H, H2, H2, H2, DO_MACC)
1911RVVCALL(OPIVV3, vmacc_vv_w, OP_SSS_W, H4, H4, H4, DO_MACC)
1912RVVCALL(OPIVV3, vmacc_vv_d, OP_SSS_D, H8, H8, H8, DO_MACC)
1913RVVCALL(OPIVV3, vnmsac_vv_b, OP_SSS_B, H1, H1, H1, DO_NMSAC)
1914RVVCALL(OPIVV3, vnmsac_vv_h, OP_SSS_H, H2, H2, H2, DO_NMSAC)
1915RVVCALL(OPIVV3, vnmsac_vv_w, OP_SSS_W, H4, H4, H4, DO_NMSAC)
1916RVVCALL(OPIVV3, vnmsac_vv_d, OP_SSS_D, H8, H8, H8, DO_NMSAC)
1917RVVCALL(OPIVV3, vmadd_vv_b, OP_SSS_B, H1, H1, H1, DO_MADD)
1918RVVCALL(OPIVV3, vmadd_vv_h, OP_SSS_H, H2, H2, H2, DO_MADD)
1919RVVCALL(OPIVV3, vmadd_vv_w, OP_SSS_W, H4, H4, H4, DO_MADD)
1920RVVCALL(OPIVV3, vmadd_vv_d, OP_SSS_D, H8, H8, H8, DO_MADD)
1921RVVCALL(OPIVV3, vnmsub_vv_b, OP_SSS_B, H1, H1, H1, DO_NMSUB)
1922RVVCALL(OPIVV3, vnmsub_vv_h, OP_SSS_H, H2, H2, H2, DO_NMSUB)
1923RVVCALL(OPIVV3, vnmsub_vv_w, OP_SSS_W, H4, H4, H4, DO_NMSUB)
1924RVVCALL(OPIVV3, vnmsub_vv_d, OP_SSS_D, H8, H8, H8, DO_NMSUB)
1925GEN_VEXT_VV(vmacc_vv_b, 1, 1, clearb)
1926GEN_VEXT_VV(vmacc_vv_h, 2, 2, clearh)
1927GEN_VEXT_VV(vmacc_vv_w, 4, 4, clearl)
1928GEN_VEXT_VV(vmacc_vv_d, 8, 8, clearq)
1929GEN_VEXT_VV(vnmsac_vv_b, 1, 1, clearb)
1930GEN_VEXT_VV(vnmsac_vv_h, 2, 2, clearh)
1931GEN_VEXT_VV(vnmsac_vv_w, 4, 4, clearl)
1932GEN_VEXT_VV(vnmsac_vv_d, 8, 8, clearq)
1933GEN_VEXT_VV(vmadd_vv_b, 1, 1, clearb)
1934GEN_VEXT_VV(vmadd_vv_h, 2, 2, clearh)
1935GEN_VEXT_VV(vmadd_vv_w, 4, 4, clearl)
1936GEN_VEXT_VV(vmadd_vv_d, 8, 8, clearq)
1937GEN_VEXT_VV(vnmsub_vv_b, 1, 1, clearb)
1938GEN_VEXT_VV(vnmsub_vv_h, 2, 2, clearh)
1939GEN_VEXT_VV(vnmsub_vv_w, 4, 4, clearl)
1940GEN_VEXT_VV(vnmsub_vv_d, 8, 8, clearq)
1941
1942#define OPIVX3(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \
1943static void do_##NAME(void *vd, target_long s1, void *vs2, int i) \
1944{ \
1945 TX2 s2 = *((T2 *)vs2 + HS2(i)); \
1946 TD d = *((TD *)vd + HD(i)); \
1947 *((TD *)vd + HD(i)) = OP(s2, (TX1)(T1)s1, d); \
1948}
1949
1950RVVCALL(OPIVX3, vmacc_vx_b, OP_SSS_B, H1, H1, DO_MACC)
1951RVVCALL(OPIVX3, vmacc_vx_h, OP_SSS_H, H2, H2, DO_MACC)
1952RVVCALL(OPIVX3, vmacc_vx_w, OP_SSS_W, H4, H4, DO_MACC)
1953RVVCALL(OPIVX3, vmacc_vx_d, OP_SSS_D, H8, H8, DO_MACC)
1954RVVCALL(OPIVX3, vnmsac_vx_b, OP_SSS_B, H1, H1, DO_NMSAC)
1955RVVCALL(OPIVX3, vnmsac_vx_h, OP_SSS_H, H2, H2, DO_NMSAC)
1956RVVCALL(OPIVX3, vnmsac_vx_w, OP_SSS_W, H4, H4, DO_NMSAC)
1957RVVCALL(OPIVX3, vnmsac_vx_d, OP_SSS_D, H8, H8, DO_NMSAC)
1958RVVCALL(OPIVX3, vmadd_vx_b, OP_SSS_B, H1, H1, DO_MADD)
1959RVVCALL(OPIVX3, vmadd_vx_h, OP_SSS_H, H2, H2, DO_MADD)
1960RVVCALL(OPIVX3, vmadd_vx_w, OP_SSS_W, H4, H4, DO_MADD)
1961RVVCALL(OPIVX3, vmadd_vx_d, OP_SSS_D, H8, H8, DO_MADD)
1962RVVCALL(OPIVX3, vnmsub_vx_b, OP_SSS_B, H1, H1, DO_NMSUB)
1963RVVCALL(OPIVX3, vnmsub_vx_h, OP_SSS_H, H2, H2, DO_NMSUB)
1964RVVCALL(OPIVX3, vnmsub_vx_w, OP_SSS_W, H4, H4, DO_NMSUB)
1965RVVCALL(OPIVX3, vnmsub_vx_d, OP_SSS_D, H8, H8, DO_NMSUB)
1966GEN_VEXT_VX(vmacc_vx_b, 1, 1, clearb)
1967GEN_VEXT_VX(vmacc_vx_h, 2, 2, clearh)
1968GEN_VEXT_VX(vmacc_vx_w, 4, 4, clearl)
1969GEN_VEXT_VX(vmacc_vx_d, 8, 8, clearq)
1970GEN_VEXT_VX(vnmsac_vx_b, 1, 1, clearb)
1971GEN_VEXT_VX(vnmsac_vx_h, 2, 2, clearh)
1972GEN_VEXT_VX(vnmsac_vx_w, 4, 4, clearl)
1973GEN_VEXT_VX(vnmsac_vx_d, 8, 8, clearq)
1974GEN_VEXT_VX(vmadd_vx_b, 1, 1, clearb)
1975GEN_VEXT_VX(vmadd_vx_h, 2, 2, clearh)
1976GEN_VEXT_VX(vmadd_vx_w, 4, 4, clearl)
1977GEN_VEXT_VX(vmadd_vx_d, 8, 8, clearq)
1978GEN_VEXT_VX(vnmsub_vx_b, 1, 1, clearb)
1979GEN_VEXT_VX(vnmsub_vx_h, 2, 2, clearh)
1980GEN_VEXT_VX(vnmsub_vx_w, 4, 4, clearl)
1981GEN_VEXT_VX(vnmsub_vx_d, 8, 8, clearq)
2b587b33
LZ		 1982
1983/* Vector Widening Integer Multiply-Add Instructions */
1984RVVCALL(OPIVV3, vwmaccu_vv_b, WOP_UUU_B, H2, H1, H1, DO_MACC)
1985RVVCALL(OPIVV3, vwmaccu_vv_h, WOP_UUU_H, H4, H2, H2, DO_MACC)
1986RVVCALL(OPIVV3, vwmaccu_vv_w, WOP_UUU_W, H8, H4, H4, DO_MACC)
1987RVVCALL(OPIVV3, vwmacc_vv_b, WOP_SSS_B, H2, H1, H1, DO_MACC)
1988RVVCALL(OPIVV3, vwmacc_vv_h, WOP_SSS_H, H4, H2, H2, DO_MACC)
1989RVVCALL(OPIVV3, vwmacc_vv_w, WOP_SSS_W, H8, H4, H4, DO_MACC)
1990RVVCALL(OPIVV3, vwmaccsu_vv_b, WOP_SSU_B, H2, H1, H1, DO_MACC)
1991RVVCALL(OPIVV3, vwmaccsu_vv_h, WOP_SSU_H, H4, H2, H2, DO_MACC)
1992RVVCALL(OPIVV3, vwmaccsu_vv_w, WOP_SSU_W, H8, H4, H4, DO_MACC)
1993GEN_VEXT_VV(vwmaccu_vv_b, 1, 2, clearh)
1994GEN_VEXT_VV(vwmaccu_vv_h, 2, 4, clearl)
1995GEN_VEXT_VV(vwmaccu_vv_w, 4, 8, clearq)
1996GEN_VEXT_VV(vwmacc_vv_b, 1, 2, clearh)
1997GEN_VEXT_VV(vwmacc_vv_h, 2, 4, clearl)
1998GEN_VEXT_VV(vwmacc_vv_w, 4, 8, clearq)
1999GEN_VEXT_VV(vwmaccsu_vv_b, 1, 2, clearh)
2000GEN_VEXT_VV(vwmaccsu_vv_h, 2, 4, clearl)
2001GEN_VEXT_VV(vwmaccsu_vv_w, 4, 8, clearq)
2002
2003RVVCALL(OPIVX3, vwmaccu_vx_b, WOP_UUU_B, H2, H1, DO_MACC)
2004RVVCALL(OPIVX3, vwmaccu_vx_h, WOP_UUU_H, H4, H2, DO_MACC)
2005RVVCALL(OPIVX3, vwmaccu_vx_w, WOP_UUU_W, H8, H4, DO_MACC)
2006RVVCALL(OPIVX3, vwmacc_vx_b, WOP_SSS_B, H2, H1, DO_MACC)
2007RVVCALL(OPIVX3, vwmacc_vx_h, WOP_SSS_H, H4, H2, DO_MACC)
2008RVVCALL(OPIVX3, vwmacc_vx_w, WOP_SSS_W, H8, H4, DO_MACC)
2009RVVCALL(OPIVX3, vwmaccsu_vx_b, WOP_SSU_B, H2, H1, DO_MACC)
2010RVVCALL(OPIVX3, vwmaccsu_vx_h, WOP_SSU_H, H4, H2, DO_MACC)
2011RVVCALL(OPIVX3, vwmaccsu_vx_w, WOP_SSU_W, H8, H4, DO_MACC)
2012RVVCALL(OPIVX3, vwmaccus_vx_b, WOP_SUS_B, H2, H1, DO_MACC)
2013RVVCALL(OPIVX3, vwmaccus_vx_h, WOP_SUS_H, H4, H2, DO_MACC)
2014RVVCALL(OPIVX3, vwmaccus_vx_w, WOP_SUS_W, H8, H4, DO_MACC)
2015GEN_VEXT_VX(vwmaccu_vx_b, 1, 2, clearh)
2016GEN_VEXT_VX(vwmaccu_vx_h, 2, 4, clearl)
2017GEN_VEXT_VX(vwmaccu_vx_w, 4, 8, clearq)
2018GEN_VEXT_VX(vwmacc_vx_b, 1, 2, clearh)
2019GEN_VEXT_VX(vwmacc_vx_h, 2, 4, clearl)
2020GEN_VEXT_VX(vwmacc_vx_w, 4, 8, clearq)
2021GEN_VEXT_VX(vwmaccsu_vx_b, 1, 2, clearh)
2022GEN_VEXT_VX(vwmaccsu_vx_h, 2, 4, clearl)
2023GEN_VEXT_VX(vwmaccsu_vx_w, 4, 8, clearq)
2024GEN_VEXT_VX(vwmaccus_vx_b, 1, 2, clearh)
2025GEN_VEXT_VX(vwmaccus_vx_h, 2, 4, clearl)
2026GEN_VEXT_VX(vwmaccus_vx_w, 4, 8, clearq)
f020a7a1
LZ		 2027
2028/* Vector Integer Merge and Move Instructions */
2029#define GEN_VEXT_VMV_VV(NAME, ETYPE, H, CLEAR_FN) \
2030void HELPER(NAME)(void *vd, void *vs1, CPURISCVState *env, \
2031 uint32_t desc) \
2032{ \
2033 uint32_t vl = env->vl; \
2034 uint32_t esz = sizeof(ETYPE); \
2035 uint32_t vlmax = vext_maxsz(desc) / esz; \
2036 uint32_t i; \
2037 \
2038 for (i = 0; i < vl; i++) { \
2039 ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
2040 *((ETYPE *)vd + H(i)) = s1; \
2041 } \
2042 CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
2043}
2044
2045GEN_VEXT_VMV_VV(vmv_v_v_b, int8_t, H1, clearb)
2046GEN_VEXT_VMV_VV(vmv_v_v_h, int16_t, H2, clearh)
2047GEN_VEXT_VMV_VV(vmv_v_v_w, int32_t, H4, clearl)
2048GEN_VEXT_VMV_VV(vmv_v_v_d, int64_t, H8, clearq)
2049
2050#define GEN_VEXT_VMV_VX(NAME, ETYPE, H, CLEAR_FN) \
2051void HELPER(NAME)(void *vd, uint64_t s1, CPURISCVState *env, \
2052 uint32_t desc) \
2053{ \
2054 uint32_t vl = env->vl; \
2055 uint32_t esz = sizeof(ETYPE); \
2056 uint32_t vlmax = vext_maxsz(desc) / esz; \
2057 uint32_t i; \
2058 \
2059 for (i = 0; i < vl; i++) { \
2060 *((ETYPE *)vd + H(i)) = (ETYPE)s1; \
2061 } \
2062 CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
2063}
2064
2065GEN_VEXT_VMV_VX(vmv_v_x_b, int8_t, H1, clearb)
2066GEN_VEXT_VMV_VX(vmv_v_x_h, int16_t, H2, clearh)
2067GEN_VEXT_VMV_VX(vmv_v_x_w, int32_t, H4, clearl)
2068GEN_VEXT_VMV_VX(vmv_v_x_d, int64_t, H8, clearq)
2069
2070#define GEN_VEXT_VMERGE_VV(NAME, ETYPE, H, CLEAR_FN) \
2071void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
2072 CPURISCVState *env, uint32_t desc) \
2073{ \
2074 uint32_t mlen = vext_mlen(desc); \
2075 uint32_t vl = env->vl; \
2076 uint32_t esz = sizeof(ETYPE); \
2077 uint32_t vlmax = vext_maxsz(desc) / esz; \
2078 uint32_t i; \
2079 \
2080 for (i = 0; i < vl; i++) { \
2081 ETYPE *vt = (!vext_elem_mask(v0, mlen, i) ? vs2 : vs1); \
2082 *((ETYPE *)vd + H(i)) = *(vt + H(i)); \
2083 } \
2084 CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
2085}
2086
2087GEN_VEXT_VMERGE_VV(vmerge_vvm_b, int8_t, H1, clearb)
2088GEN_VEXT_VMERGE_VV(vmerge_vvm_h, int16_t, H2, clearh)
2089GEN_VEXT_VMERGE_VV(vmerge_vvm_w, int32_t, H4, clearl)
2090GEN_VEXT_VMERGE_VV(vmerge_vvm_d, int64_t, H8, clearq)
2091
2092#define GEN_VEXT_VMERGE_VX(NAME, ETYPE, H, CLEAR_FN) \
2093void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
2094 void *vs2, CPURISCVState *env, uint32_t desc) \
2095{ \
2096 uint32_t mlen = vext_mlen(desc); \
2097 uint32_t vl = env->vl; \
2098 uint32_t esz = sizeof(ETYPE); \
2099 uint32_t vlmax = vext_maxsz(desc) / esz; \
2100 uint32_t i; \
2101 \
2102 for (i = 0; i < vl; i++) { \
2103 ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
2104 ETYPE d = (!vext_elem_mask(v0, mlen, i) ? s2 : \
2105 (ETYPE)(target_long)s1); \
2106 *((ETYPE *)vd + H(i)) = d; \
2107 } \
2108 CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
2109}
2110
2111GEN_VEXT_VMERGE_VX(vmerge_vxm_b, int8_t, H1, clearb)
2112GEN_VEXT_VMERGE_VX(vmerge_vxm_h, int16_t, H2, clearh)
2113GEN_VEXT_VMERGE_VX(vmerge_vxm_w, int32_t, H4, clearl)
2114GEN_VEXT_VMERGE_VX(vmerge_vxm_d, int64_t, H8, clearq)
eb2650e3
LZ		 2115
2116/*
2117 *** Vector Fixed-Point Arithmetic Instructions
2118 */
2119
2120/* Vector Single-Width Saturating Add and Subtract */
2121
2122/*
2123 * As fixed point instructions probably have round mode and saturation,
2124 * define common macros for fixed point here.
2125 */
2126typedef void opivv2_rm_fn(void *vd, void *vs1, void *vs2, int i,
2127 CPURISCVState *env, int vxrm);
2128
2129#define OPIVV2_RM(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \
2130static inline void \
2131do_##NAME(void *vd, void *vs1, void *vs2, int i, \
2132 CPURISCVState *env, int vxrm) \
2133{ \
2134 TX1 s1 = *((T1 *)vs1 + HS1(i)); \
2135 TX2 s2 = *((T2 *)vs2 + HS2(i)); \
2136 *((TD *)vd + HD(i)) = OP(env, vxrm, s2, s1); \
2137}
2138
2139static inline void
2140vext_vv_rm_1(void *vd, void *v0, void *vs1, void *vs2,
2141 CPURISCVState *env,
2142 uint32_t vl, uint32_t vm, uint32_t mlen, int vxrm,
2143 opivv2_rm_fn *fn)
2144{
2145 for (uint32_t i = 0; i < vl; i++) {
2146 if (!vm && !vext_elem_mask(v0, mlen, i)) {
2147 continue;
2148 }
2149 fn(vd, vs1, vs2, i, env, vxrm);
2150 }
2151}
2152
2153static inline void
2154vext_vv_rm_2(void *vd, void *v0, void *vs1, void *vs2,
2155 CPURISCVState *env,
2156 uint32_t desc, uint32_t esz, uint32_t dsz,
2157 opivv2_rm_fn *fn, clear_fn *clearfn)
2158{
2159 uint32_t vlmax = vext_maxsz(desc) / esz;
2160 uint32_t mlen = vext_mlen(desc);
2161 uint32_t vm = vext_vm(desc);
2162 uint32_t vl = env->vl;
2163
2164 switch (env->vxrm) {
2165 case 0: /* rnu */
2166 vext_vv_rm_1(vd, v0, vs1, vs2,
2167 env, vl, vm, mlen, 0, fn);
2168 break;
2169 case 1: /* rne */
2170 vext_vv_rm_1(vd, v0, vs1, vs2,
2171 env, vl, vm, mlen, 1, fn);
2172 break;
2173 case 2: /* rdn */
2174 vext_vv_rm_1(vd, v0, vs1, vs2,
2175 env, vl, vm, mlen, 2, fn);
2176 break;
2177 default: /* rod */
2178 vext_vv_rm_1(vd, v0, vs1, vs2,
2179 env, vl, vm, mlen, 3, fn);
2180 break;
2181 }
2182
2183 clearfn(vd, vl, vl * dsz, vlmax * dsz);
2184}
2185
2186/* generate helpers for fixed point instructions with OPIVV format */
2187#define GEN_VEXT_VV_RM(NAME, ESZ, DSZ, CLEAR_FN) \
2188void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
2189 CPURISCVState *env, uint32_t desc) \
2190{ \
2191 vext_vv_rm_2(vd, v0, vs1, vs2, env, desc, ESZ, DSZ, \
2192 do_##NAME, CLEAR_FN); \
2193}
2194
2195static inline uint8_t saddu8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b)
2196{
2197 uint8_t res = a + b;
2198 if (res < a) {
2199 res = UINT8_MAX;
2200 env->vxsat = 0x1;
2201 }
2202 return res;
2203}
2204
2205static inline uint16_t saddu16(CPURISCVState *env, int vxrm, uint16_t a,
2206 uint16_t b)
2207{
2208 uint16_t res = a + b;
2209 if (res < a) {
2210 res = UINT16_MAX;
2211 env->vxsat = 0x1;
2212 }
2213 return res;
2214}
2215
2216static inline uint32_t saddu32(CPURISCVState *env, int vxrm, uint32_t a,
2217 uint32_t b)
2218{
2219 uint32_t res = a + b;
2220 if (res < a) {
2221 res = UINT32_MAX;
2222 env->vxsat = 0x1;
2223 }
2224 return res;
2225}
2226
2227static inline uint64_t saddu64(CPURISCVState *env, int vxrm, uint64_t a,
2228 uint64_t b)
2229{
2230 uint64_t res = a + b;
2231 if (res < a) {
2232 res = UINT64_MAX;
2233 env->vxsat = 0x1;
2234 }
2235 return res;
2236}
2237
2238RVVCALL(OPIVV2_RM, vsaddu_vv_b, OP_UUU_B, H1, H1, H1, saddu8)
2239RVVCALL(OPIVV2_RM, vsaddu_vv_h, OP_UUU_H, H2, H2, H2, saddu16)
2240RVVCALL(OPIVV2_RM, vsaddu_vv_w, OP_UUU_W, H4, H4, H4, saddu32)
2241RVVCALL(OPIVV2_RM, vsaddu_vv_d, OP_UUU_D, H8, H8, H8, saddu64)
2242GEN_VEXT_VV_RM(vsaddu_vv_b, 1, 1, clearb)
2243GEN_VEXT_VV_RM(vsaddu_vv_h, 2, 2, clearh)
2244GEN_VEXT_VV_RM(vsaddu_vv_w, 4, 4, clearl)
2245GEN_VEXT_VV_RM(vsaddu_vv_d, 8, 8, clearq)
2246
2247typedef void opivx2_rm_fn(void *vd, target_long s1, void *vs2, int i,
2248 CPURISCVState *env, int vxrm);
2249
2250#define OPIVX2_RM(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \
2251static inline void \
2252do_##NAME(void *vd, target_long s1, void *vs2, int i, \
2253 CPURISCVState *env, int vxrm) \
2254{ \
2255 TX2 s2 = *((T2 *)vs2 + HS2(i)); \
2256 *((TD *)vd + HD(i)) = OP(env, vxrm, s2, (TX1)(T1)s1); \
2257}
2258
2259static inline void
2260vext_vx_rm_1(void *vd, void *v0, target_long s1, void *vs2,
2261 CPURISCVState *env,
2262 uint32_t vl, uint32_t vm, uint32_t mlen, int vxrm,
2263 opivx2_rm_fn *fn)
2264{
2265 for (uint32_t i = 0; i < vl; i++) {
2266 if (!vm && !vext_elem_mask(v0, mlen, i)) {
2267 continue;
2268 }
2269 fn(vd, s1, vs2, i, env, vxrm);
2270 }
2271}
2272
2273static inline void
2274vext_vx_rm_2(void *vd, void *v0, target_long s1, void *vs2,
2275 CPURISCVState *env,
2276 uint32_t desc, uint32_t esz, uint32_t dsz,
2277 opivx2_rm_fn *fn, clear_fn *clearfn)
2278{
2279 uint32_t vlmax = vext_maxsz(desc) / esz;
2280 uint32_t mlen = vext_mlen(desc);
2281 uint32_t vm = vext_vm(desc);
2282 uint32_t vl = env->vl;
2283
2284 switch (env->vxrm) {
2285 case 0: /* rnu */
2286 vext_vx_rm_1(vd, v0, s1, vs2,
2287 env, vl, vm, mlen, 0, fn);
2288 break;
2289 case 1: /* rne */
2290 vext_vx_rm_1(vd, v0, s1, vs2,
2291 env, vl, vm, mlen, 1, fn);
2292 break;
2293 case 2: /* rdn */
2294 vext_vx_rm_1(vd, v0, s1, vs2,
2295 env, vl, vm, mlen, 2, fn);
2296 break;
2297 default: /* rod */
2298 vext_vx_rm_1(vd, v0, s1, vs2,
2299 env, vl, vm, mlen, 3, fn);
2300 break;
2301 }
2302
2303 clearfn(vd, vl, vl * dsz, vlmax * dsz);
2304}
2305
2306/* generate helpers for fixed point instructions with OPIVX format */
2307#define GEN_VEXT_VX_RM(NAME, ESZ, DSZ, CLEAR_FN) \
2308void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
2309 void *vs2, CPURISCVState *env, uint32_t desc) \
2310{ \
2311 vext_vx_rm_2(vd, v0, s1, vs2, env, desc, ESZ, DSZ, \
2312 do_##NAME, CLEAR_FN); \
2313}
2314
2315RVVCALL(OPIVX2_RM, vsaddu_vx_b, OP_UUU_B, H1, H1, saddu8)
2316RVVCALL(OPIVX2_RM, vsaddu_vx_h, OP_UUU_H, H2, H2, saddu16)
2317RVVCALL(OPIVX2_RM, vsaddu_vx_w, OP_UUU_W, H4, H4, saddu32)
2318RVVCALL(OPIVX2_RM, vsaddu_vx_d, OP_UUU_D, H8, H8, saddu64)
2319GEN_VEXT_VX_RM(vsaddu_vx_b, 1, 1, clearb)
2320GEN_VEXT_VX_RM(vsaddu_vx_h, 2, 2, clearh)
2321GEN_VEXT_VX_RM(vsaddu_vx_w, 4, 4, clearl)
2322GEN_VEXT_VX_RM(vsaddu_vx_d, 8, 8, clearq)
2323
2324static inline int8_t sadd8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
2325{
2326 int8_t res = a + b;
2327 if ((res ^ a) & (res ^ b) & INT8_MIN) {
2328 res = a > 0 ? INT8_MAX : INT8_MIN;
2329 env->vxsat = 0x1;
2330 }
2331 return res;
2332}
2333
2334static inline int16_t sadd16(CPURISCVState *env, int vxrm, int16_t a, int16_t b)
2335{
2336 int16_t res = a + b;
2337 if ((res ^ a) & (res ^ b) & INT16_MIN) {
2338 res = a > 0 ? INT16_MAX : INT16_MIN;
2339 env->vxsat = 0x1;
2340 }
2341 return res;
2342}
2343
2344static inline int32_t sadd32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
2345{
2346 int32_t res = a + b;
2347 if ((res ^ a) & (res ^ b) & INT32_MIN) {
2348 res = a > 0 ? INT32_MAX : INT32_MIN;
2349 env->vxsat = 0x1;
2350 }
2351 return res;
2352}
2353
2354static inline int64_t sadd64(CPURISCVState *env, int vxrm, int64_t a, int64_t b)
2355{
2356 int64_t res = a + b;
2357 if ((res ^ a) & (res ^ b) & INT64_MIN) {
2358 res = a > 0 ? INT64_MAX : INT64_MIN;
2359 env->vxsat = 0x1;
2360 }
2361 return res;
2362}
2363
2364RVVCALL(OPIVV2_RM, vsadd_vv_b, OP_SSS_B, H1, H1, H1, sadd8)
2365RVVCALL(OPIVV2_RM, vsadd_vv_h, OP_SSS_H, H2, H2, H2, sadd16)
2366RVVCALL(OPIVV2_RM, vsadd_vv_w, OP_SSS_W, H4, H4, H4, sadd32)
2367RVVCALL(OPIVV2_RM, vsadd_vv_d, OP_SSS_D, H8, H8, H8, sadd64)
2368GEN_VEXT_VV_RM(vsadd_vv_b, 1, 1, clearb)
2369GEN_VEXT_VV_RM(vsadd_vv_h, 2, 2, clearh)
2370GEN_VEXT_VV_RM(vsadd_vv_w, 4, 4, clearl)
2371GEN_VEXT_VV_RM(vsadd_vv_d, 8, 8, clearq)
2372
2373RVVCALL(OPIVX2_RM, vsadd_vx_b, OP_SSS_B, H1, H1, sadd8)
2374RVVCALL(OPIVX2_RM, vsadd_vx_h, OP_SSS_H, H2, H2, sadd16)
2375RVVCALL(OPIVX2_RM, vsadd_vx_w, OP_SSS_W, H4, H4, sadd32)
2376RVVCALL(OPIVX2_RM, vsadd_vx_d, OP_SSS_D, H8, H8, sadd64)
2377GEN_VEXT_VX_RM(vsadd_vx_b, 1, 1, clearb)
2378GEN_VEXT_VX_RM(vsadd_vx_h, 2, 2, clearh)
2379GEN_VEXT_VX_RM(vsadd_vx_w, 4, 4, clearl)
2380GEN_VEXT_VX_RM(vsadd_vx_d, 8, 8, clearq)
2381
2382static inline uint8_t ssubu8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b)
2383{
2384 uint8_t res = a - b;
2385 if (res > a) {
2386 res = 0;
2387 env->vxsat = 0x1;
2388 }
2389 return res;
2390}
2391
2392static inline uint16_t ssubu16(CPURISCVState *env, int vxrm, uint16_t a,
2393 uint16_t b)
2394{
2395 uint16_t res = a - b;
2396 if (res > a) {
2397 res = 0;
2398 env->vxsat = 0x1;
2399 }
2400 return res;
2401}
2402
2403static inline uint32_t ssubu32(CPURISCVState *env, int vxrm, uint32_t a,
2404 uint32_t b)
2405{
2406 uint32_t res = a - b;
2407 if (res > a) {
2408 res = 0;
2409 env->vxsat = 0x1;
2410 }
2411 return res;
2412}
2413
2414static inline uint64_t ssubu64(CPURISCVState *env, int vxrm, uint64_t a,
2415 uint64_t b)
2416{
2417 uint64_t res = a - b;
2418 if (res > a) {
2419 res = 0;
2420 env->vxsat = 0x1;
2421 }
2422 return res;
2423}
2424
2425RVVCALL(OPIVV2_RM, vssubu_vv_b, OP_UUU_B, H1, H1, H1, ssubu8)
2426RVVCALL(OPIVV2_RM, vssubu_vv_h, OP_UUU_H, H2, H2, H2, ssubu16)
2427RVVCALL(OPIVV2_RM, vssubu_vv_w, OP_UUU_W, H4, H4, H4, ssubu32)
2428RVVCALL(OPIVV2_RM, vssubu_vv_d, OP_UUU_D, H8, H8, H8, ssubu64)
2429GEN_VEXT_VV_RM(vssubu_vv_b, 1, 1, clearb)
2430GEN_VEXT_VV_RM(vssubu_vv_h, 2, 2, clearh)
2431GEN_VEXT_VV_RM(vssubu_vv_w, 4, 4, clearl)
2432GEN_VEXT_VV_RM(vssubu_vv_d, 8, 8, clearq)
2433
2434RVVCALL(OPIVX2_RM, vssubu_vx_b, OP_UUU_B, H1, H1, ssubu8)
2435RVVCALL(OPIVX2_RM, vssubu_vx_h, OP_UUU_H, H2, H2, ssubu16)
2436RVVCALL(OPIVX2_RM, vssubu_vx_w, OP_UUU_W, H4, H4, ssubu32)
2437RVVCALL(OPIVX2_RM, vssubu_vx_d, OP_UUU_D, H8, H8, ssubu64)
2438GEN_VEXT_VX_RM(vssubu_vx_b, 1, 1, clearb)
2439GEN_VEXT_VX_RM(vssubu_vx_h, 2, 2, clearh)
2440GEN_VEXT_VX_RM(vssubu_vx_w, 4, 4, clearl)
2441GEN_VEXT_VX_RM(vssubu_vx_d, 8, 8, clearq)
2442
2443static inline int8_t ssub8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
2444{
2445 int8_t res = a - b;
2446 if ((res ^ a) & (a ^ b) & INT8_MIN) {
2447 res = a > 0 ? INT8_MAX : INT8_MIN;
2448 env->vxsat = 0x1;
2449 }
2450 return res;
2451}
2452
2453static inline int16_t ssub16(CPURISCVState *env, int vxrm, int16_t a, int16_t b)
2454{
2455 int16_t res = a - b;
2456 if ((res ^ a) & (a ^ b) & INT16_MIN) {
2457 res = a > 0 ? INT16_MAX : INT16_MIN;
2458 env->vxsat = 0x1;
2459 }
2460 return res;
2461}
2462
2463static inline int32_t ssub32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
2464{
2465 int32_t res = a - b;
2466 if ((res ^ a) & (a ^ b) & INT32_MIN) {
2467 res = a > 0 ? INT32_MAX : INT32_MIN;
2468 env->vxsat = 0x1;
2469 }
2470 return res;
2471}
2472
2473static inline int64_t ssub64(CPURISCVState *env, int vxrm, int64_t a, int64_t b)
2474{
2475 int64_t res = a - b;
2476 if ((res ^ a) & (a ^ b) & INT64_MIN) {
2477 res = a > 0 ? INT64_MAX : INT64_MIN;
2478 env->vxsat = 0x1;
2479 }
2480 return res;
2481}
2482
2483RVVCALL(OPIVV2_RM, vssub_vv_b, OP_SSS_B, H1, H1, H1, ssub8)
2484RVVCALL(OPIVV2_RM, vssub_vv_h, OP_SSS_H, H2, H2, H2, ssub16)
2485RVVCALL(OPIVV2_RM, vssub_vv_w, OP_SSS_W, H4, H4, H4, ssub32)
2486RVVCALL(OPIVV2_RM, vssub_vv_d, OP_SSS_D, H8, H8, H8, ssub64)
2487GEN_VEXT_VV_RM(vssub_vv_b, 1, 1, clearb)
2488GEN_VEXT_VV_RM(vssub_vv_h, 2, 2, clearh)
2489GEN_VEXT_VV_RM(vssub_vv_w, 4, 4, clearl)
2490GEN_VEXT_VV_RM(vssub_vv_d, 8, 8, clearq)
2491
2492RVVCALL(OPIVX2_RM, vssub_vx_b, OP_SSS_B, H1, H1, ssub8)
2493RVVCALL(OPIVX2_RM, vssub_vx_h, OP_SSS_H, H2, H2, ssub16)
2494RVVCALL(OPIVX2_RM, vssub_vx_w, OP_SSS_W, H4, H4, ssub32)
2495RVVCALL(OPIVX2_RM, vssub_vx_d, OP_SSS_D, H8, H8, ssub64)
2496GEN_VEXT_VX_RM(vssub_vx_b, 1, 1, clearb)
2497GEN_VEXT_VX_RM(vssub_vx_h, 2, 2, clearh)
2498GEN_VEXT_VX_RM(vssub_vx_w, 4, 4, clearl)
2499GEN_VEXT_VX_RM(vssub_vx_d, 8, 8, clearq)
b7aee481
LZ		 2500
2501/* Vector Single-Width Averaging Add and Subtract */
2502static inline uint8_t get_round(int vxrm, uint64_t v, uint8_t shift)
2503{
2504 uint8_t d = extract64(v, shift, 1);
2505 uint8_t d1;
2506 uint64_t D1, D2;
2507
2508 if (shift == 0 || shift > 64) {
2509 return 0;
2510 }
2511
2512 d1 = extract64(v, shift - 1, 1);
2513 D1 = extract64(v, 0, shift);
2514 if (vxrm == 0) { /* round-to-nearest-up (add +0.5 LSB) */
2515 return d1;
2516 } else if (vxrm == 1) { /* round-to-nearest-even */
2517 if (shift > 1) {
2518 D2 = extract64(v, 0, shift - 1);
2519 return d1 & ((D2 != 0) | d);
2520 } else {
2521 return d1 & d;
2522 }
2523 } else if (vxrm == 3) { /* round-to-odd (OR bits into LSB, aka "jam") */
2524 return !d & (D1 != 0);
2525 }
2526 return 0; /* round-down (truncate) */
2527}
2528
2529static inline int32_t aadd32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
2530{
2531 int64_t res = (int64_t)a + b;
2532 uint8_t round = get_round(vxrm, res, 1);
2533
2534 return (res >> 1) + round;
2535}
2536
2537static inline int64_t aadd64(CPURISCVState *env, int vxrm, int64_t a, int64_t b)
2538{
2539 int64_t res = a + b;
2540 uint8_t round = get_round(vxrm, res, 1);
2541 int64_t over = (res ^ a) & (res ^ b) & INT64_MIN;
2542
2543 /* With signed overflow, bit 64 is inverse of bit 63. */
2544 return ((res >> 1) ^ over) + round;
2545}
2546
2547RVVCALL(OPIVV2_RM, vaadd_vv_b, OP_SSS_B, H1, H1, H1, aadd32)
2548RVVCALL(OPIVV2_RM, vaadd_vv_h, OP_SSS_H, H2, H2, H2, aadd32)
2549RVVCALL(OPIVV2_RM, vaadd_vv_w, OP_SSS_W, H4, H4, H4, aadd32)
2550RVVCALL(OPIVV2_RM, vaadd_vv_d, OP_SSS_D, H8, H8, H8, aadd64)
2551GEN_VEXT_VV_RM(vaadd_vv_b, 1, 1, clearb)
2552GEN_VEXT_VV_RM(vaadd_vv_h, 2, 2, clearh)
2553GEN_VEXT_VV_RM(vaadd_vv_w, 4, 4, clearl)
2554GEN_VEXT_VV_RM(vaadd_vv_d, 8, 8, clearq)
2555
2556RVVCALL(OPIVX2_RM, vaadd_vx_b, OP_SSS_B, H1, H1, aadd32)
2557RVVCALL(OPIVX2_RM, vaadd_vx_h, OP_SSS_H, H2, H2, aadd32)
2558RVVCALL(OPIVX2_RM, vaadd_vx_w, OP_SSS_W, H4, H4, aadd32)
2559RVVCALL(OPIVX2_RM, vaadd_vx_d, OP_SSS_D, H8, H8, aadd64)
2560GEN_VEXT_VX_RM(vaadd_vx_b, 1, 1, clearb)
2561GEN_VEXT_VX_RM(vaadd_vx_h, 2, 2, clearh)
2562GEN_VEXT_VX_RM(vaadd_vx_w, 4, 4, clearl)
2563GEN_VEXT_VX_RM(vaadd_vx_d, 8, 8, clearq)
2564
2565static inline int32_t asub32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
2566{
2567 int64_t res = (int64_t)a - b;
2568 uint8_t round = get_round(vxrm, res, 1);
2569
2570 return (res >> 1) + round;
2571}
2572
2573static inline int64_t asub64(CPURISCVState *env, int vxrm, int64_t a, int64_t b)
2574{
2575 int64_t res = (int64_t)a - b;
2576 uint8_t round = get_round(vxrm, res, 1);
2577 int64_t over = (res ^ a) & (a ^ b) & INT64_MIN;
2578
2579 /* With signed overflow, bit 64 is inverse of bit 63. */
2580 return ((res >> 1) ^ over) + round;
2581}
2582
2583RVVCALL(OPIVV2_RM, vasub_vv_b, OP_SSS_B, H1, H1, H1, asub32)
2584RVVCALL(OPIVV2_RM, vasub_vv_h, OP_SSS_H, H2, H2, H2, asub32)
2585RVVCALL(OPIVV2_RM, vasub_vv_w, OP_SSS_W, H4, H4, H4, asub32)
2586RVVCALL(OPIVV2_RM, vasub_vv_d, OP_SSS_D, H8, H8, H8, asub64)
2587GEN_VEXT_VV_RM(vasub_vv_b, 1, 1, clearb)
2588GEN_VEXT_VV_RM(vasub_vv_h, 2, 2, clearh)
2589GEN_VEXT_VV_RM(vasub_vv_w, 4, 4, clearl)
2590GEN_VEXT_VV_RM(vasub_vv_d, 8, 8, clearq)
2591
2592RVVCALL(OPIVX2_RM, vasub_vx_b, OP_SSS_B, H1, H1, asub32)
2593RVVCALL(OPIVX2_RM, vasub_vx_h, OP_SSS_H, H2, H2, asub32)
2594RVVCALL(OPIVX2_RM, vasub_vx_w, OP_SSS_W, H4, H4, asub32)
2595RVVCALL(OPIVX2_RM, vasub_vx_d, OP_SSS_D, H8, H8, asub64)
2596GEN_VEXT_VX_RM(vasub_vx_b, 1, 1, clearb)
2597GEN_VEXT_VX_RM(vasub_vx_h, 2, 2, clearh)
2598GEN_VEXT_VX_RM(vasub_vx_w, 4, 4, clearl)
2599GEN_VEXT_VX_RM(vasub_vx_d, 8, 8, clearq)
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