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Commit | Line | Data |
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27a4a30e YS |
1 | /* |
2 | * QEMU RX CPU | |
3 | * | |
4 | * Copyright (c) 2019 Yoshinori Sato | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2 or later, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along with | |
16 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | ||
19 | #include "qemu/osdep.h" | |
20 | #include "qemu/qemu-print.h" | |
21 | #include "qapi/error.h" | |
22 | #include "cpu.h" | |
27a4a30e YS |
23 | #include "migration/vmstate.h" |
24 | #include "exec/exec-all.h" | |
25 | #include "hw/loader.h" | |
26 | #include "fpu/softfloat.h" | |
fafe0021 | 27 | #include "tcg/debug-assert.h" |
27a4a30e YS |
28 | |
29 | static void rx_cpu_set_pc(CPUState *cs, vaddr value) | |
30 | { | |
38688fdb | 31 | RXCPU *cpu = RX_CPU(cs); |
27a4a30e YS |
32 | |
33 | cpu->env.pc = value; | |
34 | } | |
35 | ||
e4fdf9df RH |
36 | static vaddr rx_cpu_get_pc(CPUState *cs) |
37 | { | |
38 | RXCPU *cpu = RX_CPU(cs); | |
39 | ||
40 | return cpu->env.pc; | |
41 | } | |
42 | ||
04a37d4c RH |
43 | static void rx_cpu_synchronize_from_tb(CPUState *cs, |
44 | const TranslationBlock *tb) | |
27a4a30e | 45 | { |
38688fdb | 46 | RXCPU *cpu = RX_CPU(cs); |
27a4a30e | 47 | |
8023d1ab AJ |
48 | tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); |
49 | cpu->env.pc = tb->pc; | |
27a4a30e YS |
50 | } |
51 | ||
5439d7a6 RH |
52 | static void rx_restore_state_to_opc(CPUState *cs, |
53 | const TranslationBlock *tb, | |
54 | const uint64_t *data) | |
55 | { | |
56 | RXCPU *cpu = RX_CPU(cs); | |
57 | ||
58 | cpu->env.pc = data[0]; | |
59 | } | |
60 | ||
27a4a30e YS |
61 | static bool rx_cpu_has_work(CPUState *cs) |
62 | { | |
63 | return cs->interrupt_request & | |
64 | (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR); | |
65 | } | |
66 | ||
88c41e40 | 67 | static void rx_cpu_reset_hold(Object *obj) |
27a4a30e | 68 | { |
88c41e40 | 69 | RXCPU *cpu = RX_CPU(obj); |
38688fdb | 70 | RXCPUClass *rcc = RX_CPU_GET_CLASS(cpu); |
27a4a30e YS |
71 | CPURXState *env = &cpu->env; |
72 | uint32_t *resetvec; | |
73 | ||
88c41e40 PM |
74 | if (rcc->parent_phases.hold) { |
75 | rcc->parent_phases.hold(obj); | |
76 | } | |
27a4a30e YS |
77 | |
78 | memset(env, 0, offsetof(CPURXState, end_reset_fields)); | |
79 | ||
80 | resetvec = rom_ptr(0xfffffffc, 4); | |
81 | if (resetvec) { | |
82 | /* In the case of kernel, it is ignored because it is not set. */ | |
83 | env->pc = ldl_p(resetvec); | |
84 | } | |
85 | rx_cpu_unpack_psw(env, 0, 1); | |
86 | env->regs[0] = env->isp = env->usp = 0; | |
87 | env->fpsw = 0; | |
88 | set_flush_to_zero(1, &env->fp_status); | |
89 | set_flush_inputs_to_zero(1, &env->fp_status); | |
90 | } | |
91 | ||
27a4a30e YS |
92 | static ObjectClass *rx_cpu_class_by_name(const char *cpu_model) |
93 | { | |
94 | ObjectClass *oc; | |
95 | char *typename; | |
96 | ||
97 | oc = object_class_by_name(cpu_model); | |
3a9d0d7b | 98 | if (oc != NULL && object_class_dynamic_cast(oc, TYPE_RX_CPU) != NULL) { |
27a4a30e YS |
99 | return oc; |
100 | } | |
101 | typename = g_strdup_printf(RX_CPU_TYPE_NAME("%s"), cpu_model); | |
102 | oc = object_class_by_name(typename); | |
103 | g_free(typename); | |
27a4a30e YS |
104 | |
105 | return oc; | |
106 | } | |
107 | ||
108 | static void rx_cpu_realize(DeviceState *dev, Error **errp) | |
109 | { | |
110 | CPUState *cs = CPU(dev); | |
38688fdb | 111 | RXCPUClass *rcc = RX_CPU_GET_CLASS(dev); |
27a4a30e YS |
112 | Error *local_err = NULL; |
113 | ||
114 | cpu_exec_realizefn(cs, &local_err); | |
115 | if (local_err != NULL) { | |
116 | error_propagate(errp, local_err); | |
117 | return; | |
118 | } | |
119 | ||
120 | qemu_init_vcpu(cs); | |
121 | cpu_reset(cs); | |
122 | ||
123 | rcc->parent_realize(dev, errp); | |
124 | } | |
125 | ||
126 | static void rx_cpu_set_irq(void *opaque, int no, int request) | |
127 | { | |
128 | RXCPU *cpu = opaque; | |
129 | CPUState *cs = CPU(cpu); | |
130 | int irq = request & 0xff; | |
131 | ||
132 | static const int mask[] = { | |
133 | [RX_CPU_IRQ] = CPU_INTERRUPT_HARD, | |
134 | [RX_CPU_FIR] = CPU_INTERRUPT_FIR, | |
135 | }; | |
136 | if (irq) { | |
137 | cpu->env.req_irq = irq; | |
138 | cpu->env.req_ipl = (request >> 8) & 0x0f; | |
139 | cpu_interrupt(cs, mask[no]); | |
140 | } else { | |
141 | cpu_reset_interrupt(cs, mask[no]); | |
142 | } | |
143 | } | |
144 | ||
145 | static void rx_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) | |
146 | { | |
147 | info->mach = bfd_mach_rx; | |
148 | info->print_insn = print_insn_rx; | |
149 | } | |
150 | ||
151 | static bool rx_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, | |
152 | MMUAccessType access_type, int mmu_idx, | |
153 | bool probe, uintptr_t retaddr) | |
154 | { | |
155 | uint32_t address, physical, prot; | |
156 | ||
157 | /* Linear mapping */ | |
158 | address = physical = addr & TARGET_PAGE_MASK; | |
159 | prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
160 | tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE); | |
161 | return true; | |
162 | } | |
163 | ||
164 | static void rx_cpu_init(Object *obj) | |
165 | { | |
38688fdb | 166 | RXCPU *cpu = RX_CPU(obj); |
27a4a30e | 167 | |
27a4a30e YS |
168 | qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2); |
169 | } | |
170 | ||
8b80bd28 PMD |
171 | #ifndef CONFIG_USER_ONLY |
172 | #include "hw/core/sysemu-cpu-ops.h" | |
173 | ||
174 | static const struct SysemuCPUOps rx_sysemu_ops = { | |
08928c6d | 175 | .get_phys_page_debug = rx_cpu_get_phys_page_debug, |
8b80bd28 PMD |
176 | }; |
177 | #endif | |
178 | ||
78271684 CF |
179 | #include "hw/core/tcg-cpu-ops.h" |
180 | ||
1764ad70 | 181 | static const TCGCPUOps rx_tcg_ops = { |
78271684 CF |
182 | .initialize = rx_translate_init, |
183 | .synchronize_from_tb = rx_cpu_synchronize_from_tb, | |
5439d7a6 | 184 | .restore_state_to_opc = rx_restore_state_to_opc, |
78271684 CF |
185 | .tlb_fill = rx_cpu_tlb_fill, |
186 | ||
187 | #ifndef CONFIG_USER_ONLY | |
65c575b6 | 188 | .cpu_exec_interrupt = rx_cpu_exec_interrupt, |
78271684 CF |
189 | .do_interrupt = rx_cpu_do_interrupt, |
190 | #endif /* !CONFIG_USER_ONLY */ | |
191 | }; | |
192 | ||
27a4a30e YS |
193 | static void rx_cpu_class_init(ObjectClass *klass, void *data) |
194 | { | |
195 | DeviceClass *dc = DEVICE_CLASS(klass); | |
196 | CPUClass *cc = CPU_CLASS(klass); | |
38688fdb | 197 | RXCPUClass *rcc = RX_CPU_CLASS(klass); |
88c41e40 | 198 | ResettableClass *rc = RESETTABLE_CLASS(klass); |
27a4a30e YS |
199 | |
200 | device_class_set_parent_realize(dc, rx_cpu_realize, | |
201 | &rcc->parent_realize); | |
88c41e40 PM |
202 | resettable_class_set_parent_phases(rc, NULL, rx_cpu_reset_hold, NULL, |
203 | &rcc->parent_phases); | |
27a4a30e YS |
204 | |
205 | cc->class_by_name = rx_cpu_class_by_name; | |
206 | cc->has_work = rx_cpu_has_work; | |
27a4a30e YS |
207 | cc->dump_state = rx_cpu_dump_state; |
208 | cc->set_pc = rx_cpu_set_pc; | |
e4fdf9df | 209 | cc->get_pc = rx_cpu_get_pc; |
78271684 | 210 | |
8b80bd28 PMD |
211 | #ifndef CONFIG_USER_ONLY |
212 | cc->sysemu_ops = &rx_sysemu_ops; | |
213 | #endif | |
27a4a30e YS |
214 | cc->gdb_read_register = rx_cpu_gdb_read_register; |
215 | cc->gdb_write_register = rx_cpu_gdb_write_register; | |
27a4a30e | 216 | cc->disas_set_info = rx_cpu_disas_set_info; |
27a4a30e YS |
217 | |
218 | cc->gdb_num_core_regs = 26; | |
219 | cc->gdb_core_xml_file = "rx-core.xml"; | |
78271684 | 220 | cc->tcg_ops = &rx_tcg_ops; |
27a4a30e YS |
221 | } |
222 | ||
223 | static const TypeInfo rx_cpu_info = { | |
224 | .name = TYPE_RX_CPU, | |
225 | .parent = TYPE_CPU, | |
226 | .instance_size = sizeof(RXCPU), | |
f669c992 | 227 | .instance_align = __alignof(RXCPU), |
27a4a30e YS |
228 | .instance_init = rx_cpu_init, |
229 | .abstract = true, | |
230 | .class_size = sizeof(RXCPUClass), | |
231 | .class_init = rx_cpu_class_init, | |
232 | }; | |
233 | ||
234 | static const TypeInfo rx62n_rx_cpu_info = { | |
235 | .name = TYPE_RX62N_CPU, | |
236 | .parent = TYPE_RX_CPU, | |
237 | }; | |
238 | ||
239 | static void rx_cpu_register_types(void) | |
240 | { | |
241 | type_register_static(&rx_cpu_info); | |
242 | type_register_static(&rx62n_rx_cpu_info); | |
243 | } | |
244 | ||
245 | type_init(rx_cpu_register_types) |