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Commit | Line | Data |
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27a4a30e YS |
1 | /* |
2 | * QEMU RX CPU | |
3 | * | |
4 | * Copyright (c) 2019 Yoshinori Sato | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2 or later, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along with | |
16 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | ||
19 | #include "qemu/osdep.h" | |
20 | #include "qemu/qemu-print.h" | |
21 | #include "qapi/error.h" | |
22 | #include "cpu.h" | |
27a4a30e YS |
23 | #include "migration/vmstate.h" |
24 | #include "exec/exec-all.h" | |
25 | #include "hw/loader.h" | |
26 | #include "fpu/softfloat.h" | |
fafe0021 | 27 | #include "tcg/debug-assert.h" |
27a4a30e YS |
28 | |
29 | static void rx_cpu_set_pc(CPUState *cs, vaddr value) | |
30 | { | |
38688fdb | 31 | RXCPU *cpu = RX_CPU(cs); |
27a4a30e YS |
32 | |
33 | cpu->env.pc = value; | |
34 | } | |
35 | ||
e4fdf9df RH |
36 | static vaddr rx_cpu_get_pc(CPUState *cs) |
37 | { | |
38 | RXCPU *cpu = RX_CPU(cs); | |
39 | ||
40 | return cpu->env.pc; | |
41 | } | |
42 | ||
04a37d4c RH |
43 | static void rx_cpu_synchronize_from_tb(CPUState *cs, |
44 | const TranslationBlock *tb) | |
27a4a30e | 45 | { |
38688fdb | 46 | RXCPU *cpu = RX_CPU(cs); |
27a4a30e | 47 | |
8023d1ab AJ |
48 | tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); |
49 | cpu->env.pc = tb->pc; | |
27a4a30e YS |
50 | } |
51 | ||
5439d7a6 RH |
52 | static void rx_restore_state_to_opc(CPUState *cs, |
53 | const TranslationBlock *tb, | |
54 | const uint64_t *data) | |
55 | { | |
56 | RXCPU *cpu = RX_CPU(cs); | |
57 | ||
58 | cpu->env.pc = data[0]; | |
59 | } | |
60 | ||
27a4a30e YS |
61 | static bool rx_cpu_has_work(CPUState *cs) |
62 | { | |
63 | return cs->interrupt_request & | |
64 | (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR); | |
65 | } | |
66 | ||
88c41e40 | 67 | static void rx_cpu_reset_hold(Object *obj) |
27a4a30e | 68 | { |
88c41e40 | 69 | RXCPU *cpu = RX_CPU(obj); |
38688fdb | 70 | RXCPUClass *rcc = RX_CPU_GET_CLASS(cpu); |
27a4a30e YS |
71 | CPURXState *env = &cpu->env; |
72 | uint32_t *resetvec; | |
73 | ||
88c41e40 PM |
74 | if (rcc->parent_phases.hold) { |
75 | rcc->parent_phases.hold(obj); | |
76 | } | |
27a4a30e YS |
77 | |
78 | memset(env, 0, offsetof(CPURXState, end_reset_fields)); | |
79 | ||
80 | resetvec = rom_ptr(0xfffffffc, 4); | |
81 | if (resetvec) { | |
82 | /* In the case of kernel, it is ignored because it is not set. */ | |
83 | env->pc = ldl_p(resetvec); | |
84 | } | |
85 | rx_cpu_unpack_psw(env, 0, 1); | |
86 | env->regs[0] = env->isp = env->usp = 0; | |
87 | env->fpsw = 0; | |
88 | set_flush_to_zero(1, &env->fp_status); | |
89 | set_flush_inputs_to_zero(1, &env->fp_status); | |
90 | } | |
91 | ||
92 | static void rx_cpu_list_entry(gpointer data, gpointer user_data) | |
93 | { | |
94 | ObjectClass *oc = data; | |
95 | ||
96 | qemu_printf(" %s\n", object_class_get_name(oc)); | |
97 | } | |
98 | ||
99 | void rx_cpu_list(void) | |
100 | { | |
101 | GSList *list; | |
102 | list = object_class_get_list_sorted(TYPE_RX_CPU, false); | |
103 | qemu_printf("Available CPUs:\n"); | |
104 | g_slist_foreach(list, rx_cpu_list_entry, NULL); | |
105 | g_slist_free(list); | |
106 | } | |
107 | ||
108 | static ObjectClass *rx_cpu_class_by_name(const char *cpu_model) | |
109 | { | |
110 | ObjectClass *oc; | |
111 | char *typename; | |
112 | ||
113 | oc = object_class_by_name(cpu_model); | |
114 | if (oc != NULL && object_class_dynamic_cast(oc, TYPE_RX_CPU) != NULL && | |
115 | !object_class_is_abstract(oc)) { | |
116 | return oc; | |
117 | } | |
118 | typename = g_strdup_printf(RX_CPU_TYPE_NAME("%s"), cpu_model); | |
119 | oc = object_class_by_name(typename); | |
120 | g_free(typename); | |
121 | if (oc != NULL && object_class_is_abstract(oc)) { | |
122 | oc = NULL; | |
123 | } | |
124 | ||
125 | return oc; | |
126 | } | |
127 | ||
128 | static void rx_cpu_realize(DeviceState *dev, Error **errp) | |
129 | { | |
130 | CPUState *cs = CPU(dev); | |
38688fdb | 131 | RXCPUClass *rcc = RX_CPU_GET_CLASS(dev); |
27a4a30e YS |
132 | Error *local_err = NULL; |
133 | ||
134 | cpu_exec_realizefn(cs, &local_err); | |
135 | if (local_err != NULL) { | |
136 | error_propagate(errp, local_err); | |
137 | return; | |
138 | } | |
139 | ||
140 | qemu_init_vcpu(cs); | |
141 | cpu_reset(cs); | |
142 | ||
143 | rcc->parent_realize(dev, errp); | |
144 | } | |
145 | ||
146 | static void rx_cpu_set_irq(void *opaque, int no, int request) | |
147 | { | |
148 | RXCPU *cpu = opaque; | |
149 | CPUState *cs = CPU(cpu); | |
150 | int irq = request & 0xff; | |
151 | ||
152 | static const int mask[] = { | |
153 | [RX_CPU_IRQ] = CPU_INTERRUPT_HARD, | |
154 | [RX_CPU_FIR] = CPU_INTERRUPT_FIR, | |
155 | }; | |
156 | if (irq) { | |
157 | cpu->env.req_irq = irq; | |
158 | cpu->env.req_ipl = (request >> 8) & 0x0f; | |
159 | cpu_interrupt(cs, mask[no]); | |
160 | } else { | |
161 | cpu_reset_interrupt(cs, mask[no]); | |
162 | } | |
163 | } | |
164 | ||
165 | static void rx_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) | |
166 | { | |
167 | info->mach = bfd_mach_rx; | |
168 | info->print_insn = print_insn_rx; | |
169 | } | |
170 | ||
171 | static bool rx_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, | |
172 | MMUAccessType access_type, int mmu_idx, | |
173 | bool probe, uintptr_t retaddr) | |
174 | { | |
175 | uint32_t address, physical, prot; | |
176 | ||
177 | /* Linear mapping */ | |
178 | address = physical = addr & TARGET_PAGE_MASK; | |
179 | prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
180 | tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE); | |
181 | return true; | |
182 | } | |
183 | ||
184 | static void rx_cpu_init(Object *obj) | |
185 | { | |
186 | CPUState *cs = CPU(obj); | |
38688fdb | 187 | RXCPU *cpu = RX_CPU(obj); |
27a4a30e YS |
188 | CPURXState *env = &cpu->env; |
189 | ||
190 | cpu_set_cpustate_pointers(cpu); | |
191 | cs->env_ptr = env; | |
192 | qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2); | |
193 | } | |
194 | ||
8b80bd28 PMD |
195 | #ifndef CONFIG_USER_ONLY |
196 | #include "hw/core/sysemu-cpu-ops.h" | |
197 | ||
198 | static const struct SysemuCPUOps rx_sysemu_ops = { | |
08928c6d | 199 | .get_phys_page_debug = rx_cpu_get_phys_page_debug, |
8b80bd28 PMD |
200 | }; |
201 | #endif | |
202 | ||
78271684 CF |
203 | #include "hw/core/tcg-cpu-ops.h" |
204 | ||
11906557 | 205 | static const struct TCGCPUOps rx_tcg_ops = { |
78271684 CF |
206 | .initialize = rx_translate_init, |
207 | .synchronize_from_tb = rx_cpu_synchronize_from_tb, | |
5439d7a6 | 208 | .restore_state_to_opc = rx_restore_state_to_opc, |
78271684 CF |
209 | .tlb_fill = rx_cpu_tlb_fill, |
210 | ||
211 | #ifndef CONFIG_USER_ONLY | |
65c575b6 | 212 | .cpu_exec_interrupt = rx_cpu_exec_interrupt, |
78271684 CF |
213 | .do_interrupt = rx_cpu_do_interrupt, |
214 | #endif /* !CONFIG_USER_ONLY */ | |
215 | }; | |
216 | ||
27a4a30e YS |
217 | static void rx_cpu_class_init(ObjectClass *klass, void *data) |
218 | { | |
219 | DeviceClass *dc = DEVICE_CLASS(klass); | |
220 | CPUClass *cc = CPU_CLASS(klass); | |
38688fdb | 221 | RXCPUClass *rcc = RX_CPU_CLASS(klass); |
88c41e40 | 222 | ResettableClass *rc = RESETTABLE_CLASS(klass); |
27a4a30e YS |
223 | |
224 | device_class_set_parent_realize(dc, rx_cpu_realize, | |
225 | &rcc->parent_realize); | |
88c41e40 PM |
226 | resettable_class_set_parent_phases(rc, NULL, rx_cpu_reset_hold, NULL, |
227 | &rcc->parent_phases); | |
27a4a30e YS |
228 | |
229 | cc->class_by_name = rx_cpu_class_by_name; | |
230 | cc->has_work = rx_cpu_has_work; | |
27a4a30e YS |
231 | cc->dump_state = rx_cpu_dump_state; |
232 | cc->set_pc = rx_cpu_set_pc; | |
e4fdf9df | 233 | cc->get_pc = rx_cpu_get_pc; |
78271684 | 234 | |
8b80bd28 PMD |
235 | #ifndef CONFIG_USER_ONLY |
236 | cc->sysemu_ops = &rx_sysemu_ops; | |
237 | #endif | |
27a4a30e YS |
238 | cc->gdb_read_register = rx_cpu_gdb_read_register; |
239 | cc->gdb_write_register = rx_cpu_gdb_write_register; | |
27a4a30e | 240 | cc->disas_set_info = rx_cpu_disas_set_info; |
27a4a30e YS |
241 | |
242 | cc->gdb_num_core_regs = 26; | |
243 | cc->gdb_core_xml_file = "rx-core.xml"; | |
78271684 | 244 | cc->tcg_ops = &rx_tcg_ops; |
27a4a30e YS |
245 | } |
246 | ||
247 | static const TypeInfo rx_cpu_info = { | |
248 | .name = TYPE_RX_CPU, | |
249 | .parent = TYPE_CPU, | |
250 | .instance_size = sizeof(RXCPU), | |
f669c992 | 251 | .instance_align = __alignof(RXCPU), |
27a4a30e YS |
252 | .instance_init = rx_cpu_init, |
253 | .abstract = true, | |
254 | .class_size = sizeof(RXCPUClass), | |
255 | .class_init = rx_cpu_class_init, | |
256 | }; | |
257 | ||
258 | static const TypeInfo rx62n_rx_cpu_info = { | |
259 | .name = TYPE_RX62N_CPU, | |
260 | .parent = TYPE_RX_CPU, | |
261 | }; | |
262 | ||
263 | static void rx_cpu_register_types(void) | |
264 | { | |
265 | type_register_static(&rx_cpu_info); | |
266 | type_register_static(&rx62n_rx_cpu_info); | |
267 | } | |
268 | ||
269 | type_init(rx_cpu_register_types) |