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339894be AF |
1 | /* |
2 | * QEMU SuperH CPU | |
3 | * | |
c4bb0f99 | 4 | * Copyright (c) 2005 Samuel Tardieu |
339894be AF |
5 | * Copyright (c) 2012 SUSE LINUX Products GmbH |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2.1 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
18 | * License along with this library; if not, see | |
19 | * <http://www.gnu.org/licenses/lgpl-2.1.html> | |
20 | */ | |
21 | ||
9d4c9946 | 22 | #include "qemu/osdep.h" |
da34e65c | 23 | #include "qapi/error.h" |
0442428a | 24 | #include "qemu/qemu-print.h" |
339894be | 25 | #include "cpu.h" |
1e45d31b | 26 | #include "migration/vmstate.h" |
63c91552 | 27 | #include "exec/exec-all.h" |
5f8ab000 | 28 | #include "fpu/softfloat-helpers.h" |
dd69c77c | 29 | #include "tcg/tcg.h" |
339894be | 30 | |
f45748f1 AF |
31 | static void superh_cpu_set_pc(CPUState *cs, vaddr value) |
32 | { | |
33 | SuperHCPU *cpu = SUPERH_CPU(cs); | |
34 | ||
35 | cpu->env.pc = value; | |
36 | } | |
37 | ||
e4fdf9df RH |
38 | static vaddr superh_cpu_get_pc(CPUState *cs) |
39 | { | |
40 | SuperHCPU *cpu = SUPERH_CPU(cs); | |
41 | ||
42 | return cpu->env.pc; | |
43 | } | |
44 | ||
04a37d4c RH |
45 | static void superh_cpu_synchronize_from_tb(CPUState *cs, |
46 | const TranslationBlock *tb) | |
bdf7ae5b AF |
47 | { |
48 | SuperHCPU *cpu = SUPERH_CPU(cs); | |
49 | ||
dd69c77c AJ |
50 | tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); |
51 | cpu->env.pc = tb->pc; | |
bc233163 | 52 | cpu->env.flags = tb->flags & TB_FLAG_ENVFLAGS_MASK; |
bdf7ae5b AF |
53 | } |
54 | ||
e7977326 RH |
55 | static void superh_restore_state_to_opc(CPUState *cs, |
56 | const TranslationBlock *tb, | |
57 | const uint64_t *data) | |
58 | { | |
59 | SuperHCPU *cpu = SUPERH_CPU(cs); | |
60 | ||
61 | cpu->env.pc = data[0]; | |
62 | cpu->env.flags = data[1]; | |
63 | /* | |
64 | * Theoretically delayed_pc should also be restored. In practice the | |
65 | * branch instruction is re-executed after exception, so the delayed | |
66 | * branch target will be recomputed. | |
67 | */ | |
68 | } | |
69 | ||
eb56afdb RH |
70 | #ifndef CONFIG_USER_ONLY |
71 | static bool superh_io_recompile_replay_branch(CPUState *cs, | |
72 | const TranslationBlock *tb) | |
73 | { | |
74 | SuperHCPU *cpu = SUPERH_CPU(cs); | |
75 | CPUSH4State *env = &cpu->env; | |
76 | ||
ab419fd8 | 77 | if ((env->flags & (TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND)) |
dd69c77c | 78 | && !(cs->tcg_cflags & CF_PCREL) && env->pc != tb->pc) { |
eb56afdb | 79 | env->pc -= 2; |
ab419fd8 | 80 | env->flags &= ~(TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND); |
eb56afdb RH |
81 | return true; |
82 | } | |
83 | return false; | |
84 | } | |
85 | #endif | |
86 | ||
8c2e1b00 AF |
87 | static bool superh_cpu_has_work(CPUState *cs) |
88 | { | |
89 | return cs->interrupt_request & CPU_INTERRUPT_HARD; | |
90 | } | |
91 | ||
90493830 | 92 | static void superh_cpu_reset_hold(Object *obj) |
339894be | 93 | { |
90493830 | 94 | CPUState *s = CPU(obj); |
339894be AF |
95 | SuperHCPU *cpu = SUPERH_CPU(s); |
96 | SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(cpu); | |
97 | CPUSH4State *env = &cpu->env; | |
98 | ||
90493830 PM |
99 | if (scc->parent_phases.hold) { |
100 | scc->parent_phases.hold(obj); | |
101 | } | |
339894be | 102 | |
1f5c00cf | 103 | memset(env, 0, offsetof(CPUSH4State, end_reset_fields)); |
c4bb0f99 AF |
104 | |
105 | env->pc = 0xA0000000; | |
106 | #if defined(CONFIG_USER_ONLY) | |
107 | env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */ | |
108 | set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */ | |
109 | #else | |
5ed9a259 AJ |
110 | env->sr = (1u << SR_MD) | (1u << SR_RB) | (1u << SR_BL) | |
111 | (1u << SR_I3) | (1u << SR_I2) | (1u << SR_I1) | (1u << SR_I0); | |
c4bb0f99 AF |
112 | env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */ |
113 | set_float_rounding_mode(float_round_to_zero, &env->fp_status); | |
114 | set_flush_to_zero(1, &env->fp_status); | |
115 | #endif | |
116 | set_default_nan_mode(1, &env->fp_status); | |
339894be AF |
117 | } |
118 | ||
d49dd523 PC |
119 | static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) |
120 | { | |
121 | info->mach = bfd_mach_sh4; | |
122 | info->print_insn = print_insn_sh; | |
123 | } | |
124 | ||
c1b382e7 AF |
125 | static ObjectClass *superh_cpu_class_by_name(const char *cpu_model) |
126 | { | |
127 | ObjectClass *oc; | |
d5ebe625 | 128 | char *s, *typename = NULL; |
c1b382e7 | 129 | |
d5ebe625 IM |
130 | s = g_ascii_strdown(cpu_model, -1); |
131 | if (strcmp(s, "any") == 0) { | |
132 | oc = object_class_by_name(TYPE_SH7750R_CPU); | |
133 | goto out; | |
c1b382e7 AF |
134 | } |
135 | ||
d5ebe625 IM |
136 | typename = g_strdup_printf(SUPERH_CPU_TYPE_NAME("%s"), s); |
137 | oc = object_class_by_name(typename); | |
c1b382e7 | 138 | |
d5ebe625 IM |
139 | out: |
140 | g_free(s); | |
141 | g_free(typename); | |
c1b382e7 AF |
142 | return oc; |
143 | } | |
144 | ||
c1b382e7 AF |
145 | static void sh7750r_cpu_initfn(Object *obj) |
146 | { | |
147 | SuperHCPU *cpu = SUPERH_CPU(obj); | |
148 | CPUSH4State *env = &cpu->env; | |
149 | ||
150 | env->id = SH_CPU_SH7750R; | |
c1b382e7 AF |
151 | env->features = SH_FEATURE_BCR3_AND_BCR4; |
152 | } | |
153 | ||
154 | static void sh7750r_class_init(ObjectClass *oc, void *data) | |
155 | { | |
156 | SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); | |
157 | ||
b350ab75 AF |
158 | scc->pvr = 0x00050000; |
159 | scc->prr = 0x00000100; | |
160 | scc->cvr = 0x00110000; | |
c1b382e7 AF |
161 | } |
162 | ||
c1b382e7 AF |
163 | static void sh7751r_cpu_initfn(Object *obj) |
164 | { | |
165 | SuperHCPU *cpu = SUPERH_CPU(obj); | |
166 | CPUSH4State *env = &cpu->env; | |
167 | ||
168 | env->id = SH_CPU_SH7751R; | |
c1b382e7 AF |
169 | env->features = SH_FEATURE_BCR3_AND_BCR4; |
170 | } | |
171 | ||
172 | static void sh7751r_class_init(ObjectClass *oc, void *data) | |
173 | { | |
174 | SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); | |
175 | ||
b350ab75 AF |
176 | scc->pvr = 0x04050005; |
177 | scc->prr = 0x00000113; | |
178 | scc->cvr = 0x00110000; /* Neutered caches, should be 0x20480000 */ | |
c1b382e7 AF |
179 | } |
180 | ||
c1b382e7 AF |
181 | static void sh7785_cpu_initfn(Object *obj) |
182 | { | |
183 | SuperHCPU *cpu = SUPERH_CPU(obj); | |
184 | CPUSH4State *env = &cpu->env; | |
185 | ||
186 | env->id = SH_CPU_SH7785; | |
c1b382e7 AF |
187 | env->features = SH_FEATURE_SH4A; |
188 | } | |
189 | ||
190 | static void sh7785_class_init(ObjectClass *oc, void *data) | |
191 | { | |
192 | SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); | |
193 | ||
b350ab75 AF |
194 | scc->pvr = 0x10300700; |
195 | scc->prr = 0x00000200; | |
196 | scc->cvr = 0x71440211; | |
c1b382e7 AF |
197 | } |
198 | ||
55acb588 AF |
199 | static void superh_cpu_realizefn(DeviceState *dev, Error **errp) |
200 | { | |
14a10fc3 | 201 | CPUState *cs = CPU(dev); |
55acb588 | 202 | SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(dev); |
ce5b1bbf LV |
203 | Error *local_err = NULL; |
204 | ||
205 | cpu_exec_realizefn(cs, &local_err); | |
206 | if (local_err != NULL) { | |
207 | error_propagate(errp, local_err); | |
208 | return; | |
209 | } | |
55acb588 | 210 | |
14a10fc3 AF |
211 | cpu_reset(cs); |
212 | qemu_init_vcpu(cs); | |
55acb588 AF |
213 | |
214 | scc->parent_realize(dev, errp); | |
215 | } | |
216 | ||
2b4b4906 AF |
217 | static void superh_cpu_initfn(Object *obj) |
218 | { | |
219 | SuperHCPU *cpu = SUPERH_CPU(obj); | |
220 | CPUSH4State *env = &cpu->env; | |
221 | ||
2b4b4906 AF |
222 | env->movcal_backup_tail = &(env->movcal_backup); |
223 | } | |
224 | ||
4336073b | 225 | #ifndef CONFIG_USER_ONLY |
1e45d31b AF |
226 | static const VMStateDescription vmstate_sh_cpu = { |
227 | .name = "cpu", | |
228 | .unmigratable = 1, | |
229 | }; | |
8b80bd28 PMD |
230 | |
231 | #include "hw/core/sysemu-cpu-ops.h" | |
232 | ||
233 | static const struct SysemuCPUOps sh4_sysemu_ops = { | |
08928c6d | 234 | .get_phys_page_debug = superh_cpu_get_phys_page_debug, |
8b80bd28 | 235 | }; |
4336073b | 236 | #endif |
1e45d31b | 237 | |
78271684 CF |
238 | #include "hw/core/tcg-cpu-ops.h" |
239 | ||
11906557 | 240 | static const struct TCGCPUOps superh_tcg_ops = { |
78271684 CF |
241 | .initialize = sh4_translate_init, |
242 | .synchronize_from_tb = superh_cpu_synchronize_from_tb, | |
e7977326 | 243 | .restore_state_to_opc = superh_restore_state_to_opc, |
78271684 CF |
244 | |
245 | #ifndef CONFIG_USER_ONLY | |
cac720ec | 246 | .tlb_fill = superh_cpu_tlb_fill, |
73166ca3 | 247 | .cpu_exec_interrupt = superh_cpu_exec_interrupt, |
78271684 CF |
248 | .do_interrupt = superh_cpu_do_interrupt, |
249 | .do_unaligned_access = superh_cpu_do_unaligned_access, | |
eb56afdb | 250 | .io_recompile_replay_branch = superh_io_recompile_replay_branch, |
78271684 CF |
251 | #endif /* !CONFIG_USER_ONLY */ |
252 | }; | |
253 | ||
339894be AF |
254 | static void superh_cpu_class_init(ObjectClass *oc, void *data) |
255 | { | |
1e45d31b | 256 | DeviceClass *dc = DEVICE_CLASS(oc); |
339894be AF |
257 | CPUClass *cc = CPU_CLASS(oc); |
258 | SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); | |
90493830 | 259 | ResettableClass *rc = RESETTABLE_CLASS(oc); |
339894be | 260 | |
bf853881 PMD |
261 | device_class_set_parent_realize(dc, superh_cpu_realizefn, |
262 | &scc->parent_realize); | |
55acb588 | 263 | |
90493830 PM |
264 | resettable_class_set_parent_phases(rc, NULL, superh_cpu_reset_hold, NULL, |
265 | &scc->parent_phases); | |
1e45d31b | 266 | |
c1b382e7 | 267 | cc->class_by_name = superh_cpu_class_by_name; |
8c2e1b00 | 268 | cc->has_work = superh_cpu_has_work; |
878096ee | 269 | cc->dump_state = superh_cpu_dump_state; |
f45748f1 | 270 | cc->set_pc = superh_cpu_set_pc; |
e4fdf9df | 271 | cc->get_pc = superh_cpu_get_pc; |
5b50e790 AF |
272 | cc->gdb_read_register = superh_cpu_gdb_read_register; |
273 | cc->gdb_write_register = superh_cpu_gdb_write_register; | |
f98bce2b | 274 | #ifndef CONFIG_USER_ONLY |
8b80bd28 | 275 | cc->sysemu_ops = &sh4_sysemu_ops; |
4336073b | 276 | dc->vmsd = &vmstate_sh_cpu; |
00b941e5 | 277 | #endif |
d49dd523 PC |
278 | cc->disas_set_info = superh_cpu_disas_set_info; |
279 | ||
a0e372f0 | 280 | cc->gdb_num_core_regs = 59; |
78271684 | 281 | cc->tcg_ops = &superh_tcg_ops; |
339894be AF |
282 | } |
283 | ||
974e58d2 IM |
284 | #define DEFINE_SUPERH_CPU_TYPE(type_name, cinit, initfn) \ |
285 | { \ | |
286 | .name = type_name, \ | |
287 | .parent = TYPE_SUPERH_CPU, \ | |
288 | .class_init = cinit, \ | |
289 | .instance_init = initfn, \ | |
290 | } | |
291 | static const TypeInfo superh_cpu_type_infos[] = { | |
292 | { | |
293 | .name = TYPE_SUPERH_CPU, | |
294 | .parent = TYPE_CPU, | |
295 | .instance_size = sizeof(SuperHCPU), | |
f669c992 | 296 | .instance_align = __alignof(SuperHCPU), |
974e58d2 IM |
297 | .instance_init = superh_cpu_initfn, |
298 | .abstract = true, | |
299 | .class_size = sizeof(SuperHCPUClass), | |
300 | .class_init = superh_cpu_class_init, | |
301 | }, | |
302 | DEFINE_SUPERH_CPU_TYPE(TYPE_SH7750R_CPU, sh7750r_class_init, | |
303 | sh7750r_cpu_initfn), | |
304 | DEFINE_SUPERH_CPU_TYPE(TYPE_SH7751R_CPU, sh7751r_class_init, | |
305 | sh7751r_cpu_initfn), | |
306 | DEFINE_SUPERH_CPU_TYPE(TYPE_SH7785_CPU, sh7785_class_init, | |
307 | sh7785_cpu_initfn), | |
339894be | 308 | |
974e58d2 | 309 | }; |
339894be | 310 | |
974e58d2 | 311 | DEFINE_TYPES(superh_cpu_type_infos) |