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339894be AF |
1 | /* |
2 | * QEMU SuperH CPU | |
3 | * | |
c4bb0f99 | 4 | * Copyright (c) 2005 Samuel Tardieu |
339894be AF |
5 | * Copyright (c) 2012 SUSE LINUX Products GmbH |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2.1 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
18 | * License along with this library; if not, see | |
19 | * <http://www.gnu.org/licenses/lgpl-2.1.html> | |
20 | */ | |
21 | ||
9d4c9946 | 22 | #include "qemu/osdep.h" |
da34e65c | 23 | #include "qapi/error.h" |
339894be AF |
24 | #include "cpu.h" |
25 | #include "qemu-common.h" | |
1e45d31b | 26 | #include "migration/vmstate.h" |
63c91552 | 27 | #include "exec/exec-all.h" |
339894be AF |
28 | |
29 | ||
f45748f1 AF |
30 | static void superh_cpu_set_pc(CPUState *cs, vaddr value) |
31 | { | |
32 | SuperHCPU *cpu = SUPERH_CPU(cs); | |
33 | ||
34 | cpu->env.pc = value; | |
35 | } | |
36 | ||
bdf7ae5b AF |
37 | static void superh_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) |
38 | { | |
39 | SuperHCPU *cpu = SUPERH_CPU(cs); | |
40 | ||
41 | cpu->env.pc = tb->pc; | |
ca69176d | 42 | cpu->env.flags = tb->flags & TB_FLAG_ENVFLAGS_MASK; |
bdf7ae5b AF |
43 | } |
44 | ||
8c2e1b00 AF |
45 | static bool superh_cpu_has_work(CPUState *cs) |
46 | { | |
47 | return cs->interrupt_request & CPU_INTERRUPT_HARD; | |
48 | } | |
49 | ||
339894be AF |
50 | /* CPUClass::reset() */ |
51 | static void superh_cpu_reset(CPUState *s) | |
52 | { | |
53 | SuperHCPU *cpu = SUPERH_CPU(s); | |
54 | SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(cpu); | |
55 | CPUSH4State *env = &cpu->env; | |
56 | ||
57 | scc->parent_reset(s); | |
58 | ||
1f5c00cf | 59 | memset(env, 0, offsetof(CPUSH4State, end_reset_fields)); |
c4bb0f99 AF |
60 | |
61 | env->pc = 0xA0000000; | |
62 | #if defined(CONFIG_USER_ONLY) | |
63 | env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */ | |
64 | set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */ | |
65 | #else | |
5ed9a259 AJ |
66 | env->sr = (1u << SR_MD) | (1u << SR_RB) | (1u << SR_BL) | |
67 | (1u << SR_I3) | (1u << SR_I2) | (1u << SR_I1) | (1u << SR_I0); | |
c4bb0f99 AF |
68 | env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */ |
69 | set_float_rounding_mode(float_round_to_zero, &env->fp_status); | |
70 | set_flush_to_zero(1, &env->fp_status); | |
71 | #endif | |
72 | set_default_nan_mode(1, &env->fp_status); | |
af39bc8c | 73 | set_snan_bit_is_one(1, &env->fp_status); |
339894be AF |
74 | } |
75 | ||
d49dd523 PC |
76 | static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) |
77 | { | |
78 | info->mach = bfd_mach_sh4; | |
79 | info->print_insn = print_insn_sh; | |
80 | } | |
81 | ||
c1b382e7 AF |
82 | typedef struct SuperHCPUListState { |
83 | fprintf_function cpu_fprintf; | |
84 | FILE *file; | |
85 | } SuperHCPUListState; | |
86 | ||
87 | /* Sort alphabetically by type name. */ | |
88 | static gint superh_cpu_list_compare(gconstpointer a, gconstpointer b) | |
89 | { | |
90 | ObjectClass *class_a = (ObjectClass *)a; | |
91 | ObjectClass *class_b = (ObjectClass *)b; | |
92 | const char *name_a, *name_b; | |
93 | ||
94 | name_a = object_class_get_name(class_a); | |
95 | name_b = object_class_get_name(class_b); | |
96 | return strcmp(name_a, name_b); | |
97 | } | |
98 | ||
99 | static void superh_cpu_list_entry(gpointer data, gpointer user_data) | |
100 | { | |
c1b382e7 | 101 | SuperHCPUListState *s = user_data; |
633cd135 IM |
102 | const char *typename = object_class_get_name(OBJECT_CLASS(data)); |
103 | int len = strlen(typename) - strlen(SUPERH_CPU_TYPE_SUFFIX); | |
c1b382e7 | 104 | |
633cd135 | 105 | (*s->cpu_fprintf)(s->file, "%.*s\n", len, typename); |
c1b382e7 AF |
106 | } |
107 | ||
108 | void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf) | |
109 | { | |
110 | SuperHCPUListState s = { | |
111 | .cpu_fprintf = cpu_fprintf, | |
112 | .file = f, | |
113 | }; | |
114 | GSList *list; | |
115 | ||
116 | list = object_class_get_list(TYPE_SUPERH_CPU, false); | |
117 | list = g_slist_sort(list, superh_cpu_list_compare); | |
118 | g_slist_foreach(list, superh_cpu_list_entry, &s); | |
119 | g_slist_free(list); | |
120 | } | |
121 | ||
c1b382e7 AF |
122 | static ObjectClass *superh_cpu_class_by_name(const char *cpu_model) |
123 | { | |
124 | ObjectClass *oc; | |
d5ebe625 | 125 | char *s, *typename = NULL; |
c1b382e7 | 126 | |
d5ebe625 IM |
127 | s = g_ascii_strdown(cpu_model, -1); |
128 | if (strcmp(s, "any") == 0) { | |
129 | oc = object_class_by_name(TYPE_SH7750R_CPU); | |
130 | goto out; | |
c1b382e7 AF |
131 | } |
132 | ||
d5ebe625 IM |
133 | typename = g_strdup_printf(SUPERH_CPU_TYPE_NAME("%s"), s); |
134 | oc = object_class_by_name(typename); | |
135 | if (oc != NULL && object_class_is_abstract(oc)) { | |
136 | oc = NULL; | |
c1b382e7 AF |
137 | } |
138 | ||
d5ebe625 IM |
139 | out: |
140 | g_free(s); | |
141 | g_free(typename); | |
c1b382e7 AF |
142 | return oc; |
143 | } | |
144 | ||
c1b382e7 AF |
145 | static void sh7750r_cpu_initfn(Object *obj) |
146 | { | |
147 | SuperHCPU *cpu = SUPERH_CPU(obj); | |
148 | CPUSH4State *env = &cpu->env; | |
149 | ||
150 | env->id = SH_CPU_SH7750R; | |
c1b382e7 AF |
151 | env->features = SH_FEATURE_BCR3_AND_BCR4; |
152 | } | |
153 | ||
154 | static void sh7750r_class_init(ObjectClass *oc, void *data) | |
155 | { | |
156 | SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); | |
157 | ||
b350ab75 AF |
158 | scc->pvr = 0x00050000; |
159 | scc->prr = 0x00000100; | |
160 | scc->cvr = 0x00110000; | |
c1b382e7 AF |
161 | } |
162 | ||
c1b382e7 AF |
163 | static void sh7751r_cpu_initfn(Object *obj) |
164 | { | |
165 | SuperHCPU *cpu = SUPERH_CPU(obj); | |
166 | CPUSH4State *env = &cpu->env; | |
167 | ||
168 | env->id = SH_CPU_SH7751R; | |
c1b382e7 AF |
169 | env->features = SH_FEATURE_BCR3_AND_BCR4; |
170 | } | |
171 | ||
172 | static void sh7751r_class_init(ObjectClass *oc, void *data) | |
173 | { | |
174 | SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); | |
175 | ||
b350ab75 AF |
176 | scc->pvr = 0x04050005; |
177 | scc->prr = 0x00000113; | |
178 | scc->cvr = 0x00110000; /* Neutered caches, should be 0x20480000 */ | |
c1b382e7 AF |
179 | } |
180 | ||
c1b382e7 AF |
181 | static void sh7785_cpu_initfn(Object *obj) |
182 | { | |
183 | SuperHCPU *cpu = SUPERH_CPU(obj); | |
184 | CPUSH4State *env = &cpu->env; | |
185 | ||
186 | env->id = SH_CPU_SH7785; | |
c1b382e7 AF |
187 | env->features = SH_FEATURE_SH4A; |
188 | } | |
189 | ||
190 | static void sh7785_class_init(ObjectClass *oc, void *data) | |
191 | { | |
192 | SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); | |
193 | ||
b350ab75 AF |
194 | scc->pvr = 0x10300700; |
195 | scc->prr = 0x00000200; | |
196 | scc->cvr = 0x71440211; | |
c1b382e7 AF |
197 | } |
198 | ||
55acb588 AF |
199 | static void superh_cpu_realizefn(DeviceState *dev, Error **errp) |
200 | { | |
14a10fc3 | 201 | CPUState *cs = CPU(dev); |
55acb588 | 202 | SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(dev); |
ce5b1bbf LV |
203 | Error *local_err = NULL; |
204 | ||
205 | cpu_exec_realizefn(cs, &local_err); | |
206 | if (local_err != NULL) { | |
207 | error_propagate(errp, local_err); | |
208 | return; | |
209 | } | |
55acb588 | 210 | |
14a10fc3 AF |
211 | cpu_reset(cs); |
212 | qemu_init_vcpu(cs); | |
55acb588 AF |
213 | |
214 | scc->parent_realize(dev, errp); | |
215 | } | |
216 | ||
2b4b4906 AF |
217 | static void superh_cpu_initfn(Object *obj) |
218 | { | |
c05efcb1 | 219 | CPUState *cs = CPU(obj); |
2b4b4906 AF |
220 | SuperHCPU *cpu = SUPERH_CPU(obj); |
221 | CPUSH4State *env = &cpu->env; | |
222 | ||
c05efcb1 | 223 | cs->env_ptr = env; |
2b4b4906 AF |
224 | |
225 | env->movcal_backup_tail = &(env->movcal_backup); | |
226 | } | |
227 | ||
1e45d31b AF |
228 | static const VMStateDescription vmstate_sh_cpu = { |
229 | .name = "cpu", | |
230 | .unmigratable = 1, | |
231 | }; | |
232 | ||
339894be AF |
233 | static void superh_cpu_class_init(ObjectClass *oc, void *data) |
234 | { | |
1e45d31b | 235 | DeviceClass *dc = DEVICE_CLASS(oc); |
339894be AF |
236 | CPUClass *cc = CPU_CLASS(oc); |
237 | SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); | |
238 | ||
55acb588 AF |
239 | scc->parent_realize = dc->realize; |
240 | dc->realize = superh_cpu_realizefn; | |
241 | ||
339894be AF |
242 | scc->parent_reset = cc->reset; |
243 | cc->reset = superh_cpu_reset; | |
1e45d31b | 244 | |
c1b382e7 | 245 | cc->class_by_name = superh_cpu_class_by_name; |
8c2e1b00 | 246 | cc->has_work = superh_cpu_has_work; |
97a8ea5a | 247 | cc->do_interrupt = superh_cpu_do_interrupt; |
f47ede19 | 248 | cc->cpu_exec_interrupt = superh_cpu_exec_interrupt; |
878096ee | 249 | cc->dump_state = superh_cpu_dump_state; |
f45748f1 | 250 | cc->set_pc = superh_cpu_set_pc; |
bdf7ae5b | 251 | cc->synchronize_from_tb = superh_cpu_synchronize_from_tb; |
5b50e790 AF |
252 | cc->gdb_read_register = superh_cpu_gdb_read_register; |
253 | cc->gdb_write_register = superh_cpu_gdb_write_register; | |
7510454e AF |
254 | #ifdef CONFIG_USER_ONLY |
255 | cc->handle_mmu_fault = superh_cpu_handle_mmu_fault; | |
256 | #else | |
34257c21 | 257 | cc->do_unaligned_access = superh_cpu_do_unaligned_access; |
00b941e5 AF |
258 | cc->get_phys_page_debug = superh_cpu_get_phys_page_debug; |
259 | #endif | |
d49dd523 | 260 | cc->disas_set_info = superh_cpu_disas_set_info; |
55c3ceef | 261 | cc->tcg_initialize = sh4_translate_init; |
d49dd523 | 262 | |
a0e372f0 | 263 | cc->gdb_num_core_regs = 59; |
4c315c27 | 264 | |
d49dd523 | 265 | dc->vmsd = &vmstate_sh_cpu; |
339894be AF |
266 | } |
267 | ||
974e58d2 IM |
268 | #define DEFINE_SUPERH_CPU_TYPE(type_name, cinit, initfn) \ |
269 | { \ | |
270 | .name = type_name, \ | |
271 | .parent = TYPE_SUPERH_CPU, \ | |
272 | .class_init = cinit, \ | |
273 | .instance_init = initfn, \ | |
274 | } | |
275 | static const TypeInfo superh_cpu_type_infos[] = { | |
276 | { | |
277 | .name = TYPE_SUPERH_CPU, | |
278 | .parent = TYPE_CPU, | |
279 | .instance_size = sizeof(SuperHCPU), | |
280 | .instance_init = superh_cpu_initfn, | |
281 | .abstract = true, | |
282 | .class_size = sizeof(SuperHCPUClass), | |
283 | .class_init = superh_cpu_class_init, | |
284 | }, | |
285 | DEFINE_SUPERH_CPU_TYPE(TYPE_SH7750R_CPU, sh7750r_class_init, | |
286 | sh7750r_cpu_initfn), | |
287 | DEFINE_SUPERH_CPU_TYPE(TYPE_SH7751R_CPU, sh7751r_class_init, | |
288 | sh7751r_cpu_initfn), | |
289 | DEFINE_SUPERH_CPU_TYPE(TYPE_SH7785_CPU, sh7785_class_init, | |
290 | sh7785_cpu_initfn), | |
339894be | 291 | |
974e58d2 | 292 | }; |
339894be | 293 | |
974e58d2 | 294 | DEFINE_TYPES(superh_cpu_type_infos) |