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339894be AF |
1 | /* |
2 | * QEMU SuperH CPU | |
3 | * | |
c4bb0f99 | 4 | * Copyright (c) 2005 Samuel Tardieu |
339894be AF |
5 | * Copyright (c) 2012 SUSE LINUX Products GmbH |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2.1 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
18 | * License along with this library; if not, see | |
19 | * <http://www.gnu.org/licenses/lgpl-2.1.html> | |
20 | */ | |
21 | ||
9d4c9946 | 22 | #include "qemu/osdep.h" |
da34e65c | 23 | #include "qapi/error.h" |
0442428a | 24 | #include "qemu/qemu-print.h" |
339894be | 25 | #include "cpu.h" |
1e45d31b | 26 | #include "migration/vmstate.h" |
63c91552 | 27 | #include "exec/exec-all.h" |
5f8ab000 | 28 | #include "fpu/softfloat-helpers.h" |
339894be | 29 | |
f45748f1 AF |
30 | static void superh_cpu_set_pc(CPUState *cs, vaddr value) |
31 | { | |
32 | SuperHCPU *cpu = SUPERH_CPU(cs); | |
33 | ||
34 | cpu->env.pc = value; | |
35 | } | |
36 | ||
04a37d4c RH |
37 | static void superh_cpu_synchronize_from_tb(CPUState *cs, |
38 | const TranslationBlock *tb) | |
bdf7ae5b AF |
39 | { |
40 | SuperHCPU *cpu = SUPERH_CPU(cs); | |
41 | ||
42 | cpu->env.pc = tb->pc; | |
ca69176d | 43 | cpu->env.flags = tb->flags & TB_FLAG_ENVFLAGS_MASK; |
bdf7ae5b AF |
44 | } |
45 | ||
8c2e1b00 AF |
46 | static bool superh_cpu_has_work(CPUState *cs) |
47 | { | |
48 | return cs->interrupt_request & CPU_INTERRUPT_HARD; | |
49 | } | |
50 | ||
781c67ca | 51 | static void superh_cpu_reset(DeviceState *dev) |
339894be | 52 | { |
781c67ca | 53 | CPUState *s = CPU(dev); |
339894be AF |
54 | SuperHCPU *cpu = SUPERH_CPU(s); |
55 | SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(cpu); | |
56 | CPUSH4State *env = &cpu->env; | |
57 | ||
781c67ca | 58 | scc->parent_reset(dev); |
339894be | 59 | |
1f5c00cf | 60 | memset(env, 0, offsetof(CPUSH4State, end_reset_fields)); |
c4bb0f99 AF |
61 | |
62 | env->pc = 0xA0000000; | |
63 | #if defined(CONFIG_USER_ONLY) | |
64 | env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */ | |
65 | set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */ | |
66 | #else | |
5ed9a259 AJ |
67 | env->sr = (1u << SR_MD) | (1u << SR_RB) | (1u << SR_BL) | |
68 | (1u << SR_I3) | (1u << SR_I2) | (1u << SR_I1) | (1u << SR_I0); | |
c4bb0f99 AF |
69 | env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */ |
70 | set_float_rounding_mode(float_round_to_zero, &env->fp_status); | |
71 | set_flush_to_zero(1, &env->fp_status); | |
72 | #endif | |
73 | set_default_nan_mode(1, &env->fp_status); | |
339894be AF |
74 | } |
75 | ||
d49dd523 PC |
76 | static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) |
77 | { | |
78 | info->mach = bfd_mach_sh4; | |
79 | info->print_insn = print_insn_sh; | |
80 | } | |
81 | ||
c1b382e7 AF |
82 | static void superh_cpu_list_entry(gpointer data, gpointer user_data) |
83 | { | |
633cd135 IM |
84 | const char *typename = object_class_get_name(OBJECT_CLASS(data)); |
85 | int len = strlen(typename) - strlen(SUPERH_CPU_TYPE_SUFFIX); | |
c1b382e7 | 86 | |
0442428a | 87 | qemu_printf("%.*s\n", len, typename); |
c1b382e7 AF |
88 | } |
89 | ||
0442428a | 90 | void sh4_cpu_list(void) |
c1b382e7 | 91 | { |
c1b382e7 AF |
92 | GSList *list; |
93 | ||
47c66009 | 94 | list = object_class_get_list_sorted(TYPE_SUPERH_CPU, false); |
0442428a | 95 | g_slist_foreach(list, superh_cpu_list_entry, NULL); |
c1b382e7 AF |
96 | g_slist_free(list); |
97 | } | |
98 | ||
c1b382e7 AF |
99 | static ObjectClass *superh_cpu_class_by_name(const char *cpu_model) |
100 | { | |
101 | ObjectClass *oc; | |
d5ebe625 | 102 | char *s, *typename = NULL; |
c1b382e7 | 103 | |
d5ebe625 IM |
104 | s = g_ascii_strdown(cpu_model, -1); |
105 | if (strcmp(s, "any") == 0) { | |
106 | oc = object_class_by_name(TYPE_SH7750R_CPU); | |
107 | goto out; | |
c1b382e7 AF |
108 | } |
109 | ||
d5ebe625 IM |
110 | typename = g_strdup_printf(SUPERH_CPU_TYPE_NAME("%s"), s); |
111 | oc = object_class_by_name(typename); | |
112 | if (oc != NULL && object_class_is_abstract(oc)) { | |
113 | oc = NULL; | |
c1b382e7 AF |
114 | } |
115 | ||
d5ebe625 IM |
116 | out: |
117 | g_free(s); | |
118 | g_free(typename); | |
c1b382e7 AF |
119 | return oc; |
120 | } | |
121 | ||
c1b382e7 AF |
122 | static void sh7750r_cpu_initfn(Object *obj) |
123 | { | |
124 | SuperHCPU *cpu = SUPERH_CPU(obj); | |
125 | CPUSH4State *env = &cpu->env; | |
126 | ||
127 | env->id = SH_CPU_SH7750R; | |
c1b382e7 AF |
128 | env->features = SH_FEATURE_BCR3_AND_BCR4; |
129 | } | |
130 | ||
131 | static void sh7750r_class_init(ObjectClass *oc, void *data) | |
132 | { | |
133 | SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); | |
134 | ||
b350ab75 AF |
135 | scc->pvr = 0x00050000; |
136 | scc->prr = 0x00000100; | |
137 | scc->cvr = 0x00110000; | |
c1b382e7 AF |
138 | } |
139 | ||
c1b382e7 AF |
140 | static void sh7751r_cpu_initfn(Object *obj) |
141 | { | |
142 | SuperHCPU *cpu = SUPERH_CPU(obj); | |
143 | CPUSH4State *env = &cpu->env; | |
144 | ||
145 | env->id = SH_CPU_SH7751R; | |
c1b382e7 AF |
146 | env->features = SH_FEATURE_BCR3_AND_BCR4; |
147 | } | |
148 | ||
149 | static void sh7751r_class_init(ObjectClass *oc, void *data) | |
150 | { | |
151 | SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); | |
152 | ||
b350ab75 AF |
153 | scc->pvr = 0x04050005; |
154 | scc->prr = 0x00000113; | |
155 | scc->cvr = 0x00110000; /* Neutered caches, should be 0x20480000 */ | |
c1b382e7 AF |
156 | } |
157 | ||
c1b382e7 AF |
158 | static void sh7785_cpu_initfn(Object *obj) |
159 | { | |
160 | SuperHCPU *cpu = SUPERH_CPU(obj); | |
161 | CPUSH4State *env = &cpu->env; | |
162 | ||
163 | env->id = SH_CPU_SH7785; | |
c1b382e7 AF |
164 | env->features = SH_FEATURE_SH4A; |
165 | } | |
166 | ||
167 | static void sh7785_class_init(ObjectClass *oc, void *data) | |
168 | { | |
169 | SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); | |
170 | ||
b350ab75 AF |
171 | scc->pvr = 0x10300700; |
172 | scc->prr = 0x00000200; | |
173 | scc->cvr = 0x71440211; | |
c1b382e7 AF |
174 | } |
175 | ||
55acb588 AF |
176 | static void superh_cpu_realizefn(DeviceState *dev, Error **errp) |
177 | { | |
14a10fc3 | 178 | CPUState *cs = CPU(dev); |
55acb588 | 179 | SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(dev); |
ce5b1bbf LV |
180 | Error *local_err = NULL; |
181 | ||
182 | cpu_exec_realizefn(cs, &local_err); | |
183 | if (local_err != NULL) { | |
184 | error_propagate(errp, local_err); | |
185 | return; | |
186 | } | |
55acb588 | 187 | |
14a10fc3 AF |
188 | cpu_reset(cs); |
189 | qemu_init_vcpu(cs); | |
55acb588 AF |
190 | |
191 | scc->parent_realize(dev, errp); | |
192 | } | |
193 | ||
2b4b4906 AF |
194 | static void superh_cpu_initfn(Object *obj) |
195 | { | |
196 | SuperHCPU *cpu = SUPERH_CPU(obj); | |
197 | CPUSH4State *env = &cpu->env; | |
198 | ||
7506ed90 | 199 | cpu_set_cpustate_pointers(cpu); |
2b4b4906 AF |
200 | |
201 | env->movcal_backup_tail = &(env->movcal_backup); | |
202 | } | |
203 | ||
1e45d31b AF |
204 | static const VMStateDescription vmstate_sh_cpu = { |
205 | .name = "cpu", | |
206 | .unmigratable = 1, | |
207 | }; | |
208 | ||
78271684 CF |
209 | #include "hw/core/tcg-cpu-ops.h" |
210 | ||
211 | static struct TCGCPUOps superh_tcg_ops = { | |
212 | .initialize = sh4_translate_init, | |
213 | .synchronize_from_tb = superh_cpu_synchronize_from_tb, | |
214 | .cpu_exec_interrupt = superh_cpu_exec_interrupt, | |
215 | .tlb_fill = superh_cpu_tlb_fill, | |
216 | ||
217 | #ifndef CONFIG_USER_ONLY | |
218 | .do_interrupt = superh_cpu_do_interrupt, | |
219 | .do_unaligned_access = superh_cpu_do_unaligned_access, | |
220 | #endif /* !CONFIG_USER_ONLY */ | |
221 | }; | |
222 | ||
339894be AF |
223 | static void superh_cpu_class_init(ObjectClass *oc, void *data) |
224 | { | |
1e45d31b | 225 | DeviceClass *dc = DEVICE_CLASS(oc); |
339894be AF |
226 | CPUClass *cc = CPU_CLASS(oc); |
227 | SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); | |
228 | ||
bf853881 PMD |
229 | device_class_set_parent_realize(dc, superh_cpu_realizefn, |
230 | &scc->parent_realize); | |
55acb588 | 231 | |
781c67ca | 232 | device_class_set_parent_reset(dc, superh_cpu_reset, &scc->parent_reset); |
1e45d31b | 233 | |
c1b382e7 | 234 | cc->class_by_name = superh_cpu_class_by_name; |
8c2e1b00 | 235 | cc->has_work = superh_cpu_has_work; |
878096ee | 236 | cc->dump_state = superh_cpu_dump_state; |
f45748f1 | 237 | cc->set_pc = superh_cpu_set_pc; |
5b50e790 AF |
238 | cc->gdb_read_register = superh_cpu_gdb_read_register; |
239 | cc->gdb_write_register = superh_cpu_gdb_write_register; | |
f98bce2b | 240 | #ifndef CONFIG_USER_ONLY |
00b941e5 AF |
241 | cc->get_phys_page_debug = superh_cpu_get_phys_page_debug; |
242 | #endif | |
d49dd523 PC |
243 | cc->disas_set_info = superh_cpu_disas_set_info; |
244 | ||
a0e372f0 | 245 | cc->gdb_num_core_regs = 59; |
4c315c27 | 246 | |
d49dd523 | 247 | dc->vmsd = &vmstate_sh_cpu; |
78271684 | 248 | cc->tcg_ops = &superh_tcg_ops; |
339894be AF |
249 | } |
250 | ||
974e58d2 IM |
251 | #define DEFINE_SUPERH_CPU_TYPE(type_name, cinit, initfn) \ |
252 | { \ | |
253 | .name = type_name, \ | |
254 | .parent = TYPE_SUPERH_CPU, \ | |
255 | .class_init = cinit, \ | |
256 | .instance_init = initfn, \ | |
257 | } | |
258 | static const TypeInfo superh_cpu_type_infos[] = { | |
259 | { | |
260 | .name = TYPE_SUPERH_CPU, | |
261 | .parent = TYPE_CPU, | |
262 | .instance_size = sizeof(SuperHCPU), | |
263 | .instance_init = superh_cpu_initfn, | |
264 | .abstract = true, | |
265 | .class_size = sizeof(SuperHCPUClass), | |
266 | .class_init = superh_cpu_class_init, | |
267 | }, | |
268 | DEFINE_SUPERH_CPU_TYPE(TYPE_SH7750R_CPU, sh7750r_class_init, | |
269 | sh7750r_cpu_initfn), | |
270 | DEFINE_SUPERH_CPU_TYPE(TYPE_SH7751R_CPU, sh7751r_class_init, | |
271 | sh7751r_cpu_initfn), | |
272 | DEFINE_SUPERH_CPU_TYPE(TYPE_SH7785_CPU, sh7785_class_init, | |
273 | sh7785_cpu_initfn), | |
339894be | 274 | |
974e58d2 | 275 | }; |
339894be | 276 | |
974e58d2 | 277 | DEFINE_TYPES(superh_cpu_type_infos) |