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Commit | Line | Data |
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fdf9b3e8 FB |
1 | /* |
2 | * SH4 emulation | |
5fafdf24 | 3 | * |
fdf9b3e8 FB |
4 | * Copyright (c) 2005 Samuel Tardieu |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
6faf2b6c | 9 | * version 2.1 of the License, or (at your option) any later version. |
fdf9b3e8 FB |
10 | * |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
fdf9b3e8 | 18 | */ |
9d4c9946 | 19 | #include "qemu/osdep.h" |
3e457172 | 20 | #include "cpu.h" |
2ef6175a | 21 | #include "exec/helper-proto.h" |
63c91552 | 22 | #include "exec/exec-all.h" |
f08b6170 | 23 | #include "exec/cpu_ldst.h" |
24f91e81 | 24 | #include "fpu/softfloat.h" |
fdf9b3e8 | 25 | |
fdf9b3e8 FB |
26 | #ifndef CONFIG_USER_ONLY |
27 | ||
34257c21 AJ |
28 | void superh_cpu_do_unaligned_access(CPUState *cs, vaddr addr, |
29 | MMUAccessType access_type, | |
30 | int mmu_idx, uintptr_t retaddr) | |
31 | { | |
32 | switch (access_type) { | |
33 | case MMU_INST_FETCH: | |
34 | case MMU_DATA_LOAD: | |
35 | cs->exception_index = 0x0e0; | |
36 | break; | |
37 | case MMU_DATA_STORE: | |
38 | cs->exception_index = 0x100; | |
39 | break; | |
40 | } | |
41 | cpu_loop_exit_restore(cs, retaddr); | |
42 | } | |
43 | ||
fdf9b3e8 FB |
44 | #endif |
45 | ||
485d0035 | 46 | void helper_ldtlb(CPUSH4State *env) |
ea2b542a AJ |
47 | { |
48 | #ifdef CONFIG_USER_ONLY | |
dad1c8ec | 49 | cpu_abort(env_cpu(env), "Unhandled ldtlb"); |
ea2b542a AJ |
50 | #else |
51 | cpu_load_tlb(env); | |
52 | #endif | |
53 | } | |
54 | ||
10127400 AJ |
55 | static inline void QEMU_NORETURN raise_exception(CPUSH4State *env, int index, |
56 | uintptr_t retaddr) | |
e6afc2f4 | 57 | { |
dad1c8ec | 58 | CPUState *cs = env_cpu(env); |
27103424 AF |
59 | |
60 | cs->exception_index = index; | |
57e2d417 | 61 | cpu_loop_exit_restore(cs, retaddr); |
e6afc2f4 AJ |
62 | } |
63 | ||
485d0035 | 64 | void helper_raise_illegal_instruction(CPUSH4State *env) |
fd4bab10 | 65 | { |
10127400 | 66 | raise_exception(env, 0x180, 0); |
fd4bab10 AJ |
67 | } |
68 | ||
485d0035 | 69 | void helper_raise_slot_illegal_instruction(CPUSH4State *env) |
e6afc2f4 | 70 | { |
10127400 | 71 | raise_exception(env, 0x1a0, 0); |
e6afc2f4 AJ |
72 | } |
73 | ||
485d0035 | 74 | void helper_raise_fpu_disable(CPUSH4State *env) |
d8299bcc | 75 | { |
10127400 | 76 | raise_exception(env, 0x800, 0); |
d8299bcc AJ |
77 | } |
78 | ||
485d0035 | 79 | void helper_raise_slot_fpu_disable(CPUSH4State *env) |
d8299bcc | 80 | { |
10127400 | 81 | raise_exception(env, 0x820, 0); |
d8299bcc AJ |
82 | } |
83 | ||
485d0035 | 84 | void helper_debug(CPUSH4State *env) |
e6afc2f4 | 85 | { |
10127400 | 86 | raise_exception(env, EXCP_DEBUG, 0); |
e6afc2f4 AJ |
87 | } |
88 | ||
10127400 | 89 | void helper_sleep(CPUSH4State *env) |
e6afc2f4 | 90 | { |
dad1c8ec | 91 | CPUState *cs = env_cpu(env); |
259186a7 AF |
92 | |
93 | cs->halted = 1; | |
efac4154 | 94 | env->in_sleep = 1; |
10127400 | 95 | raise_exception(env, EXCP_HLT, 0); |
e6afc2f4 AJ |
96 | } |
97 | ||
485d0035 | 98 | void helper_trapa(CPUSH4State *env, uint32_t tra) |
e6afc2f4 AJ |
99 | { |
100 | env->tra = tra << 2; | |
10127400 | 101 | raise_exception(env, 0x160, 0); |
e6afc2f4 AJ |
102 | } |
103 | ||
4bfa602b RH |
104 | void helper_exclusive(CPUSH4State *env) |
105 | { | |
106 | /* We do not want cpu_restore_state to run. */ | |
29a0af61 | 107 | cpu_loop_exit_atomic(env_cpu(env), 0); |
4bfa602b RH |
108 | } |
109 | ||
485d0035 | 110 | void helper_movcal(CPUSH4State *env, uint32_t address, uint32_t value) |
852d481f EI |
111 | { |
112 | if (cpu_sh4_is_cached (env, address)) | |
113 | { | |
01a72012 PM |
114 | memory_content *r = g_new(memory_content, 1); |
115 | ||
852d481f EI |
116 | r->address = address; |
117 | r->value = value; | |
118 | r->next = NULL; | |
119 | ||
120 | *(env->movcal_backup_tail) = r; | |
121 | env->movcal_backup_tail = &(r->next); | |
122 | } | |
123 | } | |
124 | ||
485d0035 | 125 | void helper_discard_movcal_backup(CPUSH4State *env) |
852d481f EI |
126 | { |
127 | memory_content *current = env->movcal_backup; | |
128 | ||
129 | while(current) | |
130 | { | |
131 | memory_content *next = current->next; | |
01a72012 | 132 | g_free(current); |
852d481f | 133 | env->movcal_backup = current = next; |
b9d38e95 | 134 | if (current == NULL) |
852d481f EI |
135 | env->movcal_backup_tail = &(env->movcal_backup); |
136 | } | |
137 | } | |
138 | ||
485d0035 | 139 | void helper_ocbi(CPUSH4State *env, uint32_t address) |
852d481f EI |
140 | { |
141 | memory_content **current = &(env->movcal_backup); | |
142 | while (*current) | |
143 | { | |
144 | uint32_t a = (*current)->address; | |
145 | if ((a & ~0x1F) == (address & ~0x1F)) | |
146 | { | |
147 | memory_content *next = (*current)->next; | |
485d0035 | 148 | cpu_stl_data(env, a, (*current)->value); |
852d481f | 149 | |
b9d38e95 | 150 | if (next == NULL) |
852d481f EI |
151 | { |
152 | env->movcal_backup_tail = current; | |
153 | } | |
154 | ||
01a72012 | 155 | g_free(*current); |
852d481f EI |
156 | *current = next; |
157 | break; | |
158 | } | |
159 | } | |
160 | } | |
161 | ||
485d0035 | 162 | void helper_macl(CPUSH4State *env, uint32_t arg0, uint32_t arg1) |
fdf9b3e8 FB |
163 | { |
164 | int64_t res; | |
165 | ||
166 | res = ((uint64_t) env->mach << 32) | env->macl; | |
6f06939b | 167 | res += (int64_t) (int32_t) arg0 *(int64_t) (int32_t) arg1; |
fdf9b3e8 FB |
168 | env->mach = (res >> 32) & 0xffffffff; |
169 | env->macl = res & 0xffffffff; | |
5ed9a259 | 170 | if (env->sr & (1u << SR_S)) { |
fdf9b3e8 FB |
171 | if (res < 0) |
172 | env->mach |= 0xffff0000; | |
173 | else | |
174 | env->mach &= 0x00007fff; | |
175 | } | |
176 | } | |
177 | ||
485d0035 | 178 | void helper_macw(CPUSH4State *env, uint32_t arg0, uint32_t arg1) |
fdf9b3e8 FB |
179 | { |
180 | int64_t res; | |
181 | ||
182 | res = ((uint64_t) env->mach << 32) | env->macl; | |
6f06939b | 183 | res += (int64_t) (int16_t) arg0 *(int64_t) (int16_t) arg1; |
fdf9b3e8 FB |
184 | env->mach = (res >> 32) & 0xffffffff; |
185 | env->macl = res & 0xffffffff; | |
5ed9a259 | 186 | if (env->sr & (1u << SR_S)) { |
fdf9b3e8 FB |
187 | if (res < -0x80000000) { |
188 | env->mach = 1; | |
189 | env->macl = 0x80000000; | |
190 | } else if (res > 0x000000007fffffff) { | |
191 | env->mach = 1; | |
192 | env->macl = 0x7fffffff; | |
193 | } | |
194 | } | |
195 | } | |
196 | ||
485d0035 | 197 | void helper_ld_fpscr(CPUSH4State *env, uint32_t val) |
390af821 | 198 | { |
26ac1ea5 AJ |
199 | env->fpscr = val & FPSCR_MASK; |
200 | if ((val & FPSCR_RM_MASK) == FPSCR_RM_ZERO) { | |
390af821 | 201 | set_float_rounding_mode(float_round_to_zero, &env->fp_status); |
26ac1ea5 | 202 | } else { |
390af821 | 203 | set_float_rounding_mode(float_round_nearest_even, &env->fp_status); |
26ac1ea5 | 204 | } |
a0d4ac33 | 205 | set_flush_to_zero((val & FPSCR_DN) != 0, &env->fp_status); |
390af821 | 206 | } |
cc4ba6a9 | 207 | |
485d0035 | 208 | static void update_fpscr(CPUSH4State *env, uintptr_t retaddr) |
21829e9b AJ |
209 | { |
210 | int xcpt, cause, enable; | |
211 | ||
212 | xcpt = get_float_exception_flags(&env->fp_status); | |
213 | ||
801f4dac AJ |
214 | /* Clear the cause entries */ |
215 | env->fpscr &= ~FPSCR_CAUSE_MASK; | |
21829e9b AJ |
216 | |
217 | if (unlikely(xcpt)) { | |
218 | if (xcpt & float_flag_invalid) { | |
801f4dac | 219 | env->fpscr |= FPSCR_CAUSE_V; |
21829e9b AJ |
220 | } |
221 | if (xcpt & float_flag_divbyzero) { | |
801f4dac | 222 | env->fpscr |= FPSCR_CAUSE_Z; |
21829e9b AJ |
223 | } |
224 | if (xcpt & float_flag_overflow) { | |
801f4dac | 225 | env->fpscr |= FPSCR_CAUSE_O; |
21829e9b AJ |
226 | } |
227 | if (xcpt & float_flag_underflow) { | |
801f4dac | 228 | env->fpscr |= FPSCR_CAUSE_U; |
21829e9b AJ |
229 | } |
230 | if (xcpt & float_flag_inexact) { | |
801f4dac | 231 | env->fpscr |= FPSCR_CAUSE_I; |
21829e9b AJ |
232 | } |
233 | ||
801f4dac AJ |
234 | /* Accumulate in flag entries */ |
235 | env->fpscr |= (env->fpscr & FPSCR_CAUSE_MASK) | |
236 | >> (FPSCR_CAUSE_SHIFT - FPSCR_FLAG_SHIFT); | |
21829e9b AJ |
237 | |
238 | /* Generate an exception if enabled */ | |
239 | cause = (env->fpscr & FPSCR_CAUSE_MASK) >> FPSCR_CAUSE_SHIFT; | |
240 | enable = (env->fpscr & FPSCR_ENABLE_MASK) >> FPSCR_ENABLE_SHIFT; | |
241 | if (cause & enable) { | |
10127400 | 242 | raise_exception(env, 0x120, retaddr); |
21829e9b AJ |
243 | } |
244 | } | |
245 | } | |
246 | ||
485d0035 | 247 | float32 helper_fadd_FT(CPUSH4State *env, float32 t0, float32 t1) |
cc4ba6a9 | 248 | { |
21829e9b | 249 | set_float_exception_flags(0, &env->fp_status); |
d6c424c5 | 250 | t0 = float32_add(t0, t1, &env->fp_status); |
485d0035 | 251 | update_fpscr(env, GETPC()); |
d6c424c5 | 252 | return t0; |
cc4ba6a9 AJ |
253 | } |
254 | ||
485d0035 | 255 | float64 helper_fadd_DT(CPUSH4State *env, float64 t0, float64 t1) |
cc4ba6a9 | 256 | { |
21829e9b | 257 | set_float_exception_flags(0, &env->fp_status); |
d6c424c5 | 258 | t0 = float64_add(t0, t1, &env->fp_status); |
485d0035 | 259 | update_fpscr(env, GETPC()); |
d6c424c5 | 260 | return t0; |
cc4ba6a9 AJ |
261 | } |
262 | ||
92f1f83e | 263 | uint32_t helper_fcmp_eq_FT(CPUSH4State *env, float32 t0, float32 t1) |
cc4ba6a9 | 264 | { |
21829e9b | 265 | int relation; |
9850d1e8 | 266 | |
21829e9b | 267 | set_float_exception_flags(0, &env->fp_status); |
d6c424c5 | 268 | relation = float32_compare(t0, t1, &env->fp_status); |
fea7d77d | 269 | update_fpscr(env, GETPC()); |
92f1f83e | 270 | return relation == float_relation_equal; |
cc4ba6a9 AJ |
271 | } |
272 | ||
92f1f83e | 273 | uint32_t helper_fcmp_eq_DT(CPUSH4State *env, float64 t0, float64 t1) |
cc4ba6a9 | 274 | { |
21829e9b | 275 | int relation; |
9850d1e8 | 276 | |
21829e9b | 277 | set_float_exception_flags(0, &env->fp_status); |
d6c424c5 | 278 | relation = float64_compare(t0, t1, &env->fp_status); |
fea7d77d | 279 | update_fpscr(env, GETPC()); |
92f1f83e | 280 | return relation == float_relation_equal; |
cc4ba6a9 AJ |
281 | } |
282 | ||
92f1f83e | 283 | uint32_t helper_fcmp_gt_FT(CPUSH4State *env, float32 t0, float32 t1) |
cc4ba6a9 | 284 | { |
21829e9b | 285 | int relation; |
9850d1e8 | 286 | |
21829e9b | 287 | set_float_exception_flags(0, &env->fp_status); |
d6c424c5 | 288 | relation = float32_compare(t0, t1, &env->fp_status); |
fea7d77d | 289 | update_fpscr(env, GETPC()); |
92f1f83e | 290 | return relation == float_relation_greater; |
cc4ba6a9 AJ |
291 | } |
292 | ||
92f1f83e | 293 | uint32_t helper_fcmp_gt_DT(CPUSH4State *env, float64 t0, float64 t1) |
cc4ba6a9 | 294 | { |
21829e9b | 295 | int relation; |
9850d1e8 | 296 | |
21829e9b | 297 | set_float_exception_flags(0, &env->fp_status); |
d6c424c5 | 298 | relation = float64_compare(t0, t1, &env->fp_status); |
fea7d77d | 299 | update_fpscr(env, GETPC()); |
92f1f83e | 300 | return relation == float_relation_greater; |
cc4ba6a9 AJ |
301 | } |
302 | ||
485d0035 | 303 | float64 helper_fcnvsd_FT_DT(CPUSH4State *env, float32 t0) |
cc4ba6a9 | 304 | { |
d6c424c5 | 305 | float64 ret; |
21829e9b | 306 | set_float_exception_flags(0, &env->fp_status); |
d6c424c5 | 307 | ret = float32_to_float64(t0, &env->fp_status); |
485d0035 | 308 | update_fpscr(env, GETPC()); |
d6c424c5 | 309 | return ret; |
cc4ba6a9 AJ |
310 | } |
311 | ||
485d0035 | 312 | float32 helper_fcnvds_DT_FT(CPUSH4State *env, float64 t0) |
cc4ba6a9 | 313 | { |
d6c424c5 | 314 | float32 ret; |
21829e9b | 315 | set_float_exception_flags(0, &env->fp_status); |
d6c424c5 | 316 | ret = float64_to_float32(t0, &env->fp_status); |
485d0035 | 317 | update_fpscr(env, GETPC()); |
d6c424c5 | 318 | return ret; |
cc4ba6a9 AJ |
319 | } |
320 | ||
485d0035 | 321 | float32 helper_fdiv_FT(CPUSH4State *env, float32 t0, float32 t1) |
cc4ba6a9 | 322 | { |
21829e9b | 323 | set_float_exception_flags(0, &env->fp_status); |
d6c424c5 | 324 | t0 = float32_div(t0, t1, &env->fp_status); |
485d0035 | 325 | update_fpscr(env, GETPC()); |
d6c424c5 | 326 | return t0; |
cc4ba6a9 AJ |
327 | } |
328 | ||
485d0035 | 329 | float64 helper_fdiv_DT(CPUSH4State *env, float64 t0, float64 t1) |
cc4ba6a9 | 330 | { |
21829e9b | 331 | set_float_exception_flags(0, &env->fp_status); |
d6c424c5 | 332 | t0 = float64_div(t0, t1, &env->fp_status); |
485d0035 | 333 | update_fpscr(env, GETPC()); |
d6c424c5 | 334 | return t0; |
cc4ba6a9 AJ |
335 | } |
336 | ||
485d0035 | 337 | float32 helper_float_FT(CPUSH4State *env, uint32_t t0) |
cc4ba6a9 | 338 | { |
d6c424c5 | 339 | float32 ret; |
21829e9b | 340 | set_float_exception_flags(0, &env->fp_status); |
d6c424c5 | 341 | ret = int32_to_float32(t0, &env->fp_status); |
485d0035 | 342 | update_fpscr(env, GETPC()); |
d6c424c5 | 343 | return ret; |
cc4ba6a9 AJ |
344 | } |
345 | ||
485d0035 | 346 | float64 helper_float_DT(CPUSH4State *env, uint32_t t0) |
cc4ba6a9 | 347 | { |
d6c424c5 | 348 | float64 ret; |
21829e9b | 349 | set_float_exception_flags(0, &env->fp_status); |
d6c424c5 | 350 | ret = int32_to_float64(t0, &env->fp_status); |
485d0035 | 351 | update_fpscr(env, GETPC()); |
d6c424c5 | 352 | return ret; |
cc4ba6a9 AJ |
353 | } |
354 | ||
485d0035 | 355 | float32 helper_fmac_FT(CPUSH4State *env, float32 t0, float32 t1, float32 t2) |
5b7141a1 | 356 | { |
21829e9b | 357 | set_float_exception_flags(0, &env->fp_status); |
ff2086fe | 358 | t0 = float32_muladd(t0, t1, t2, 0, &env->fp_status); |
485d0035 | 359 | update_fpscr(env, GETPC()); |
d6c424c5 | 360 | return t0; |
5b7141a1 AJ |
361 | } |
362 | ||
485d0035 | 363 | float32 helper_fmul_FT(CPUSH4State *env, float32 t0, float32 t1) |
cc4ba6a9 | 364 | { |
21829e9b | 365 | set_float_exception_flags(0, &env->fp_status); |
d6c424c5 | 366 | t0 = float32_mul(t0, t1, &env->fp_status); |
485d0035 | 367 | update_fpscr(env, GETPC()); |
d6c424c5 | 368 | return t0; |
cc4ba6a9 AJ |
369 | } |
370 | ||
485d0035 | 371 | float64 helper_fmul_DT(CPUSH4State *env, float64 t0, float64 t1) |
cc4ba6a9 | 372 | { |
21829e9b | 373 | set_float_exception_flags(0, &env->fp_status); |
d6c424c5 | 374 | t0 = float64_mul(t0, t1, &env->fp_status); |
485d0035 | 375 | update_fpscr(env, GETPC()); |
d6c424c5 | 376 | return t0; |
cc4ba6a9 AJ |
377 | } |
378 | ||
485d0035 | 379 | float32 helper_fsqrt_FT(CPUSH4State *env, float32 t0) |
cc4ba6a9 | 380 | { |
21829e9b | 381 | set_float_exception_flags(0, &env->fp_status); |
d6c424c5 | 382 | t0 = float32_sqrt(t0, &env->fp_status); |
485d0035 | 383 | update_fpscr(env, GETPC()); |
d6c424c5 | 384 | return t0; |
cc4ba6a9 AJ |
385 | } |
386 | ||
485d0035 | 387 | float64 helper_fsqrt_DT(CPUSH4State *env, float64 t0) |
cc4ba6a9 | 388 | { |
21829e9b | 389 | set_float_exception_flags(0, &env->fp_status); |
d6c424c5 | 390 | t0 = float64_sqrt(t0, &env->fp_status); |
485d0035 | 391 | update_fpscr(env, GETPC()); |
d6c424c5 | 392 | return t0; |
cc4ba6a9 AJ |
393 | } |
394 | ||
11b7aa23 RH |
395 | float32 helper_fsrra_FT(CPUSH4State *env, float32 t0) |
396 | { | |
397 | set_float_exception_flags(0, &env->fp_status); | |
398 | /* "Approximate" 1/sqrt(x) via actual computation. */ | |
399 | t0 = float32_sqrt(t0, &env->fp_status); | |
400 | t0 = float32_div(float32_one, t0, &env->fp_status); | |
401 | /* Since this is supposed to be an approximation, an imprecision | |
402 | exception is required. One supposes this also follows the usual | |
403 | IEEE rule that other exceptions take precidence. */ | |
404 | if (get_float_exception_flags(&env->fp_status) == 0) { | |
405 | set_float_exception_flags(float_flag_inexact, &env->fp_status); | |
406 | } | |
407 | update_fpscr(env, GETPC()); | |
408 | return t0; | |
409 | } | |
410 | ||
485d0035 | 411 | float32 helper_fsub_FT(CPUSH4State *env, float32 t0, float32 t1) |
cc4ba6a9 | 412 | { |
21829e9b | 413 | set_float_exception_flags(0, &env->fp_status); |
d6c424c5 | 414 | t0 = float32_sub(t0, t1, &env->fp_status); |
485d0035 | 415 | update_fpscr(env, GETPC()); |
d6c424c5 | 416 | return t0; |
cc4ba6a9 AJ |
417 | } |
418 | ||
485d0035 | 419 | float64 helper_fsub_DT(CPUSH4State *env, float64 t0, float64 t1) |
cc4ba6a9 | 420 | { |
21829e9b | 421 | set_float_exception_flags(0, &env->fp_status); |
d6c424c5 | 422 | t0 = float64_sub(t0, t1, &env->fp_status); |
485d0035 | 423 | update_fpscr(env, GETPC()); |
d6c424c5 | 424 | return t0; |
cc4ba6a9 AJ |
425 | } |
426 | ||
485d0035 | 427 | uint32_t helper_ftrc_FT(CPUSH4State *env, float32 t0) |
cc4ba6a9 | 428 | { |
21829e9b | 429 | uint32_t ret; |
21829e9b | 430 | set_float_exception_flags(0, &env->fp_status); |
d6c424c5 | 431 | ret = float32_to_int32_round_to_zero(t0, &env->fp_status); |
485d0035 | 432 | update_fpscr(env, GETPC()); |
21829e9b | 433 | return ret; |
cc4ba6a9 AJ |
434 | } |
435 | ||
485d0035 | 436 | uint32_t helper_ftrc_DT(CPUSH4State *env, float64 t0) |
cc4ba6a9 | 437 | { |
21829e9b | 438 | uint32_t ret; |
21829e9b | 439 | set_float_exception_flags(0, &env->fp_status); |
d6c424c5 | 440 | ret = float64_to_int32_round_to_zero(t0, &env->fp_status); |
485d0035 | 441 | update_fpscr(env, GETPC()); |
21829e9b | 442 | return ret; |
cc4ba6a9 | 443 | } |
af8c2bde | 444 | |
485d0035 | 445 | void helper_fipr(CPUSH4State *env, uint32_t m, uint32_t n) |
af8c2bde AJ |
446 | { |
447 | int bank, i; | |
448 | float32 r, p; | |
449 | ||
450 | bank = (env->sr & FPSCR_FR) ? 16 : 0; | |
451 | r = float32_zero; | |
452 | set_float_exception_flags(0, &env->fp_status); | |
453 | ||
454 | for (i = 0 ; i < 4 ; i++) { | |
455 | p = float32_mul(env->fregs[bank + m + i], | |
456 | env->fregs[bank + n + i], | |
457 | &env->fp_status); | |
458 | r = float32_add(r, p, &env->fp_status); | |
459 | } | |
485d0035 | 460 | update_fpscr(env, GETPC()); |
af8c2bde AJ |
461 | |
462 | env->fregs[bank + n + 3] = r; | |
463 | } | |
17075f10 | 464 | |
485d0035 | 465 | void helper_ftrv(CPUSH4State *env, uint32_t n) |
17075f10 AJ |
466 | { |
467 | int bank_matrix, bank_vector; | |
468 | int i, j; | |
469 | float32 r[4]; | |
470 | float32 p; | |
471 | ||
472 | bank_matrix = (env->sr & FPSCR_FR) ? 0 : 16; | |
473 | bank_vector = (env->sr & FPSCR_FR) ? 16 : 0; | |
474 | set_float_exception_flags(0, &env->fp_status); | |
475 | for (i = 0 ; i < 4 ; i++) { | |
476 | r[i] = float32_zero; | |
477 | for (j = 0 ; j < 4 ; j++) { | |
478 | p = float32_mul(env->fregs[bank_matrix + 4 * j + i], | |
479 | env->fregs[bank_vector + j], | |
480 | &env->fp_status); | |
481 | r[i] = float32_add(r[i], p, &env->fp_status); | |
482 | } | |
483 | } | |
485d0035 | 484 | update_fpscr(env, GETPC()); |
17075f10 AJ |
485 | |
486 | for (i = 0 ; i < 4 ; i++) { | |
487 | env->fregs[bank_vector + i] = r[i]; | |
488 | } | |
489 | } |