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qom: Introduce CPUClass.tcg_initialize
[mirror_qemu.git] / target / sparc / translate.c
CommitLineData
7a3f1944
FB		 1/*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
3475187d 5 Copyright (C) 2003-2005 Fabrice Bellard
7a3f1944
FB		 6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
16
17 You should have received a copy of the GNU Lesser General Public
8167ee88 18 License along with this library; if not, see <http://www.gnu.org/licenses/>.
7a3f1944
FB		 19 */
20
db5ebe5f 21#include "qemu/osdep.h"
7a3f1944
FB		 22
23#include "cpu.h"
76cad711 24#include "disas/disas.h"
2ef6175a 25#include "exec/helper-proto.h"
63c91552 26#include "exec/exec-all.h"
57fec1fe 27#include "tcg-op.h"
f08b6170 28#include "exec/cpu_ldst.h"
7a3f1944 29
2ef6175a 30#include "exec/helper-gen.h"
a7812ae4 31
a7e30d84 32#include "trace-tcg.h"
508127e2 33#include "exec/log.h"
0cc1f4bf 34#include "asi.h"
a7e30d84
LV		 35
36
7a3f1944
FB		 37#define DEBUG_DISAS
38
72cbca10
FB		 39#define DYNAMIC_PC 1 /* dynamic pc value */
40#define JUMP_PC 2 /* dynamic pc value which takes only two values
41 according to jump_pc[T2] */
42
1a2fb1c0 43/* global register indexes */
1bcea73e
LV		 44static TCGv_env cpu_env;
45static TCGv_ptr cpu_regwptr;
25517f99
PB		 46static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
47static TCGv_i32 cpu_cc_op;
a7812ae4 48static TCGv_i32 cpu_psr;
d2dc4069
RH		 49static TCGv cpu_fsr, cpu_pc, cpu_npc;
50static TCGv cpu_regs[32];
255e1fcb
BS		 51static TCGv cpu_y;
52#ifndef CONFIG_USER_ONLY
53static TCGv cpu_tbr;
54#endif
5793f2a4 55static TCGv cpu_cond;
dc99a3f2 56#ifdef TARGET_SPARC64
a6d567e5 57static TCGv_i32 cpu_xcc, cpu_fprs;
a7812ae4 58static TCGv cpu_gsr;
255e1fcb 59static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr;
a7812ae4 60static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver;
255e1fcb
BS		 61#else
62static TCGv cpu_wim;
dc99a3f2 63#endif
714547bb 64/* Floating point registers */
30038fd8 65static TCGv_i64 cpu_fpr[TARGET_DPREGS];
1a2fb1c0 66
022c62cb 67#include "exec/gen-icount.h"
2e70f6ef 68
7a3f1944 69typedef struct DisasContext {
0f8a249a
BS		 70 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
71 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
72cbca10 72 target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
cf495bcf 73 int is_br;
e8af50a3 74 int mem_idx;
c9b459aa
AT		 75 bool fpu_enabled;
76 bool address_mask_32bit;
77 bool singlestep;
78#ifndef CONFIG_USER_ONLY
79 bool supervisor;
80#ifdef TARGET_SPARC64
81 bool hypervisor;
82#endif
83#endif
84
8393617c 85 uint32_t cc_op; /* current CC operation */
cf495bcf 86 struct TranslationBlock *tb;
5578ceab 87 sparc_def_t *def;
30038fd8 88 TCGv_i32 t32[3];
88023616 89 TCGv ttl[5];
30038fd8 90 int n_t32;
88023616 91 int n_ttl;
a6d567e5 92#ifdef TARGET_SPARC64
f9c816c0 93 int fprs_dirty;
a6d567e5
RH		 94 int asi;
95#endif
7a3f1944
FB		 96} DisasContext;
97
416fcaea
RH		 98typedef struct {
99 TCGCond cond;
100 bool is_bool;
101 bool g1, g2;
102 TCGv c1, c2;
103} DisasCompare;
104
3475187d 105// This function uses non-native bit order
dc1a6971
BS		 106#define GET_FIELD(X, FROM, TO) \
107 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
7a3f1944 108
3475187d 109// This function uses the order in the manuals, i.e. bit 0 is 2^0
dc1a6971 110#define GET_FIELD_SP(X, FROM, TO) \
3475187d
FB		 111 GET_FIELD(X, 31 - (TO), 31 - (FROM))
112
113#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
46d38ba8 114#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
3475187d
FB		 115
116#ifdef TARGET_SPARC64
0387d928 117#define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
1f587329 118#define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
3475187d 119#else
c185970a 120#define DFPREG(r) (r & 0x1e)
1f587329 121#define QFPREG(r) (r & 0x1c)
3475187d
FB		 122#endif
123
b158a785
BS		 124#define UA2005_HTRAP_MASK 0xff
125#define V8_TRAP_MASK 0x7f
126
3475187d
FB		 127static int sign_extend(int x, int len)
128{
129 len = 32 - len;
130 return (x << len) >> len;
131}
132
7a3f1944
FB		 133#define IS_IMM (insn & (1<<13))
134
2ae23e17
RH		 135static inline TCGv_i32 get_temp_i32(DisasContext *dc)
136{
137 TCGv_i32 t;
138 assert(dc->n_t32 < ARRAY_SIZE(dc->t32));
139 dc->t32[dc->n_t32++] = t = tcg_temp_new_i32();
140 return t;
141}
142
143static inline TCGv get_temp_tl(DisasContext *dc)
144{
145 TCGv t;
146 assert(dc->n_ttl < ARRAY_SIZE(dc->ttl));
147 dc->ttl[dc->n_ttl++] = t = tcg_temp_new();
148 return t;
149}
150
f9c816c0 151static inline void gen_update_fprs_dirty(DisasContext *dc, int rd)
141ae5c1
RH		 152{
153#if defined(TARGET_SPARC64)
f9c816c0
RH		 154 int bit = (rd < 32) ? 1 : 2;
155 /* If we know we've already set this bit within the TB,
156 we can avoid setting it again. */
157 if (!(dc->fprs_dirty & bit)) {
158 dc->fprs_dirty |= bit;
159 tcg_gen_ori_i32(cpu_fprs, cpu_fprs, bit);
160 }
141ae5c1
RH		 161#endif
162}
163
ff07ec83 164/* floating point registers moves */
208ae657
RH		 165static TCGv_i32 gen_load_fpr_F(DisasContext *dc, unsigned int src)
166{
30038fd8
RH		 167#if TCG_TARGET_REG_BITS == 32
168 if (src & 1) {
169 return TCGV_LOW(cpu_fpr[src / 2]);
170 } else {
171 return TCGV_HIGH(cpu_fpr[src / 2]);
172 }
173#else
dc41aa7d 174 TCGv_i32 ret = get_temp_i32(dc);
30038fd8 175 if (src & 1) {
dc41aa7d 176 tcg_gen_extrl_i64_i32(ret, cpu_fpr[src / 2]);
30038fd8 177 } else {
dc41aa7d 178 tcg_gen_extrh_i64_i32(ret, cpu_fpr[src / 2]);
30038fd8 179 }
dc41aa7d 180 return ret;
30038fd8 181#endif
208ae657
RH		 182}
183
184static void gen_store_fpr_F(DisasContext *dc, unsigned int dst, TCGv_i32 v)
185{
30038fd8
RH		 186#if TCG_TARGET_REG_BITS == 32
187 if (dst & 1) {
188 tcg_gen_mov_i32(TCGV_LOW(cpu_fpr[dst / 2]), v);
189 } else {
190 tcg_gen_mov_i32(TCGV_HIGH(cpu_fpr[dst / 2]), v);
191 }
192#else
dc41aa7d 193 TCGv_i64 t = (TCGv_i64)v;
30038fd8
RH		 194 tcg_gen_deposit_i64(cpu_fpr[dst / 2], cpu_fpr[dst / 2], t,
195 (dst & 1 ? 0 : 32), 32);
196#endif
f9c816c0 197 gen_update_fprs_dirty(dc, dst);
208ae657
RH		 198}
199
ba5f5179 200static TCGv_i32 gen_dest_fpr_F(DisasContext *dc)
208ae657 201{
ba5f5179 202 return get_temp_i32(dc);
208ae657
RH		 203}
204
96eda024
RH		 205static TCGv_i64 gen_load_fpr_D(DisasContext *dc, unsigned int src)
206{
96eda024 207 src = DFPREG(src);
30038fd8 208 return cpu_fpr[src / 2];
96eda024
RH		 209}
210
211static void gen_store_fpr_D(DisasContext *dc, unsigned int dst, TCGv_i64 v)
212{
213 dst = DFPREG(dst);
30038fd8 214 tcg_gen_mov_i64(cpu_fpr[dst / 2], v);
f9c816c0 215 gen_update_fprs_dirty(dc, dst);
96eda024
RH		 216}
217
3886b8a3 218static TCGv_i64 gen_dest_fpr_D(DisasContext *dc, unsigned int dst)
96eda024 219{
3886b8a3 220 return cpu_fpr[DFPREG(dst) / 2];
96eda024
RH		 221}
222
ff07ec83
BS		 223static void gen_op_load_fpr_QT0(unsigned int src)
224{
30038fd8
RH		 225 tcg_gen_st_i64(cpu_fpr[src / 2], cpu_env, offsetof(CPUSPARCState, qt0) +
226 offsetof(CPU_QuadU, ll.upper));
227 tcg_gen_st_i64(cpu_fpr[src/2 + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
228 offsetof(CPU_QuadU, ll.lower));
ff07ec83
BS		 229}
230
231static void gen_op_load_fpr_QT1(unsigned int src)
232{
30038fd8
RH		 233 tcg_gen_st_i64(cpu_fpr[src / 2], cpu_env, offsetof(CPUSPARCState, qt1) +
234 offsetof(CPU_QuadU, ll.upper));
235 tcg_gen_st_i64(cpu_fpr[src/2 + 1], cpu_env, offsetof(CPUSPARCState, qt1) +
236 offsetof(CPU_QuadU, ll.lower));
ff07ec83
BS		 237}
238
239static void gen_op_store_QT0_fpr(unsigned int dst)
240{
30038fd8
RH		 241 tcg_gen_ld_i64(cpu_fpr[dst / 2], cpu_env, offsetof(CPUSPARCState, qt0) +
242 offsetof(CPU_QuadU, ll.upper));
243 tcg_gen_ld_i64(cpu_fpr[dst/2 + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
244 offsetof(CPU_QuadU, ll.lower));
ff07ec83 245}
1f587329 246
f939ffe5
RH		 247static void gen_store_fpr_Q(DisasContext *dc, unsigned int dst,
248 TCGv_i64 v1, TCGv_i64 v2)
249{
250 dst = QFPREG(dst);
251
252 tcg_gen_mov_i64(cpu_fpr[dst / 2], v1);
253 tcg_gen_mov_i64(cpu_fpr[dst / 2 + 1], v2);
254 gen_update_fprs_dirty(dc, dst);
255}
256
ac11f776 257#ifdef TARGET_SPARC64
f939ffe5
RH		 258static TCGv_i64 gen_load_fpr_Q0(DisasContext *dc, unsigned int src)
259{
260 src = QFPREG(src);
261 return cpu_fpr[src / 2];
262}
263
264static TCGv_i64 gen_load_fpr_Q1(DisasContext *dc, unsigned int src)
265{
266 src = QFPREG(src);
267 return cpu_fpr[src / 2 + 1];
268}
269
f9c816c0 270static void gen_move_Q(DisasContext *dc, unsigned int rd, unsigned int rs)
ac11f776
RH		 271{
272 rd = QFPREG(rd);
273 rs = QFPREG(rs);
274
30038fd8
RH		 275 tcg_gen_mov_i64(cpu_fpr[rd / 2], cpu_fpr[rs / 2]);
276 tcg_gen_mov_i64(cpu_fpr[rd / 2 + 1], cpu_fpr[rs / 2 + 1]);
f9c816c0 277 gen_update_fprs_dirty(dc, rd);
ac11f776
RH		 278}
279#endif
280
81ad8ba2
BS		 281/* moves */
282#ifdef CONFIG_USER_ONLY
3475187d 283#define supervisor(dc) 0
81ad8ba2 284#ifdef TARGET_SPARC64
e9ebed4d 285#define hypervisor(dc) 0
81ad8ba2 286#endif
3475187d 287#else
81ad8ba2 288#ifdef TARGET_SPARC64
c9b459aa
AT		 289#define hypervisor(dc) (dc->hypervisor)
290#define supervisor(dc) (dc->supervisor | dc->hypervisor)
6f27aba6 291#else
c9b459aa 292#define supervisor(dc) (dc->supervisor)
3475187d 293#endif
81ad8ba2
BS		 294#endif
295
2cade6a3
BS		 296#ifdef TARGET_SPARC64
297#ifndef TARGET_ABI32
298#define AM_CHECK(dc) ((dc)->address_mask_32bit)
1a2fb1c0 299#else
2cade6a3
BS		 300#define AM_CHECK(dc) (1)
301#endif
1a2fb1c0 302#endif
3391c818 303
2cade6a3
BS		 304static inline void gen_address_mask(DisasContext *dc, TCGv addr)
305{
306#ifdef TARGET_SPARC64
307 if (AM_CHECK(dc))
308 tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
309#endif
310}
311
88023616
RH		 312static inline TCGv gen_load_gpr(DisasContext *dc, int reg)
313{
d2dc4069
RH		 314 if (reg > 0) {
315 assert(reg < 32);
316 return cpu_regs[reg];
317 } else {
88023616 318 TCGv t = get_temp_tl(dc);
d2dc4069 319 tcg_gen_movi_tl(t, 0);
88023616 320 return t;
88023616
RH		 321 }
322}
323
324static inline void gen_store_gpr(DisasContext *dc, int reg, TCGv v)
325{
326 if (reg > 0) {
d2dc4069
RH		 327 assert(reg < 32);
328 tcg_gen_mov_tl(cpu_regs[reg], v);
88023616
RH		 329 }
330}
331
332static inline TCGv gen_dest_gpr(DisasContext *dc, int reg)
333{
d2dc4069
RH		 334 if (reg > 0) {
335 assert(reg < 32);
336 return cpu_regs[reg];
88023616 337 } else {
d2dc4069 338 return get_temp_tl(dc);
88023616
RH		 339 }
340}
341
90aa39a1
SF		 342static inline bool use_goto_tb(DisasContext *s, target_ulong pc,
343 target_ulong npc)
344{
345 if (unlikely(s->singlestep)) {
346 return false;
347 }
348
349#ifndef CONFIG_USER_ONLY
350 return (pc & TARGET_PAGE_MASK) == (s->tb->pc & TARGET_PAGE_MASK) &&
351 (npc & TARGET_PAGE_MASK) == (s->tb->pc & TARGET_PAGE_MASK);
352#else
353 return true;
354#endif
355}
356
5fafdf24 357static inline void gen_goto_tb(DisasContext *s, int tb_num,
6e256c93
FB		 358 target_ulong pc, target_ulong npc)
359{
90aa39a1 360 if (use_goto_tb(s, pc, npc)) {
6e256c93 361 /* jump to same page: we can use a direct jump */
57fec1fe 362 tcg_gen_goto_tb(tb_num);
2f5680ee
BS		 363 tcg_gen_movi_tl(cpu_pc, pc);
364 tcg_gen_movi_tl(cpu_npc, npc);
90aa39a1 365 tcg_gen_exit_tb((uintptr_t)s->tb + tb_num);
6e256c93
FB		 366 } else {
367 /* jump to another page: currently not optimized */
2f5680ee
BS		 368 tcg_gen_movi_tl(cpu_pc, pc);
369 tcg_gen_movi_tl(cpu_npc, npc);
57fec1fe 370 tcg_gen_exit_tb(0);
6e256c93
FB		 371 }
372}
373
19f329ad 374// XXX suboptimal
a7812ae4 375static inline void gen_mov_reg_N(TCGv reg, TCGv_i32 src)
19f329ad 376{
8911f501 377 tcg_gen_extu_i32_tl(reg, src);
0b1183e3 378 tcg_gen_extract_tl(reg, reg, PSR_NEG_SHIFT, 1);
19f329ad
BS		 379}
380
a7812ae4 381static inline void gen_mov_reg_Z(TCGv reg, TCGv_i32 src)
19f329ad 382{
8911f501 383 tcg_gen_extu_i32_tl(reg, src);
0b1183e3 384 tcg_gen_extract_tl(reg, reg, PSR_ZERO_SHIFT, 1);
19f329ad
BS		 385}
386
a7812ae4 387static inline void gen_mov_reg_V(TCGv reg, TCGv_i32 src)
19f329ad 388{
8911f501 389 tcg_gen_extu_i32_tl(reg, src);
0b1183e3 390 tcg_gen_extract_tl(reg, reg, PSR_OVF_SHIFT, 1);
19f329ad
BS		 391}
392
a7812ae4 393static inline void gen_mov_reg_C(TCGv reg, TCGv_i32 src)
19f329ad 394{
8911f501 395 tcg_gen_extu_i32_tl(reg, src);
0b1183e3 396 tcg_gen_extract_tl(reg, reg, PSR_CARRY_SHIFT, 1);
19f329ad
BS		 397}
398
4af984a7 399static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 400{
4af984a7 401 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 402 tcg_gen_mov_tl(cpu_cc_src2, src2);
5c6a0628 403 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
bdf9f35d 404 tcg_gen_mov_tl(dst, cpu_cc_dst);
41d72852
BS		 405}
406
70c48285 407static TCGv_i32 gen_add32_carry32(void)
dc99a3f2 408{
70c48285
RH		 409 TCGv_i32 carry_32, cc_src1_32, cc_src2_32;
410
411 /* Carry is computed from a previous add: (dst < src) */
412#if TARGET_LONG_BITS == 64
413 cc_src1_32 = tcg_temp_new_i32();
414 cc_src2_32 = tcg_temp_new_i32();
ecc7b3aa
RH		 415 tcg_gen_extrl_i64_i32(cc_src1_32, cpu_cc_dst);
416 tcg_gen_extrl_i64_i32(cc_src2_32, cpu_cc_src);
70c48285
RH		 417#else
418 cc_src1_32 = cpu_cc_dst;
419 cc_src2_32 = cpu_cc_src;
420#endif
421
422 carry_32 = tcg_temp_new_i32();
423 tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32);
424
425#if TARGET_LONG_BITS == 64
426 tcg_temp_free_i32(cc_src1_32);
427 tcg_temp_free_i32(cc_src2_32);
428#endif
429
430 return carry_32;
41d72852
BS		 431}
432
70c48285 433static TCGv_i32 gen_sub32_carry32(void)
41d72852 434{
70c48285
RH		 435 TCGv_i32 carry_32, cc_src1_32, cc_src2_32;
436
437 /* Carry is computed from a previous borrow: (src1 < src2) */
438#if TARGET_LONG_BITS == 64
439 cc_src1_32 = tcg_temp_new_i32();
440 cc_src2_32 = tcg_temp_new_i32();
ecc7b3aa
RH		 441 tcg_gen_extrl_i64_i32(cc_src1_32, cpu_cc_src);
442 tcg_gen_extrl_i64_i32(cc_src2_32, cpu_cc_src2);
70c48285
RH		 443#else
444 cc_src1_32 = cpu_cc_src;
445 cc_src2_32 = cpu_cc_src2;
446#endif
447
448 carry_32 = tcg_temp_new_i32();
449 tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32);
450
451#if TARGET_LONG_BITS == 64
452 tcg_temp_free_i32(cc_src1_32);
453 tcg_temp_free_i32(cc_src2_32);
454#endif
455
456 return carry_32;
457}
458
459static void gen_op_addx_int(DisasContext *dc, TCGv dst, TCGv src1,
460 TCGv src2, int update_cc)
461{
462 TCGv_i32 carry_32;
463 TCGv carry;
464
465 switch (dc->cc_op) {
466 case CC_OP_DIV:
467 case CC_OP_LOGIC:
468 /* Carry is known to be zero. Fall back to plain ADD. */
469 if (update_cc) {
470 gen_op_add_cc(dst, src1, src2);
471 } else {
472 tcg_gen_add_tl(dst, src1, src2);
473 }
474 return;
475
476 case CC_OP_ADD:
477 case CC_OP_TADD:
478 case CC_OP_TADDTV:
15fe216f
RH		 479 if (TARGET_LONG_BITS == 32) {
480 /* We can re-use the host's hardware carry generation by using
481 an ADD2 opcode. We discard the low part of the output.
482 Ideally we'd combine this operation with the add that
483 generated the carry in the first place. */
484 carry = tcg_temp_new();
485 tcg_gen_add2_tl(carry, dst, cpu_cc_src, src1, cpu_cc_src2, src2);
486 tcg_temp_free(carry);
70c48285
RH		 487 goto add_done;
488 }
70c48285
RH		 489 carry_32 = gen_add32_carry32();
490 break;
491
492 case CC_OP_SUB:
493 case CC_OP_TSUB:
494 case CC_OP_TSUBTV:
495 carry_32 = gen_sub32_carry32();
496 break;
497
498 default:
499 /* We need external help to produce the carry. */
500 carry_32 = tcg_temp_new_i32();
2ffd9176 501 gen_helper_compute_C_icc(carry_32, cpu_env);
70c48285
RH		 502 break;
503 }
504
505#if TARGET_LONG_BITS == 64
506 carry = tcg_temp_new();
507 tcg_gen_extu_i32_i64(carry, carry_32);
508#else
509 carry = carry_32;
510#endif
511
512 tcg_gen_add_tl(dst, src1, src2);
513 tcg_gen_add_tl(dst, dst, carry);
514
515 tcg_temp_free_i32(carry_32);
516#if TARGET_LONG_BITS == 64
517 tcg_temp_free(carry);
518#endif
519
70c48285 520 add_done:
70c48285
RH		 521 if (update_cc) {
522 tcg_gen_mov_tl(cpu_cc_src, src1);
523 tcg_gen_mov_tl(cpu_cc_src2, src2);
524 tcg_gen_mov_tl(cpu_cc_dst, dst);
525 tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADDX);
526 dc->cc_op = CC_OP_ADDX;
527 }
dc99a3f2
BS		 528}
529
41d72852 530static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 531{
4af984a7 532 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 533 tcg_gen_mov_tl(cpu_cc_src2, src2);
41d72852 534 tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
d4b0d468 535 tcg_gen_mov_tl(dst, cpu_cc_dst);
41d72852
BS		 536}
537
70c48285
RH		 538static void gen_op_subx_int(DisasContext *dc, TCGv dst, TCGv src1,
539 TCGv src2, int update_cc)
41d72852 540{
70c48285
RH		 541 TCGv_i32 carry_32;
542 TCGv carry;
41d72852 543
70c48285
RH		 544 switch (dc->cc_op) {
545 case CC_OP_DIV:
546 case CC_OP_LOGIC:
547 /* Carry is known to be zero. Fall back to plain SUB. */
548 if (update_cc) {
549 gen_op_sub_cc(dst, src1, src2);
550 } else {
551 tcg_gen_sub_tl(dst, src1, src2);
552 }
553 return;
554
555 case CC_OP_ADD:
556 case CC_OP_TADD:
557 case CC_OP_TADDTV:
558 carry_32 = gen_add32_carry32();
559 break;
560
561 case CC_OP_SUB:
562 case CC_OP_TSUB:
563 case CC_OP_TSUBTV:
15fe216f
RH		 564 if (TARGET_LONG_BITS == 32) {
565 /* We can re-use the host's hardware carry generation by using
566 a SUB2 opcode. We discard the low part of the output.
567 Ideally we'd combine this operation with the add that
568 generated the carry in the first place. */
569 carry = tcg_temp_new();
570 tcg_gen_sub2_tl(carry, dst, cpu_cc_src, src1, cpu_cc_src2, src2);
571 tcg_temp_free(carry);
70c48285
RH		 572 goto sub_done;
573 }
70c48285
RH		 574 carry_32 = gen_sub32_carry32();
575 break;
576
577 default:
578 /* We need external help to produce the carry. */
579 carry_32 = tcg_temp_new_i32();
2ffd9176 580 gen_helper_compute_C_icc(carry_32, cpu_env);
70c48285
RH		 581 break;
582 }
583
584#if TARGET_LONG_BITS == 64
585 carry = tcg_temp_new();
586 tcg_gen_extu_i32_i64(carry, carry_32);
587#else
588 carry = carry_32;
589#endif
590
591 tcg_gen_sub_tl(dst, src1, src2);
592 tcg_gen_sub_tl(dst, dst, carry);
593
594 tcg_temp_free_i32(carry_32);
595#if TARGET_LONG_BITS == 64
596 tcg_temp_free(carry);
597#endif
598
70c48285 599 sub_done:
70c48285
RH		 600 if (update_cc) {
601 tcg_gen_mov_tl(cpu_cc_src, src1);
602 tcg_gen_mov_tl(cpu_cc_src2, src2);
603 tcg_gen_mov_tl(cpu_cc_dst, dst);
604 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUBX);
605 dc->cc_op = CC_OP_SUBX;
606 }
dc99a3f2
BS		 607}
608
4af984a7 609static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
d9bdab86 610{
de9e9d9f 611 TCGv r_temp, zero, t0;
d9bdab86 612
a7812ae4 613 r_temp = tcg_temp_new();
de9e9d9f 614 t0 = tcg_temp_new();
d9bdab86
BS		 615
616 /* old op:
617 if (!(env->y & 1))
618 T1 = 0;
619 */
6cb675b0 620 zero = tcg_const_tl(0);
72ccba79 621 tcg_gen_andi_tl(cpu_cc_src, src1, 0xffffffff);
255e1fcb 622 tcg_gen_andi_tl(r_temp, cpu_y, 0x1);
72ccba79 623 tcg_gen_andi_tl(cpu_cc_src2, src2, 0xffffffff);
6cb675b0
RH		 624 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_cc_src2, r_temp, zero,
625 zero, cpu_cc_src2);
626 tcg_temp_free(zero);
d9bdab86
BS		 627
628 // b2 = T0 & 1;
629 // env->y = (b2 << 31) | (env->y >> 1);
0b1183e3 630 tcg_gen_extract_tl(t0, cpu_y, 1, 31);
08d64e0d 631 tcg_gen_deposit_tl(cpu_y, t0, cpu_cc_src, 31, 1);
d9bdab86
BS		 632
633 // b1 = N ^ V;
de9e9d9f 634 gen_mov_reg_N(t0, cpu_psr);
d9bdab86 635 gen_mov_reg_V(r_temp, cpu_psr);
de9e9d9f 636 tcg_gen_xor_tl(t0, t0, r_temp);
2ea815ca 637 tcg_temp_free(r_temp);
d9bdab86
BS		 638
639 // T0 = (b1 << 31) | (T0 >> 1);
640 // src1 = T0;
de9e9d9f 641 tcg_gen_shli_tl(t0, t0, 31);
6f551262 642 tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
de9e9d9f
RH		 643 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
644 tcg_temp_free(t0);
d9bdab86 645
5c6a0628 646 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
d9bdab86 647
5c6a0628 648 tcg_gen_mov_tl(dst, cpu_cc_dst);
d9bdab86
BS		 649}
650
fb170183 651static inline void gen_op_multiply(TCGv dst, TCGv src1, TCGv src2, int sign_ext)
8879d139 652{
528692a8 653#if TARGET_LONG_BITS == 32
fb170183 654 if (sign_ext) {
528692a8 655 tcg_gen_muls2_tl(dst, cpu_y, src1, src2);
fb170183 656 } else {
528692a8 657 tcg_gen_mulu2_tl(dst, cpu_y, src1, src2);
fb170183 658 }
528692a8
RH		 659#else
660 TCGv t0 = tcg_temp_new_i64();
661 TCGv t1 = tcg_temp_new_i64();
fb170183 662
528692a8
RH		 663 if (sign_ext) {
664 tcg_gen_ext32s_i64(t0, src1);
665 tcg_gen_ext32s_i64(t1, src2);
666 } else {
667 tcg_gen_ext32u_i64(t0, src1);
668 tcg_gen_ext32u_i64(t1, src2);
669 }
fb170183 670
528692a8
RH		 671 tcg_gen_mul_i64(dst, t0, t1);
672 tcg_temp_free(t0);
673 tcg_temp_free(t1);
fb170183 674
528692a8
RH		 675 tcg_gen_shri_i64(cpu_y, dst, 32);
676#endif
8879d139
BS		 677}
678
fb170183 679static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
8879d139 680{
fb170183
IK		 681 /* zero-extend truncated operands before multiplication */
682 gen_op_multiply(dst, src1, src2, 0);
683}
8879d139 684
fb170183
IK		 685static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
686{
687 /* sign-extend truncated operands before multiplication */
688 gen_op_multiply(dst, src1, src2, 1);
8879d139
BS		 689}
690
19f329ad
BS		 691// 1
692static inline void gen_op_eval_ba(TCGv dst)
693{
694 tcg_gen_movi_tl(dst, 1);
695}
696
697// Z
a7812ae4 698static inline void gen_op_eval_be(TCGv dst, TCGv_i32 src)
19f329ad
BS		 699{
700 gen_mov_reg_Z(dst, src);
701}
702
703// Z | (N ^ V)
a7812ae4 704static inline void gen_op_eval_ble(TCGv dst, TCGv_i32 src)
19f329ad 705{
de9e9d9f
RH		 706 TCGv t0 = tcg_temp_new();
707 gen_mov_reg_N(t0, src);
19f329ad 708 gen_mov_reg_V(dst, src);
de9e9d9f
RH		 709 tcg_gen_xor_tl(dst, dst, t0);
710 gen_mov_reg_Z(t0, src);
711 tcg_gen_or_tl(dst, dst, t0);
712 tcg_temp_free(t0);
19f329ad
BS		 713}
714
715// N ^ V
a7812ae4 716static inline void gen_op_eval_bl(TCGv dst, TCGv_i32 src)
19f329ad 717{
de9e9d9f
RH		 718 TCGv t0 = tcg_temp_new();
719 gen_mov_reg_V(t0, src);
19f329ad 720 gen_mov_reg_N(dst, src);
de9e9d9f
RH		 721 tcg_gen_xor_tl(dst, dst, t0);
722 tcg_temp_free(t0);
19f329ad
BS		 723}
724
725// C | Z
a7812ae4 726static inline void gen_op_eval_bleu(TCGv dst, TCGv_i32 src)
19f329ad 727{
de9e9d9f
RH		 728 TCGv t0 = tcg_temp_new();
729 gen_mov_reg_Z(t0, src);
19f329ad 730 gen_mov_reg_C(dst, src);
de9e9d9f
RH		 731 tcg_gen_or_tl(dst, dst, t0);
732 tcg_temp_free(t0);
19f329ad
BS		 733}
734
735// C
a7812ae4 736static inline void gen_op_eval_bcs(TCGv dst, TCGv_i32 src)
19f329ad
BS		 737{
738 gen_mov_reg_C(dst, src);
739}
740
741// V
a7812ae4 742static inline void gen_op_eval_bvs(TCGv dst, TCGv_i32 src)
19f329ad
BS		 743{
744 gen_mov_reg_V(dst, src);
745}
746
747// 0
748static inline void gen_op_eval_bn(TCGv dst)
749{
750 tcg_gen_movi_tl(dst, 0);
751}
752
753// N
a7812ae4 754static inline void gen_op_eval_bneg(TCGv dst, TCGv_i32 src)
19f329ad
BS		 755{
756 gen_mov_reg_N(dst, src);
757}
758
759// !Z
a7812ae4 760static inline void gen_op_eval_bne(TCGv dst, TCGv_i32 src)
19f329ad
BS		 761{
762 gen_mov_reg_Z(dst, src);
763 tcg_gen_xori_tl(dst, dst, 0x1);
764}
765
766// !(Z | (N ^ V))
a7812ae4 767static inline void gen_op_eval_bg(TCGv dst, TCGv_i32 src)
19f329ad 768{
de9e9d9f 769 gen_op_eval_ble(dst, src);
19f329ad
BS		 770 tcg_gen_xori_tl(dst, dst, 0x1);
771}
772
773// !(N ^ V)
a7812ae4 774static inline void gen_op_eval_bge(TCGv dst, TCGv_i32 src)
19f329ad 775{
de9e9d9f 776 gen_op_eval_bl(dst, src);
19f329ad
BS		 777 tcg_gen_xori_tl(dst, dst, 0x1);
778}
779
780// !(C | Z)
a7812ae4 781static inline void gen_op_eval_bgu(TCGv dst, TCGv_i32 src)
19f329ad 782{
de9e9d9f 783 gen_op_eval_bleu(dst, src);
19f329ad
BS		 784 tcg_gen_xori_tl(dst, dst, 0x1);
785}
786
787// !C
a7812ae4 788static inline void gen_op_eval_bcc(TCGv dst, TCGv_i32 src)
19f329ad
BS		 789{
790 gen_mov_reg_C(dst, src);
791 tcg_gen_xori_tl(dst, dst, 0x1);
792}
793
794// !N
a7812ae4 795static inline void gen_op_eval_bpos(TCGv dst, TCGv_i32 src)
19f329ad
BS		 796{
797 gen_mov_reg_N(dst, src);
798 tcg_gen_xori_tl(dst, dst, 0x1);
799}
800
801// !V
a7812ae4 802static inline void gen_op_eval_bvc(TCGv dst, TCGv_i32 src)
19f329ad
BS		 803{
804 gen_mov_reg_V(dst, src);
805 tcg_gen_xori_tl(dst, dst, 0x1);
806}
807
808/*
809 FPSR bit field FCC1 | FCC0:
810 0 =
811 1 <
812 2 >
813 3 unordered
814*/
815static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
816 unsigned int fcc_offset)
817{
ba6a9d8c 818 tcg_gen_shri_tl(reg, src, FSR_FCC0_SHIFT + fcc_offset);
19f329ad
BS		 819 tcg_gen_andi_tl(reg, reg, 0x1);
820}
821
822static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
823 unsigned int fcc_offset)
824{
ba6a9d8c 825 tcg_gen_shri_tl(reg, src, FSR_FCC1_SHIFT + fcc_offset);
19f329ad
BS		 826 tcg_gen_andi_tl(reg, reg, 0x1);
827}
828
829// !0: FCC0 | FCC1
830static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
831 unsigned int fcc_offset)
832{
de9e9d9f 833 TCGv t0 = tcg_temp_new();
19f329ad 834 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 835 gen_mov_reg_FCC1(t0, src, fcc_offset);
836 tcg_gen_or_tl(dst, dst, t0);
837 tcg_temp_free(t0);
19f329ad
BS		 838}
839
840// 1 or 2: FCC0 ^ FCC1
841static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
842 unsigned int fcc_offset)
843{
de9e9d9f 844 TCGv t0 = tcg_temp_new();
19f329ad 845 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 846 gen_mov_reg_FCC1(t0, src, fcc_offset);
847 tcg_gen_xor_tl(dst, dst, t0);
848 tcg_temp_free(t0);
19f329ad
BS		 849}
850
851// 1 or 3: FCC0
852static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
853 unsigned int fcc_offset)
854{
855 gen_mov_reg_FCC0(dst, src, fcc_offset);
856}
857
858// 1: FCC0 & !FCC1
859static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
860 unsigned int fcc_offset)
861{
de9e9d9f 862 TCGv t0 = tcg_temp_new();
19f329ad 863 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 864 gen_mov_reg_FCC1(t0, src, fcc_offset);
865 tcg_gen_andc_tl(dst, dst, t0);
866 tcg_temp_free(t0);
19f329ad
BS		 867}
868
869// 2 or 3: FCC1
870static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
871 unsigned int fcc_offset)
872{
873 gen_mov_reg_FCC1(dst, src, fcc_offset);
874}
875
876// 2: !FCC0 & FCC1
877static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
878 unsigned int fcc_offset)
879{
de9e9d9f 880 TCGv t0 = tcg_temp_new();
19f329ad 881 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 882 gen_mov_reg_FCC1(t0, src, fcc_offset);
883 tcg_gen_andc_tl(dst, t0, dst);
884 tcg_temp_free(t0);
19f329ad
BS		 885}
886
887// 3: FCC0 & FCC1
888static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
889 unsigned int fcc_offset)
890{
de9e9d9f 891 TCGv t0 = tcg_temp_new();
19f329ad 892 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 893 gen_mov_reg_FCC1(t0, src, fcc_offset);
894 tcg_gen_and_tl(dst, dst, t0);
895 tcg_temp_free(t0);
19f329ad
BS		 896}
897
898// 0: !(FCC0 | FCC1)
899static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
900 unsigned int fcc_offset)
901{
de9e9d9f 902 TCGv t0 = tcg_temp_new();
19f329ad 903 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 904 gen_mov_reg_FCC1(t0, src, fcc_offset);
905 tcg_gen_or_tl(dst, dst, t0);
19f329ad 906 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 907 tcg_temp_free(t0);
19f329ad
BS		 908}
909
910// 0 or 3: !(FCC0 ^ FCC1)
911static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
912 unsigned int fcc_offset)
913{
de9e9d9f 914 TCGv t0 = tcg_temp_new();
19f329ad 915 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 916 gen_mov_reg_FCC1(t0, src, fcc_offset);
917 tcg_gen_xor_tl(dst, dst, t0);
19f329ad 918 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 919 tcg_temp_free(t0);
19f329ad
BS		 920}
921
922// 0 or 2: !FCC0
923static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
924 unsigned int fcc_offset)
925{
926 gen_mov_reg_FCC0(dst, src, fcc_offset);
927 tcg_gen_xori_tl(dst, dst, 0x1);
928}
929
930// !1: !(FCC0 & !FCC1)
931static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
932 unsigned int fcc_offset)
933{
de9e9d9f 934 TCGv t0 = tcg_temp_new();
19f329ad 935 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 936 gen_mov_reg_FCC1(t0, src, fcc_offset);
937 tcg_gen_andc_tl(dst, dst, t0);
19f329ad 938 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 939 tcg_temp_free(t0);
19f329ad
BS		 940}
941
942// 0 or 1: !FCC1
943static inline void gen_op_eval_fble(TCGv dst, TCGv src,
944 unsigned int fcc_offset)
945{
946 gen_mov_reg_FCC1(dst, src, fcc_offset);
947 tcg_gen_xori_tl(dst, dst, 0x1);
948}
949
950// !2: !(!FCC0 & FCC1)
951static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
952 unsigned int fcc_offset)
953{
de9e9d9f 954 TCGv t0 = tcg_temp_new();
19f329ad 955 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 956 gen_mov_reg_FCC1(t0, src, fcc_offset);
957 tcg_gen_andc_tl(dst, t0, dst);
19f329ad 958 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 959 tcg_temp_free(t0);
19f329ad
BS		 960}
961
962// !3: !(FCC0 & FCC1)
963static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
964 unsigned int fcc_offset)
965{
de9e9d9f 966 TCGv t0 = tcg_temp_new();
19f329ad 967 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 968 gen_mov_reg_FCC1(t0, src, fcc_offset);
969 tcg_gen_and_tl(dst, dst, t0);
19f329ad 970 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 971 tcg_temp_free(t0);
19f329ad
BS		 972}
973
46525e1f 974static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
19f329ad 975 target_ulong pc2, TCGv r_cond)
83469015 976{
42a268c2 977 TCGLabel *l1 = gen_new_label();
83469015 978
cb63669a 979 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
83469015 980
6e256c93 981 gen_goto_tb(dc, 0, pc1, pc1 + 4);
83469015
FB		 982
983 gen_set_label(l1);
6e256c93 984 gen_goto_tb(dc, 1, pc2, pc2 + 4);
83469015
FB		 985}
986
bfa31b76 987static void gen_branch_a(DisasContext *dc, target_ulong pc1)
83469015 988{
42a268c2 989 TCGLabel *l1 = gen_new_label();
bfa31b76 990 target_ulong npc = dc->npc;
83469015 991
bfa31b76 992 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cond, 0, l1);
83469015 993
bfa31b76 994 gen_goto_tb(dc, 0, npc, pc1);
83469015
FB		 995
996 gen_set_label(l1);
bfa31b76
RH		 997 gen_goto_tb(dc, 1, npc + 4, npc + 8);
998
999 dc->is_br = 1;
83469015
FB		 1000}
1001
2bf2e019
RH		 1002static void gen_branch_n(DisasContext *dc, target_ulong pc1)
1003{
1004 target_ulong npc = dc->npc;
1005
1006 if (likely(npc != DYNAMIC_PC)) {
1007 dc->pc = npc;
1008 dc->jump_pc[0] = pc1;
1009 dc->jump_pc[1] = npc + 4;
1010 dc->npc = JUMP_PC;
1011 } else {
1012 TCGv t, z;
1013
1014 tcg_gen_mov_tl(cpu_pc, cpu_npc);
1015
1016 tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
1017 t = tcg_const_tl(pc1);
1018 z = tcg_const_tl(0);
1019 tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, cpu_cond, z, t, cpu_npc);
1020 tcg_temp_free(t);
1021 tcg_temp_free(z);
1022
1023 dc->pc = DYNAMIC_PC;
1024 }
1025}
1026
2e655fe7 1027static inline void gen_generic_branch(DisasContext *dc)
83469015 1028{
61316742
RH		 1029 TCGv npc0 = tcg_const_tl(dc->jump_pc[0]);
1030 TCGv npc1 = tcg_const_tl(dc->jump_pc[1]);
1031 TCGv zero = tcg_const_tl(0);
19f329ad 1032
61316742 1033 tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, cpu_cond, zero, npc0, npc1);
83469015 1034
61316742
RH		 1035 tcg_temp_free(npc0);
1036 tcg_temp_free(npc1);
1037 tcg_temp_free(zero);
83469015
FB		 1038}
1039
4af984a7
BS		 1040/* call this function before using the condition register as it may
1041 have been set for a jump */
dee8913c 1042static inline void flush_cond(DisasContext *dc)
83469015
FB		 1043{
1044 if (dc->npc == JUMP_PC) {
2e655fe7 1045 gen_generic_branch(dc);
83469015
FB		 1046 dc->npc = DYNAMIC_PC;
1047 }
1048}
1049
934da7ee 1050static inline void save_npc(DisasContext *dc)
72cbca10
FB		 1051{
1052 if (dc->npc == JUMP_PC) {
2e655fe7 1053 gen_generic_branch(dc);
72cbca10
FB		 1054 dc->npc = DYNAMIC_PC;
1055 } else if (dc->npc != DYNAMIC_PC) {
2f5680ee 1056 tcg_gen_movi_tl(cpu_npc, dc->npc);
72cbca10
FB		 1057 }
1058}
1059
20132b96 1060static inline void update_psr(DisasContext *dc)
72cbca10 1061{
cfa90513
BS		 1062 if (dc->cc_op != CC_OP_FLAGS) {
1063 dc->cc_op = CC_OP_FLAGS;
2ffd9176 1064 gen_helper_compute_psr(cpu_env);
cfa90513 1065 }
20132b96
RH		 1066}
1067
1068static inline void save_state(DisasContext *dc)
1069{
1070 tcg_gen_movi_tl(cpu_pc, dc->pc);
934da7ee 1071 save_npc(dc);
72cbca10
FB		 1072}
1073
4fbe0067
RH		 1074static void gen_exception(DisasContext *dc, int which)
1075{
1076 TCGv_i32 t;
1077
1078 save_state(dc);
1079 t = tcg_const_i32(which);
1080 gen_helper_raise_exception(cpu_env, t);
1081 tcg_temp_free_i32(t);
1082 dc->is_br = 1;
1083}
1084
35e94905
RH		 1085static void gen_check_align(TCGv addr, int mask)
1086{
1087 TCGv_i32 r_mask = tcg_const_i32(mask);
1088 gen_helper_check_align(cpu_env, addr, r_mask);
1089 tcg_temp_free_i32(r_mask);
1090}
1091
13a6dd00 1092static inline void gen_mov_pc_npc(DisasContext *dc)
0bee699e
FB		 1093{
1094 if (dc->npc == JUMP_PC) {
2e655fe7 1095 gen_generic_branch(dc);
48d5c82b 1096 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0bee699e
FB		 1097 dc->pc = DYNAMIC_PC;
1098 } else if (dc->npc == DYNAMIC_PC) {
48d5c82b 1099 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0bee699e
FB		 1100 dc->pc = DYNAMIC_PC;
1101 } else {
1102 dc->pc = dc->npc;
1103 }
1104}
1105
38bc628b
BS		 1106static inline void gen_op_next_insn(void)
1107{
48d5c82b
BS		 1108 tcg_gen_mov_tl(cpu_pc, cpu_npc);
1109 tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
38bc628b
BS		 1110}
1111
416fcaea
RH		 1112static void free_compare(DisasCompare *cmp)
1113{
1114 if (!cmp->g1) {
1115 tcg_temp_free(cmp->c1);
1116 }
1117 if (!cmp->g2) {
1118 tcg_temp_free(cmp->c2);
1119 }
1120}
1121
2a484ecf 1122static void gen_compare(DisasCompare *cmp, bool xcc, unsigned int cond,
416fcaea 1123 DisasContext *dc)
19f329ad 1124{
2a484ecf 1125 static int subcc_cond[16] = {
96b5a3d3 1126 TCG_COND_NEVER,
2a484ecf
RH		 1127 TCG_COND_EQ,
1128 TCG_COND_LE,
1129 TCG_COND_LT,
1130 TCG_COND_LEU,
1131 TCG_COND_LTU,
1132 -1, /* neg */
1133 -1, /* overflow */
96b5a3d3 1134 TCG_COND_ALWAYS,
2a484ecf
RH		 1135 TCG_COND_NE,
1136 TCG_COND_GT,
1137 TCG_COND_GE,
1138 TCG_COND_GTU,
1139 TCG_COND_GEU,
1140 -1, /* pos */
1141 -1, /* no overflow */
1142 };
1143
96b5a3d3
RH		 1144 static int logic_cond[16] = {
1145 TCG_COND_NEVER,
1146 TCG_COND_EQ, /* eq: Z */
1147 TCG_COND_LE, /* le: Z | (N ^ V) -> Z | N */
1148 TCG_COND_LT, /* lt: N ^ V -> N */
1149 TCG_COND_EQ, /* leu: C | Z -> Z */
1150 TCG_COND_NEVER, /* ltu: C -> 0 */
1151 TCG_COND_LT, /* neg: N */
1152 TCG_COND_NEVER, /* vs: V -> 0 */
1153 TCG_COND_ALWAYS,
1154 TCG_COND_NE, /* ne: !Z */
1155 TCG_COND_GT, /* gt: !(Z | (N ^ V)) -> !(Z | N) */
1156 TCG_COND_GE, /* ge: !(N ^ V) -> !N */
1157 TCG_COND_NE, /* gtu: !(C | Z) -> !Z */
1158 TCG_COND_ALWAYS, /* geu: !C -> 1 */
1159 TCG_COND_GE, /* pos: !N */
1160 TCG_COND_ALWAYS, /* vc: !V -> 1 */
1161 };
1162
a7812ae4 1163 TCGv_i32 r_src;
416fcaea
RH		 1164 TCGv r_dst;
1165
3475187d 1166#ifdef TARGET_SPARC64
2a484ecf 1167 if (xcc) {
dc99a3f2 1168 r_src = cpu_xcc;
2a484ecf 1169 } else {
dc99a3f2 1170 r_src = cpu_psr;
2a484ecf 1171 }
3475187d 1172#else
dc99a3f2 1173 r_src = cpu_psr;
3475187d 1174#endif
2a484ecf 1175
8393617c 1176 switch (dc->cc_op) {
96b5a3d3
RH		 1177 case CC_OP_LOGIC:
1178 cmp->cond = logic_cond[cond];
1179 do_compare_dst_0:
1180 cmp->is_bool = false;
1181 cmp->g2 = false;
1182 cmp->c2 = tcg_const_tl(0);
1183#ifdef TARGET_SPARC64
1184 if (!xcc) {
1185 cmp->g1 = false;
1186 cmp->c1 = tcg_temp_new();
1187 tcg_gen_ext32s_tl(cmp->c1, cpu_cc_dst);
1188 break;
1189 }
1190#endif
1191 cmp->g1 = true;
1192 cmp->c1 = cpu_cc_dst;
1193 break;
1194
2a484ecf
RH		 1195 case CC_OP_SUB:
1196 switch (cond) {
1197 case 6: /* neg */
1198 case 14: /* pos */
1199 cmp->cond = (cond == 6 ? TCG_COND_LT : TCG_COND_GE);
96b5a3d3 1200 goto do_compare_dst_0;
2a484ecf 1201
2a484ecf
RH		 1202 case 7: /* overflow */
1203 case 15: /* !overflow */
1204 goto do_dynamic;
1205
1206 default:
1207 cmp->cond = subcc_cond[cond];
1208 cmp->is_bool = false;
1209#ifdef TARGET_SPARC64
1210 if (!xcc) {
1211 /* Note that sign-extension works for unsigned compares as
1212 long as both operands are sign-extended. */
1213 cmp->g1 = cmp->g2 = false;
1214 cmp->c1 = tcg_temp_new();
1215 cmp->c2 = tcg_temp_new();
1216 tcg_gen_ext32s_tl(cmp->c1, cpu_cc_src);
1217 tcg_gen_ext32s_tl(cmp->c2, cpu_cc_src2);
0fa2a066 1218 break;
2a484ecf
RH		 1219 }
1220#endif
1221 cmp->g1 = cmp->g2 = true;
1222 cmp->c1 = cpu_cc_src;
1223 cmp->c2 = cpu_cc_src2;
1224 break;
1225 }
8393617c 1226 break;
2a484ecf 1227
8393617c 1228 default:
2a484ecf 1229 do_dynamic:
2ffd9176 1230 gen_helper_compute_psr(cpu_env);
8393617c 1231 dc->cc_op = CC_OP_FLAGS;
2a484ecf
RH		 1232 /* FALLTHRU */
1233
1234 case CC_OP_FLAGS:
1235 /* We're going to generate a boolean result. */
1236 cmp->cond = TCG_COND_NE;
1237 cmp->is_bool = true;
1238 cmp->g1 = cmp->g2 = false;
1239 cmp->c1 = r_dst = tcg_temp_new();
1240 cmp->c2 = tcg_const_tl(0);
1241
1242 switch (cond) {
1243 case 0x0:
1244 gen_op_eval_bn(r_dst);
1245 break;
1246 case 0x1:
1247 gen_op_eval_be(r_dst, r_src);
1248 break;
1249 case 0x2:
1250 gen_op_eval_ble(r_dst, r_src);
1251 break;
1252 case 0x3:
1253 gen_op_eval_bl(r_dst, r_src);
1254 break;
1255 case 0x4:
1256 gen_op_eval_bleu(r_dst, r_src);
1257 break;
1258 case 0x5:
1259 gen_op_eval_bcs(r_dst, r_src);
1260 break;
1261 case 0x6:
1262 gen_op_eval_bneg(r_dst, r_src);
1263 break;
1264 case 0x7:
1265 gen_op_eval_bvs(r_dst, r_src);
1266 break;
1267 case 0x8:
1268 gen_op_eval_ba(r_dst);
1269 break;
1270 case 0x9:
1271 gen_op_eval_bne(r_dst, r_src);
1272 break;
1273 case 0xa:
1274 gen_op_eval_bg(r_dst, r_src);
1275 break;
1276 case 0xb:
1277 gen_op_eval_bge(r_dst, r_src);
1278 break;
1279 case 0xc:
1280 gen_op_eval_bgu(r_dst, r_src);
1281 break;
1282 case 0xd:
1283 gen_op_eval_bcc(r_dst, r_src);
1284 break;
1285 case 0xe:
1286 gen_op_eval_bpos(r_dst, r_src);
1287 break;
1288 case 0xf:
1289 gen_op_eval_bvc(r_dst, r_src);
1290 break;
1291 }
19f329ad
BS		 1292 break;
1293 }
1294}
7a3f1944 1295
416fcaea 1296static void gen_fcompare(DisasCompare *cmp, unsigned int cc, unsigned int cond)
e8af50a3 1297{
19f329ad 1298 unsigned int offset;
416fcaea
RH		 1299 TCGv r_dst;
1300
1301 /* For now we still generate a straight boolean result. */
1302 cmp->cond = TCG_COND_NE;
1303 cmp->is_bool = true;
1304 cmp->g1 = cmp->g2 = false;
1305 cmp->c1 = r_dst = tcg_temp_new();
1306 cmp->c2 = tcg_const_tl(0);
19f329ad 1307
19f329ad
BS		 1308 switch (cc) {
1309 default:
1310 case 0x0:
1311 offset = 0;
1312 break;
1313 case 0x1:
1314 offset = 32 - 10;
1315 break;
1316 case 0x2:
1317 offset = 34 - 10;
1318 break;
1319 case 0x3:
1320 offset = 36 - 10;
1321 break;
1322 }
1323
1324 switch (cond) {
1325 case 0x0:
1326 gen_op_eval_bn(r_dst);
1327 break;
1328 case 0x1:
87e92502 1329 gen_op_eval_fbne(r_dst, cpu_fsr, offset);
19f329ad
BS		 1330 break;
1331 case 0x2:
87e92502 1332 gen_op_eval_fblg(r_dst, cpu_fsr, offset);
19f329ad
BS		 1333 break;
1334 case 0x3:
87e92502 1335 gen_op_eval_fbul(r_dst, cpu_fsr, offset);
19f329ad
BS		 1336 break;
1337 case 0x4:
87e92502 1338 gen_op_eval_fbl(r_dst, cpu_fsr, offset);
19f329ad
BS		 1339 break;
1340 case 0x5:
87e92502 1341 gen_op_eval_fbug(r_dst, cpu_fsr, offset);
19f329ad
BS		 1342 break;
1343 case 0x6:
87e92502 1344 gen_op_eval_fbg(r_dst, cpu_fsr, offset);
19f329ad
BS		 1345 break;
1346 case 0x7:
87e92502 1347 gen_op_eval_fbu(r_dst, cpu_fsr, offset);
19f329ad
BS		 1348 break;
1349 case 0x8:
1350 gen_op_eval_ba(r_dst);
1351 break;
1352 case 0x9:
87e92502 1353 gen_op_eval_fbe(r_dst, cpu_fsr, offset);
19f329ad
BS		 1354 break;
1355 case 0xa:
87e92502 1356 gen_op_eval_fbue(r_dst, cpu_fsr, offset);
19f329ad
BS		 1357 break;
1358 case 0xb:
87e92502 1359 gen_op_eval_fbge(r_dst, cpu_fsr, offset);
19f329ad
BS		 1360 break;
1361 case 0xc:
87e92502 1362 gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
19f329ad
BS		 1363 break;
1364 case 0xd:
87e92502 1365 gen_op_eval_fble(r_dst, cpu_fsr, offset);
19f329ad
BS		 1366 break;
1367 case 0xe:
87e92502 1368 gen_op_eval_fbule(r_dst, cpu_fsr, offset);
19f329ad
BS		 1369 break;
1370 case 0xf:
87e92502 1371 gen_op_eval_fbo(r_dst, cpu_fsr, offset);
19f329ad
BS		 1372 break;
1373 }
e8af50a3 1374}
00f219bf 1375
416fcaea
RH		 1376static void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond,
1377 DisasContext *dc)
1378{
1379 DisasCompare cmp;
1380 gen_compare(&cmp, cc, cond, dc);
1381
1382 /* The interface is to return a boolean in r_dst. */
1383 if (cmp.is_bool) {
1384 tcg_gen_mov_tl(r_dst, cmp.c1);
1385 } else {
1386 tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
1387 }
1388
1389 free_compare(&cmp);
1390}
1391
1392static void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
1393{
1394 DisasCompare cmp;
1395 gen_fcompare(&cmp, cc, cond);
1396
1397 /* The interface is to return a boolean in r_dst. */
1398 if (cmp.is_bool) {
1399 tcg_gen_mov_tl(r_dst, cmp.c1);
1400 } else {
1401 tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
1402 }
1403
1404 free_compare(&cmp);
1405}
1406
19f329ad 1407#ifdef TARGET_SPARC64
00f219bf
BS		 1408// Inverted logic
1409static const int gen_tcg_cond_reg[8] = {
1410 -1,
1411 TCG_COND_NE,
1412 TCG_COND_GT,
1413 TCG_COND_GE,
1414 -1,
1415 TCG_COND_EQ,
1416 TCG_COND_LE,
1417 TCG_COND_LT,
1418};
19f329ad 1419
416fcaea
RH		 1420static void gen_compare_reg(DisasCompare *cmp, int cond, TCGv r_src)
1421{
1422 cmp->cond = tcg_invert_cond(gen_tcg_cond_reg[cond]);
1423 cmp->is_bool = false;
1424 cmp->g1 = true;
1425 cmp->g2 = false;
1426 cmp->c1 = r_src;
1427 cmp->c2 = tcg_const_tl(0);
1428}
1429
4af984a7 1430static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
19f329ad 1431{
416fcaea
RH		 1432 DisasCompare cmp;
1433 gen_compare_reg(&cmp, cond, r_src);
19f329ad 1434
416fcaea
RH		 1435 /* The interface is to return a boolean in r_dst. */
1436 tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
1437
1438 free_compare(&cmp);
19f329ad 1439}
3475187d 1440#endif
cf495bcf 1441
d4a288ef 1442static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc)
7a3f1944 1443{
cf495bcf 1444 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b 1445 target_ulong target = dc->pc + offset;
5fafdf24 1446
22036a49
AT		 1447#ifdef TARGET_SPARC64
1448 if (unlikely(AM_CHECK(dc))) {
1449 target &= 0xffffffffULL;
1450 }
1451#endif
cf495bcf 1452 if (cond == 0x0) {
0f8a249a
BS		 1453 /* unconditional not taken */
1454 if (a) {
1455 dc->pc = dc->npc + 4;
1456 dc->npc = dc->pc + 4;
1457 } else {
1458 dc->pc = dc->npc;
1459 dc->npc = dc->pc + 4;
1460 }
cf495bcf 1461 } else if (cond == 0x8) {
0f8a249a
BS		 1462 /* unconditional taken */
1463 if (a) {
1464 dc->pc = target;
1465 dc->npc = dc->pc + 4;
1466 } else {
1467 dc->pc = dc->npc;
1468 dc->npc = target;
c27e2752 1469 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0f8a249a 1470 }
cf495bcf 1471 } else {
dee8913c 1472 flush_cond(dc);
d4a288ef 1473 gen_cond(cpu_cond, cc, cond, dc);
0f8a249a 1474 if (a) {
bfa31b76 1475 gen_branch_a(dc, target);
0f8a249a 1476 } else {
2bf2e019 1477 gen_branch_n(dc, target);
0f8a249a 1478 }
cf495bcf 1479 }
7a3f1944
FB		 1480}
1481
d4a288ef 1482static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc)
e8af50a3
FB		 1483{
1484 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b
FB		 1485 target_ulong target = dc->pc + offset;
1486
22036a49
AT		 1487#ifdef TARGET_SPARC64
1488 if (unlikely(AM_CHECK(dc))) {
1489 target &= 0xffffffffULL;
1490 }
1491#endif
e8af50a3 1492 if (cond == 0x0) {
0f8a249a
BS		 1493 /* unconditional not taken */
1494 if (a) {
1495 dc->pc = dc->npc + 4;
1496 dc->npc = dc->pc + 4;
1497 } else {
1498 dc->pc = dc->npc;
1499 dc->npc = dc->pc + 4;
1500 }
e8af50a3 1501 } else if (cond == 0x8) {
0f8a249a
BS		 1502 /* unconditional taken */
1503 if (a) {
1504 dc->pc = target;
1505 dc->npc = dc->pc + 4;
1506 } else {
1507 dc->pc = dc->npc;
1508 dc->npc = target;
c27e2752 1509 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0f8a249a 1510 }
e8af50a3 1511 } else {
dee8913c 1512 flush_cond(dc);
d4a288ef 1513 gen_fcond(cpu_cond, cc, cond);
0f8a249a 1514 if (a) {
bfa31b76 1515 gen_branch_a(dc, target);
0f8a249a 1516 } else {
2bf2e019 1517 gen_branch_n(dc, target);
0f8a249a 1518 }
e8af50a3
FB		 1519 }
1520}
1521
3475187d 1522#ifdef TARGET_SPARC64
4af984a7 1523static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
d4a288ef 1524 TCGv r_reg)
7a3f1944 1525{
3475187d
FB		 1526 unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1527 target_ulong target = dc->pc + offset;
1528
22036a49
AT		 1529 if (unlikely(AM_CHECK(dc))) {
1530 target &= 0xffffffffULL;
1531 }
dee8913c 1532 flush_cond(dc);
d4a288ef 1533 gen_cond_reg(cpu_cond, cond, r_reg);
3475187d 1534 if (a) {
bfa31b76 1535 gen_branch_a(dc, target);
3475187d 1536 } else {
2bf2e019 1537 gen_branch_n(dc, target);
3475187d 1538 }
7a3f1944
FB		 1539}
1540
a7812ae4 1541static inline void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
7e8c2b6c 1542{
714547bb
BS		 1543 switch (fccno) {
1544 case 0:
7385aed2 1545 gen_helper_fcmps(cpu_fsr, cpu_env, r_rs1, r_rs2);
714547bb
BS		 1546 break;
1547 case 1:
7385aed2 1548 gen_helper_fcmps_fcc1(cpu_fsr, cpu_env, r_rs1, r_rs2);
714547bb
BS		 1549 break;
1550 case 2:
7385aed2 1551 gen_helper_fcmps_fcc2(cpu_fsr, cpu_env, r_rs1, r_rs2);
714547bb
BS		 1552 break;
1553 case 3:
7385aed2 1554 gen_helper_fcmps_fcc3(cpu_fsr, cpu_env, r_rs1, r_rs2);
714547bb
BS		 1555 break;
1556 }
7e8c2b6c
BS		 1557}
1558
03fb8cfc 1559static inline void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1560{
a7812ae4
PB		 1561 switch (fccno) {
1562 case 0:
7385aed2 1563 gen_helper_fcmpd(cpu_fsr, cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1564 break;
1565 case 1:
7385aed2 1566 gen_helper_fcmpd_fcc1(cpu_fsr, cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1567 break;
1568 case 2:
7385aed2 1569 gen_helper_fcmpd_fcc2(cpu_fsr, cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1570 break;
1571 case 3:
7385aed2 1572 gen_helper_fcmpd_fcc3(cpu_fsr, cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1573 break;
1574 }
7e8c2b6c
BS		 1575}
1576
7e8c2b6c
BS		 1577static inline void gen_op_fcmpq(int fccno)
1578{
a7812ae4
PB		 1579 switch (fccno) {
1580 case 0:
7385aed2 1581 gen_helper_fcmpq(cpu_fsr, cpu_env);
a7812ae4
PB		 1582 break;
1583 case 1:
7385aed2 1584 gen_helper_fcmpq_fcc1(cpu_fsr, cpu_env);
a7812ae4
PB		 1585 break;
1586 case 2:
7385aed2 1587 gen_helper_fcmpq_fcc2(cpu_fsr, cpu_env);
a7812ae4
PB		 1588 break;
1589 case 3:
7385aed2 1590 gen_helper_fcmpq_fcc3(cpu_fsr, cpu_env);
a7812ae4
PB		 1591 break;
1592 }
7e8c2b6c 1593}
7e8c2b6c 1594
a7812ae4 1595static inline void gen_op_fcmpes(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
7e8c2b6c 1596{
714547bb
BS		 1597 switch (fccno) {
1598 case 0:
7385aed2 1599 gen_helper_fcmpes(cpu_fsr, cpu_env, r_rs1, r_rs2);
714547bb
BS		 1600 break;
1601 case 1:
7385aed2 1602 gen_helper_fcmpes_fcc1(cpu_fsr, cpu_env, r_rs1, r_rs2);
714547bb
BS		 1603 break;
1604 case 2:
7385aed2 1605 gen_helper_fcmpes_fcc2(cpu_fsr, cpu_env, r_rs1, r_rs2);
714547bb
BS		 1606 break;
1607 case 3:
7385aed2 1608 gen_helper_fcmpes_fcc3(cpu_fsr, cpu_env, r_rs1, r_rs2);
714547bb
BS		 1609 break;
1610 }
7e8c2b6c
BS		 1611}
1612
03fb8cfc 1613static inline void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1614{
a7812ae4
PB		 1615 switch (fccno) {
1616 case 0:
7385aed2 1617 gen_helper_fcmped(cpu_fsr, cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1618 break;
1619 case 1:
7385aed2 1620 gen_helper_fcmped_fcc1(cpu_fsr, cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1621 break;
1622 case 2:
7385aed2 1623 gen_helper_fcmped_fcc2(cpu_fsr, cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1624 break;
1625 case 3:
7385aed2 1626 gen_helper_fcmped_fcc3(cpu_fsr, cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1627 break;
1628 }
7e8c2b6c
BS		 1629}
1630
7e8c2b6c
BS		 1631static inline void gen_op_fcmpeq(int fccno)
1632{
a7812ae4
PB		 1633 switch (fccno) {
1634 case 0:
7385aed2 1635 gen_helper_fcmpeq(cpu_fsr, cpu_env);
a7812ae4
PB		 1636 break;
1637 case 1:
7385aed2 1638 gen_helper_fcmpeq_fcc1(cpu_fsr, cpu_env);
a7812ae4
PB		 1639 break;
1640 case 2:
7385aed2 1641 gen_helper_fcmpeq_fcc2(cpu_fsr, cpu_env);
a7812ae4
PB		 1642 break;
1643 case 3:
7385aed2 1644 gen_helper_fcmpeq_fcc3(cpu_fsr, cpu_env);
a7812ae4
PB		 1645 break;
1646 }
7e8c2b6c 1647}
7e8c2b6c
BS		 1648
1649#else
1650
714547bb 1651static inline void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2)
7e8c2b6c 1652{
7385aed2 1653 gen_helper_fcmps(cpu_fsr, cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1654}
1655
03fb8cfc 1656static inline void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1657{
7385aed2 1658 gen_helper_fcmpd(cpu_fsr, cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1659}
1660
7e8c2b6c
BS		 1661static inline void gen_op_fcmpq(int fccno)
1662{
7385aed2 1663 gen_helper_fcmpq(cpu_fsr, cpu_env);
7e8c2b6c 1664}
7e8c2b6c 1665
714547bb 1666static inline void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2)
7e8c2b6c 1667{
7385aed2 1668 gen_helper_fcmpes(cpu_fsr, cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1669}
1670
03fb8cfc 1671static inline void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1672{
7385aed2 1673 gen_helper_fcmped(cpu_fsr, cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1674}
1675
7e8c2b6c
BS		 1676static inline void gen_op_fcmpeq(int fccno)
1677{
7385aed2 1678 gen_helper_fcmpeq(cpu_fsr, cpu_env);
7e8c2b6c
BS		 1679}
1680#endif
1681
4fbe0067 1682static void gen_op_fpexception_im(DisasContext *dc, int fsr_flags)
134d77a1 1683{
47ad35f1 1684 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_NMASK);
87e92502 1685 tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
4fbe0067 1686 gen_exception(dc, TT_FP_EXCP);
134d77a1
BS		 1687}
1688
5b12f1e8 1689static int gen_trap_ifnofpu(DisasContext *dc)
a80dde08
FB		 1690{
1691#if !defined(CONFIG_USER_ONLY)
1692 if (!dc->fpu_enabled) {
4fbe0067 1693 gen_exception(dc, TT_NFPU_INSN);
a80dde08
FB		 1694 return 1;
1695 }
1696#endif
1697 return 0;
1698}
1699
7e8c2b6c
BS		 1700static inline void gen_op_clear_ieee_excp_and_FTT(void)
1701{
47ad35f1 1702 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_CEXC_NMASK);
7e8c2b6c
BS		 1703}
1704
61f17f6e
RH		 1705static inline void gen_fop_FF(DisasContext *dc, int rd, int rs,
1706 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32))
1707{
1708 TCGv_i32 dst, src;
1709
61f17f6e 1710 src = gen_load_fpr_F(dc, rs);
ba5f5179 1711 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1712
1713 gen(dst, cpu_env, src);
7385aed2 1714 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1715
61f17f6e
RH		 1716 gen_store_fpr_F(dc, rd, dst);
1717}
1718
1719static inline void gen_ne_fop_FF(DisasContext *dc, int rd, int rs,
1720 void (*gen)(TCGv_i32, TCGv_i32))
1721{
1722 TCGv_i32 dst, src;
1723
1724 src = gen_load_fpr_F(dc, rs);
ba5f5179 1725 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1726
1727 gen(dst, src);
1728
1729 gen_store_fpr_F(dc, rd, dst);
1730}
1731
1732static inline void gen_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2,
1733 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32))
1734{
1735 TCGv_i32 dst, src1, src2;
1736
61f17f6e
RH		 1737 src1 = gen_load_fpr_F(dc, rs1);
1738 src2 = gen_load_fpr_F(dc, rs2);
ba5f5179 1739 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1740
1741 gen(dst, cpu_env, src1, src2);
7385aed2 1742 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1743
61f17f6e
RH		 1744 gen_store_fpr_F(dc, rd, dst);
1745}
1746
1747#ifdef TARGET_SPARC64
1748static inline void gen_ne_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2,
1749 void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32))
1750{
1751 TCGv_i32 dst, src1, src2;
1752
1753 src1 = gen_load_fpr_F(dc, rs1);
1754 src2 = gen_load_fpr_F(dc, rs2);
ba5f5179 1755 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1756
1757 gen(dst, src1, src2);
1758
1759 gen_store_fpr_F(dc, rd, dst);
1760}
1761#endif
1762
1763static inline void gen_fop_DD(DisasContext *dc, int rd, int rs,
1764 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64))
1765{
1766 TCGv_i64 dst, src;
1767
61f17f6e 1768 src = gen_load_fpr_D(dc, rs);
3886b8a3 1769 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1770
1771 gen(dst, cpu_env, src);
7385aed2 1772 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1773
61f17f6e
RH		 1774 gen_store_fpr_D(dc, rd, dst);
1775}
1776
1777#ifdef TARGET_SPARC64
1778static inline void gen_ne_fop_DD(DisasContext *dc, int rd, int rs,
1779 void (*gen)(TCGv_i64, TCGv_i64))
1780{
1781 TCGv_i64 dst, src;
1782
1783 src = gen_load_fpr_D(dc, rs);
3886b8a3 1784 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1785
1786 gen(dst, src);
1787
1788 gen_store_fpr_D(dc, rd, dst);
1789}
1790#endif
1791
1792static inline void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1793 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64))
1794{
1795 TCGv_i64 dst, src1, src2;
1796
61f17f6e
RH		 1797 src1 = gen_load_fpr_D(dc, rs1);
1798 src2 = gen_load_fpr_D(dc, rs2);
3886b8a3 1799 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1800
1801 gen(dst, cpu_env, src1, src2);
7385aed2 1802 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1803
61f17f6e
RH		 1804 gen_store_fpr_D(dc, rd, dst);
1805}
1806
1807#ifdef TARGET_SPARC64
1808static inline void gen_ne_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1809 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64))
1810{
1811 TCGv_i64 dst, src1, src2;
1812
1813 src1 = gen_load_fpr_D(dc, rs1);
1814 src2 = gen_load_fpr_D(dc, rs2);
3886b8a3 1815 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1816
1817 gen(dst, src1, src2);
1818
1819 gen_store_fpr_D(dc, rd, dst);
1820}
f888300b 1821
2dedf314
RH		 1822static inline void gen_gsr_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1823 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
1824{
1825 TCGv_i64 dst, src1, src2;
1826
1827 src1 = gen_load_fpr_D(dc, rs1);
1828 src2 = gen_load_fpr_D(dc, rs2);
3886b8a3 1829 dst = gen_dest_fpr_D(dc, rd);
2dedf314
RH		 1830
1831 gen(dst, cpu_gsr, src1, src2);
1832
1833 gen_store_fpr_D(dc, rd, dst);
1834}
1835
f888300b
RH		 1836static inline void gen_ne_fop_DDDD(DisasContext *dc, int rd, int rs1, int rs2,
1837 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
1838{
1839 TCGv_i64 dst, src0, src1, src2;
1840
1841 src1 = gen_load_fpr_D(dc, rs1);
1842 src2 = gen_load_fpr_D(dc, rs2);
1843 src0 = gen_load_fpr_D(dc, rd);
3886b8a3 1844 dst = gen_dest_fpr_D(dc, rd);
f888300b
RH		 1845
1846 gen(dst, src0, src1, src2);
1847
1848 gen_store_fpr_D(dc, rd, dst);
1849}
61f17f6e
RH		 1850#endif
1851
1852static inline void gen_fop_QQ(DisasContext *dc, int rd, int rs,
1853 void (*gen)(TCGv_ptr))
1854{
61f17f6e
RH		 1855 gen_op_load_fpr_QT1(QFPREG(rs));
1856
1857 gen(cpu_env);
7385aed2 1858 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1859
61f17f6e 1860 gen_op_store_QT0_fpr(QFPREG(rd));
f9c816c0 1861 gen_update_fprs_dirty(dc, QFPREG(rd));
61f17f6e
RH		 1862}
1863
1864#ifdef TARGET_SPARC64
1865static inline void gen_ne_fop_QQ(DisasContext *dc, int rd, int rs,
1866 void (*gen)(TCGv_ptr))
1867{
1868 gen_op_load_fpr_QT1(QFPREG(rs));
1869
1870 gen(cpu_env);
1871
1872 gen_op_store_QT0_fpr(QFPREG(rd));
f9c816c0 1873 gen_update_fprs_dirty(dc, QFPREG(rd));
61f17f6e
RH		 1874}
1875#endif
1876
1877static inline void gen_fop_QQQ(DisasContext *dc, int rd, int rs1, int rs2,
1878 void (*gen)(TCGv_ptr))
1879{
61f17f6e
RH		 1880 gen_op_load_fpr_QT0(QFPREG(rs1));
1881 gen_op_load_fpr_QT1(QFPREG(rs2));
1882
1883 gen(cpu_env);
7385aed2 1884 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1885
61f17f6e 1886 gen_op_store_QT0_fpr(QFPREG(rd));
f9c816c0 1887 gen_update_fprs_dirty(dc, QFPREG(rd));
61f17f6e
RH		 1888}
1889
1890static inline void gen_fop_DFF(DisasContext *dc, int rd, int rs1, int rs2,
1891 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32, TCGv_i32))
1892{
1893 TCGv_i64 dst;
1894 TCGv_i32 src1, src2;
1895
61f17f6e
RH		 1896 src1 = gen_load_fpr_F(dc, rs1);
1897 src2 = gen_load_fpr_F(dc, rs2);
3886b8a3 1898 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1899
1900 gen(dst, cpu_env, src1, src2);
7385aed2 1901 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1902
61f17f6e
RH		 1903 gen_store_fpr_D(dc, rd, dst);
1904}
1905
1906static inline void gen_fop_QDD(DisasContext *dc, int rd, int rs1, int rs2,
1907 void (*gen)(TCGv_ptr, TCGv_i64, TCGv_i64))
1908{
1909 TCGv_i64 src1, src2;
1910
61f17f6e
RH		 1911 src1 = gen_load_fpr_D(dc, rs1);
1912 src2 = gen_load_fpr_D(dc, rs2);
1913
1914 gen(cpu_env, src1, src2);
7385aed2 1915 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1916
61f17f6e 1917 gen_op_store_QT0_fpr(QFPREG(rd));
f9c816c0 1918 gen_update_fprs_dirty(dc, QFPREG(rd));
61f17f6e
RH		 1919}
1920
1921#ifdef TARGET_SPARC64
1922static inline void gen_fop_DF(DisasContext *dc, int rd, int rs,
1923 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32))
1924{
1925 TCGv_i64 dst;
1926 TCGv_i32 src;
1927
61f17f6e 1928 src = gen_load_fpr_F(dc, rs);
3886b8a3 1929 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1930
1931 gen(dst, cpu_env, src);
7385aed2 1932 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1933
61f17f6e
RH		 1934 gen_store_fpr_D(dc, rd, dst);
1935}
1936#endif
1937
1938static inline void gen_ne_fop_DF(DisasContext *dc, int rd, int rs,
1939 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32))
1940{
1941 TCGv_i64 dst;
1942 TCGv_i32 src;
1943
1944 src = gen_load_fpr_F(dc, rs);
3886b8a3 1945 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1946
1947 gen(dst, cpu_env, src);
1948
1949 gen_store_fpr_D(dc, rd, dst);
1950}
1951
1952static inline void gen_fop_FD(DisasContext *dc, int rd, int rs,
1953 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i64))
1954{
1955 TCGv_i32 dst;
1956 TCGv_i64 src;
1957
61f17f6e 1958 src = gen_load_fpr_D(dc, rs);
ba5f5179 1959 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1960
1961 gen(dst, cpu_env, src);
7385aed2 1962 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1963
61f17f6e
RH		 1964 gen_store_fpr_F(dc, rd, dst);
1965}
1966
1967static inline void gen_fop_FQ(DisasContext *dc, int rd, int rs,
1968 void (*gen)(TCGv_i32, TCGv_ptr))
1969{
1970 TCGv_i32 dst;
1971
61f17f6e 1972 gen_op_load_fpr_QT1(QFPREG(rs));
ba5f5179 1973 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1974
1975 gen(dst, cpu_env);
7385aed2 1976 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1977
61f17f6e
RH		 1978 gen_store_fpr_F(dc, rd, dst);
1979}
1980
1981static inline void gen_fop_DQ(DisasContext *dc, int rd, int rs,
1982 void (*gen)(TCGv_i64, TCGv_ptr))
1983{
1984 TCGv_i64 dst;
1985
61f17f6e 1986 gen_op_load_fpr_QT1(QFPREG(rs));
3886b8a3 1987 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1988
1989 gen(dst, cpu_env);
7385aed2 1990 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1991
61f17f6e
RH		 1992 gen_store_fpr_D(dc, rd, dst);
1993}
1994
1995static inline void gen_ne_fop_QF(DisasContext *dc, int rd, int rs,
1996 void (*gen)(TCGv_ptr, TCGv_i32))
1997{
1998 TCGv_i32 src;
1999
2000 src = gen_load_fpr_F(dc, rs);
2001
2002 gen(cpu_env, src);
2003
2004 gen_op_store_QT0_fpr(QFPREG(rd));
f9c816c0 2005 gen_update_fprs_dirty(dc, QFPREG(rd));
61f17f6e
RH		 2006}
2007
2008static inline void gen_ne_fop_QD(DisasContext *dc, int rd, int rs,
2009 void (*gen)(TCGv_ptr, TCGv_i64))
2010{
2011 TCGv_i64 src;
2012
2013 src = gen_load_fpr_D(dc, rs);
2014
2015 gen(cpu_env, src);
2016
2017 gen_op_store_QT0_fpr(QFPREG(rd));
f9c816c0 2018 gen_update_fprs_dirty(dc, QFPREG(rd));
61f17f6e
RH		 2019}
2020
4fb554bc
RH		 2021static void gen_swap(DisasContext *dc, TCGv dst, TCGv src,
2022 TCGv addr, int mmu_idx, TCGMemOp memop)
2023{
4fb554bc 2024 gen_address_mask(dc, addr);
da1bcae6 2025 tcg_gen_atomic_xchg_tl(dst, addr, src, mmu_idx, memop);
4fb554bc
RH		 2026}
2027
fbb4bbb6
RH		 2028static void gen_ldstub(DisasContext *dc, TCGv dst, TCGv addr, int mmu_idx)
2029{
da1bcae6 2030 TCGv m1 = tcg_const_tl(0xff);
fbb4bbb6 2031 gen_address_mask(dc, addr);
da1bcae6
RH		 2032 tcg_gen_atomic_xchg_tl(dst, addr, m1, mmu_idx, MO_UB);
2033 tcg_temp_free(m1);
fbb4bbb6
RH		 2034}
2035
1a2fb1c0 2036/* asi moves */
22e70060 2037#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
7ec1e5ea
RH		 2038typedef enum {
2039 GET_ASI_HELPER,
2040 GET_ASI_EXCP,
f0913be0 2041 GET_ASI_DIRECT,
e4dc0052 2042 GET_ASI_DTWINX,
ca5ce572
RH		 2043 GET_ASI_BLOCK,
2044 GET_ASI_SHORT,
34810610
RH		 2045 GET_ASI_BCOPY,
2046 GET_ASI_BFILL,
7ec1e5ea
RH		 2047} ASIType;
2048
2049typedef struct {
2050 ASIType type;
a6d567e5 2051 int asi;
f0913be0
RH		 2052 int mem_idx;
2053 TCGMemOp memop;
7ec1e5ea 2054} DisasASI;
1a2fb1c0 2055
f0913be0 2056static DisasASI get_asi(DisasContext *dc, int insn, TCGMemOp memop)
7ec1e5ea
RH		 2057{
2058 int asi = GET_FIELD(insn, 19, 26);
2059 ASIType type = GET_ASI_HELPER;
f0913be0 2060 int mem_idx = dc->mem_idx;
7ec1e5ea
RH		 2061
2062#ifndef TARGET_SPARC64
2063 /* Before v9, all asis are immediate and privileged. */
1a2fb1c0 2064 if (IS_IMM) {
22e70060 2065 gen_exception(dc, TT_ILL_INSN);
7ec1e5ea
RH		 2066 type = GET_ASI_EXCP;
2067 } else if (supervisor(dc)
2068 /* Note that LEON accepts ASI_USERDATA in user mode, for
2069 use with CASA. Also note that previous versions of
0cc1f4bf
RH		 2070 QEMU allowed (and old versions of gcc emitted) ASI_P
2071 for LEON, which is incorrect. */
2072 || (asi == ASI_USERDATA
7ec1e5ea 2073 && (dc->def->features & CPU_FEATURE_CASA))) {
f0913be0
RH		 2074 switch (asi) {
2075 case ASI_USERDATA: /* User data access */
2076 mem_idx = MMU_USER_IDX;
2077 type = GET_ASI_DIRECT;
2078 break;
2079 case ASI_KERNELDATA: /* Supervisor data access */
2080 mem_idx = MMU_KERNEL_IDX;
2081 type = GET_ASI_DIRECT;
2082 break;
7f87c905
RH		 2083 case ASI_M_BYPASS: /* MMU passthrough */
2084 case ASI_LEON_BYPASS: /* LEON MMU passthrough */
2085 mem_idx = MMU_PHYS_IDX;
2086 type = GET_ASI_DIRECT;
2087 break;
34810610
RH		 2088 case ASI_M_BCOPY: /* Block copy, sta access */
2089 mem_idx = MMU_KERNEL_IDX;
2090 type = GET_ASI_BCOPY;
2091 break;
2092 case ASI_M_BFILL: /* Block fill, stda access */
2093 mem_idx = MMU_KERNEL_IDX;
2094 type = GET_ASI_BFILL;
2095 break;
f0913be0 2096 }
1a2fb1c0 2097 } else {
7ec1e5ea
RH		 2098 gen_exception(dc, TT_PRIV_INSN);
2099 type = GET_ASI_EXCP;
2100 }
2101#else
2102 if (IS_IMM) {
2103 asi = dc->asi;
1a2fb1c0 2104 }
f0913be0
RH		 2105 /* With v9, all asis below 0x80 are privileged. */
2106 /* ??? We ought to check cpu_has_hypervisor, but we didn't copy
2107 down that bit into DisasContext. For the moment that's ok,
2108 since the direct implementations below doesn't have any ASIs
2109 in the restricted [0x30, 0x7f] range, and the check will be
2110 done properly in the helper. */
2111 if (!supervisor(dc) && asi < 0x80) {
2112 gen_exception(dc, TT_PRIV_ACT);
2113 type = GET_ASI_EXCP;
2114 } else {
2115 switch (asi) {
7f87c905
RH		 2116 case ASI_REAL: /* Bypass */
2117 case ASI_REAL_IO: /* Bypass, non-cacheable */
2118 case ASI_REAL_L: /* Bypass LE */
2119 case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */
2120 case ASI_TWINX_REAL: /* Real address, twinx */
2121 case ASI_TWINX_REAL_L: /* Real address, twinx, LE */
34a6e13d
RH		 2122 case ASI_QUAD_LDD_PHYS:
2123 case ASI_QUAD_LDD_PHYS_L:
7f87c905
RH		 2124 mem_idx = MMU_PHYS_IDX;
2125 break;
f0913be0
RH		 2126 case ASI_N: /* Nucleus */
2127 case ASI_NL: /* Nucleus LE */
e4dc0052
RH		 2128 case ASI_TWINX_N:
2129 case ASI_TWINX_NL:
34a6e13d
RH		 2130 case ASI_NUCLEUS_QUAD_LDD:
2131 case ASI_NUCLEUS_QUAD_LDD_L:
9a10756d 2132 if (hypervisor(dc)) {
84f8f587 2133 mem_idx = MMU_PHYS_IDX;
9a10756d
AT		 2134 } else {
2135 mem_idx = MMU_NUCLEUS_IDX;
2136 }
f0913be0
RH		 2137 break;
2138 case ASI_AIUP: /* As if user primary */
2139 case ASI_AIUPL: /* As if user primary LE */
e4dc0052
RH		 2140 case ASI_TWINX_AIUP:
2141 case ASI_TWINX_AIUP_L:
ca5ce572
RH		 2142 case ASI_BLK_AIUP_4V:
2143 case ASI_BLK_AIUP_L_4V:
2144 case ASI_BLK_AIUP:
2145 case ASI_BLK_AIUPL:
f0913be0
RH		 2146 mem_idx = MMU_USER_IDX;
2147 break;
2148 case ASI_AIUS: /* As if user secondary */
2149 case ASI_AIUSL: /* As if user secondary LE */
e4dc0052
RH		 2150 case ASI_TWINX_AIUS:
2151 case ASI_TWINX_AIUS_L:
ca5ce572
RH		 2152 case ASI_BLK_AIUS_4V:
2153 case ASI_BLK_AIUS_L_4V:
2154 case ASI_BLK_AIUS:
2155 case ASI_BLK_AIUSL:
f0913be0
RH		 2156 mem_idx = MMU_USER_SECONDARY_IDX;
2157 break;
2158 case ASI_S: /* Secondary */
2159 case ASI_SL: /* Secondary LE */
e4dc0052
RH		 2160 case ASI_TWINX_S:
2161 case ASI_TWINX_SL:
ca5ce572
RH		 2162 case ASI_BLK_COMMIT_S:
2163 case ASI_BLK_S:
2164 case ASI_BLK_SL:
2165 case ASI_FL8_S:
2166 case ASI_FL8_SL:
2167 case ASI_FL16_S:
2168 case ASI_FL16_SL:
f0913be0
RH		 2169 if (mem_idx == MMU_USER_IDX) {
2170 mem_idx = MMU_USER_SECONDARY_IDX;
2171 } else if (mem_idx == MMU_KERNEL_IDX) {
2172 mem_idx = MMU_KERNEL_SECONDARY_IDX;
2173 }
2174 break;
2175 case ASI_P: /* Primary */
2176 case ASI_PL: /* Primary LE */
e4dc0052
RH		 2177 case ASI_TWINX_P:
2178 case ASI_TWINX_PL:
ca5ce572
RH		 2179 case ASI_BLK_COMMIT_P:
2180 case ASI_BLK_P:
2181 case ASI_BLK_PL:
2182 case ASI_FL8_P:
2183 case ASI_FL8_PL:
2184 case ASI_FL16_P:
2185 case ASI_FL16_PL:
f0913be0
RH		 2186 break;
2187 }
2188 switch (asi) {
7f87c905
RH		 2189 case ASI_REAL:
2190 case ASI_REAL_IO:
2191 case ASI_REAL_L:
2192 case ASI_REAL_IO_L:
f0913be0
RH		 2193 case ASI_N:
2194 case ASI_NL:
2195 case ASI_AIUP:
2196 case ASI_AIUPL:
2197 case ASI_AIUS:
2198 case ASI_AIUSL:
2199 case ASI_S:
2200 case ASI_SL:
2201 case ASI_P:
2202 case ASI_PL:
2203 type = GET_ASI_DIRECT;
2204 break;
7f87c905
RH		 2205 case ASI_TWINX_REAL:
2206 case ASI_TWINX_REAL_L:
e4dc0052
RH		 2207 case ASI_TWINX_N:
2208 case ASI_TWINX_NL:
2209 case ASI_TWINX_AIUP:
2210 case ASI_TWINX_AIUP_L:
2211 case ASI_TWINX_AIUS:
2212 case ASI_TWINX_AIUS_L:
2213 case ASI_TWINX_P:
2214 case ASI_TWINX_PL:
2215 case ASI_TWINX_S:
2216 case ASI_TWINX_SL:
34a6e13d
RH		 2217 case ASI_QUAD_LDD_PHYS:
2218 case ASI_QUAD_LDD_PHYS_L:
2219 case ASI_NUCLEUS_QUAD_LDD:
2220 case ASI_NUCLEUS_QUAD_LDD_L:
e4dc0052
RH		 2221 type = GET_ASI_DTWINX;
2222 break;
ca5ce572
RH		 2223 case ASI_BLK_COMMIT_P:
2224 case ASI_BLK_COMMIT_S:
2225 case ASI_BLK_AIUP_4V:
2226 case ASI_BLK_AIUP_L_4V:
2227 case ASI_BLK_AIUP:
2228 case ASI_BLK_AIUPL:
2229 case ASI_BLK_AIUS_4V:
2230 case ASI_BLK_AIUS_L_4V:
2231 case ASI_BLK_AIUS:
2232 case ASI_BLK_AIUSL:
2233 case ASI_BLK_S:
2234 case ASI_BLK_SL:
2235 case ASI_BLK_P:
2236 case ASI_BLK_PL:
2237 type = GET_ASI_BLOCK;
2238 break;
2239 case ASI_FL8_S:
2240 case ASI_FL8_SL:
2241 case ASI_FL8_P:
2242 case ASI_FL8_PL:
2243 memop = MO_UB;
2244 type = GET_ASI_SHORT;
2245 break;
2246 case ASI_FL16_S:
2247 case ASI_FL16_SL:
2248 case ASI_FL16_P:
2249 case ASI_FL16_PL:
2250 memop = MO_TEUW;
2251 type = GET_ASI_SHORT;
2252 break;
f0913be0
RH		 2253 }
2254 /* The little-endian asis all have bit 3 set. */
2255 if (asi & 8) {
2256 memop ^= MO_BSWAP;
2257 }
2258 }
7ec1e5ea
RH		 2259#endif
2260
f0913be0 2261 return (DisasASI){ type, asi, mem_idx, memop };
0425bee5
BS		 2262}
2263
22e70060 2264static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr,
1d65b0f5 2265 int insn, TCGMemOp memop)
0425bee5 2266{
f0913be0 2267 DisasASI da = get_asi(dc, insn, memop);
0425bee5 2268
7ec1e5ea
RH		 2269 switch (da.type) {
2270 case GET_ASI_EXCP:
2271 break;
e4dc0052
RH		 2272 case GET_ASI_DTWINX: /* Reserved for ldda. */
2273 gen_exception(dc, TT_ILL_INSN);
2274 break;
f0913be0
RH		 2275 case GET_ASI_DIRECT:
2276 gen_address_mask(dc, addr);
2277 tcg_gen_qemu_ld_tl(dst, addr, da.mem_idx, da.memop);
2278 break;
7ec1e5ea
RH		 2279 default:
2280 {
2281 TCGv_i32 r_asi = tcg_const_i32(da.asi);
6850811e 2282 TCGv_i32 r_mop = tcg_const_i32(memop);
7ec1e5ea
RH		 2283
2284 save_state(dc);
22e70060 2285#ifdef TARGET_SPARC64
6850811e 2286 gen_helper_ld_asi(dst, cpu_env, addr, r_asi, r_mop);
22e70060 2287#else
7ec1e5ea
RH		 2288 {
2289 TCGv_i64 t64 = tcg_temp_new_i64();
6850811e 2290 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_mop);
7ec1e5ea
RH		 2291 tcg_gen_trunc_i64_tl(dst, t64);
2292 tcg_temp_free_i64(t64);
2293 }
22e70060 2294#endif
6850811e 2295 tcg_temp_free_i32(r_mop);
7ec1e5ea
RH		 2296 tcg_temp_free_i32(r_asi);
2297 }
2298 break;
2299 }
1a2fb1c0
BS		 2300}
2301
22e70060 2302static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr,
1d65b0f5 2303 int insn, TCGMemOp memop)
1a2fb1c0 2304{
f0913be0 2305 DisasASI da = get_asi(dc, insn, memop);
1a2fb1c0 2306
7ec1e5ea
RH		 2307 switch (da.type) {
2308 case GET_ASI_EXCP:
2309 break;
e4dc0052 2310 case GET_ASI_DTWINX: /* Reserved for stda. */
3390537b 2311#ifndef TARGET_SPARC64
e4dc0052
RH		 2312 gen_exception(dc, TT_ILL_INSN);
2313 break;
3390537b
AT		 2314#else
2315 if (!(dc->def->features & CPU_FEATURE_HYPV)) {
2316 /* Pre OpenSPARC CPUs don't have these */
2317 gen_exception(dc, TT_ILL_INSN);
2318 return;
2319 }
2320 /* in OpenSPARC T1+ CPUs TWINX ASIs in store instructions
2321 * are ST_BLKINIT_ ASIs */
2322 /* fall through */
2323#endif
f0913be0
RH		 2324 case GET_ASI_DIRECT:
2325 gen_address_mask(dc, addr);
2326 tcg_gen_qemu_st_tl(src, addr, da.mem_idx, da.memop);
2327 break;
34810610
RH		 2328#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
2329 case GET_ASI_BCOPY:
2330 /* Copy 32 bytes from the address in SRC to ADDR. */
2331 /* ??? The original qemu code suggests 4-byte alignment, dropping
2332 the low bits, but the only place I can see this used is in the
2333 Linux kernel with 32 byte alignment, which would make more sense
2334 as a cacheline-style operation. */
2335 {
2336 TCGv saddr = tcg_temp_new();
2337 TCGv daddr = tcg_temp_new();
2338 TCGv four = tcg_const_tl(4);
2339 TCGv_i32 tmp = tcg_temp_new_i32();
2340 int i;
2341
2342 tcg_gen_andi_tl(saddr, src, -4);
2343 tcg_gen_andi_tl(daddr, addr, -4);
2344 for (i = 0; i < 32; i += 4) {
2345 /* Since the loads and stores are paired, allow the
2346 copy to happen in the host endianness. */
2347 tcg_gen_qemu_ld_i32(tmp, saddr, da.mem_idx, MO_UL);
2348 tcg_gen_qemu_st_i32(tmp, daddr, da.mem_idx, MO_UL);
2349 tcg_gen_add_tl(saddr, saddr, four);
2350 tcg_gen_add_tl(daddr, daddr, four);
2351 }
2352
2353 tcg_temp_free(saddr);
2354 tcg_temp_free(daddr);
2355 tcg_temp_free(four);
2356 tcg_temp_free_i32(tmp);
2357 }
2358 break;
2359#endif
7ec1e5ea
RH		 2360 default:
2361 {
2362 TCGv_i32 r_asi = tcg_const_i32(da.asi);
6850811e 2363 TCGv_i32 r_mop = tcg_const_i32(memop & MO_SIZE);
7ec1e5ea
RH		 2364
2365 save_state(dc);
22e70060 2366#ifdef TARGET_SPARC64
6850811e 2367 gen_helper_st_asi(cpu_env, addr, src, r_asi, r_mop);
22e70060 2368#else
7ec1e5ea
RH		 2369 {
2370 TCGv_i64 t64 = tcg_temp_new_i64();
2371 tcg_gen_extu_tl_i64(t64, src);
6850811e 2372 gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_mop);
7ec1e5ea
RH		 2373 tcg_temp_free_i64(t64);
2374 }
22e70060 2375#endif
6850811e 2376 tcg_temp_free_i32(r_mop);
7ec1e5ea
RH		 2377 tcg_temp_free_i32(r_asi);
2378
2379 /* A write to a TLB register may alter page maps. End the TB. */
2380 dc->npc = DYNAMIC_PC;
2381 }
2382 break;
2383 }
1a2fb1c0
BS		 2384}
2385
22e70060
RH		 2386static void gen_swap_asi(DisasContext *dc, TCGv dst, TCGv src,
2387 TCGv addr, int insn)
1a2fb1c0 2388{
f0913be0 2389 DisasASI da = get_asi(dc, insn, MO_TEUL);
22e70060 2390
7ec1e5ea
RH		 2391 switch (da.type) {
2392 case GET_ASI_EXCP:
2393 break;
4fb554bc
RH		 2394 case GET_ASI_DIRECT:
2395 gen_swap(dc, dst, src, addr, da.mem_idx, da.memop);
2396 break;
7ec1e5ea 2397 default:
4fb554bc
RH		 2398 /* ??? Should be DAE_invalid_asi. */
2399 gen_exception(dc, TT_DATA_ACCESS);
7ec1e5ea
RH		 2400 break;
2401 }
1a2fb1c0
BS		 2402}
2403
5a7267b6 2404static void gen_cas_asi(DisasContext *dc, TCGv addr, TCGv cmpv,
22e70060
RH		 2405 int insn, int rd)
2406{
f0913be0 2407 DisasASI da = get_asi(dc, insn, MO_TEUL);
5a7267b6 2408 TCGv oldv;
22e70060 2409
7268adeb
RH		 2410 switch (da.type) {
2411 case GET_ASI_EXCP:
7ec1e5ea 2412 return;
7268adeb 2413 case GET_ASI_DIRECT:
7268adeb 2414 oldv = tcg_temp_new();
5a7267b6
RH		 2415 tcg_gen_atomic_cmpxchg_tl(oldv, addr, cmpv, gen_load_gpr(dc, rd),
2416 da.mem_idx, da.memop);
7268adeb 2417 gen_store_gpr(dc, rd, oldv);
7268adeb 2418 tcg_temp_free(oldv);
7268adeb
RH		 2419 break;
2420 default:
2421 /* ??? Should be DAE_invalid_asi. */
2422 gen_exception(dc, TT_DATA_ACCESS);
2423 break;
7ec1e5ea 2424 }
22e70060
RH		 2425}
2426
2427static void gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn)
2428{
f0913be0 2429 DisasASI da = get_asi(dc, insn, MO_UB);
22e70060 2430
7ec1e5ea
RH		 2431 switch (da.type) {
2432 case GET_ASI_EXCP:
2433 break;
fbb4bbb6
RH		 2434 case GET_ASI_DIRECT:
2435 gen_ldstub(dc, dst, addr, da.mem_idx);
2436 break;
7ec1e5ea 2437 default:
3db010c3
RH		 2438 /* ??? In theory, this should be raise DAE_invalid_asi.
2439 But the SS-20 roms do ldstuba [%l0] #ASI_M_CTL, %o1. */
2440 if (parallel_cpus) {
2441 gen_helper_exit_atomic(cpu_env);
2442 } else {
2443 TCGv_i32 r_asi = tcg_const_i32(da.asi);
2444 TCGv_i32 r_mop = tcg_const_i32(MO_UB);
2445 TCGv_i64 s64, t64;
2446
2447 save_state(dc);
2448 t64 = tcg_temp_new_i64();
2449 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_mop);
2450
2451 s64 = tcg_const_i64(0xff);
2452 gen_helper_st_asi(cpu_env, addr, s64, r_asi, r_mop);
2453 tcg_temp_free_i64(s64);
2454 tcg_temp_free_i32(r_mop);
2455 tcg_temp_free_i32(r_asi);
2456
2457 tcg_gen_trunc_i64_tl(dst, t64);
2458 tcg_temp_free_i64(t64);
2459
2460 /* End the TB. */
2461 dc->npc = DYNAMIC_PC;
2462 }
7ec1e5ea
RH		 2463 break;
2464 }
22e70060
RH		 2465}
2466#endif
2467
2468#ifdef TARGET_SPARC64
2469static void gen_ldf_asi(DisasContext *dc, TCGv addr,
2470 int insn, int size, int rd)
1a2fb1c0 2471{
f0913be0 2472 DisasASI da = get_asi(dc, insn, (size == 4 ? MO_TEUL : MO_TEQ));
7705091c 2473 TCGv_i32 d32;
cb21b4da 2474 TCGv_i64 d64;
1a2fb1c0 2475
7ec1e5ea
RH		 2476 switch (da.type) {
2477 case GET_ASI_EXCP:
2478 break;
7705091c
RH		 2479
2480 case GET_ASI_DIRECT:
2481 gen_address_mask(dc, addr);
2482 switch (size) {
2483 case 4:
2484 d32 = gen_dest_fpr_F(dc);
2485 tcg_gen_qemu_ld_i32(d32, addr, da.mem_idx, da.memop);
2486 gen_store_fpr_F(dc, rd, d32);
2487 break;
2488 case 8:
cb21b4da
RH		 2489 tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da.mem_idx,
2490 da.memop | MO_ALIGN_4);
7705091c
RH		 2491 break;
2492 case 16:
cb21b4da
RH		 2493 d64 = tcg_temp_new_i64();
2494 tcg_gen_qemu_ld_i64(d64, addr, da.mem_idx, da.memop | MO_ALIGN_4);
7705091c 2495 tcg_gen_addi_tl(addr, addr, 8);
cb21b4da
RH		 2496 tcg_gen_qemu_ld_i64(cpu_fpr[rd/2+1], addr, da.mem_idx,
2497 da.memop | MO_ALIGN_4);
2498 tcg_gen_mov_i64(cpu_fpr[rd / 2], d64);
2499 tcg_temp_free_i64(d64);
7705091c
RH		 2500 break;
2501 default:
2502 g_assert_not_reached();
2503 }
2504 break;
2505
ca5ce572
RH		 2506 case GET_ASI_BLOCK:
2507 /* Valid for lddfa on aligned registers only. */
2508 if (size == 8 && (rd & 7) == 0) {
80883227 2509 TCGMemOp memop;
ca5ce572
RH		 2510 TCGv eight;
2511 int i;
2512
ca5ce572
RH		 2513 gen_address_mask(dc, addr);
2514
80883227
RH		 2515 /* The first operation checks required alignment. */
2516 memop = da.memop | MO_ALIGN_64;
ca5ce572
RH		 2517 eight = tcg_const_tl(8);
2518 for (i = 0; ; ++i) {
2519 tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + i], addr,
80883227 2520 da.mem_idx, memop);
ca5ce572
RH		 2521 if (i == 7) {
2522 break;
2523 }
2524 tcg_gen_add_tl(addr, addr, eight);
80883227 2525 memop = da.memop;
ca5ce572
RH		 2526 }
2527 tcg_temp_free(eight);
2528 } else {
2529 gen_exception(dc, TT_ILL_INSN);
2530 }
2531 break;
2532
2533 case GET_ASI_SHORT:
2534 /* Valid for lddfa only. */
2535 if (size == 8) {
2536 gen_address_mask(dc, addr);
2537 tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da.mem_idx, da.memop);
2538 } else {
2539 gen_exception(dc, TT_ILL_INSN);
2540 }
2541 break;
2542
7ec1e5ea
RH		 2543 default:
2544 {
2545 TCGv_i32 r_asi = tcg_const_i32(da.asi);
f2fe396f 2546 TCGv_i32 r_mop = tcg_const_i32(da.memop);
7ec1e5ea
RH		 2547
2548 save_state(dc);
f2fe396f
RH		 2549 /* According to the table in the UA2011 manual, the only
2550 other asis that are valid for ldfa/lddfa/ldqfa are
2551 the NO_FAULT asis. We still need a helper for these,
2552 but we can just use the integer asi helper for them. */
2553 switch (size) {
2554 case 4:
cb21b4da
RH		 2555 d64 = tcg_temp_new_i64();
2556 gen_helper_ld_asi(d64, cpu_env, addr, r_asi, r_mop);
2557 d32 = gen_dest_fpr_F(dc);
2558 tcg_gen_extrl_i64_i32(d32, d64);
2559 tcg_temp_free_i64(d64);
2560 gen_store_fpr_F(dc, rd, d32);
f2fe396f
RH		 2561 break;
2562 case 8:
2563 gen_helper_ld_asi(cpu_fpr[rd / 2], cpu_env, addr, r_asi, r_mop);
2564 break;
2565 case 16:
cb21b4da
RH		 2566 d64 = tcg_temp_new_i64();
2567 gen_helper_ld_asi(d64, cpu_env, addr, r_asi, r_mop);
f2fe396f
RH		 2568 tcg_gen_addi_tl(addr, addr, 8);
2569 gen_helper_ld_asi(cpu_fpr[rd/2+1], cpu_env, addr, r_asi, r_mop);
cb21b4da
RH		 2570 tcg_gen_mov_i64(cpu_fpr[rd / 2], d64);
2571 tcg_temp_free_i64(d64);
f2fe396f
RH		 2572 break;
2573 default:
2574 g_assert_not_reached();
2575 }
2576 tcg_temp_free_i32(r_mop);
7ec1e5ea
RH		 2577 tcg_temp_free_i32(r_asi);
2578 }
2579 break;
2580 }
1a2fb1c0
BS		 2581}
2582
22e70060
RH		 2583static void gen_stf_asi(DisasContext *dc, TCGv addr,
2584 int insn, int size, int rd)
1a2fb1c0 2585{
f0913be0 2586 DisasASI da = get_asi(dc, insn, (size == 4 ? MO_TEUL : MO_TEQ));
7705091c 2587 TCGv_i32 d32;
1a2fb1c0 2588
7ec1e5ea
RH		 2589 switch (da.type) {
2590 case GET_ASI_EXCP:
2591 break;
7705091c
RH		 2592
2593 case GET_ASI_DIRECT:
2594 gen_address_mask(dc, addr);
2595 switch (size) {
2596 case 4:
2597 d32 = gen_load_fpr_F(dc, rd);
2598 tcg_gen_qemu_st_i32(d32, addr, da.mem_idx, da.memop);
2599 break;
2600 case 8:
cb21b4da
RH		 2601 tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx,
2602 da.memop | MO_ALIGN_4);
7705091c
RH		 2603 break;
2604 case 16:
cb21b4da
RH		 2605 /* Only 4-byte alignment required. However, it is legal for the
2606 cpu to signal the alignment fault, and the OS trap handler is
2607 required to fix it up. Requiring 16-byte alignment here avoids
2608 having to probe the second page before performing the first
2609 write. */
f939ffe5
RH		 2610 tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx,
2611 da.memop | MO_ALIGN_16);
7705091c
RH		 2612 tcg_gen_addi_tl(addr, addr, 8);
2613 tcg_gen_qemu_st_i64(cpu_fpr[rd/2+1], addr, da.mem_idx, da.memop);
2614 break;
2615 default:
2616 g_assert_not_reached();
2617 }
2618 break;
2619
ca5ce572
RH		 2620 case GET_ASI_BLOCK:
2621 /* Valid for stdfa on aligned registers only. */
2622 if (size == 8 && (rd & 7) == 0) {
80883227 2623 TCGMemOp memop;
ca5ce572
RH		 2624 TCGv eight;
2625 int i;
2626
ca5ce572
RH		 2627 gen_address_mask(dc, addr);
2628
80883227
RH		 2629 /* The first operation checks required alignment. */
2630 memop = da.memop | MO_ALIGN_64;
ca5ce572
RH		 2631 eight = tcg_const_tl(8);
2632 for (i = 0; ; ++i) {
2633 tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + i], addr,
80883227 2634 da.mem_idx, memop);
ca5ce572
RH		 2635 if (i == 7) {
2636 break;
2637 }
2638 tcg_gen_add_tl(addr, addr, eight);
80883227 2639 memop = da.memop;
ca5ce572
RH		 2640 }
2641 tcg_temp_free(eight);
2642 } else {
2643 gen_exception(dc, TT_ILL_INSN);
2644 }
2645 break;
2646
2647 case GET_ASI_SHORT:
2648 /* Valid for stdfa only. */
2649 if (size == 8) {
2650 gen_address_mask(dc, addr);
2651 tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx, da.memop);
2652 } else {
2653 gen_exception(dc, TT_ILL_INSN);
2654 }
2655 break;
2656
7ec1e5ea 2657 default:
f2fe396f
RH		 2658 /* According to the table in the UA2011 manual, the only
2659 other asis that are valid for ldfa/lddfa/ldqfa are
2660 the PST* asis, which aren't currently handled. */
2661 gen_exception(dc, TT_ILL_INSN);
7ec1e5ea
RH		 2662 break;
2663 }
1a2fb1c0
BS		 2664}
2665
e4dc0052 2666static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd)
1a2fb1c0 2667{
f0913be0 2668 DisasASI da = get_asi(dc, insn, MO_TEQ);
e4dc0052
RH		 2669 TCGv_i64 hi = gen_dest_gpr(dc, rd);
2670 TCGv_i64 lo = gen_dest_gpr(dc, rd + 1);
1a2fb1c0 2671
7ec1e5ea
RH		 2672 switch (da.type) {
2673 case GET_ASI_EXCP:
e4dc0052
RH		 2674 return;
2675
2676 case GET_ASI_DTWINX:
e4dc0052 2677 gen_address_mask(dc, addr);
80883227 2678 tcg_gen_qemu_ld_i64(hi, addr, da.mem_idx, da.memop | MO_ALIGN_16);
e4dc0052
RH		 2679 tcg_gen_addi_tl(addr, addr, 8);
2680 tcg_gen_qemu_ld_i64(lo, addr, da.mem_idx, da.memop);
7ec1e5ea 2681 break;
e4dc0052
RH		 2682
2683 case GET_ASI_DIRECT:
2684 {
2685 TCGv_i64 tmp = tcg_temp_new_i64();
2686
2687 gen_address_mask(dc, addr);
2688 tcg_gen_qemu_ld_i64(tmp, addr, da.mem_idx, da.memop);
2689
2690 /* Note that LE ldda acts as if each 32-bit register
2691 result is byte swapped. Having just performed one
2692 64-bit bswap, we need now to swap the writebacks. */
2693 if ((da.memop & MO_BSWAP) == MO_TE) {
2694 tcg_gen_extr32_i64(lo, hi, tmp);
2695 } else {
2696 tcg_gen_extr32_i64(hi, lo, tmp);
2697 }
2698 tcg_temp_free_i64(tmp);
2699 }
2700 break;
2701
7ec1e5ea 2702 default:
918d9a2c
RH		 2703 /* ??? In theory we've handled all of the ASIs that are valid
2704 for ldda, and this should raise DAE_invalid_asi. However,
2705 real hardware allows others. This can be seen with e.g.
2706 FreeBSD 10.3 wrt ASI_IC_TAG. */
7ec1e5ea
RH		 2707 {
2708 TCGv_i32 r_asi = tcg_const_i32(da.asi);
918d9a2c
RH		 2709 TCGv_i32 r_mop = tcg_const_i32(da.memop);
2710 TCGv_i64 tmp = tcg_temp_new_i64();
7ec1e5ea
RH		 2711
2712 save_state(dc);
918d9a2c 2713 gen_helper_ld_asi(tmp, cpu_env, addr, r_asi, r_mop);
7ec1e5ea 2714 tcg_temp_free_i32(r_asi);
918d9a2c 2715 tcg_temp_free_i32(r_mop);
3f4288eb 2716
918d9a2c
RH		 2717 /* See above. */
2718 if ((da.memop & MO_BSWAP) == MO_TE) {
2719 tcg_gen_extr32_i64(lo, hi, tmp);
2720 } else {
2721 tcg_gen_extr32_i64(hi, lo, tmp);
2722 }
2723 tcg_temp_free_i64(tmp);
7ec1e5ea
RH		 2724 }
2725 break;
2726 }
e4dc0052
RH		 2727
2728 gen_store_gpr(dc, rd, hi);
2729 gen_store_gpr(dc, rd + 1, lo);
0425bee5
BS		 2730}
2731
22e70060
RH		 2732static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
2733 int insn, int rd)
0425bee5 2734{
f0913be0 2735 DisasASI da = get_asi(dc, insn, MO_TEQ);
c7785e16 2736 TCGv lo = gen_load_gpr(dc, rd + 1);
a7ec4229 2737
7ec1e5ea
RH		 2738 switch (da.type) {
2739 case GET_ASI_EXCP:
2740 break;
e4dc0052
RH		 2741
2742 case GET_ASI_DTWINX:
e4dc0052 2743 gen_address_mask(dc, addr);
80883227 2744 tcg_gen_qemu_st_i64(hi, addr, da.mem_idx, da.memop | MO_ALIGN_16);
e4dc0052
RH		 2745 tcg_gen_addi_tl(addr, addr, 8);
2746 tcg_gen_qemu_st_i64(lo, addr, da.mem_idx, da.memop);
2747 break;
2748
2749 case GET_ASI_DIRECT:
2750 {
2751 TCGv_i64 t64 = tcg_temp_new_i64();
2752
2753 /* Note that LE stda acts as if each 32-bit register result is
2754 byte swapped. We will perform one 64-bit LE store, so now
2755 we must swap the order of the construction. */
2756 if ((da.memop & MO_BSWAP) == MO_TE) {
2757 tcg_gen_concat32_i64(t64, lo, hi);
2758 } else {
2759 tcg_gen_concat32_i64(t64, hi, lo);
2760 }
2761 gen_address_mask(dc, addr);
2762 tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop);
2763 tcg_temp_free_i64(t64);
2764 }
2765 break;
2766
7ec1e5ea 2767 default:
918d9a2c
RH		 2768 /* ??? In theory we've handled all of the ASIs that are valid
2769 for stda, and this should raise DAE_invalid_asi. */
7ec1e5ea
RH		 2770 {
2771 TCGv_i32 r_asi = tcg_const_i32(da.asi);
918d9a2c
RH		 2772 TCGv_i32 r_mop = tcg_const_i32(da.memop);
2773 TCGv_i64 t64 = tcg_temp_new_i64();
7ec1e5ea 2774
918d9a2c
RH		 2775 /* See above. */
2776 if ((da.memop & MO_BSWAP) == MO_TE) {
2777 tcg_gen_concat32_i64(t64, lo, hi);
2778 } else {
2779 tcg_gen_concat32_i64(t64, hi, lo);
2780 }
7ec1e5ea 2781
918d9a2c 2782 save_state(dc);
6850811e
RH		 2783 gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_mop);
2784 tcg_temp_free_i32(r_mop);
7ec1e5ea
RH		 2785 tcg_temp_free_i32(r_asi);
2786 tcg_temp_free_i64(t64);
2787 }
2788 break;
2789 }
1a2fb1c0
BS		 2790}
2791
7268adeb 2792static void gen_casx_asi(DisasContext *dc, TCGv addr, TCGv cmpv,
22e70060 2793 int insn, int rd)
1a2fb1c0 2794{
f0913be0 2795 DisasASI da = get_asi(dc, insn, MO_TEQ);
5a7267b6 2796 TCGv oldv;
1a2fb1c0 2797
7268adeb
RH		 2798 switch (da.type) {
2799 case GET_ASI_EXCP:
7ec1e5ea 2800 return;
7268adeb
RH		 2801 case GET_ASI_DIRECT:
2802 oldv = tcg_temp_new();
5a7267b6
RH		 2803 tcg_gen_atomic_cmpxchg_tl(oldv, addr, cmpv, gen_load_gpr(dc, rd),
2804 da.mem_idx, da.memop);
7268adeb
RH		 2805 gen_store_gpr(dc, rd, oldv);
2806 tcg_temp_free(oldv);
7268adeb
RH		 2807 break;
2808 default:
2809 /* ??? Should be DAE_invalid_asi. */
2810 gen_exception(dc, TT_DATA_ACCESS);
2811 break;
2812 }
1a2fb1c0
BS		 2813}
2814
2815#elif !defined(CONFIG_USER_ONLY)
e4dc0052 2816static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd)
1a2fb1c0 2817{
d2dc4069
RH		 2818 /* ??? Work around an apparent bug in Ubuntu gcc 4.8.2-10ubuntu2+12,
2819 whereby "rd + 1" elicits "error: array subscript is above array".
2820 Since we have already asserted that rd is even, the semantics
2821 are unchanged. */
7ec1e5ea 2822 TCGv lo = gen_dest_gpr(dc, rd | 1);
e4dc0052 2823 TCGv hi = gen_dest_gpr(dc, rd);
7ec1e5ea 2824 TCGv_i64 t64 = tcg_temp_new_i64();
f0913be0 2825 DisasASI da = get_asi(dc, insn, MO_TEQ);
7ec1e5ea
RH		 2826
2827 switch (da.type) {
2828 case GET_ASI_EXCP:
2829 tcg_temp_free_i64(t64);
2830 return;
e4dc0052
RH		 2831 case GET_ASI_DIRECT:
2832 gen_address_mask(dc, addr);
2833 tcg_gen_qemu_ld_i64(t64, addr, da.mem_idx, da.memop);
2834 break;
7ec1e5ea
RH		 2835 default:
2836 {
2837 TCGv_i32 r_asi = tcg_const_i32(da.asi);
6850811e 2838 TCGv_i32 r_mop = tcg_const_i32(MO_Q);
7ec1e5ea
RH		 2839
2840 save_state(dc);
6850811e
RH		 2841 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_mop);
2842 tcg_temp_free_i32(r_mop);
7ec1e5ea
RH		 2843 tcg_temp_free_i32(r_asi);
2844 }
2845 break;
2846 }
c7785e16 2847
7ec1e5ea 2848 tcg_gen_extr_i64_i32(lo, hi, t64);
1ec789ab 2849 tcg_temp_free_i64(t64);
7ec1e5ea 2850 gen_store_gpr(dc, rd | 1, lo);
c7785e16 2851 gen_store_gpr(dc, rd, hi);
0425bee5
BS		 2852}
2853
22e70060
RH		 2854static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
2855 int insn, int rd)
0425bee5 2856{
f0913be0 2857 DisasASI da = get_asi(dc, insn, MO_TEQ);
c7785e16 2858 TCGv lo = gen_load_gpr(dc, rd + 1);
1ec789ab 2859 TCGv_i64 t64 = tcg_temp_new_i64();
a7ec4229 2860
1ec789ab 2861 tcg_gen_concat_tl_i64(t64, lo, hi);
7ec1e5ea
RH		 2862
2863 switch (da.type) {
2864 case GET_ASI_EXCP:
2865 break;
e4dc0052
RH		 2866 case GET_ASI_DIRECT:
2867 gen_address_mask(dc, addr);
2868 tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop);
2869 break;
34810610
RH		 2870 case GET_ASI_BFILL:
2871 /* Store 32 bytes of T64 to ADDR. */
2872 /* ??? The original qemu code suggests 8-byte alignment, dropping
2873 the low bits, but the only place I can see this used is in the
2874 Linux kernel with 32 byte alignment, which would make more sense
2875 as a cacheline-style operation. */
2876 {
2877 TCGv d_addr = tcg_temp_new();
2878 TCGv eight = tcg_const_tl(8);
2879 int i;
2880
2881 tcg_gen_andi_tl(d_addr, addr, -8);
2882 for (i = 0; i < 32; i += 8) {
2883 tcg_gen_qemu_st_i64(t64, d_addr, da.mem_idx, da.memop);
2884 tcg_gen_add_tl(d_addr, d_addr, eight);
2885 }
2886
2887 tcg_temp_free(d_addr);
2888 tcg_temp_free(eight);
2889 }
2890 break;
7ec1e5ea
RH		 2891 default:
2892 {
2893 TCGv_i32 r_asi = tcg_const_i32(da.asi);
6850811e 2894 TCGv_i32 r_mop = tcg_const_i32(MO_Q);
7ec1e5ea
RH		 2895
2896 save_state(dc);
6850811e
RH		 2897 gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_mop);
2898 tcg_temp_free_i32(r_mop);
7ec1e5ea
RH		 2899 tcg_temp_free_i32(r_asi);
2900 }
2901 break;
2902 }
2903
1ec789ab 2904 tcg_temp_free_i64(t64);
1a2fb1c0
BS		 2905}
2906#endif
2907
9d1d4e34 2908static TCGv get_src1(DisasContext *dc, unsigned int insn)
9322a4bf 2909{
9d1d4e34
RH		 2910 unsigned int rs1 = GET_FIELD(insn, 13, 17);
2911 return gen_load_gpr(dc, rs1);
9322a4bf
BS		 2912}
2913
9d1d4e34 2914static TCGv get_src2(DisasContext *dc, unsigned int insn)
a49d9390 2915{
a49d9390 2916 if (IS_IMM) { /* immediate */
42a8aa83 2917 target_long simm = GET_FIELDs(insn, 19, 31);
9d1d4e34
RH		 2918 TCGv t = get_temp_tl(dc);
2919 tcg_gen_movi_tl(t, simm);
2920 return t;
2921 } else { /* register */
42a8aa83 2922 unsigned int rs2 = GET_FIELD(insn, 27, 31);
9d1d4e34 2923 return gen_load_gpr(dc, rs2);
a49d9390 2924 }
a49d9390
BS		 2925}
2926
8194f35a 2927#ifdef TARGET_SPARC64
7e480893
RH		 2928static void gen_fmovs(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2929{
2930 TCGv_i32 c32, zero, dst, s1, s2;
2931
2932 /* We have two choices here: extend the 32 bit data and use movcond_i64,
2933 or fold the comparison down to 32 bits and use movcond_i32. Choose
2934 the later. */
2935 c32 = tcg_temp_new_i32();
2936 if (cmp->is_bool) {
ecc7b3aa 2937 tcg_gen_extrl_i64_i32(c32, cmp->c1);
7e480893
RH		 2938 } else {
2939 TCGv_i64 c64 = tcg_temp_new_i64();
2940 tcg_gen_setcond_i64(cmp->cond, c64, cmp->c1, cmp->c2);
ecc7b3aa 2941 tcg_gen_extrl_i64_i32(c32, c64);
7e480893
RH		 2942 tcg_temp_free_i64(c64);
2943 }
2944
2945 s1 = gen_load_fpr_F(dc, rs);
2946 s2 = gen_load_fpr_F(dc, rd);
ba5f5179 2947 dst = gen_dest_fpr_F(dc);
7e480893
RH		 2948 zero = tcg_const_i32(0);
2949
2950 tcg_gen_movcond_i32(TCG_COND_NE, dst, c32, zero, s1, s2);
2951
2952 tcg_temp_free_i32(c32);
2953 tcg_temp_free_i32(zero);
2954 gen_store_fpr_F(dc, rd, dst);
2955}
2956
2957static void gen_fmovd(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2958{
3886b8a3 2959 TCGv_i64 dst = gen_dest_fpr_D(dc, rd);
7e480893
RH		 2960 tcg_gen_movcond_i64(cmp->cond, dst, cmp->c1, cmp->c2,
2961 gen_load_fpr_D(dc, rs),
2962 gen_load_fpr_D(dc, rd));
2963 gen_store_fpr_D(dc, rd, dst);
2964}
2965
2966static void gen_fmovq(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2967{
2968 int qd = QFPREG(rd);
2969 int qs = QFPREG(rs);
2970
2971 tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2], cmp->c1, cmp->c2,
2972 cpu_fpr[qs / 2], cpu_fpr[qd / 2]);
2973 tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2 + 1], cmp->c1, cmp->c2,
2974 cpu_fpr[qs / 2 + 1], cpu_fpr[qd / 2 + 1]);
2975
f9c816c0 2976 gen_update_fprs_dirty(dc, qd);
7e480893
RH		 2977}
2978
a2035e83 2979#ifndef CONFIG_USER_ONLY
1bcea73e 2980static inline void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_env cpu_env)
8194f35a 2981{
b551ec04 2982 TCGv_i32 r_tl = tcg_temp_new_i32();
8194f35a
IK		 2983
2984 /* load env->tl into r_tl */
b551ec04 2985 tcg_gen_ld_i32(r_tl, cpu_env, offsetof(CPUSPARCState, tl));
8194f35a
IK		 2986
2987 /* tl = [0 ... MAXTL_MASK] where MAXTL_MASK must be power of 2 */
b551ec04 2988 tcg_gen_andi_i32(r_tl, r_tl, MAXTL_MASK);
8194f35a
IK		 2989
2990 /* calculate offset to current trap state from env->ts, reuse r_tl */
b551ec04 2991 tcg_gen_muli_i32(r_tl, r_tl, sizeof (trap_state));
c5f9864e 2992 tcg_gen_addi_ptr(r_tsptr, cpu_env, offsetof(CPUSPARCState, ts));
8194f35a
IK		 2993
2994 /* tsptr = env->ts[env->tl & MAXTL_MASK] */
b551ec04
JF		 2995 {
2996 TCGv_ptr r_tl_tmp = tcg_temp_new_ptr();
2997 tcg_gen_ext_i32_ptr(r_tl_tmp, r_tl);
2998 tcg_gen_add_ptr(r_tsptr, r_tsptr, r_tl_tmp);
bc57c114 2999 tcg_temp_free_ptr(r_tl_tmp);
b551ec04 3000 }
8194f35a 3001
b551ec04 3002 tcg_temp_free_i32(r_tl);
8194f35a 3003}
a2035e83 3004#endif
6c073553
RH		 3005
3006static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2,
3007 int width, bool cc, bool left)
3008{
3009 TCGv lo1, lo2, t1, t2;
3010 uint64_t amask, tabl, tabr;
3011 int shift, imask, omask;
3012
3013 if (cc) {
3014 tcg_gen_mov_tl(cpu_cc_src, s1);
3015 tcg_gen_mov_tl(cpu_cc_src2, s2);
3016 tcg_gen_sub_tl(cpu_cc_dst, s1, s2);
3017 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
3018 dc->cc_op = CC_OP_SUB;
3019 }
3020
3021 /* Theory of operation: there are two tables, left and right (not to
3022 be confused with the left and right versions of the opcode). These
3023 are indexed by the low 3 bits of the inputs. To make things "easy",
3024 these tables are loaded into two constants, TABL and TABR below.
3025 The operation index = (input & imask) << shift calculates the index
3026 into the constant, while val = (table >> index) & omask calculates
3027 the value we're looking for. */
3028 switch (width) {
3029 case 8:
3030 imask = 0x7;
3031 shift = 3;
3032 omask = 0xff;
3033 if (left) {
3034 tabl = 0x80c0e0f0f8fcfeffULL;
3035 tabr = 0xff7f3f1f0f070301ULL;
3036 } else {
3037 tabl = 0x0103070f1f3f7fffULL;
3038 tabr = 0xfffefcf8f0e0c080ULL;
3039 }
3040 break;
3041 case 16:
3042 imask = 0x6;
3043 shift = 1;
3044 omask = 0xf;
3045 if (left) {
3046 tabl = 0x8cef;
3047 tabr = 0xf731;
3048 } else {
3049 tabl = 0x137f;
3050 tabr = 0xfec8;
3051 }
3052 break;
3053 case 32:
3054 imask = 0x4;
3055 shift = 0;
3056 omask = 0x3;
3057 if (left) {
3058 tabl = (2 << 2) | 3;
3059 tabr = (3 << 2) | 1;
3060 } else {
3061 tabl = (1 << 2) | 3;
3062 tabr = (3 << 2) | 2;
3063 }
3064 break;
3065 default:
3066 abort();
3067 }
3068
3069 lo1 = tcg_temp_new();
3070 lo2 = tcg_temp_new();
3071 tcg_gen_andi_tl(lo1, s1, imask);
3072 tcg_gen_andi_tl(lo2, s2, imask);
3073 tcg_gen_shli_tl(lo1, lo1, shift);
3074 tcg_gen_shli_tl(lo2, lo2, shift);
3075
3076 t1 = tcg_const_tl(tabl);
3077 t2 = tcg_const_tl(tabr);
3078 tcg_gen_shr_tl(lo1, t1, lo1);
3079 tcg_gen_shr_tl(lo2, t2, lo2);
3080 tcg_gen_andi_tl(dst, lo1, omask);
3081 tcg_gen_andi_tl(lo2, lo2, omask);
3082
3083 amask = -8;
3084 if (AM_CHECK(dc)) {
3085 amask &= 0xffffffffULL;
3086 }
3087 tcg_gen_andi_tl(s1, s1, amask);
3088 tcg_gen_andi_tl(s2, s2, amask);
3089
3090 /* We want to compute
3091 dst = (s1 == s2 ? lo1 : lo1 & lo2).
3092 We've already done dst = lo1, so this reduces to
3093 dst &= (s1 == s2 ? -1 : lo2)
3094 Which we perform by
3095 lo2 |= -(s1 == s2)
3096 dst &= lo2
3097 */
3098 tcg_gen_setcond_tl(TCG_COND_EQ, t1, s1, s2);
3099 tcg_gen_neg_tl(t1, t1);
3100 tcg_gen_or_tl(lo2, lo2, t1);
3101 tcg_gen_and_tl(dst, dst, lo2);
3102
3103 tcg_temp_free(lo1);
3104 tcg_temp_free(lo2);
3105 tcg_temp_free(t1);
3106 tcg_temp_free(t2);
3107}
add545ab
RH		 3108
3109static void gen_alignaddr(TCGv dst, TCGv s1, TCGv s2, bool left)
3110{
3111 TCGv tmp = tcg_temp_new();
3112
3113 tcg_gen_add_tl(tmp, s1, s2);
3114 tcg_gen_andi_tl(dst, tmp, -8);
3115 if (left) {
3116 tcg_gen_neg_tl(tmp, tmp);
3117 }
3118 tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, tmp, 0, 3);
3119
3120 tcg_temp_free(tmp);
3121}
50c796f9
RH		 3122
3123static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2)
3124{
3125 TCGv t1, t2, shift;
3126
3127 t1 = tcg_temp_new();
3128 t2 = tcg_temp_new();
3129 shift = tcg_temp_new();
3130
3131 tcg_gen_andi_tl(shift, gsr, 7);
3132 tcg_gen_shli_tl(shift, shift, 3);
3133 tcg_gen_shl_tl(t1, s1, shift);
3134
3135 /* A shift of 64 does not produce 0 in TCG. Divide this into a
3136 shift of (up to 63) followed by a constant shift of 1. */
3137 tcg_gen_xori_tl(shift, shift, 63);
3138 tcg_gen_shr_tl(t2, s2, shift);
3139 tcg_gen_shri_tl(t2, t2, 1);
3140
3141 tcg_gen_or_tl(dst, t1, t2);
3142
3143 tcg_temp_free(t1);
3144 tcg_temp_free(t2);
3145 tcg_temp_free(shift);
3146}
8194f35a
IK		 3147#endif
3148
64a88d5d 3149#define CHECK_IU_FEATURE(dc, FEATURE) \
5578ceab 3150 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
64a88d5d
BS		 3151 goto illegal_insn;
3152#define CHECK_FPU_FEATURE(dc, FEATURE) \
5578ceab 3153 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
64a88d5d
BS		 3154 goto nfpu_insn;
3155
0bee699e 3156/* before an instruction, dc->pc must be static */
0184e266 3157static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
cf495bcf 3158{
0184e266 3159 unsigned int opc, rs1, rs2, rd;
a4273524 3160 TCGv cpu_src1, cpu_src2;
208ae657 3161 TCGv_i32 cpu_src1_32, cpu_src2_32, cpu_dst_32;
96eda024 3162 TCGv_i64 cpu_src1_64, cpu_src2_64, cpu_dst_64;
67526b20 3163 target_long simm;
7a3f1944 3164
cf495bcf 3165 opc = GET_FIELD(insn, 0, 1);
cf495bcf 3166 rd = GET_FIELD(insn, 2, 6);
6ae20372 3167
cf495bcf 3168 switch (opc) {
0f8a249a
BS		 3169 case 0: /* branches/sethi */
3170 {
3171 unsigned int xop = GET_FIELD(insn, 7, 9);
3172 int32_t target;
3173 switch (xop) {
3475187d 3174#ifdef TARGET_SPARC64
0f8a249a
BS		 3175 case 0x1: /* V9 BPcc */
3176 {
3177 int cc;
3178
3179 target = GET_FIELD_SP(insn, 0, 18);
86f1f2ae 3180 target = sign_extend(target, 19);
0f8a249a
BS		 3181 target <<= 2;
3182 cc = GET_FIELD_SP(insn, 20, 21);
3183 if (cc == 0)
d4a288ef 3184 do_branch(dc, target, insn, 0);
0f8a249a 3185 else if (cc == 2)
d4a288ef 3186 do_branch(dc, target, insn, 1);
0f8a249a
BS		 3187 else
3188 goto illegal_insn;
3189 goto jmp_insn;
3190 }
3191 case 0x3: /* V9 BPr */
3192 {
3193 target = GET_FIELD_SP(insn, 0, 13) |
13846e70 3194 (GET_FIELD_SP(insn, 20, 21) << 14);
0f8a249a
BS		 3195 target = sign_extend(target, 16);
3196 target <<= 2;
9d1d4e34 3197 cpu_src1 = get_src1(dc, insn);
d4a288ef 3198 do_branch_reg(dc, target, insn, cpu_src1);
0f8a249a
BS		 3199 goto jmp_insn;
3200 }
3201 case 0x5: /* V9 FBPcc */
3202 {
3203 int cc = GET_FIELD_SP(insn, 20, 21);
5b12f1e8 3204 if (gen_trap_ifnofpu(dc)) {
a80dde08 3205 goto jmp_insn;
5b12f1e8 3206 }
0f8a249a
BS		 3207 target = GET_FIELD_SP(insn, 0, 18);
3208 target = sign_extend(target, 19);
3209 target <<= 2;
d4a288ef 3210 do_fbranch(dc, target, insn, cc);
0f8a249a
BS		 3211 goto jmp_insn;
3212 }
a4d17f19 3213#else
0f8a249a
BS		 3214 case 0x7: /* CBN+x */
3215 {
3216 goto ncp_insn;
3217 }
3218#endif
3219 case 0x2: /* BN+x */
3220 {
3221 target = GET_FIELD(insn, 10, 31);
3222 target = sign_extend(target, 22);
3223 target <<= 2;
d4a288ef 3224 do_branch(dc, target, insn, 0);
0f8a249a
BS		 3225 goto jmp_insn;
3226 }
3227 case 0x6: /* FBN+x */
3228 {
5b12f1e8 3229 if (gen_trap_ifnofpu(dc)) {
a80dde08 3230 goto jmp_insn;
5b12f1e8 3231 }
0f8a249a
BS		 3232 target = GET_FIELD(insn, 10, 31);
3233 target = sign_extend(target, 22);
3234 target <<= 2;
d4a288ef 3235 do_fbranch(dc, target, insn, 0);
0f8a249a
BS		 3236 goto jmp_insn;
3237 }
3238 case 0x4: /* SETHI */
97ea2859
RH		 3239 /* Special-case %g0 because that's the canonical nop. */
3240 if (rd) {
0f8a249a 3241 uint32_t value = GET_FIELD(insn, 10, 31);
97ea2859
RH		 3242 TCGv t = gen_dest_gpr(dc, rd);
3243 tcg_gen_movi_tl(t, value << 10);
3244 gen_store_gpr(dc, rd, t);
0f8a249a 3245 }
0f8a249a
BS		 3246 break;
3247 case 0x0: /* UNIMPL */
3248 default:
3475187d 3249 goto illegal_insn;
0f8a249a
BS		 3250 }
3251 break;
3252 }
3253 break;
dc1a6971
BS		 3254 case 1: /*CALL*/
3255 {
0f8a249a 3256 target_long target = GET_FIELDs(insn, 2, 31) << 2;
97ea2859 3257 TCGv o7 = gen_dest_gpr(dc, 15);
cf495bcf 3258
97ea2859
RH		 3259 tcg_gen_movi_tl(o7, dc->pc);
3260 gen_store_gpr(dc, 15, o7);
0f8a249a 3261 target += dc->pc;
13a6dd00 3262 gen_mov_pc_npc(dc);
22036a49
AT		 3263#ifdef TARGET_SPARC64
3264 if (unlikely(AM_CHECK(dc))) {
3265 target &= 0xffffffffULL;
3266 }
3267#endif
0f8a249a
BS		 3268 dc->npc = target;
3269 }
3270 goto jmp_insn;
3271 case 2: /* FPU & Logical Operations */
3272 {
3273 unsigned int xop = GET_FIELD(insn, 7, 12);
e7d51b34 3274 TCGv cpu_dst = get_temp_tl(dc);
de9e9d9f 3275 TCGv cpu_tmp0;
5793f2a4 3276
0f8a249a 3277 if (xop == 0x3a) { /* generate trap */
bd49ed41
RH		 3278 int cond = GET_FIELD(insn, 3, 6);
3279 TCGv_i32 trap;
42a268c2
RH		 3280 TCGLabel *l1 = NULL;
3281 int mask;
3475187d 3282
bd49ed41
RH		 3283 if (cond == 0) {
3284 /* Trap never. */
3285 break;
cf495bcf 3286 }
b04d9890 3287
bd49ed41 3288 save_state(dc);
b04d9890 3289
bd49ed41
RH		 3290 if (cond != 8) {
3291 /* Conditional trap. */
3a49e759 3292 DisasCompare cmp;
3475187d 3293#ifdef TARGET_SPARC64
0f8a249a
BS		 3294 /* V9 icc/xcc */
3295 int cc = GET_FIELD_SP(insn, 11, 12);
3a49e759
RH		 3296 if (cc == 0) {
3297 gen_compare(&cmp, 0, cond, dc);
3298 } else if (cc == 2) {
3299 gen_compare(&cmp, 1, cond, dc);
3300 } else {
0f8a249a 3301 goto illegal_insn;
3a49e759 3302 }
3475187d 3303#else
3a49e759 3304 gen_compare(&cmp, 0, cond, dc);
3475187d 3305#endif
b158a785 3306 l1 = gen_new_label();
3a49e759
RH		 3307 tcg_gen_brcond_tl(tcg_invert_cond(cmp.cond),
3308 cmp.c1, cmp.c2, l1);
3309 free_compare(&cmp);
bd49ed41 3310 }
b158a785 3311
bd49ed41
RH		 3312 mask = ((dc->def->features & CPU_FEATURE_HYPV) && supervisor(dc)
3313 ? UA2005_HTRAP_MASK : V8_TRAP_MASK);
3314
3315 /* Don't use the normal temporaries, as they may well have
3316 gone out of scope with the branch above. While we're
3317 doing that we might as well pre-truncate to 32-bit. */
3318 trap = tcg_temp_new_i32();
3319
3320 rs1 = GET_FIELD_SP(insn, 14, 18);
3321 if (IS_IMM) {
5c65df36 3322 rs2 = GET_FIELD_SP(insn, 0, 7);
bd49ed41
RH		 3323 if (rs1 == 0) {
3324 tcg_gen_movi_i32(trap, (rs2 & mask) + TT_TRAP);
3325 /* Signal that the trap value is fully constant. */
3326 mask = 0;
3327 } else {
97ea2859 3328 TCGv t1 = gen_load_gpr(dc, rs1);
bd49ed41 3329 tcg_gen_trunc_tl_i32(trap, t1);
bd49ed41
RH		 3330 tcg_gen_addi_i32(trap, trap, rs2);
3331 }
3332 } else {
97ea2859 3333 TCGv t1, t2;
bd49ed41 3334 rs2 = GET_FIELD_SP(insn, 0, 4);
97ea2859
RH		 3335 t1 = gen_load_gpr(dc, rs1);
3336 t2 = gen_load_gpr(dc, rs2);
bd49ed41
RH		 3337 tcg_gen_add_tl(t1, t1, t2);
3338 tcg_gen_trunc_tl_i32(trap, t1);
bd49ed41
RH		 3339 }
3340 if (mask != 0) {
3341 tcg_gen_andi_i32(trap, trap, mask);
3342 tcg_gen_addi_i32(trap, trap, TT_TRAP);
3343 }
3344
3345 gen_helper_raise_exception(cpu_env, trap);
3346 tcg_temp_free_i32(trap);
b158a785 3347
fe1755cb
RH		 3348 if (cond == 8) {
3349 /* An unconditional trap ends the TB. */
3350 dc->is_br = 1;
3351 goto jmp_insn;
3352 } else {
3353 /* A conditional trap falls through to the next insn. */
b158a785 3354 gen_set_label(l1);
fe1755cb 3355 break;
cf495bcf
FB		 3356 }
3357 } else if (xop == 0x28) {
3358 rs1 = GET_FIELD(insn, 13, 17);
3359 switch(rs1) {
3360 case 0: /* rdy */
65fe7b09
BS		 3361#ifndef TARGET_SPARC64
3362 case 0x01 ... 0x0e: /* undefined in the SPARCv8
3363 manual, rdy on the microSPARC
3364 II */
3365 case 0x0f: /* stbar in the SPARCv8 manual,
3366 rdy on the microSPARC II */
3367 case 0x10 ... 0x1f: /* implementation-dependent in the
3368 SPARCv8 manual, rdy on the
3369 microSPARC II */
4a2ba232
FC		 3370 /* Read Asr17 */
3371 if (rs1 == 0x11 && dc->def->features & CPU_FEATURE_ASR17) {
97ea2859 3372 TCGv t = gen_dest_gpr(dc, rd);
4a2ba232 3373 /* Read Asr17 for a Leon3 monoprocessor */
97ea2859
RH		 3374 tcg_gen_movi_tl(t, (1 << 8) | (dc->def->nwindows - 1));
3375 gen_store_gpr(dc, rd, t);
4a2ba232
FC		 3376 break;
3377 }
65fe7b09 3378#endif
97ea2859 3379 gen_store_gpr(dc, rd, cpu_y);
cf495bcf 3380 break;
3475187d 3381#ifdef TARGET_SPARC64
0f8a249a 3382 case 0x2: /* V9 rdccr */
20132b96 3383 update_psr(dc);
063c3675 3384 gen_helper_rdccr(cpu_dst, cpu_env);
97ea2859 3385 gen_store_gpr(dc, rd, cpu_dst);
3475187d 3386 break;
0f8a249a 3387 case 0x3: /* V9 rdasi */
a6d567e5 3388 tcg_gen_movi_tl(cpu_dst, dc->asi);
97ea2859 3389 gen_store_gpr(dc, rd, cpu_dst);
3475187d 3390 break;
0f8a249a 3391 case 0x4: /* V9 rdtick */
ccd4a219 3392 {
a7812ae4 3393 TCGv_ptr r_tickptr;
c9a46442 3394 TCGv_i32 r_const;
ccd4a219 3395
a7812ae4 3396 r_tickptr = tcg_temp_new_ptr();
c9a46442 3397 r_const = tcg_const_i32(dc->mem_idx);
ccd4a219 3398 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3399 offsetof(CPUSPARCState, tick));
c9a46442
MCA		 3400 gen_helper_tick_get_count(cpu_dst, cpu_env, r_tickptr,
3401 r_const);
a7812ae4 3402 tcg_temp_free_ptr(r_tickptr);
c9a46442 3403 tcg_temp_free_i32(r_const);
97ea2859 3404 gen_store_gpr(dc, rd, cpu_dst);
ccd4a219 3405 }
3475187d 3406 break;
0f8a249a 3407 case 0x5: /* V9 rdpc */
2ea815ca 3408 {
97ea2859 3409 TCGv t = gen_dest_gpr(dc, rd);
22036a49 3410 if (unlikely(AM_CHECK(dc))) {
97ea2859 3411 tcg_gen_movi_tl(t, dc->pc & 0xffffffffULL);
22036a49 3412 } else {
97ea2859 3413 tcg_gen_movi_tl(t, dc->pc);
22036a49 3414 }
97ea2859 3415 gen_store_gpr(dc, rd, t);
2ea815ca 3416 }
0f8a249a
BS		 3417 break;
3418 case 0x6: /* V9 rdfprs */
255e1fcb 3419 tcg_gen_ext_i32_tl(cpu_dst, cpu_fprs);
97ea2859 3420 gen_store_gpr(dc, rd, cpu_dst);
3475187d 3421 break;
65fe7b09
BS		 3422 case 0xf: /* V9 membar */
3423 break; /* no effect */
0f8a249a 3424 case 0x13: /* Graphics Status */
5b12f1e8 3425 if (gen_trap_ifnofpu(dc)) {
725cb90b 3426 goto jmp_insn;
5b12f1e8 3427 }
97ea2859 3428 gen_store_gpr(dc, rd, cpu_gsr);
725cb90b 3429 break;
9d926598 3430 case 0x16: /* Softint */
e86ceb0d
RH		 3431 tcg_gen_ld32s_tl(cpu_dst, cpu_env,
3432 offsetof(CPUSPARCState, softint));
97ea2859 3433 gen_store_gpr(dc, rd, cpu_dst);
9d926598 3434 break;
0f8a249a 3435 case 0x17: /* Tick compare */
97ea2859 3436 gen_store_gpr(dc, rd, cpu_tick_cmpr);
83469015 3437 break;
0f8a249a 3438 case 0x18: /* System tick */
ccd4a219 3439 {
a7812ae4 3440 TCGv_ptr r_tickptr;
c9a46442 3441 TCGv_i32 r_const;
ccd4a219 3442
a7812ae4 3443 r_tickptr = tcg_temp_new_ptr();
c9a46442 3444 r_const = tcg_const_i32(dc->mem_idx);
ccd4a219 3445 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3446 offsetof(CPUSPARCState, stick));
c9a46442
MCA		 3447 gen_helper_tick_get_count(cpu_dst, cpu_env, r_tickptr,
3448 r_const);
a7812ae4 3449 tcg_temp_free_ptr(r_tickptr);
c9a46442 3450 tcg_temp_free_i32(r_const);
97ea2859 3451 gen_store_gpr(dc, rd, cpu_dst);
ccd4a219 3452 }
83469015 3453 break;
0f8a249a 3454 case 0x19: /* System tick compare */
97ea2859 3455 gen_store_gpr(dc, rd, cpu_stick_cmpr);
83469015 3456 break;
b8e31b3c
AT		 3457 case 0x1a: /* UltraSPARC-T1 Strand status */
3458 /* XXX HYPV check maybe not enough, UA2005 & UA2007 describe
3459 * this ASR as impl. dep
3460 */
3461 CHECK_IU_FEATURE(dc, HYPV);
3462 {
3463 TCGv t = gen_dest_gpr(dc, rd);
3464 tcg_gen_movi_tl(t, 1UL);
3465 gen_store_gpr(dc, rd, t);
3466 }
3467 break;
0f8a249a
BS		 3468 case 0x10: /* Performance Control */
3469 case 0x11: /* Performance Instrumentation Counter */
3470 case 0x12: /* Dispatch Control */
3471 case 0x14: /* Softint set, WO */
3472 case 0x15: /* Softint clear, WO */
3475187d
FB		 3473#endif
3474 default:
cf495bcf
FB		 3475 goto illegal_insn;
3476 }
e8af50a3 3477#if !defined(CONFIG_USER_ONLY)
e9ebed4d 3478 } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
3475187d 3479#ifndef TARGET_SPARC64
20132b96 3480 if (!supervisor(dc)) {
0f8a249a 3481 goto priv_insn;
20132b96
RH		 3482 }
3483 update_psr(dc);
063c3675 3484 gen_helper_rdpsr(cpu_dst, cpu_env);
e9ebed4d 3485#else
fb79ceb9 3486 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 3487 if (!hypervisor(dc))
3488 goto priv_insn;
3489 rs1 = GET_FIELD(insn, 13, 17);
3490 switch (rs1) {
3491 case 0: // hpstate
f7f17ef7
AT		 3492 tcg_gen_ld_i64(cpu_dst, cpu_env,
3493 offsetof(CPUSPARCState, hpstate));
e9ebed4d
BS		 3494 break;
3495 case 1: // htstate
3496 // gen_op_rdhtstate();
3497 break;
3498 case 3: // hintp
255e1fcb 3499 tcg_gen_mov_tl(cpu_dst, cpu_hintp);
e9ebed4d
BS		 3500 break;
3501 case 5: // htba
255e1fcb 3502 tcg_gen_mov_tl(cpu_dst, cpu_htba);
e9ebed4d
BS		 3503 break;
3504 case 6: // hver
255e1fcb 3505 tcg_gen_mov_tl(cpu_dst, cpu_hver);
e9ebed4d
BS		 3506 break;
3507 case 31: // hstick_cmpr
255e1fcb 3508 tcg_gen_mov_tl(cpu_dst, cpu_hstick_cmpr);
e9ebed4d
BS		 3509 break;
3510 default:
3511 goto illegal_insn;
3512 }
3513#endif
97ea2859 3514 gen_store_gpr(dc, rd, cpu_dst);
e8af50a3 3515 break;
3475187d 3516 } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
de9e9d9f 3517 if (!supervisor(dc)) {
0f8a249a 3518 goto priv_insn;
de9e9d9f
RH		 3519 }
3520 cpu_tmp0 = get_temp_tl(dc);
3475187d
FB		 3521#ifdef TARGET_SPARC64
3522 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 3523 switch (rs1) {
3524 case 0: // tpc
375ee38b 3525 {
a7812ae4 3526 TCGv_ptr r_tsptr;
375ee38b 3527
a7812ae4 3528 r_tsptr = tcg_temp_new_ptr();
8194f35a 3529 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
a7812ae4 3530 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
375ee38b 3531 offsetof(trap_state, tpc));
a7812ae4 3532 tcg_temp_free_ptr(r_tsptr);
375ee38b 3533 }
0f8a249a
BS		 3534 break;
3535 case 1: // tnpc
375ee38b 3536 {
a7812ae4 3537 TCGv_ptr r_tsptr;
375ee38b 3538
a7812ae4 3539 r_tsptr = tcg_temp_new_ptr();
8194f35a 3540 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 3541 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
375ee38b 3542 offsetof(trap_state, tnpc));
a7812ae4 3543 tcg_temp_free_ptr(r_tsptr);
375ee38b 3544 }
0f8a249a
BS		 3545 break;
3546 case 2: // tstate
375ee38b 3547 {
a7812ae4 3548 TCGv_ptr r_tsptr;
375ee38b 3549
a7812ae4 3550 r_tsptr = tcg_temp_new_ptr();
8194f35a 3551 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 3552 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
375ee38b 3553 offsetof(trap_state, tstate));
a7812ae4 3554 tcg_temp_free_ptr(r_tsptr);
375ee38b 3555 }
0f8a249a
BS		 3556 break;
3557 case 3: // tt
375ee38b 3558 {
45778f99 3559 TCGv_ptr r_tsptr = tcg_temp_new_ptr();
375ee38b 3560
8194f35a 3561 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
45778f99
RH		 3562 tcg_gen_ld32s_tl(cpu_tmp0, r_tsptr,
3563 offsetof(trap_state, tt));
a7812ae4 3564 tcg_temp_free_ptr(r_tsptr);
375ee38b 3565 }
0f8a249a
BS		 3566 break;
3567 case 4: // tick
ccd4a219 3568 {
a7812ae4 3569 TCGv_ptr r_tickptr;
c9a46442 3570 TCGv_i32 r_const;
ccd4a219 3571
a7812ae4 3572 r_tickptr = tcg_temp_new_ptr();
c9a46442 3573 r_const = tcg_const_i32(dc->mem_idx);
ccd4a219 3574 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3575 offsetof(CPUSPARCState, tick));
c9a46442
MCA		 3576 gen_helper_tick_get_count(cpu_tmp0, cpu_env,
3577 r_tickptr, r_const);
a7812ae4 3578 tcg_temp_free_ptr(r_tickptr);
c9a46442 3579 tcg_temp_free_i32(r_const);
ccd4a219 3580 }
0f8a249a
BS		 3581 break;
3582 case 5: // tba
255e1fcb 3583 tcg_gen_mov_tl(cpu_tmp0, cpu_tbr);
0f8a249a
BS		 3584 break;
3585 case 6: // pstate
45778f99
RH		 3586 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3587 offsetof(CPUSPARCState, pstate));
0f8a249a
BS		 3588 break;
3589 case 7: // tl
45778f99
RH		 3590 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3591 offsetof(CPUSPARCState, tl));
0f8a249a
BS		 3592 break;
3593 case 8: // pil
45778f99
RH		 3594 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3595 offsetof(CPUSPARCState, psrpil));
0f8a249a
BS		 3596 break;
3597 case 9: // cwp
063c3675 3598 gen_helper_rdcwp(cpu_tmp0, cpu_env);
0f8a249a
BS		 3599 break;
3600 case 10: // cansave
45778f99
RH		 3601 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3602 offsetof(CPUSPARCState, cansave));
0f8a249a
BS		 3603 break;
3604 case 11: // canrestore
45778f99
RH		 3605 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3606 offsetof(CPUSPARCState, canrestore));
0f8a249a
BS		 3607 break;
3608 case 12: // cleanwin
45778f99
RH		 3609 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3610 offsetof(CPUSPARCState, cleanwin));
0f8a249a
BS		 3611 break;
3612 case 13: // otherwin
45778f99
RH		 3613 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3614 offsetof(CPUSPARCState, otherwin));
0f8a249a
BS		 3615 break;
3616 case 14: // wstate
45778f99
RH		 3617 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3618 offsetof(CPUSPARCState, wstate));
0f8a249a 3619 break;
e9ebed4d 3620 case 16: // UA2005 gl
fb79ceb9 3621 CHECK_IU_FEATURE(dc, GL);
45778f99
RH		 3622 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3623 offsetof(CPUSPARCState, gl));
e9ebed4d
BS		 3624 break;
3625 case 26: // UA2005 strand status
fb79ceb9 3626 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 3627 if (!hypervisor(dc))
3628 goto priv_insn;
527067d8 3629 tcg_gen_mov_tl(cpu_tmp0, cpu_ssr);
e9ebed4d 3630 break;
0f8a249a 3631 case 31: // ver
255e1fcb 3632 tcg_gen_mov_tl(cpu_tmp0, cpu_ver);
0f8a249a
BS		 3633 break;
3634 case 15: // fq
3635 default:
3636 goto illegal_insn;
3637 }
3475187d 3638#else
255e1fcb 3639 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_wim);
3475187d 3640#endif
97ea2859 3641 gen_store_gpr(dc, rd, cpu_tmp0);
e8af50a3 3642 break;
3475187d
FB		 3643 } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
3644#ifdef TARGET_SPARC64
063c3675 3645 gen_helper_flushw(cpu_env);
3475187d 3646#else
0f8a249a
BS		 3647 if (!supervisor(dc))
3648 goto priv_insn;
97ea2859 3649 gen_store_gpr(dc, rd, cpu_tbr);
3475187d 3650#endif
e8af50a3
FB		 3651 break;
3652#endif
0f8a249a 3653 } else if (xop == 0x34) { /* FPU Operations */
5b12f1e8 3654 if (gen_trap_ifnofpu(dc)) {
a80dde08 3655 goto jmp_insn;
5b12f1e8 3656 }
0f8a249a 3657 gen_op_clear_ieee_excp_and_FTT();
e8af50a3 3658 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 3659 rs2 = GET_FIELD(insn, 27, 31);
3660 xop = GET_FIELD(insn, 18, 26);
02c79d78 3661
0f8a249a 3662 switch (xop) {
dc1a6971 3663 case 0x1: /* fmovs */
208ae657
RH		 3664 cpu_src1_32 = gen_load_fpr_F(dc, rs2);
3665 gen_store_fpr_F(dc, rd, cpu_src1_32);
dc1a6971
BS		 3666 break;
3667 case 0x5: /* fnegs */
61f17f6e 3668 gen_ne_fop_FF(dc, rd, rs2, gen_helper_fnegs);
dc1a6971
BS		 3669 break;
3670 case 0x9: /* fabss */
61f17f6e 3671 gen_ne_fop_FF(dc, rd, rs2, gen_helper_fabss);
dc1a6971
BS		 3672 break;
3673 case 0x29: /* fsqrts */
3674 CHECK_FPU_FEATURE(dc, FSQRT);
61f17f6e 3675 gen_fop_FF(dc, rd, rs2, gen_helper_fsqrts);
dc1a6971
BS		 3676 break;
3677 case 0x2a: /* fsqrtd */
3678 CHECK_FPU_FEATURE(dc, FSQRT);
61f17f6e 3679 gen_fop_DD(dc, rd, rs2, gen_helper_fsqrtd);
dc1a6971
BS		 3680 break;
3681 case 0x2b: /* fsqrtq */
3682 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3683 gen_fop_QQ(dc, rd, rs2, gen_helper_fsqrtq);
dc1a6971
BS		 3684 break;
3685 case 0x41: /* fadds */
61f17f6e 3686 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fadds);
dc1a6971
BS		 3687 break;
3688 case 0x42: /* faddd */
61f17f6e 3689 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_faddd);
dc1a6971
BS		 3690 break;
3691 case 0x43: /* faddq */
3692 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3693 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_faddq);
dc1a6971
BS		 3694 break;
3695 case 0x45: /* fsubs */
61f17f6e 3696 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fsubs);
dc1a6971
BS		 3697 break;
3698 case 0x46: /* fsubd */
61f17f6e 3699 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fsubd);
dc1a6971
BS		 3700 break;
3701 case 0x47: /* fsubq */
3702 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3703 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fsubq);
dc1a6971
BS		 3704 break;
3705 case 0x49: /* fmuls */
3706 CHECK_FPU_FEATURE(dc, FMUL);
61f17f6e 3707 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fmuls);
dc1a6971
BS		 3708 break;
3709 case 0x4a: /* fmuld */
3710 CHECK_FPU_FEATURE(dc, FMUL);
61f17f6e 3711 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld);
dc1a6971
BS		 3712 break;
3713 case 0x4b: /* fmulq */
3714 CHECK_FPU_FEATURE(dc, FLOAT128);
3715 CHECK_FPU_FEATURE(dc, FMUL);
61f17f6e 3716 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fmulq);
dc1a6971
BS		 3717 break;
3718 case 0x4d: /* fdivs */
61f17f6e 3719 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fdivs);
dc1a6971
BS		 3720 break;
3721 case 0x4e: /* fdivd */
61f17f6e 3722 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fdivd);
dc1a6971
BS		 3723 break;
3724 case 0x4f: /* fdivq */
3725 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3726 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fdivq);
dc1a6971
BS		 3727 break;
3728 case 0x69: /* fsmuld */
3729 CHECK_FPU_FEATURE(dc, FSMULD);
61f17f6e 3730 gen_fop_DFF(dc, rd, rs1, rs2, gen_helper_fsmuld);
dc1a6971
BS		 3731 break;
3732 case 0x6e: /* fdmulq */
3733 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3734 gen_fop_QDD(dc, rd, rs1, rs2, gen_helper_fdmulq);
dc1a6971
BS		 3735 break;
3736 case 0xc4: /* fitos */
61f17f6e 3737 gen_fop_FF(dc, rd, rs2, gen_helper_fitos);
dc1a6971
BS		 3738 break;
3739 case 0xc6: /* fdtos */
61f17f6e 3740 gen_fop_FD(dc, rd, rs2, gen_helper_fdtos);
dc1a6971
BS		 3741 break;
3742 case 0xc7: /* fqtos */
3743 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3744 gen_fop_FQ(dc, rd, rs2, gen_helper_fqtos);
dc1a6971
BS		 3745 break;
3746 case 0xc8: /* fitod */
61f17f6e 3747 gen_ne_fop_DF(dc, rd, rs2, gen_helper_fitod);
dc1a6971
BS		 3748 break;
3749 case 0xc9: /* fstod */
61f17f6e 3750 gen_ne_fop_DF(dc, rd, rs2, gen_helper_fstod);
dc1a6971
BS		 3751 break;
3752 case 0xcb: /* fqtod */
3753 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3754 gen_fop_DQ(dc, rd, rs2, gen_helper_fqtod);
dc1a6971
BS		 3755 break;
3756 case 0xcc: /* fitoq */
3757 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3758 gen_ne_fop_QF(dc, rd, rs2, gen_helper_fitoq);
dc1a6971
BS		 3759 break;
3760 case 0xcd: /* fstoq */
3761 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3762 gen_ne_fop_QF(dc, rd, rs2, gen_helper_fstoq);
dc1a6971
BS		 3763 break;
3764 case 0xce: /* fdtoq */
3765 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3766 gen_ne_fop_QD(dc, rd, rs2, gen_helper_fdtoq);
dc1a6971
BS		 3767 break;
3768 case 0xd1: /* fstoi */
61f17f6e 3769 gen_fop_FF(dc, rd, rs2, gen_helper_fstoi);
dc1a6971
BS		 3770 break;
3771 case 0xd2: /* fdtoi */
61f17f6e 3772 gen_fop_FD(dc, rd, rs2, gen_helper_fdtoi);
dc1a6971
BS		 3773 break;
3774 case 0xd3: /* fqtoi */
3775 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3776 gen_fop_FQ(dc, rd, rs2, gen_helper_fqtoi);
dc1a6971 3777 break;
3475187d 3778#ifdef TARGET_SPARC64
dc1a6971 3779 case 0x2: /* V9 fmovd */
96eda024
RH		 3780 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
3781 gen_store_fpr_D(dc, rd, cpu_src1_64);
dc1a6971
BS		 3782 break;
3783 case 0x3: /* V9 fmovq */
3784 CHECK_FPU_FEATURE(dc, FLOAT128);
f9c816c0 3785 gen_move_Q(dc, rd, rs2);
dc1a6971
BS		 3786 break;
3787 case 0x6: /* V9 fnegd */
61f17f6e 3788 gen_ne_fop_DD(dc, rd, rs2, gen_helper_fnegd);
dc1a6971
BS		 3789 break;
3790 case 0x7: /* V9 fnegq */
3791 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3792 gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fnegq);
dc1a6971
BS		 3793 break;
3794 case 0xa: /* V9 fabsd */
61f17f6e 3795 gen_ne_fop_DD(dc, rd, rs2, gen_helper_fabsd);
dc1a6971
BS		 3796 break;
3797 case 0xb: /* V9 fabsq */
3798 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3799 gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fabsq);
dc1a6971
BS		 3800 break;
3801 case 0x81: /* V9 fstox */
61f17f6e 3802 gen_fop_DF(dc, rd, rs2, gen_helper_fstox);
dc1a6971
BS		 3803 break;
3804 case 0x82: /* V9 fdtox */
61f17f6e 3805 gen_fop_DD(dc, rd, rs2, gen_helper_fdtox);
dc1a6971
BS		 3806 break;
3807 case 0x83: /* V9 fqtox */
3808 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3809 gen_fop_DQ(dc, rd, rs2, gen_helper_fqtox);
dc1a6971
BS		 3810 break;
3811 case 0x84: /* V9 fxtos */
61f17f6e 3812 gen_fop_FD(dc, rd, rs2, gen_helper_fxtos);
dc1a6971
BS		 3813 break;
3814 case 0x88: /* V9 fxtod */
61f17f6e 3815 gen_fop_DD(dc, rd, rs2, gen_helper_fxtod);
dc1a6971
BS		 3816 break;
3817 case 0x8c: /* V9 fxtoq */
3818 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3819 gen_ne_fop_QD(dc, rd, rs2, gen_helper_fxtoq);
dc1a6971 3820 break;
0f8a249a 3821#endif
dc1a6971
BS		 3822 default:
3823 goto illegal_insn;
0f8a249a
BS		 3824 }
3825 } else if (xop == 0x35) { /* FPU Operations */
3475187d 3826#ifdef TARGET_SPARC64
0f8a249a 3827 int cond;
3475187d 3828#endif
5b12f1e8 3829 if (gen_trap_ifnofpu(dc)) {
a80dde08 3830 goto jmp_insn;
5b12f1e8 3831 }
0f8a249a 3832 gen_op_clear_ieee_excp_and_FTT();
cf495bcf 3833 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 3834 rs2 = GET_FIELD(insn, 27, 31);
3835 xop = GET_FIELD(insn, 18, 26);
dcf24905 3836
690995a6
RH		 3837#ifdef TARGET_SPARC64
3838#define FMOVR(sz) \
3839 do { \
3840 DisasCompare cmp; \
e7c8afb9 3841 cond = GET_FIELD_SP(insn, 10, 12); \
9d1d4e34 3842 cpu_src1 = get_src1(dc, insn); \
690995a6
RH		 3843 gen_compare_reg(&cmp, cond, cpu_src1); \
3844 gen_fmov##sz(dc, &cmp, rd, rs2); \
3845 free_compare(&cmp); \
3846 } while (0)
3847
3848 if ((xop & 0x11f) == 0x005) { /* V9 fmovsr */
3849 FMOVR(s);
0f8a249a
BS		 3850 break;
3851 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
690995a6 3852 FMOVR(d);
0f8a249a
BS		 3853 break;
3854 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
64a88d5d 3855 CHECK_FPU_FEATURE(dc, FLOAT128);
690995a6 3856 FMOVR(q);
1f587329 3857 break;
0f8a249a 3858 }
690995a6 3859#undef FMOVR
0f8a249a
BS		 3860#endif
3861 switch (xop) {
3475187d 3862#ifdef TARGET_SPARC64
7e480893
RH		 3863#define FMOVCC(fcc, sz) \
3864 do { \
3865 DisasCompare cmp; \
714547bb 3866 cond = GET_FIELD_SP(insn, 14, 17); \
7e480893
RH		 3867 gen_fcompare(&cmp, fcc, cond); \
3868 gen_fmov##sz(dc, &cmp, rd, rs2); \
3869 free_compare(&cmp); \
3870 } while (0)
3871
0f8a249a 3872 case 0x001: /* V9 fmovscc %fcc0 */
7e480893 3873 FMOVCC(0, s);
0f8a249a
BS		 3874 break;
3875 case 0x002: /* V9 fmovdcc %fcc0 */
7e480893 3876 FMOVCC(0, d);
0f8a249a
BS		 3877 break;
3878 case 0x003: /* V9 fmovqcc %fcc0 */
64a88d5d 3879 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3880 FMOVCC(0, q);
1f587329 3881 break;
0f8a249a 3882 case 0x041: /* V9 fmovscc %fcc1 */
7e480893 3883 FMOVCC(1, s);
0f8a249a
BS		 3884 break;
3885 case 0x042: /* V9 fmovdcc %fcc1 */
7e480893 3886 FMOVCC(1, d);
0f8a249a
BS		 3887 break;
3888 case 0x043: /* V9 fmovqcc %fcc1 */
64a88d5d 3889 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3890 FMOVCC(1, q);
1f587329 3891 break;
0f8a249a 3892 case 0x081: /* V9 fmovscc %fcc2 */
7e480893 3893 FMOVCC(2, s);
0f8a249a
BS		 3894 break;
3895 case 0x082: /* V9 fmovdcc %fcc2 */
7e480893 3896 FMOVCC(2, d);
0f8a249a
BS		 3897 break;
3898 case 0x083: /* V9 fmovqcc %fcc2 */
64a88d5d 3899 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3900 FMOVCC(2, q);
1f587329 3901 break;
0f8a249a 3902 case 0x0c1: /* V9 fmovscc %fcc3 */
7e480893 3903 FMOVCC(3, s);
0f8a249a
BS		 3904 break;
3905 case 0x0c2: /* V9 fmovdcc %fcc3 */
7e480893 3906 FMOVCC(3, d);
0f8a249a
BS		 3907 break;
3908 case 0x0c3: /* V9 fmovqcc %fcc3 */
64a88d5d 3909 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3910 FMOVCC(3, q);
1f587329 3911 break;
7e480893
RH		 3912#undef FMOVCC
3913#define FMOVCC(xcc, sz) \
3914 do { \
3915 DisasCompare cmp; \
714547bb 3916 cond = GET_FIELD_SP(insn, 14, 17); \
7e480893
RH		 3917 gen_compare(&cmp, xcc, cond, dc); \
3918 gen_fmov##sz(dc, &cmp, rd, rs2); \
3919 free_compare(&cmp); \
3920 } while (0)
19f329ad 3921
0f8a249a 3922 case 0x101: /* V9 fmovscc %icc */
7e480893 3923 FMOVCC(0, s);
0f8a249a
BS		 3924 break;
3925 case 0x102: /* V9 fmovdcc %icc */
7e480893 3926 FMOVCC(0, d);
b7d69dc2 3927 break;
0f8a249a 3928 case 0x103: /* V9 fmovqcc %icc */
64a88d5d 3929 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3930 FMOVCC(0, q);
1f587329 3931 break;
0f8a249a 3932 case 0x181: /* V9 fmovscc %xcc */
7e480893 3933 FMOVCC(1, s);
0f8a249a
BS		 3934 break;
3935 case 0x182: /* V9 fmovdcc %xcc */
7e480893 3936 FMOVCC(1, d);
0f8a249a
BS		 3937 break;
3938 case 0x183: /* V9 fmovqcc %xcc */
64a88d5d 3939 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3940 FMOVCC(1, q);
1f587329 3941 break;
7e480893 3942#undef FMOVCC
1f587329
BS		 3943#endif
3944 case 0x51: /* fcmps, V9 %fcc */
208ae657
RH		 3945 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
3946 cpu_src2_32 = gen_load_fpr_F(dc, rs2);
3947 gen_op_fcmps(rd & 3, cpu_src1_32, cpu_src2_32);
0f8a249a 3948 break;
1f587329 3949 case 0x52: /* fcmpd, V9 %fcc */
03fb8cfc
RH		 3950 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
3951 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
3952 gen_op_fcmpd(rd & 3, cpu_src1_64, cpu_src2_64);
0f8a249a 3953 break;
1f587329 3954 case 0x53: /* fcmpq, V9 %fcc */
64a88d5d 3955 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329
BS		 3956 gen_op_load_fpr_QT0(QFPREG(rs1));
3957 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 3958 gen_op_fcmpq(rd & 3);
1f587329 3959 break;
0f8a249a 3960 case 0x55: /* fcmpes, V9 %fcc */
208ae657
RH		 3961 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
3962 cpu_src2_32 = gen_load_fpr_F(dc, rs2);
3963 gen_op_fcmpes(rd & 3, cpu_src1_32, cpu_src2_32);
0f8a249a
BS		 3964 break;
3965 case 0x56: /* fcmped, V9 %fcc */
03fb8cfc
RH		 3966 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
3967 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
3968 gen_op_fcmped(rd & 3, cpu_src1_64, cpu_src2_64);
0f8a249a 3969 break;
1f587329 3970 case 0x57: /* fcmpeq, V9 %fcc */
64a88d5d 3971 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329
BS		 3972 gen_op_load_fpr_QT0(QFPREG(rs1));
3973 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 3974 gen_op_fcmpeq(rd & 3);
1f587329 3975 break;
0f8a249a
BS		 3976 default:
3977 goto illegal_insn;
3978 }
0f8a249a 3979 } else if (xop == 0x2) {
97ea2859 3980 TCGv dst = gen_dest_gpr(dc, rd);
e80cfcfc 3981 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a 3982 if (rs1 == 0) {
97ea2859 3983 /* clr/mov shortcut : or %g0, x, y -> mov x, y */
0f8a249a 3984 if (IS_IMM) { /* immediate */
67526b20 3985 simm = GET_FIELDs(insn, 19, 31);
97ea2859
RH		 3986 tcg_gen_movi_tl(dst, simm);
3987 gen_store_gpr(dc, rd, dst);
0f8a249a
BS		 3988 } else { /* register */
3989 rs2 = GET_FIELD(insn, 27, 31);
97ea2859
RH		 3990 if (rs2 == 0) {
3991 tcg_gen_movi_tl(dst, 0);
3992 gen_store_gpr(dc, rd, dst);
3993 } else {
3994 cpu_src2 = gen_load_gpr(dc, rs2);
3995 gen_store_gpr(dc, rd, cpu_src2);
3996 }
0f8a249a 3997 }
0f8a249a 3998 } else {
9d1d4e34 3999 cpu_src1 = get_src1(dc, insn);
0f8a249a 4000 if (IS_IMM) { /* immediate */
67526b20 4001 simm = GET_FIELDs(insn, 19, 31);
97ea2859
RH		 4002 tcg_gen_ori_tl(dst, cpu_src1, simm);
4003 gen_store_gpr(dc, rd, dst);
0f8a249a 4004 } else { /* register */
0f8a249a 4005 rs2 = GET_FIELD(insn, 27, 31);
97ea2859
RH		 4006 if (rs2 == 0) {
4007 /* mov shortcut: or x, %g0, y -> mov x, y */
4008 gen_store_gpr(dc, rd, cpu_src1);
4009 } else {
4010 cpu_src2 = gen_load_gpr(dc, rs2);
4011 tcg_gen_or_tl(dst, cpu_src1, cpu_src2);
4012 gen_store_gpr(dc, rd, dst);
4013 }
0f8a249a 4014 }
0f8a249a 4015 }
83469015 4016#ifdef TARGET_SPARC64
0f8a249a 4017 } else if (xop == 0x25) { /* sll, V9 sllx */
9d1d4e34 4018 cpu_src1 = get_src1(dc, insn);
0f8a249a 4019 if (IS_IMM) { /* immediate */
67526b20 4020 simm = GET_FIELDs(insn, 20, 31);
1a2fb1c0 4021 if (insn & (1 << 12)) {
67526b20 4022 tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x3f);
1a2fb1c0 4023 } else {
67526b20 4024 tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x1f);
1a2fb1c0 4025 }
0f8a249a 4026 } else { /* register */
83469015 4027 rs2 = GET_FIELD(insn, 27, 31);
97ea2859 4028 cpu_src2 = gen_load_gpr(dc, rs2);
de9e9d9f 4029 cpu_tmp0 = get_temp_tl(dc);
1a2fb1c0 4030 if (insn & (1 << 12)) {
6ae20372 4031 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
1a2fb1c0 4032 } else {
6ae20372 4033 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
1a2fb1c0 4034 }
01b1fa6d 4035 tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0);
83469015 4036 }
97ea2859 4037 gen_store_gpr(dc, rd, cpu_dst);
0f8a249a 4038 } else if (xop == 0x26) { /* srl, V9 srlx */
9d1d4e34 4039 cpu_src1 = get_src1(dc, insn);
0f8a249a 4040 if (IS_IMM) { /* immediate */
67526b20 4041 simm = GET_FIELDs(insn, 20, 31);
1a2fb1c0 4042 if (insn & (1 << 12)) {
67526b20 4043 tcg_gen_shri_i64(cpu_dst, cpu_src1, simm & 0x3f);
1a2fb1c0 4044 } else {
6ae20372 4045 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
67526b20 4046 tcg_gen_shri_i64(cpu_dst, cpu_dst, simm & 0x1f);
1a2fb1c0 4047 }
0f8a249a 4048 } else { /* register */
83469015 4049 rs2 = GET_FIELD(insn, 27, 31);
97ea2859 4050 cpu_src2 = gen_load_gpr(dc, rs2);
de9e9d9f 4051 cpu_tmp0 = get_temp_tl(dc);
1a2fb1c0 4052 if (insn & (1 << 12)) {
6ae20372
BS		 4053 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
4054 tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0);
1a2fb1c0 4055 } else {
6ae20372
BS		 4056 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
4057 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
4058 tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0);
1a2fb1c0 4059 }
83469015 4060 }
97ea2859 4061 gen_store_gpr(dc, rd, cpu_dst);
0f8a249a 4062 } else if (xop == 0x27) { /* sra, V9 srax */
9d1d4e34 4063 cpu_src1 = get_src1(dc, insn);
0f8a249a 4064 if (IS_IMM) { /* immediate */
67526b20 4065 simm = GET_FIELDs(insn, 20, 31);
1a2fb1c0 4066 if (insn & (1 << 12)) {
67526b20 4067 tcg_gen_sari_i64(cpu_dst, cpu_src1, simm & 0x3f);
1a2fb1c0 4068 } else {
97ea2859 4069 tcg_gen_ext32s_i64(cpu_dst, cpu_src1);
67526b20 4070 tcg_gen_sari_i64(cpu_dst, cpu_dst, simm & 0x1f);
1a2fb1c0 4071 }
0f8a249a 4072 } else { /* register */
83469015 4073 rs2 = GET_FIELD(insn, 27, 31);
97ea2859 4074 cpu_src2 = gen_load_gpr(dc, rs2);
de9e9d9f 4075 cpu_tmp0 = get_temp_tl(dc);
1a2fb1c0 4076 if (insn & (1 << 12)) {
6ae20372
BS		 4077 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
4078 tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0);
1a2fb1c0 4079 } else {
6ae20372 4080 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
97ea2859 4081 tcg_gen_ext32s_i64(cpu_dst, cpu_src1);
6ae20372 4082 tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0);
1a2fb1c0 4083 }
83469015 4084 }
97ea2859 4085 gen_store_gpr(dc, rd, cpu_dst);
e80cfcfc 4086#endif
fcc72045 4087 } else if (xop < 0x36) {
cf495bcf 4088 if (xop < 0x20) {
9d1d4e34
RH		 4089 cpu_src1 = get_src1(dc, insn);
4090 cpu_src2 = get_src2(dc, insn);
cf495bcf 4091 switch (xop & ~0x10) {
b89e94af 4092 case 0x0: /* add */
97ea2859
RH		 4093 if (xop & 0x10) {
4094 gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
4095 tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
4096 dc->cc_op = CC_OP_ADD;
41d72852 4097 } else {
97ea2859 4098 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
41d72852 4099 }
cf495bcf 4100 break;
b89e94af 4101 case 0x1: /* and */
97ea2859 4102 tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
41d72852 4103 if (xop & 0x10) {
38482a77
BS		 4104 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4105 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4106 dc->cc_op = CC_OP_LOGIC;
41d72852 4107 }
cf495bcf 4108 break;
b89e94af 4109 case 0x2: /* or */
97ea2859 4110 tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 4111 if (xop & 0x10) {
38482a77
BS		 4112 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4113 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4114 dc->cc_op = CC_OP_LOGIC;
8393617c 4115 }
0f8a249a 4116 break;
b89e94af 4117 case 0x3: /* xor */
97ea2859 4118 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 4119 if (xop & 0x10) {
38482a77
BS		 4120 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4121 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4122 dc->cc_op = CC_OP_LOGIC;
8393617c 4123 }
cf495bcf 4124 break;
b89e94af 4125 case 0x4: /* sub */
97ea2859
RH		 4126 if (xop & 0x10) {
4127 gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
4128 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
4129 dc->cc_op = CC_OP_SUB;
41d72852 4130 } else {
97ea2859 4131 tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
41d72852 4132 }
cf495bcf 4133 break;
b89e94af 4134 case 0x5: /* andn */
97ea2859 4135 tcg_gen_andc_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 4136 if (xop & 0x10) {
38482a77
BS		 4137 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4138 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4139 dc->cc_op = CC_OP_LOGIC;
8393617c 4140 }
cf495bcf 4141 break;
b89e94af 4142 case 0x6: /* orn */
97ea2859 4143 tcg_gen_orc_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 4144 if (xop & 0x10) {
38482a77
BS		 4145 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4146 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4147 dc->cc_op = CC_OP_LOGIC;
8393617c 4148 }
cf495bcf 4149 break;
b89e94af 4150 case 0x7: /* xorn */
97ea2859 4151 tcg_gen_eqv_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 4152 if (xop & 0x10) {
38482a77
BS		 4153 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4154 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4155 dc->cc_op = CC_OP_LOGIC;
8393617c 4156 }
cf495bcf 4157 break;
b89e94af 4158 case 0x8: /* addx, V9 addc */
70c48285
RH		 4159 gen_op_addx_int(dc, cpu_dst, cpu_src1, cpu_src2,
4160 (xop & 0x10));
cf495bcf 4161 break;
ded3ab80 4162#ifdef TARGET_SPARC64
0f8a249a 4163 case 0x9: /* V9 mulx */
97ea2859 4164 tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
ded3ab80
PB		 4165 break;
4166#endif
b89e94af 4167 case 0xa: /* umul */
64a88d5d 4168 CHECK_IU_FEATURE(dc, MUL);
6ae20372 4169 gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
8393617c 4170 if (xop & 0x10) {
38482a77
BS		 4171 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4172 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4173 dc->cc_op = CC_OP_LOGIC;
8393617c 4174 }
cf495bcf 4175 break;
b89e94af 4176 case 0xb: /* smul */
64a88d5d 4177 CHECK_IU_FEATURE(dc, MUL);
6ae20372 4178 gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
8393617c 4179 if (xop & 0x10) {
38482a77
BS		 4180 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4181 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4182 dc->cc_op = CC_OP_LOGIC;
8393617c 4183 }
cf495bcf 4184 break;
b89e94af 4185 case 0xc: /* subx, V9 subc */
70c48285
RH		 4186 gen_op_subx_int(dc, cpu_dst, cpu_src1, cpu_src2,
4187 (xop & 0x10));
cf495bcf 4188 break;
ded3ab80 4189#ifdef TARGET_SPARC64
0f8a249a 4190 case 0xd: /* V9 udivx */
c28ae41e 4191 gen_helper_udivx(cpu_dst, cpu_env, cpu_src1, cpu_src2);
ded3ab80
PB		 4192 break;
4193#endif
b89e94af 4194 case 0xe: /* udiv */
64a88d5d 4195 CHECK_IU_FEATURE(dc, DIV);
8393617c 4196 if (xop & 0x10) {
7a5e4488
BS		 4197 gen_helper_udiv_cc(cpu_dst, cpu_env, cpu_src1,
4198 cpu_src2);
6c78ea32 4199 dc->cc_op = CC_OP_DIV;
0fcec41e 4200 } else {
7a5e4488
BS		 4201 gen_helper_udiv(cpu_dst, cpu_env, cpu_src1,
4202 cpu_src2);
8393617c 4203 }
cf495bcf 4204 break;
b89e94af 4205 case 0xf: /* sdiv */
64a88d5d 4206 CHECK_IU_FEATURE(dc, DIV);
8393617c 4207 if (xop & 0x10) {
7a5e4488
BS		 4208 gen_helper_sdiv_cc(cpu_dst, cpu_env, cpu_src1,
4209 cpu_src2);
6c78ea32 4210 dc->cc_op = CC_OP_DIV;
0fcec41e 4211 } else {
7a5e4488
BS		 4212 gen_helper_sdiv(cpu_dst, cpu_env, cpu_src1,
4213 cpu_src2);
8393617c 4214 }
cf495bcf
FB		 4215 break;
4216 default:
4217 goto illegal_insn;
4218 }
97ea2859 4219 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 4220 } else {
9d1d4e34
RH		 4221 cpu_src1 = get_src1(dc, insn);
4222 cpu_src2 = get_src2(dc, insn);
cf495bcf 4223 switch (xop) {
0f8a249a 4224 case 0x20: /* taddcc */
a2ea4aa9 4225 gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
97ea2859 4226 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92
BS		 4227 tcg_gen_movi_i32(cpu_cc_op, CC_OP_TADD);
4228 dc->cc_op = CC_OP_TADD;
0f8a249a
BS		 4229 break;
4230 case 0x21: /* tsubcc */
a2ea4aa9 4231 gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
97ea2859 4232 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92
BS		 4233 tcg_gen_movi_i32(cpu_cc_op, CC_OP_TSUB);
4234 dc->cc_op = CC_OP_TSUB;
0f8a249a
BS		 4235 break;
4236 case 0x22: /* taddcctv */
a2ea4aa9
RH		 4237 gen_helper_taddcctv(cpu_dst, cpu_env,
4238 cpu_src1, cpu_src2);
97ea2859 4239 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92 4240 dc->cc_op = CC_OP_TADDTV;
0f8a249a
BS		 4241 break;
4242 case 0x23: /* tsubcctv */
a2ea4aa9
RH		 4243 gen_helper_tsubcctv(cpu_dst, cpu_env,
4244 cpu_src1, cpu_src2);
97ea2859 4245 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92 4246 dc->cc_op = CC_OP_TSUBTV;
0f8a249a 4247 break;
cf495bcf 4248 case 0x24: /* mulscc */
20132b96 4249 update_psr(dc);
6ae20372 4250 gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
97ea2859 4251 gen_store_gpr(dc, rd, cpu_dst);
d084469c
BS		 4252 tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
4253 dc->cc_op = CC_OP_ADD;
cf495bcf 4254 break;
83469015 4255#ifndef TARGET_SPARC64
0f8a249a 4256 case 0x25: /* sll */
e35298cd 4257 if (IS_IMM) { /* immediate */
67526b20
BS		 4258 simm = GET_FIELDs(insn, 20, 31);
4259 tcg_gen_shli_tl(cpu_dst, cpu_src1, simm & 0x1f);
e35298cd 4260 } else { /* register */
de9e9d9f 4261 cpu_tmp0 = get_temp_tl(dc);
e35298cd
BS		 4262 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
4263 tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
4264 }
97ea2859 4265 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 4266 break;
83469015 4267 case 0x26: /* srl */
e35298cd 4268 if (IS_IMM) { /* immediate */
67526b20
BS		 4269 simm = GET_FIELDs(insn, 20, 31);
4270 tcg_gen_shri_tl(cpu_dst, cpu_src1, simm & 0x1f);
e35298cd 4271 } else { /* register */
de9e9d9f 4272 cpu_tmp0 = get_temp_tl(dc);
e35298cd
BS		 4273 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
4274 tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
4275 }
97ea2859 4276 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 4277 break;
83469015 4278 case 0x27: /* sra */
e35298cd 4279 if (IS_IMM) { /* immediate */
67526b20
BS		 4280 simm = GET_FIELDs(insn, 20, 31);
4281 tcg_gen_sari_tl(cpu_dst, cpu_src1, simm & 0x1f);
e35298cd 4282 } else { /* register */
de9e9d9f 4283 cpu_tmp0 = get_temp_tl(dc);
e35298cd
BS		 4284 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
4285 tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
4286 }
97ea2859 4287 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 4288 break;
83469015 4289#endif
cf495bcf
FB		 4290 case 0x30:
4291 {
de9e9d9f 4292 cpu_tmp0 = get_temp_tl(dc);
cf495bcf 4293 switch(rd) {
3475187d 4294 case 0: /* wry */
5068cbd9
BS		 4295 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4296 tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
cf495bcf 4297 break;
65fe7b09
BS		 4298#ifndef TARGET_SPARC64
4299 case 0x01 ... 0x0f: /* undefined in the
4300 SPARCv8 manual, nop
4301 on the microSPARC
4302 II */
4303 case 0x10 ... 0x1f: /* implementation-dependent
4304 in the SPARCv8
4305 manual, nop on the
4306 microSPARC II */
d1c36ba7
RH		 4307 if ((rd == 0x13) && (dc->def->features &
4308 CPU_FEATURE_POWERDOWN)) {
4309 /* LEON3 power-down */
1cf892ca 4310 save_state(dc);
d1c36ba7
RH		 4311 gen_helper_power_down(cpu_env);
4312 }
65fe7b09
BS		 4313 break;
4314#else
0f8a249a 4315 case 0x2: /* V9 wrccr */
7b04bd5c
RH		 4316 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4317 gen_helper_wrccr(cpu_env, cpu_tmp0);
8393617c
BS		 4318 tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
4319 dc->cc_op = CC_OP_FLAGS;
0f8a249a
BS		 4320 break;
4321 case 0x3: /* V9 wrasi */
7b04bd5c
RH		 4322 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4323 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xff);
a6d567e5
RH		 4324 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
4325 offsetof(CPUSPARCState, asi));
4326 /* End TB to notice changed ASI. */
4327 save_state(dc);
4328 gen_op_next_insn();
4329 tcg_gen_exit_tb(0);
4330 dc->is_br = 1;
0f8a249a
BS		 4331 break;
4332 case 0x6: /* V9 wrfprs */
7b04bd5c
RH		 4333 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4334 tcg_gen_trunc_tl_i32(cpu_fprs, cpu_tmp0);
f9c816c0 4335 dc->fprs_dirty = 0;
66442b07 4336 save_state(dc);
3299908c 4337 gen_op_next_insn();
57fec1fe 4338 tcg_gen_exit_tb(0);
3299908c 4339 dc->is_br = 1;
0f8a249a
BS		 4340 break;
4341 case 0xf: /* V9 sir, nop if user */
3475187d 4342#if !defined(CONFIG_USER_ONLY)
6ad6135d 4343 if (supervisor(dc)) {
1a2fb1c0 4344 ; // XXX
6ad6135d 4345 }
3475187d 4346#endif
0f8a249a
BS		 4347 break;
4348 case 0x13: /* Graphics Status */
5b12f1e8 4349 if (gen_trap_ifnofpu(dc)) {
725cb90b 4350 goto jmp_insn;
5b12f1e8 4351 }
255e1fcb 4352 tcg_gen_xor_tl(cpu_gsr, cpu_src1, cpu_src2);
0f8a249a 4353 break;
9d926598
BS		 4354 case 0x14: /* Softint set */
4355 if (!supervisor(dc))
4356 goto illegal_insn;
aeff993c
RH		 4357 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4358 gen_helper_set_softint(cpu_env, cpu_tmp0);
9d926598
BS		 4359 break;
4360 case 0x15: /* Softint clear */
4361 if (!supervisor(dc))
4362 goto illegal_insn;
aeff993c
RH		 4363 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4364 gen_helper_clear_softint(cpu_env, cpu_tmp0);
9d926598
BS		 4365 break;
4366 case 0x16: /* Softint write */
4367 if (!supervisor(dc))
4368 goto illegal_insn;
aeff993c
RH		 4369 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4370 gen_helper_write_softint(cpu_env, cpu_tmp0);
9d926598 4371 break;
0f8a249a 4372 case 0x17: /* Tick compare */
83469015 4373#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 4374 if (!supervisor(dc))
4375 goto illegal_insn;
83469015 4376#endif
ccd4a219 4377 {
a7812ae4 4378 TCGv_ptr r_tickptr;
ccd4a219 4379
255e1fcb 4380 tcg_gen_xor_tl(cpu_tick_cmpr, cpu_src1,
6ae20372 4381 cpu_src2);
a7812ae4 4382 r_tickptr = tcg_temp_new_ptr();
ccd4a219 4383 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 4384 offsetof(CPUSPARCState, tick));
a7812ae4
PB		 4385 gen_helper_tick_set_limit(r_tickptr,
4386 cpu_tick_cmpr);
4387 tcg_temp_free_ptr(r_tickptr);
ccd4a219 4388 }
0f8a249a
BS		 4389 break;
4390 case 0x18: /* System tick */
83469015 4391#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 4392 if (!supervisor(dc))
4393 goto illegal_insn;
83469015 4394#endif
ccd4a219 4395 {
a7812ae4 4396 TCGv_ptr r_tickptr;
ccd4a219 4397
7b04bd5c 4398 tcg_gen_xor_tl(cpu_tmp0, cpu_src1,
6ae20372 4399 cpu_src2);
a7812ae4 4400 r_tickptr = tcg_temp_new_ptr();
ccd4a219 4401 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 4402 offsetof(CPUSPARCState, stick));
a7812ae4 4403 gen_helper_tick_set_count(r_tickptr,
7b04bd5c 4404 cpu_tmp0);
a7812ae4 4405 tcg_temp_free_ptr(r_tickptr);
ccd4a219 4406 }
0f8a249a
BS		 4407 break;
4408 case 0x19: /* System tick compare */
83469015 4409#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 4410 if (!supervisor(dc))
4411 goto illegal_insn;
3475187d 4412#endif
ccd4a219 4413 {
a7812ae4 4414 TCGv_ptr r_tickptr;
ccd4a219 4415
255e1fcb 4416 tcg_gen_xor_tl(cpu_stick_cmpr, cpu_src1,
6ae20372 4417 cpu_src2);
a7812ae4 4418 r_tickptr = tcg_temp_new_ptr();
ccd4a219 4419 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 4420 offsetof(CPUSPARCState, stick));
a7812ae4
PB		 4421 gen_helper_tick_set_limit(r_tickptr,
4422 cpu_stick_cmpr);
4423 tcg_temp_free_ptr(r_tickptr);
ccd4a219 4424 }
0f8a249a 4425 break;
83469015 4426
0f8a249a 4427 case 0x10: /* Performance Control */
77f193da
BS		 4428 case 0x11: /* Performance Instrumentation
4429 Counter */
0f8a249a 4430 case 0x12: /* Dispatch Control */
83469015 4431#endif
3475187d 4432 default:
cf495bcf
FB		 4433 goto illegal_insn;
4434 }
4435 }
4436 break;
e8af50a3 4437#if !defined(CONFIG_USER_ONLY)
af7bf89b 4438 case 0x31: /* wrpsr, V9 saved, restored */
e8af50a3 4439 {
0f8a249a
BS		 4440 if (!supervisor(dc))
4441 goto priv_insn;
3475187d 4442#ifdef TARGET_SPARC64
0f8a249a
BS		 4443 switch (rd) {
4444 case 0:
063c3675 4445 gen_helper_saved(cpu_env);
0f8a249a
BS		 4446 break;
4447 case 1:
063c3675 4448 gen_helper_restored(cpu_env);
0f8a249a 4449 break;
e9ebed4d
BS		 4450 case 2: /* UA2005 allclean */
4451 case 3: /* UA2005 otherw */
4452 case 4: /* UA2005 normalw */
4453 case 5: /* UA2005 invalw */
4454 // XXX
0f8a249a 4455 default:
3475187d
FB		 4456 goto illegal_insn;
4457 }
4458#else
de9e9d9f 4459 cpu_tmp0 = get_temp_tl(dc);
7b04bd5c
RH		 4460 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4461 gen_helper_wrpsr(cpu_env, cpu_tmp0);
8393617c
BS		 4462 tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
4463 dc->cc_op = CC_OP_FLAGS;
66442b07 4464 save_state(dc);
9e61bde5 4465 gen_op_next_insn();
57fec1fe 4466 tcg_gen_exit_tb(0);
0f8a249a 4467 dc->is_br = 1;
3475187d 4468#endif
e8af50a3
FB		 4469 }
4470 break;
af7bf89b 4471 case 0x32: /* wrwim, V9 wrpr */
e8af50a3 4472 {
0f8a249a
BS		 4473 if (!supervisor(dc))
4474 goto priv_insn;
de9e9d9f 4475 cpu_tmp0 = get_temp_tl(dc);
ece43b8d 4476 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3475187d 4477#ifdef TARGET_SPARC64
0f8a249a
BS		 4478 switch (rd) {
4479 case 0: // tpc
375ee38b 4480 {
a7812ae4 4481 TCGv_ptr r_tsptr;
375ee38b 4482
a7812ae4 4483 r_tsptr = tcg_temp_new_ptr();
8194f35a 4484 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 4485 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
375ee38b 4486 offsetof(trap_state, tpc));
a7812ae4 4487 tcg_temp_free_ptr(r_tsptr);
375ee38b 4488 }
0f8a249a
BS		 4489 break;
4490 case 1: // tnpc
375ee38b 4491 {
a7812ae4 4492 TCGv_ptr r_tsptr;
375ee38b 4493
a7812ae4 4494 r_tsptr = tcg_temp_new_ptr();
8194f35a 4495 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 4496 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
375ee38b 4497 offsetof(trap_state, tnpc));
a7812ae4 4498 tcg_temp_free_ptr(r_tsptr);
375ee38b 4499 }
0f8a249a
BS		 4500 break;
4501 case 2: // tstate
375ee38b 4502 {
a7812ae4 4503 TCGv_ptr r_tsptr;
375ee38b 4504
a7812ae4 4505 r_tsptr = tcg_temp_new_ptr();
8194f35a 4506 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 4507 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
77f193da
BS		 4508 offsetof(trap_state,
4509 tstate));
a7812ae4 4510 tcg_temp_free_ptr(r_tsptr);
375ee38b 4511 }
0f8a249a
BS		 4512 break;
4513 case 3: // tt
375ee38b 4514 {
a7812ae4 4515 TCGv_ptr r_tsptr;
375ee38b 4516
a7812ae4 4517 r_tsptr = tcg_temp_new_ptr();
8194f35a 4518 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
7b9e066b
RH		 4519 tcg_gen_st32_tl(cpu_tmp0, r_tsptr,
4520 offsetof(trap_state, tt));
a7812ae4 4521 tcg_temp_free_ptr(r_tsptr);
375ee38b 4522 }
0f8a249a
BS		 4523 break;
4524 case 4: // tick
ccd4a219 4525 {
a7812ae4 4526 TCGv_ptr r_tickptr;
ccd4a219 4527
a7812ae4 4528 r_tickptr = tcg_temp_new_ptr();
ccd4a219 4529 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 4530 offsetof(CPUSPARCState, tick));
a7812ae4
PB		 4531 gen_helper_tick_set_count(r_tickptr,
4532 cpu_tmp0);
4533 tcg_temp_free_ptr(r_tickptr);
ccd4a219 4534 }
0f8a249a
BS		 4535 break;
4536 case 5: // tba
255e1fcb 4537 tcg_gen_mov_tl(cpu_tbr, cpu_tmp0);
0f8a249a
BS		 4538 break;
4539 case 6: // pstate
6234ac09
RH		 4540 save_state(dc);
4541 gen_helper_wrpstate(cpu_env, cpu_tmp0);
4542 dc->npc = DYNAMIC_PC;
0f8a249a
BS		 4543 break;
4544 case 7: // tl
6234ac09 4545 save_state(dc);
7b9e066b 4546 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
6234ac09
RH		 4547 offsetof(CPUSPARCState, tl));
4548 dc->npc = DYNAMIC_PC;
0f8a249a
BS		 4549 break;
4550 case 8: // pil
063c3675 4551 gen_helper_wrpil(cpu_env, cpu_tmp0);
0f8a249a
BS		 4552 break;
4553 case 9: // cwp
063c3675 4554 gen_helper_wrcwp(cpu_env, cpu_tmp0);
0f8a249a
BS		 4555 break;
4556 case 10: // cansave
7b9e066b
RH		 4557 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
4558 offsetof(CPUSPARCState,
4559 cansave));
0f8a249a
BS		 4560 break;
4561 case 11: // canrestore
7b9e066b
RH		 4562 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
4563 offsetof(CPUSPARCState,
4564 canrestore));
0f8a249a
BS		 4565 break;
4566 case 12: // cleanwin
7b9e066b
RH		 4567 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
4568 offsetof(CPUSPARCState,
4569 cleanwin));
0f8a249a
BS		 4570 break;
4571 case 13: // otherwin
7b9e066b
RH		 4572 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
4573 offsetof(CPUSPARCState,
4574 otherwin));
0f8a249a
BS		 4575 break;
4576 case 14: // wstate
7b9e066b
RH		 4577 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
4578 offsetof(CPUSPARCState,
4579 wstate));
0f8a249a 4580 break;
e9ebed4d 4581 case 16: // UA2005 gl
fb79ceb9 4582 CHECK_IU_FEATURE(dc, GL);
cbc3a6a4 4583 gen_helper_wrgl(cpu_env, cpu_tmp0);
e9ebed4d
BS		 4584 break;
4585 case 26: // UA2005 strand status
fb79ceb9 4586 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 4587 if (!hypervisor(dc))
4588 goto priv_insn;
527067d8 4589 tcg_gen_mov_tl(cpu_ssr, cpu_tmp0);
e9ebed4d 4590 break;
0f8a249a
BS		 4591 default:
4592 goto illegal_insn;
4593 }
3475187d 4594#else
7b9e066b
RH		 4595 tcg_gen_trunc_tl_i32(cpu_wim, cpu_tmp0);
4596 if (dc->def->nwindows != 32) {
4597 tcg_gen_andi_tl(cpu_wim, cpu_wim,
c93e7817 4598 (1 << dc->def->nwindows) - 1);
7b9e066b 4599 }
3475187d 4600#endif
e8af50a3
FB		 4601 }
4602 break;
e9ebed4d 4603 case 0x33: /* wrtbr, UA2005 wrhpr */
e8af50a3 4604 {
e9ebed4d 4605#ifndef TARGET_SPARC64
0f8a249a
BS		 4606 if (!supervisor(dc))
4607 goto priv_insn;
255e1fcb 4608 tcg_gen_xor_tl(cpu_tbr, cpu_src1, cpu_src2);
e9ebed4d 4609#else
fb79ceb9 4610 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 4611 if (!hypervisor(dc))
4612 goto priv_insn;
de9e9d9f 4613 cpu_tmp0 = get_temp_tl(dc);
ece43b8d 4614 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
e9ebed4d
BS		 4615 switch (rd) {
4616 case 0: // hpstate
f7f17ef7
AT		 4617 tcg_gen_st_i64(cpu_tmp0, cpu_env,
4618 offsetof(CPUSPARCState,
4619 hpstate));
66442b07 4620 save_state(dc);
e9ebed4d 4621 gen_op_next_insn();
57fec1fe 4622 tcg_gen_exit_tb(0);
e9ebed4d
BS		 4623 dc->is_br = 1;
4624 break;
4625 case 1: // htstate
4626 // XXX gen_op_wrhtstate();
4627 break;
4628 case 3: // hintp
255e1fcb 4629 tcg_gen_mov_tl(cpu_hintp, cpu_tmp0);
e9ebed4d
BS		 4630 break;
4631 case 5: // htba
255e1fcb 4632 tcg_gen_mov_tl(cpu_htba, cpu_tmp0);
e9ebed4d
BS		 4633 break;
4634 case 31: // hstick_cmpr
ccd4a219 4635 {
a7812ae4 4636 TCGv_ptr r_tickptr;
ccd4a219 4637
255e1fcb 4638 tcg_gen_mov_tl(cpu_hstick_cmpr, cpu_tmp0);
a7812ae4 4639 r_tickptr = tcg_temp_new_ptr();
ccd4a219 4640 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 4641 offsetof(CPUSPARCState, hstick));
a7812ae4
PB		 4642 gen_helper_tick_set_limit(r_tickptr,
4643 cpu_hstick_cmpr);
4644 tcg_temp_free_ptr(r_tickptr);
ccd4a219 4645 }
e9ebed4d
BS		 4646 break;
4647 case 6: // hver readonly
4648 default:
4649 goto illegal_insn;
4650 }
4651#endif
e8af50a3
FB		 4652 }
4653 break;
4654#endif
3475187d 4655#ifdef TARGET_SPARC64
0f8a249a
BS		 4656 case 0x2c: /* V9 movcc */
4657 {
4658 int cc = GET_FIELD_SP(insn, 11, 12);
4659 int cond = GET_FIELD_SP(insn, 14, 17);
f52879b4 4660 DisasCompare cmp;
97ea2859 4661 TCGv dst;
00f219bf 4662
0f8a249a 4663 if (insn & (1 << 18)) {
f52879b4
RH		 4664 if (cc == 0) {
4665 gen_compare(&cmp, 0, cond, dc);
4666 } else if (cc == 2) {
4667 gen_compare(&cmp, 1, cond, dc);
4668 } else {
0f8a249a 4669 goto illegal_insn;
f52879b4 4670 }
0f8a249a 4671 } else {
f52879b4 4672 gen_fcompare(&cmp, cc, cond);
0f8a249a 4673 }
00f219bf 4674
f52879b4
RH		 4675 /* The get_src2 above loaded the normal 13-bit
4676 immediate field, not the 11-bit field we have
4677 in movcc. But it did handle the reg case. */
4678 if (IS_IMM) {
67526b20 4679 simm = GET_FIELD_SPs(insn, 0, 10);
f52879b4 4680 tcg_gen_movi_tl(cpu_src2, simm);
00f219bf 4681 }
f52879b4 4682
97ea2859
RH		 4683 dst = gen_load_gpr(dc, rd);
4684 tcg_gen_movcond_tl(cmp.cond, dst,
f52879b4 4685 cmp.c1, cmp.c2,
97ea2859 4686 cpu_src2, dst);
f52879b4 4687 free_compare(&cmp);
97ea2859 4688 gen_store_gpr(dc, rd, dst);
0f8a249a
BS		 4689 break;
4690 }
4691 case 0x2d: /* V9 sdivx */
c28ae41e 4692 gen_helper_sdivx(cpu_dst, cpu_env, cpu_src1, cpu_src2);
97ea2859 4693 gen_store_gpr(dc, rd, cpu_dst);
0f8a249a
BS		 4694 break;
4695 case 0x2e: /* V9 popc */
08da3180 4696 tcg_gen_ctpop_tl(cpu_dst, cpu_src2);
97ea2859
RH		 4697 gen_store_gpr(dc, rd, cpu_dst);
4698 break;
0f8a249a
BS		 4699 case 0x2f: /* V9 movr */
4700 {
4701 int cond = GET_FIELD_SP(insn, 10, 12);
c33f80f5 4702 DisasCompare cmp;
97ea2859 4703 TCGv dst;
00f219bf 4704
c33f80f5 4705 gen_compare_reg(&cmp, cond, cpu_src1);
2ea815ca 4706
c33f80f5
RH		 4707 /* The get_src2 above loaded the normal 13-bit
4708 immediate field, not the 10-bit field we have
4709 in movr. But it did handle the reg case. */
4710 if (IS_IMM) {
67526b20 4711 simm = GET_FIELD_SPs(insn, 0, 9);
c33f80f5 4712 tcg_gen_movi_tl(cpu_src2, simm);
0f8a249a 4713 }
c33f80f5 4714
97ea2859
RH		 4715 dst = gen_load_gpr(dc, rd);
4716 tcg_gen_movcond_tl(cmp.cond, dst,
c33f80f5 4717 cmp.c1, cmp.c2,
97ea2859 4718 cpu_src2, dst);
c33f80f5 4719 free_compare(&cmp);
97ea2859 4720 gen_store_gpr(dc, rd, dst);
0f8a249a
BS		 4721 break;
4722 }
4723#endif
4724 default:
4725 goto illegal_insn;
4726 }
4727 }
3299908c
BS		 4728 } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
4729#ifdef TARGET_SPARC64
4730 int opf = GET_FIELD_SP(insn, 5, 13);
4731 rs1 = GET_FIELD(insn, 13, 17);
4732 rs2 = GET_FIELD(insn, 27, 31);
5b12f1e8 4733 if (gen_trap_ifnofpu(dc)) {
e9ebed4d 4734 goto jmp_insn;
5b12f1e8 4735 }
3299908c
BS		 4736
4737 switch (opf) {
e9ebed4d 4738 case 0x000: /* VIS I edge8cc */
6c073553 4739 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4740 cpu_src1 = gen_load_gpr(dc, rs1);
4741 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4742 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 0);
97ea2859 4743 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4744 break;
e9ebed4d 4745 case 0x001: /* VIS II edge8n */
6c073553 4746 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4747 cpu_src1 = gen_load_gpr(dc, rs1);
4748 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4749 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 0);
97ea2859 4750 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4751 break;
e9ebed4d 4752 case 0x002: /* VIS I edge8lcc */
6c073553 4753 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4754 cpu_src1 = gen_load_gpr(dc, rs1);
4755 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4756 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 1);
97ea2859 4757 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4758 break;
e9ebed4d 4759 case 0x003: /* VIS II edge8ln */
6c073553 4760 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4761 cpu_src1 = gen_load_gpr(dc, rs1);
4762 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4763 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 1);
97ea2859 4764 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4765 break;
e9ebed4d 4766 case 0x004: /* VIS I edge16cc */
6c073553 4767 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4768 cpu_src1 = gen_load_gpr(dc, rs1);
4769 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4770 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 0);
97ea2859 4771 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4772 break;
e9ebed4d 4773 case 0x005: /* VIS II edge16n */
6c073553 4774 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4775 cpu_src1 = gen_load_gpr(dc, rs1);
4776 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4777 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 0);
97ea2859 4778 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4779 break;
e9ebed4d 4780 case 0x006: /* VIS I edge16lcc */
6c073553 4781 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4782 cpu_src1 = gen_load_gpr(dc, rs1);
4783 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4784 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 1);
97ea2859 4785 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4786 break;
e9ebed4d 4787 case 0x007: /* VIS II edge16ln */
6c073553 4788 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4789 cpu_src1 = gen_load_gpr(dc, rs1);
4790 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4791 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 1);
97ea2859 4792 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4793 break;
e9ebed4d 4794 case 0x008: /* VIS I edge32cc */
6c073553 4795 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4796 cpu_src1 = gen_load_gpr(dc, rs1);
4797 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4798 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 0);
97ea2859 4799 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4800 break;
e9ebed4d 4801 case 0x009: /* VIS II edge32n */
6c073553 4802 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4803 cpu_src1 = gen_load_gpr(dc, rs1);
4804 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4805 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 0);
97ea2859 4806 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4807 break;
e9ebed4d 4808 case 0x00a: /* VIS I edge32lcc */
6c073553 4809 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4810 cpu_src1 = gen_load_gpr(dc, rs1);
4811 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4812 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 1);
97ea2859 4813 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4814 break;
e9ebed4d 4815 case 0x00b: /* VIS II edge32ln */
6c073553 4816 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4817 cpu_src1 = gen_load_gpr(dc, rs1);
4818 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4819 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 1);
97ea2859 4820 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4821 break;
e9ebed4d 4822 case 0x010: /* VIS I array8 */
64a88d5d 4823 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4824 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4825 cpu_src2 = gen_load_gpr(dc, rs2);
f027c3b1 4826 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
97ea2859 4827 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4828 break;
4829 case 0x012: /* VIS I array16 */
64a88d5d 4830 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4831 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4832 cpu_src2 = gen_load_gpr(dc, rs2);
f027c3b1 4833 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
6ae20372 4834 tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
97ea2859 4835 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4836 break;
4837 case 0x014: /* VIS I array32 */
64a88d5d 4838 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4839 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4840 cpu_src2 = gen_load_gpr(dc, rs2);
f027c3b1 4841 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
6ae20372 4842 tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
97ea2859 4843 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d 4844 break;
3299908c 4845 case 0x018: /* VIS I alignaddr */
64a88d5d 4846 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4847 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4848 cpu_src2 = gen_load_gpr(dc, rs2);
add545ab 4849 gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 0);
97ea2859 4850 gen_store_gpr(dc, rd, cpu_dst);
3299908c
BS		 4851 break;
4852 case 0x01a: /* VIS I alignaddrl */
add545ab 4853 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4854 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4855 cpu_src2 = gen_load_gpr(dc, rs2);
add545ab 4856 gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 1);
97ea2859 4857 gen_store_gpr(dc, rd, cpu_dst);
add545ab
RH		 4858 break;
4859 case 0x019: /* VIS II bmask */
793a137a 4860 CHECK_FPU_FEATURE(dc, VIS2);
9d1d4e34
RH		 4861 cpu_src1 = gen_load_gpr(dc, rs1);
4862 cpu_src2 = gen_load_gpr(dc, rs2);
793a137a
RH		 4863 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4864 tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, cpu_dst, 32, 32);
97ea2859 4865 gen_store_gpr(dc, rd, cpu_dst);
793a137a 4866 break;
e9ebed4d 4867 case 0x020: /* VIS I fcmple16 */
64a88d5d 4868 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4869 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4870 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4871 gen_helper_fcmple16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4872 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4873 break;
4874 case 0x022: /* VIS I fcmpne16 */
64a88d5d 4875 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4876 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4877 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4878 gen_helper_fcmpne16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4879 gen_store_gpr(dc, rd, cpu_dst);
3299908c 4880 break;
e9ebed4d 4881 case 0x024: /* VIS I fcmple32 */
64a88d5d 4882 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4883 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4884 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4885 gen_helper_fcmple32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4886 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4887 break;
4888 case 0x026: /* VIS I fcmpne32 */
64a88d5d 4889 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4890 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4891 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4892 gen_helper_fcmpne32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4893 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4894 break;
4895 case 0x028: /* VIS I fcmpgt16 */
64a88d5d 4896 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4897 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4898 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4899 gen_helper_fcmpgt16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4900 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4901 break;
4902 case 0x02a: /* VIS I fcmpeq16 */
64a88d5d 4903 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4904 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4905 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4906 gen_helper_fcmpeq16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4907 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4908 break;
4909 case 0x02c: /* VIS I fcmpgt32 */
64a88d5d 4910 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4911 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4912 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4913 gen_helper_fcmpgt32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4914 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4915 break;
4916 case 0x02e: /* VIS I fcmpeq32 */
64a88d5d 4917 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4918 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4919 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4920 gen_helper_fcmpeq32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4921 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4922 break;
4923 case 0x031: /* VIS I fmul8x16 */
64a88d5d 4924 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4925 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16);
e9ebed4d
BS		 4926 break;
4927 case 0x033: /* VIS I fmul8x16au */
64a88d5d 4928 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4929 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16au);
e9ebed4d
BS		 4930 break;
4931 case 0x035: /* VIS I fmul8x16al */
64a88d5d 4932 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4933 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16al);
e9ebed4d
BS		 4934 break;
4935 case 0x036: /* VIS I fmul8sux16 */
64a88d5d 4936 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4937 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8sux16);
e9ebed4d
BS		 4938 break;
4939 case 0x037: /* VIS I fmul8ulx16 */
64a88d5d 4940 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4941 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8ulx16);
e9ebed4d
BS		 4942 break;
4943 case 0x038: /* VIS I fmuld8sux16 */
64a88d5d 4944 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4945 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8sux16);
e9ebed4d
BS		 4946 break;
4947 case 0x039: /* VIS I fmuld8ulx16 */
64a88d5d 4948 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4949 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8ulx16);
e9ebed4d
BS		 4950 break;
4951 case 0x03a: /* VIS I fpack32 */
2dedf314
RH		 4952 CHECK_FPU_FEATURE(dc, VIS1);
4953 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpack32);
4954 break;
e9ebed4d 4955 case 0x03b: /* VIS I fpack16 */
2dedf314
RH		 4956 CHECK_FPU_FEATURE(dc, VIS1);
4957 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
ba5f5179 4958 cpu_dst_32 = gen_dest_fpr_F(dc);
2dedf314
RH		 4959 gen_helper_fpack16(cpu_dst_32, cpu_gsr, cpu_src1_64);
4960 gen_store_fpr_F(dc, rd, cpu_dst_32);
4961 break;
e9ebed4d 4962 case 0x03d: /* VIS I fpackfix */
2dedf314
RH		 4963 CHECK_FPU_FEATURE(dc, VIS1);
4964 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
ba5f5179 4965 cpu_dst_32 = gen_dest_fpr_F(dc);
2dedf314
RH		 4966 gen_helper_fpackfix(cpu_dst_32, cpu_gsr, cpu_src1_64);
4967 gen_store_fpr_F(dc, rd, cpu_dst_32);
4968 break;
f888300b
RH		 4969 case 0x03e: /* VIS I pdist */
4970 CHECK_FPU_FEATURE(dc, VIS1);
4971 gen_ne_fop_DDDD(dc, rd, rs1, rs2, gen_helper_pdist);
4972 break;
3299908c 4973 case 0x048: /* VIS I faligndata */
64a88d5d 4974 CHECK_FPU_FEATURE(dc, VIS1);
50c796f9 4975 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_faligndata);
3299908c 4976 break;
e9ebed4d 4977 case 0x04b: /* VIS I fpmerge */
64a88d5d 4978 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4979 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpmerge);
e9ebed4d
BS		 4980 break;
4981 case 0x04c: /* VIS II bshuffle */
793a137a
RH		 4982 CHECK_FPU_FEATURE(dc, VIS2);
4983 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_bshuffle);
4984 break;
e9ebed4d 4985 case 0x04d: /* VIS I fexpand */
64a88d5d 4986 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4987 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fexpand);
e9ebed4d
BS		 4988 break;
4989 case 0x050: /* VIS I fpadd16 */
64a88d5d 4990 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4991 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd16);
e9ebed4d
BS		 4992 break;
4993 case 0x051: /* VIS I fpadd16s */
64a88d5d 4994 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4995 gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpadd16s);
e9ebed4d
BS		 4996 break;
4997 case 0x052: /* VIS I fpadd32 */
64a88d5d 4998 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4999 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd32);
e9ebed4d
BS		 5000 break;
5001 case 0x053: /* VIS I fpadd32s */
64a88d5d 5002 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5003 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_add_i32);
e9ebed4d
BS		 5004 break;
5005 case 0x054: /* VIS I fpsub16 */
64a88d5d 5006 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5007 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub16);
e9ebed4d
BS		 5008 break;
5009 case 0x055: /* VIS I fpsub16s */
64a88d5d 5010 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5011 gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpsub16s);
e9ebed4d
BS		 5012 break;
5013 case 0x056: /* VIS I fpsub32 */
64a88d5d 5014 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5015 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub32);
e9ebed4d
BS		 5016 break;
5017 case 0x057: /* VIS I fpsub32s */
64a88d5d 5018 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5019 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_sub_i32);
e9ebed4d 5020 break;
3299908c 5021 case 0x060: /* VIS I fzero */
64a88d5d 5022 CHECK_FPU_FEATURE(dc, VIS1);
3886b8a3 5023 cpu_dst_64 = gen_dest_fpr_D(dc, rd);
96eda024
RH		 5024 tcg_gen_movi_i64(cpu_dst_64, 0);
5025 gen_store_fpr_D(dc, rd, cpu_dst_64);
3299908c
BS		 5026 break;
5027 case 0x061: /* VIS I fzeros */
64a88d5d 5028 CHECK_FPU_FEATURE(dc, VIS1);
ba5f5179 5029 cpu_dst_32 = gen_dest_fpr_F(dc);
208ae657
RH		 5030 tcg_gen_movi_i32(cpu_dst_32, 0);
5031 gen_store_fpr_F(dc, rd, cpu_dst_32);
3299908c 5032 break;
e9ebed4d 5033 case 0x062: /* VIS I fnor */
64a88d5d 5034 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5035 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nor_i64);
e9ebed4d
BS		 5036 break;
5037 case 0x063: /* VIS I fnors */
64a88d5d 5038 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5039 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_nor_i32);
e9ebed4d
BS		 5040 break;
5041 case 0x064: /* VIS I fandnot2 */
64a88d5d 5042 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5043 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_andc_i64);
e9ebed4d
BS		 5044 break;
5045 case 0x065: /* VIS I fandnot2s */
64a88d5d 5046 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5047 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_andc_i32);
e9ebed4d
BS		 5048 break;
5049 case 0x066: /* VIS I fnot2 */
64a88d5d 5050 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5051 gen_ne_fop_DD(dc, rd, rs2, tcg_gen_not_i64);
e9ebed4d
BS		 5052 break;
5053 case 0x067: /* VIS I fnot2s */
64a88d5d 5054 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5055 gen_ne_fop_FF(dc, rd, rs2, tcg_gen_not_i32);
e9ebed4d
BS		 5056 break;
5057 case 0x068: /* VIS I fandnot1 */
64a88d5d 5058 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5059 gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_andc_i64);
e9ebed4d
BS		 5060 break;
5061 case 0x069: /* VIS I fandnot1s */
64a88d5d 5062 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5063 gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_andc_i32);
e9ebed4d
BS		 5064 break;
5065 case 0x06a: /* VIS I fnot1 */
64a88d5d 5066 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5067 gen_ne_fop_DD(dc, rd, rs1, tcg_gen_not_i64);
e9ebed4d
BS		 5068 break;
5069 case 0x06b: /* VIS I fnot1s */
64a88d5d 5070 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5071 gen_ne_fop_FF(dc, rd, rs1, tcg_gen_not_i32);
e9ebed4d
BS		 5072 break;
5073 case 0x06c: /* VIS I fxor */
64a88d5d 5074 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5075 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_xor_i64);
e9ebed4d
BS		 5076 break;
5077 case 0x06d: /* VIS I fxors */
64a88d5d 5078 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5079 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_xor_i32);
e9ebed4d
BS		 5080 break;
5081 case 0x06e: /* VIS I fnand */
64a88d5d 5082 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5083 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nand_i64);
e9ebed4d
BS		 5084 break;
5085 case 0x06f: /* VIS I fnands */
64a88d5d 5086 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5087 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_nand_i32);
e9ebed4d
BS		 5088 break;
5089 case 0x070: /* VIS I fand */
64a88d5d 5090 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5091 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_and_i64);
e9ebed4d
BS		 5092 break;
5093 case 0x071: /* VIS I fands */
64a88d5d 5094 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5095 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_and_i32);
e9ebed4d
BS		 5096 break;
5097 case 0x072: /* VIS I fxnor */
64a88d5d 5098 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5099 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_eqv_i64);
e9ebed4d
BS		 5100 break;
5101 case 0x073: /* VIS I fxnors */
64a88d5d 5102 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5103 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_eqv_i32);
e9ebed4d 5104 break;
3299908c 5105 case 0x074: /* VIS I fsrc1 */
64a88d5d 5106 CHECK_FPU_FEATURE(dc, VIS1);
96eda024
RH		 5107 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
5108 gen_store_fpr_D(dc, rd, cpu_src1_64);
3299908c
BS		 5109 break;
5110 case 0x075: /* VIS I fsrc1s */
64a88d5d 5111 CHECK_FPU_FEATURE(dc, VIS1);
208ae657
RH		 5112 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
5113 gen_store_fpr_F(dc, rd, cpu_src1_32);
3299908c 5114 break;
e9ebed4d 5115 case 0x076: /* VIS I fornot2 */
64a88d5d 5116 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5117 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_orc_i64);
e9ebed4d
BS		 5118 break;
5119 case 0x077: /* VIS I fornot2s */
64a88d5d 5120 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5121 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_orc_i32);
e9ebed4d 5122 break;
3299908c 5123 case 0x078: /* VIS I fsrc2 */
64a88d5d 5124 CHECK_FPU_FEATURE(dc, VIS1);
96eda024
RH		 5125 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
5126 gen_store_fpr_D(dc, rd, cpu_src1_64);
3299908c
BS		 5127 break;
5128 case 0x079: /* VIS I fsrc2s */
64a88d5d 5129 CHECK_FPU_FEATURE(dc, VIS1);
208ae657
RH		 5130 cpu_src1_32 = gen_load_fpr_F(dc, rs2);
5131 gen_store_fpr_F(dc, rd, cpu_src1_32);
3299908c 5132 break;
e9ebed4d 5133 case 0x07a: /* VIS I fornot1 */
64a88d5d 5134 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5135 gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_orc_i64);
e9ebed4d
BS		 5136 break;
5137 case 0x07b: /* VIS I fornot1s */
64a88d5d 5138 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5139 gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_orc_i32);
e9ebed4d
BS		 5140 break;
5141 case 0x07c: /* VIS I for */
64a88d5d 5142 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5143 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_or_i64);
e9ebed4d
BS		 5144 break;
5145 case 0x07d: /* VIS I fors */
64a88d5d 5146 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5147 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_or_i32);
e9ebed4d 5148 break;
3299908c 5149 case 0x07e: /* VIS I fone */
64a88d5d 5150 CHECK_FPU_FEATURE(dc, VIS1);
3886b8a3 5151 cpu_dst_64 = gen_dest_fpr_D(dc, rd);
96eda024
RH		 5152 tcg_gen_movi_i64(cpu_dst_64, -1);
5153 gen_store_fpr_D(dc, rd, cpu_dst_64);
3299908c
BS		 5154 break;
5155 case 0x07f: /* VIS I fones */
64a88d5d 5156 CHECK_FPU_FEATURE(dc, VIS1);
ba5f5179 5157 cpu_dst_32 = gen_dest_fpr_F(dc);
208ae657
RH		 5158 tcg_gen_movi_i32(cpu_dst_32, -1);
5159 gen_store_fpr_F(dc, rd, cpu_dst_32);
3299908c 5160 break;
e9ebed4d
BS		 5161 case 0x080: /* VIS I shutdown */
5162 case 0x081: /* VIS II siam */
5163 // XXX
5164 goto illegal_insn;
3299908c
BS		 5165 default:
5166 goto illegal_insn;
5167 }
5168#else
0f8a249a 5169 goto ncp_insn;
3299908c
BS		 5170#endif
5171 } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
fcc72045 5172#ifdef TARGET_SPARC64
0f8a249a 5173 goto illegal_insn;
fcc72045 5174#else
0f8a249a 5175 goto ncp_insn;
fcc72045 5176#endif
3475187d 5177#ifdef TARGET_SPARC64
0f8a249a 5178 } else if (xop == 0x39) { /* V9 return */
66442b07 5179 save_state(dc);
9d1d4e34 5180 cpu_src1 = get_src1(dc, insn);
de9e9d9f 5181 cpu_tmp0 = get_temp_tl(dc);
0f8a249a 5182 if (IS_IMM) { /* immediate */
67526b20 5183 simm = GET_FIELDs(insn, 19, 31);
7b04bd5c 5184 tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm);
0f8a249a 5185 } else { /* register */
3475187d 5186 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 5187 if (rs2) {
97ea2859 5188 cpu_src2 = gen_load_gpr(dc, rs2);
7b04bd5c 5189 tcg_gen_add_tl(cpu_tmp0, cpu_src1, cpu_src2);
97ea2859 5190 } else {
7b04bd5c 5191 tcg_gen_mov_tl(cpu_tmp0, cpu_src1);
97ea2859 5192 }
3475187d 5193 }
063c3675 5194 gen_helper_restore(cpu_env);
13a6dd00 5195 gen_mov_pc_npc(dc);
35e94905 5196 gen_check_align(cpu_tmp0, 3);
7b04bd5c 5197 tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
0f8a249a
BS		 5198 dc->npc = DYNAMIC_PC;
5199 goto jmp_insn;
3475187d 5200#endif
0f8a249a 5201 } else {
9d1d4e34 5202 cpu_src1 = get_src1(dc, insn);
de9e9d9f 5203 cpu_tmp0 = get_temp_tl(dc);
0f8a249a 5204 if (IS_IMM) { /* immediate */
67526b20 5205 simm = GET_FIELDs(insn, 19, 31);
7b04bd5c 5206 tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm);
0f8a249a 5207 } else { /* register */
e80cfcfc 5208 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 5209 if (rs2) {
97ea2859 5210 cpu_src2 = gen_load_gpr(dc, rs2);
7b04bd5c 5211 tcg_gen_add_tl(cpu_tmp0, cpu_src1, cpu_src2);
97ea2859 5212 } else {
7b04bd5c 5213 tcg_gen_mov_tl(cpu_tmp0, cpu_src1);
97ea2859 5214 }
cf495bcf 5215 }
0f8a249a
BS		 5216 switch (xop) {
5217 case 0x38: /* jmpl */
5218 {
35e94905 5219 TCGv t = gen_dest_gpr(dc, rd);
97ea2859
RH		 5220 tcg_gen_movi_tl(t, dc->pc);
5221 gen_store_gpr(dc, rd, t);
35e94905 5222
13a6dd00 5223 gen_mov_pc_npc(dc);
35e94905 5224 gen_check_align(cpu_tmp0, 3);
7b04bd5c
RH		 5225 gen_address_mask(dc, cpu_tmp0);
5226 tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
0f8a249a
BS		 5227 dc->npc = DYNAMIC_PC;
5228 }
5229 goto jmp_insn;
3475187d 5230#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
0f8a249a
BS		 5231 case 0x39: /* rett, V9 return */
5232 {
5233 if (!supervisor(dc))
5234 goto priv_insn;
13a6dd00 5235 gen_mov_pc_npc(dc);
35e94905 5236 gen_check_align(cpu_tmp0, 3);
7b04bd5c 5237 tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
0f8a249a 5238 dc->npc = DYNAMIC_PC;
063c3675 5239 gen_helper_rett(cpu_env);
0f8a249a
BS		 5240 }
5241 goto jmp_insn;
5242#endif
5243 case 0x3b: /* flush */
5578ceab 5244 if (!((dc)->def->features & CPU_FEATURE_FLUSH))
64a88d5d 5245 goto unimp_flush;
dcfd14b3 5246 /* nop */
0f8a249a
BS		 5247 break;
5248 case 0x3c: /* save */
063c3675 5249 gen_helper_save(cpu_env);
7b04bd5c 5250 gen_store_gpr(dc, rd, cpu_tmp0);
0f8a249a
BS		 5251 break;
5252 case 0x3d: /* restore */
063c3675 5253 gen_helper_restore(cpu_env);
7b04bd5c 5254 gen_store_gpr(dc, rd, cpu_tmp0);
0f8a249a 5255 break;
3475187d 5256#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
0f8a249a
BS		 5257 case 0x3e: /* V9 done/retry */
5258 {
5259 switch (rd) {
5260 case 0:
5261 if (!supervisor(dc))
5262 goto priv_insn;
5263 dc->npc = DYNAMIC_PC;
5264 dc->pc = DYNAMIC_PC;
063c3675 5265 gen_helper_done(cpu_env);
0f8a249a
BS		 5266 goto jmp_insn;
5267 case 1:
5268 if (!supervisor(dc))
5269 goto priv_insn;
5270 dc->npc = DYNAMIC_PC;
5271 dc->pc = DYNAMIC_PC;
063c3675 5272 gen_helper_retry(cpu_env);
0f8a249a
BS		 5273 goto jmp_insn;
5274 default:
5275 goto illegal_insn;
5276 }
5277 }
5278 break;
5279#endif
5280 default:
5281 goto illegal_insn;
5282 }
cf495bcf 5283 }
0f8a249a
BS		 5284 break;
5285 }
5286 break;
5287 case 3: /* load/store instructions */
5288 {
5289 unsigned int xop = GET_FIELD(insn, 7, 12);
5e6ed439
RH		 5290 /* ??? gen_address_mask prevents us from using a source
5291 register directly. Always generate a temporary. */
5292 TCGv cpu_addr = get_temp_tl(dc);
9322a4bf 5293
5e6ed439
RH		 5294 tcg_gen_mov_tl(cpu_addr, get_src1(dc, insn));
5295 if (xop == 0x3c || xop == 0x3e) {
5296 /* V9 casa/casxa : no offset */
71817e48 5297 } else if (IS_IMM) { /* immediate */
67526b20 5298 simm = GET_FIELDs(insn, 19, 31);
5e6ed439
RH		 5299 if (simm != 0) {
5300 tcg_gen_addi_tl(cpu_addr, cpu_addr, simm);
5301 }
0f8a249a
BS		 5302 } else { /* register */
5303 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 5304 if (rs2 != 0) {
5e6ed439 5305 tcg_gen_add_tl(cpu_addr, cpu_addr, gen_load_gpr(dc, rs2));
97ea2859 5306 }
0f8a249a 5307 }
2f2ecb83
BS		 5308 if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
5309 (xop > 0x17 && xop <= 0x1d ) ||
5310 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
81634eea
RH		 5311 TCGv cpu_val = gen_dest_gpr(dc, rd);
5312
0f8a249a 5313 switch (xop) {
b89e94af 5314 case 0x0: /* ld, V9 lduw, load unsigned word */
2cade6a3 5315 gen_address_mask(dc, cpu_addr);
6ae20372 5316 tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5317 break;
b89e94af 5318 case 0x1: /* ldub, load unsigned byte */
2cade6a3 5319 gen_address_mask(dc, cpu_addr);
6ae20372 5320 tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5321 break;
b89e94af 5322 case 0x2: /* lduh, load unsigned halfword */
2cade6a3 5323 gen_address_mask(dc, cpu_addr);
6ae20372 5324 tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5325 break;
b89e94af 5326 case 0x3: /* ldd, load double word */
0f8a249a 5327 if (rd & 1)
d4218d99 5328 goto illegal_insn;
1a2fb1c0 5329 else {
abcc7191 5330 TCGv_i64 t64;
2ea815ca 5331
2cade6a3 5332 gen_address_mask(dc, cpu_addr);
abcc7191
RH		 5333 t64 = tcg_temp_new_i64();
5334 tcg_gen_qemu_ld64(t64, cpu_addr, dc->mem_idx);
de9e9d9f
RH		 5335 tcg_gen_trunc_i64_tl(cpu_val, t64);
5336 tcg_gen_ext32u_tl(cpu_val, cpu_val);
5337 gen_store_gpr(dc, rd + 1, cpu_val);
abcc7191
RH		 5338 tcg_gen_shri_i64(t64, t64, 32);
5339 tcg_gen_trunc_i64_tl(cpu_val, t64);
5340 tcg_temp_free_i64(t64);
de9e9d9f 5341 tcg_gen_ext32u_tl(cpu_val, cpu_val);
1a2fb1c0 5342 }
0f8a249a 5343 break;
b89e94af 5344 case 0x9: /* ldsb, load signed byte */
2cade6a3 5345 gen_address_mask(dc, cpu_addr);
6ae20372 5346 tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5347 break;
b89e94af 5348 case 0xa: /* ldsh, load signed halfword */
2cade6a3 5349 gen_address_mask(dc, cpu_addr);
6ae20372 5350 tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5351 break;
fbb4bbb6
RH		 5352 case 0xd: /* ldstub */
5353 gen_ldstub(dc, cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5354 break;
de9e9d9f
RH		 5355 case 0x0f:
5356 /* swap, swap register with memory. Also atomically */
4fb554bc
RH		 5357 CHECK_IU_FEATURE(dc, SWAP);
5358 cpu_src1 = gen_load_gpr(dc, rd);
5359 gen_swap(dc, cpu_val, cpu_src1, cpu_addr,
5360 dc->mem_idx, MO_TEUL);
0f8a249a 5361 break;
3475187d 5362#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
b89e94af 5363 case 0x10: /* lda, V9 lduwa, load word alternate */
1d65b0f5 5364 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEUL);
0f8a249a 5365 break;
b89e94af 5366 case 0x11: /* lduba, load unsigned byte alternate */
1d65b0f5 5367 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_UB);
0f8a249a 5368 break;
b89e94af 5369 case 0x12: /* lduha, load unsigned halfword alternate */
1d65b0f5 5370 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEUW);
0f8a249a 5371 break;
b89e94af 5372 case 0x13: /* ldda, load double word alternate */
7ec1e5ea 5373 if (rd & 1) {
d4218d99 5374 goto illegal_insn;
7ec1e5ea 5375 }
e4dc0052 5376 gen_ldda_asi(dc, cpu_addr, insn, rd);
db166940 5377 goto skip_move;
b89e94af 5378 case 0x19: /* ldsba, load signed byte alternate */
1d65b0f5 5379 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_SB);
0f8a249a 5380 break;
b89e94af 5381 case 0x1a: /* ldsha, load signed halfword alternate */
1d65b0f5 5382 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TESW);
0f8a249a
BS		 5383 break;
5384 case 0x1d: /* ldstuba -- XXX: should be atomically */
22e70060 5385 gen_ldstub_asi(dc, cpu_val, cpu_addr, insn);
0f8a249a 5386 break;
b89e94af 5387 case 0x1f: /* swapa, swap reg with alt. memory. Also
77f193da 5388 atomically */
64a88d5d 5389 CHECK_IU_FEATURE(dc, SWAP);
06828032 5390 cpu_src1 = gen_load_gpr(dc, rd);
22e70060 5391 gen_swap_asi(dc, cpu_val, cpu_src1, cpu_addr, insn);
0f8a249a 5392 break;
3475187d
FB		 5393
5394#ifndef TARGET_SPARC64
0f8a249a
BS		 5395 case 0x30: /* ldc */
5396 case 0x31: /* ldcsr */
5397 case 0x33: /* lddc */
5398 goto ncp_insn;
3475187d
FB		 5399#endif
5400#endif
5401#ifdef TARGET_SPARC64
0f8a249a 5402 case 0x08: /* V9 ldsw */
2cade6a3 5403 gen_address_mask(dc, cpu_addr);
6ae20372 5404 tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 5405 break;
5406 case 0x0b: /* V9 ldx */
2cade6a3 5407 gen_address_mask(dc, cpu_addr);
6ae20372 5408 tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 5409 break;
5410 case 0x18: /* V9 ldswa */
1d65b0f5 5411 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TESL);
0f8a249a
BS		 5412 break;
5413 case 0x1b: /* V9 ldxa */
1d65b0f5 5414 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEQ);
0f8a249a
BS		 5415 break;
5416 case 0x2d: /* V9 prefetch, no effect */
5417 goto skip_move;
5418 case 0x30: /* V9 ldfa */
5b12f1e8 5419 if (gen_trap_ifnofpu(dc)) {
8872eb4f
TS		 5420 goto jmp_insn;
5421 }
22e70060 5422 gen_ldf_asi(dc, cpu_addr, insn, 4, rd);
f9c816c0 5423 gen_update_fprs_dirty(dc, rd);
81ad8ba2 5424 goto skip_move;
0f8a249a 5425 case 0x33: /* V9 lddfa */
5b12f1e8 5426 if (gen_trap_ifnofpu(dc)) {
8872eb4f
TS		 5427 goto jmp_insn;
5428 }
22e70060 5429 gen_ldf_asi(dc, cpu_addr, insn, 8, DFPREG(rd));
f9c816c0 5430 gen_update_fprs_dirty(dc, DFPREG(rd));
81ad8ba2 5431 goto skip_move;
0f8a249a
BS		 5432 case 0x3d: /* V9 prefetcha, no effect */
5433 goto skip_move;
5434 case 0x32: /* V9 ldqfa */
64a88d5d 5435 CHECK_FPU_FEATURE(dc, FLOAT128);
5b12f1e8 5436 if (gen_trap_ifnofpu(dc)) {
8872eb4f
TS		 5437 goto jmp_insn;
5438 }
22e70060 5439 gen_ldf_asi(dc, cpu_addr, insn, 16, QFPREG(rd));
f9c816c0 5440 gen_update_fprs_dirty(dc, QFPREG(rd));
1f587329 5441 goto skip_move;
0f8a249a
BS		 5442#endif
5443 default:
5444 goto illegal_insn;
5445 }
97ea2859 5446 gen_store_gpr(dc, rd, cpu_val);
db166940 5447#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
0f8a249a 5448 skip_move: ;
3475187d 5449#endif
0f8a249a 5450 } else if (xop >= 0x20 && xop < 0x24) {
5b12f1e8 5451 if (gen_trap_ifnofpu(dc)) {
a80dde08 5452 goto jmp_insn;
5b12f1e8 5453 }
0f8a249a 5454 switch (xop) {
b89e94af 5455 case 0x20: /* ldf, load fpreg */
2cade6a3 5456 gen_address_mask(dc, cpu_addr);
ba5f5179 5457 cpu_dst_32 = gen_dest_fpr_F(dc);
cb21b4da
RH		 5458 tcg_gen_qemu_ld_i32(cpu_dst_32, cpu_addr,
5459 dc->mem_idx, MO_TEUL);
208ae657 5460 gen_store_fpr_F(dc, rd, cpu_dst_32);
0f8a249a 5461 break;
3a3b925d
BS		 5462 case 0x21: /* ldfsr, V9 ldxfsr */
5463#ifdef TARGET_SPARC64
2cade6a3 5464 gen_address_mask(dc, cpu_addr);
3a3b925d 5465 if (rd == 1) {
abcc7191 5466 TCGv_i64 t64 = tcg_temp_new_i64();
cb21b4da
RH		 5467 tcg_gen_qemu_ld_i64(t64, cpu_addr,
5468 dc->mem_idx, MO_TEQ);
7385aed2 5469 gen_helper_ldxfsr(cpu_fsr, cpu_env, cpu_fsr, t64);
abcc7191 5470 tcg_temp_free_i64(t64);
f8641947 5471 break;
fe987e23 5472 }
f8641947 5473#endif
de9e9d9f 5474 cpu_dst_32 = get_temp_i32(dc);
cb21b4da
RH		 5475 tcg_gen_qemu_ld_i32(cpu_dst_32, cpu_addr,
5476 dc->mem_idx, MO_TEUL);
7385aed2 5477 gen_helper_ldfsr(cpu_fsr, cpu_env, cpu_fsr, cpu_dst_32);
0f8a249a 5478 break;
b89e94af 5479 case 0x22: /* ldqf, load quad fpreg */
f939ffe5
RH		 5480 CHECK_FPU_FEATURE(dc, FLOAT128);
5481 gen_address_mask(dc, cpu_addr);
5482 cpu_src1_64 = tcg_temp_new_i64();
cb21b4da
RH		 5483 tcg_gen_qemu_ld_i64(cpu_src1_64, cpu_addr, dc->mem_idx,
5484 MO_TEQ | MO_ALIGN_4);
f939ffe5
RH		 5485 tcg_gen_addi_tl(cpu_addr, cpu_addr, 8);
5486 cpu_src2_64 = tcg_temp_new_i64();
cb21b4da
RH		 5487 tcg_gen_qemu_ld_i64(cpu_src2_64, cpu_addr, dc->mem_idx,
5488 MO_TEQ | MO_ALIGN_4);
f939ffe5
RH		 5489 gen_store_fpr_Q(dc, rd, cpu_src1_64, cpu_src2_64);
5490 tcg_temp_free_i64(cpu_src1_64);
5491 tcg_temp_free_i64(cpu_src2_64);
1f587329 5492 break;
b89e94af 5493 case 0x23: /* lddf, load double fpreg */
03fb8cfc 5494 gen_address_mask(dc, cpu_addr);
3886b8a3 5495 cpu_dst_64 = gen_dest_fpr_D(dc, rd);
cb21b4da
RH		 5496 tcg_gen_qemu_ld_i64(cpu_dst_64, cpu_addr, dc->mem_idx,
5497 MO_TEQ | MO_ALIGN_4);
03fb8cfc 5498 gen_store_fpr_D(dc, rd, cpu_dst_64);
0f8a249a
BS		 5499 break;
5500 default:
5501 goto illegal_insn;
5502 }
dc1a6971 5503 } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) ||
0f8a249a 5504 xop == 0xe || xop == 0x1e) {
81634eea
RH		 5505 TCGv cpu_val = gen_load_gpr(dc, rd);
5506
0f8a249a 5507 switch (xop) {
b89e94af 5508 case 0x4: /* st, store word */
2cade6a3 5509 gen_address_mask(dc, cpu_addr);
6ae20372 5510 tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5511 break;
b89e94af 5512 case 0x5: /* stb, store byte */
2cade6a3 5513 gen_address_mask(dc, cpu_addr);
6ae20372 5514 tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5515 break;
b89e94af 5516 case 0x6: /* sth, store halfword */
2cade6a3 5517 gen_address_mask(dc, cpu_addr);
6ae20372 5518 tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5519 break;
b89e94af 5520 case 0x7: /* std, store double word */
0f8a249a 5521 if (rd & 1)
d4218d99 5522 goto illegal_insn;
1a2fb1c0 5523 else {
abcc7191 5524 TCGv_i64 t64;
81634eea 5525 TCGv lo;
1a2fb1c0 5526
2cade6a3 5527 gen_address_mask(dc, cpu_addr);
81634eea 5528 lo = gen_load_gpr(dc, rd + 1);
abcc7191
RH		 5529 t64 = tcg_temp_new_i64();
5530 tcg_gen_concat_tl_i64(t64, lo, cpu_val);
5531 tcg_gen_qemu_st64(t64, cpu_addr, dc->mem_idx);
5532 tcg_temp_free_i64(t64);
7fa76c0b 5533 }
0f8a249a 5534 break;
3475187d 5535#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
b89e94af 5536 case 0x14: /* sta, V9 stwa, store word alternate */
1d65b0f5 5537 gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUL);
d39c0b99 5538 break;
b89e94af 5539 case 0x15: /* stba, store byte alternate */
1d65b0f5 5540 gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_UB);
d39c0b99 5541 break;
b89e94af 5542 case 0x16: /* stha, store halfword alternate */
1d65b0f5 5543 gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUW);
d39c0b99 5544 break;
b89e94af 5545 case 0x17: /* stda, store double word alternate */
7ec1e5ea 5546 if (rd & 1) {
0f8a249a 5547 goto illegal_insn;
1a2fb1c0 5548 }
7ec1e5ea 5549 gen_stda_asi(dc, cpu_val, cpu_addr, insn, rd);
d39c0b99 5550 break;
e80cfcfc 5551#endif
3475187d 5552#ifdef TARGET_SPARC64
0f8a249a 5553 case 0x0e: /* V9 stx */
2cade6a3 5554 gen_address_mask(dc, cpu_addr);
6ae20372 5555 tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 5556 break;
5557 case 0x1e: /* V9 stxa */
1d65b0f5 5558 gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEQ);
0f8a249a 5559 break;
3475187d 5560#endif
0f8a249a
BS		 5561 default:
5562 goto illegal_insn;
5563 }
5564 } else if (xop > 0x23 && xop < 0x28) {
5b12f1e8 5565 if (gen_trap_ifnofpu(dc)) {
a80dde08 5566 goto jmp_insn;
5b12f1e8 5567 }
0f8a249a 5568 switch (xop) {
b89e94af 5569 case 0x24: /* stf, store fpreg */
cb21b4da
RH		 5570 gen_address_mask(dc, cpu_addr);
5571 cpu_src1_32 = gen_load_fpr_F(dc, rd);
5572 tcg_gen_qemu_st_i32(cpu_src1_32, cpu_addr,
5573 dc->mem_idx, MO_TEUL);
0f8a249a
BS		 5574 break;
5575 case 0x25: /* stfsr, V9 stxfsr */
f8641947 5576 {
3a3b925d 5577#ifdef TARGET_SPARC64
f8641947
RH		 5578 gen_address_mask(dc, cpu_addr);
5579 if (rd == 1) {
ba2397d1 5580 tcg_gen_qemu_st64(cpu_fsr, cpu_addr, dc->mem_idx);
f8641947
RH		 5581 break;
5582 }
3a3b925d 5583#endif
ba2397d1 5584 tcg_gen_qemu_st32(cpu_fsr, cpu_addr, dc->mem_idx);
f8641947 5585 }
0f8a249a 5586 break;
1f587329
BS		 5587 case 0x26:
5588#ifdef TARGET_SPARC64
1f587329 5589 /* V9 stqf, store quad fpreg */
f939ffe5
RH		 5590 CHECK_FPU_FEATURE(dc, FLOAT128);
5591 gen_address_mask(dc, cpu_addr);
5592 /* ??? While stqf only requires 4-byte alignment, it is
5593 legal for the cpu to signal the unaligned exception.
5594 The OS trap handler is then required to fix it up.
5595 For qemu, this avoids having to probe the second page
5596 before performing the first write. */
5597 cpu_src1_64 = gen_load_fpr_Q0(dc, rd);
5598 tcg_gen_qemu_st_i64(cpu_src1_64, cpu_addr,
5599 dc->mem_idx, MO_TEQ | MO_ALIGN_16);
5600 tcg_gen_addi_tl(cpu_addr, cpu_addr, 8);
5601 cpu_src2_64 = gen_load_fpr_Q1(dc, rd);
5602 tcg_gen_qemu_st_i64(cpu_src1_64, cpu_addr,
5603 dc->mem_idx, MO_TEQ);
1f587329 5604 break;
1f587329
BS		 5605#else /* !TARGET_SPARC64 */
5606 /* stdfq, store floating point queue */
5607#if defined(CONFIG_USER_ONLY)
5608 goto illegal_insn;
5609#else
0f8a249a
BS		 5610 if (!supervisor(dc))
5611 goto priv_insn;
5b12f1e8 5612 if (gen_trap_ifnofpu(dc)) {
0f8a249a 5613 goto jmp_insn;
5b12f1e8 5614 }
0f8a249a 5615 goto nfq_insn;
1f587329 5616#endif
0f8a249a 5617#endif
b89e94af 5618 case 0x27: /* stdf, store double fpreg */
03fb8cfc
RH		 5619 gen_address_mask(dc, cpu_addr);
5620 cpu_src1_64 = gen_load_fpr_D(dc, rd);
cb21b4da
RH		 5621 tcg_gen_qemu_st_i64(cpu_src1_64, cpu_addr, dc->mem_idx,
5622 MO_TEQ | MO_ALIGN_4);
0f8a249a
BS		 5623 break;
5624 default:
5625 goto illegal_insn;
5626 }
5627 } else if (xop > 0x33 && xop < 0x3f) {
5628 switch (xop) {
a4d17f19 5629#ifdef TARGET_SPARC64
0f8a249a 5630 case 0x34: /* V9 stfa */
5b12f1e8 5631 if (gen_trap_ifnofpu(dc)) {
5f06b547
TS		 5632 goto jmp_insn;
5633 }
22e70060 5634 gen_stf_asi(dc, cpu_addr, insn, 4, rd);
0f8a249a 5635 break;
1f587329 5636 case 0x36: /* V9 stqfa */
2ea815ca 5637 {
2ea815ca 5638 CHECK_FPU_FEATURE(dc, FLOAT128);
5b12f1e8 5639 if (gen_trap_ifnofpu(dc)) {
5f06b547
TS		 5640 goto jmp_insn;
5641 }
22e70060 5642 gen_stf_asi(dc, cpu_addr, insn, 16, QFPREG(rd));
2ea815ca 5643 }
1f587329 5644 break;
0f8a249a 5645 case 0x37: /* V9 stdfa */
5b12f1e8 5646 if (gen_trap_ifnofpu(dc)) {
5f06b547
TS		 5647 goto jmp_insn;
5648 }
22e70060 5649 gen_stf_asi(dc, cpu_addr, insn, 8, DFPREG(rd));
0f8a249a 5650 break;
0f8a249a 5651 case 0x3e: /* V9 casxa */
a4273524
RH		 5652 rs2 = GET_FIELD(insn, 27, 31);
5653 cpu_src2 = gen_load_gpr(dc, rs2);
81634eea 5654 gen_casx_asi(dc, cpu_addr, cpu_src2, insn, rd);
0f8a249a 5655 break;
a4d17f19 5656#else
0f8a249a
BS		 5657 case 0x34: /* stc */
5658 case 0x35: /* stcsr */
5659 case 0x36: /* stdcq */
5660 case 0x37: /* stdc */
5661 goto ncp_insn;
16c358e9
SH		 5662#endif
5663#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
5664 case 0x3c: /* V9 or LEON3 casa */
5665#ifndef TARGET_SPARC64
5666 CHECK_IU_FEATURE(dc, CASA);
16c358e9
SH		 5667#endif
5668 rs2 = GET_FIELD(insn, 27, 31);
5669 cpu_src2 = gen_load_gpr(dc, rs2);
5670 gen_cas_asi(dc, cpu_addr, cpu_src2, insn, rd);
5671 break;
0f8a249a
BS		 5672#endif
5673 default:
5674 goto illegal_insn;
5675 }
a4273524 5676 } else {
0f8a249a 5677 goto illegal_insn;
a4273524 5678 }
0f8a249a
BS		 5679 }
5680 break;
cf495bcf
FB		 5681 }
5682 /* default case for non jump instructions */
72cbca10 5683 if (dc->npc == DYNAMIC_PC) {
0f8a249a
BS		 5684 dc->pc = DYNAMIC_PC;
5685 gen_op_next_insn();
72cbca10
FB		 5686 } else if (dc->npc == JUMP_PC) {
5687 /* we can do a static jump */
6ae20372 5688 gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
72cbca10
FB		 5689 dc->is_br = 1;
5690 } else {
0f8a249a
BS		 5691 dc->pc = dc->npc;
5692 dc->npc = dc->npc + 4;
cf495bcf 5693 }
e80cfcfc 5694 jmp_insn:
42a8aa83 5695 goto egress;
cf495bcf 5696 illegal_insn:
4fbe0067 5697 gen_exception(dc, TT_ILL_INSN);
42a8aa83 5698 goto egress;
64a88d5d 5699 unimp_flush:
4fbe0067 5700 gen_exception(dc, TT_UNIMP_FLUSH);
42a8aa83 5701 goto egress;
e80cfcfc 5702#if !defined(CONFIG_USER_ONLY)
e8af50a3 5703 priv_insn:
4fbe0067 5704 gen_exception(dc, TT_PRIV_INSN);
42a8aa83 5705 goto egress;
64a88d5d 5706#endif
e80cfcfc 5707 nfpu_insn:
4fbe0067 5708 gen_op_fpexception_im(dc, FSR_FTT_UNIMPFPOP);
42a8aa83 5709 goto egress;
64a88d5d 5710#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
9143e598 5711 nfq_insn:
4fbe0067 5712 gen_op_fpexception_im(dc, FSR_FTT_SEQ_ERROR);
42a8aa83 5713 goto egress;
9143e598 5714#endif
fcc72045
BS		 5715#ifndef TARGET_SPARC64
5716 ncp_insn:
4fbe0067 5717 gen_exception(dc, TT_NCP_INSN);
42a8aa83 5718 goto egress;
fcc72045 5719#endif
42a8aa83 5720 egress:
30038fd8
RH		 5721 if (dc->n_t32 != 0) {
5722 int i;
5723 for (i = dc->n_t32 - 1; i >= 0; --i) {
5724 tcg_temp_free_i32(dc->t32[i]);
5725 }
5726 dc->n_t32 = 0;
5727 }
88023616
RH		 5728 if (dc->n_ttl != 0) {
5729 int i;
5730 for (i = dc->n_ttl - 1; i >= 0; --i) {
5731 tcg_temp_free(dc->ttl[i]);
5732 }
5733 dc->n_ttl = 0;
5734 }
7a3f1944
FB		 5735}
5736
9c489ea6 5737void gen_intermediate_code(CPUState *cs, TranslationBlock * tb)
7a3f1944 5738{
9c489ea6 5739 CPUSPARCState *env = cs->env_ptr;
72cbca10 5740 target_ulong pc_start, last_pc;
cf495bcf 5741 DisasContext dc1, *dc = &dc1;
2e70f6ef
PB		 5742 int num_insns;
5743 int max_insns;
0184e266 5744 unsigned int insn;
cf495bcf
FB		 5745
5746 memset(dc, 0, sizeof(DisasContext));
cf495bcf 5747 dc->tb = tb;
72cbca10 5748 pc_start = tb->pc;
cf495bcf 5749 dc->pc = pc_start;
e80cfcfc 5750 last_pc = dc->pc;
72cbca10 5751 dc->npc = (target_ulong) tb->cs_base;
8393617c 5752 dc->cc_op = CC_OP_DYNAMIC;
99a23063 5753 dc->mem_idx = tb->flags & TB_FLAG_MMU_MASK;
576e1c4c 5754 dc->def = &env->def;
f838e2c5
BS		 5755 dc->fpu_enabled = tb_fpu_enabled(tb->flags);
5756 dc->address_mask_32bit = tb_am_enabled(tb->flags);
ed2803da 5757 dc->singlestep = (cs->singlestep_enabled || singlestep);
c9b459aa
AT		 5758#ifndef CONFIG_USER_ONLY
5759 dc->supervisor = (tb->flags & TB_FLAG_SUPER) != 0;
5760#endif
a6d567e5 5761#ifdef TARGET_SPARC64
f9c816c0 5762 dc->fprs_dirty = 0;
a6d567e5 5763 dc->asi = (tb->flags >> TB_FLAG_ASI_SHIFT) & 0xff;
c9b459aa
AT		 5764#ifndef CONFIG_USER_ONLY
5765 dc->hypervisor = (tb->flags & TB_FLAG_HYPER) != 0;
5766#endif
a6d567e5 5767#endif
cf495bcf 5768
2e70f6ef
PB		 5769 num_insns = 0;
5770 max_insns = tb->cflags & CF_COUNT_MASK;
190ce7fb 5771 if (max_insns == 0) {
2e70f6ef 5772 max_insns = CF_COUNT_MASK;
190ce7fb
RH		 5773 }
5774 if (max_insns > TCG_MAX_INSNS) {
5775 max_insns = TCG_MAX_INSNS;
5776 }
5777
cd42d5b2 5778 gen_tb_start(tb);
cf495bcf 5779 do {
a3d5ad76
RH		 5780 if (dc->npc & JUMP_PC) {
5781 assert(dc->jump_pc[1] == dc->pc + 4);
5782 tcg_gen_insn_start(dc->pc, dc->jump_pc[0] | JUMP_PC);
5783 } else {
5784 tcg_gen_insn_start(dc->pc, dc->npc);
5785 }
959082fc 5786 num_insns++;
522a0d4e 5787 last_pc = dc->pc;
667b8e29 5788
b933066a
RH		 5789 if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
5790 if (dc->pc != pc_start) {
5791 save_state(dc);
5792 }
5793 gen_helper_debug(cpu_env);
5794 tcg_gen_exit_tb(0);
5795 dc->is_br = 1;
5796 goto exit_gen_loop;
5797 }
5798
959082fc 5799 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
2e70f6ef 5800 gen_io_start();
667b8e29
RH		 5801 }
5802
0184e266 5803 insn = cpu_ldl_code(env, dc->pc);
b09b2fd3 5804
0184e266 5805 disas_sparc_insn(dc, insn);
0f8a249a
BS		 5806
5807 if (dc->is_br)
5808 break;
5809 /* if the next PC is different, we abort now */
5810 if (dc->pc != (last_pc + 4))
5811 break;
d39c0b99
FB		 5812 /* if we reach a page boundary, we stop generation so that the
5813 PC of a TT_TFAULT exception is always in the right page */
5814 if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
5815 break;
e80cfcfc
FB		 5816 /* if single step mode, we generate only one instruction and
5817 generate an exception */
060718c1 5818 if (dc->singlestep) {
e80cfcfc
FB		 5819 break;
5820 }
fe700adb 5821 } while (!tcg_op_buf_full() &&
2e70f6ef
PB		 5822 (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32) &&
5823 num_insns < max_insns);
e80cfcfc
FB		 5824
5825 exit_gen_loop:
b09b2fd3 5826 if (tb->cflags & CF_LAST_IO) {
2e70f6ef 5827 gen_io_end();
b09b2fd3 5828 }
72cbca10 5829 if (!dc->is_br) {
5fafdf24 5830 if (dc->pc != DYNAMIC_PC &&
72cbca10
FB		 5831 (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
5832 /* static PC and NPC: we can use direct chaining */
2f5680ee 5833 gen_goto_tb(dc, 0, dc->pc, dc->npc);
72cbca10 5834 } else {
b09b2fd3 5835 if (dc->pc != DYNAMIC_PC) {
2f5680ee 5836 tcg_gen_movi_tl(cpu_pc, dc->pc);
b09b2fd3 5837 }
934da7ee 5838 save_npc(dc);
57fec1fe 5839 tcg_gen_exit_tb(0);
72cbca10
FB		 5840 }
5841 }
806f352d 5842 gen_tb_end(tb, num_insns);
0a7df5da 5843
4e5e1215
RH		 5844 tb->size = last_pc + 4 - pc_start;
5845 tb->icount = num_insns;
5846
7a3f1944 5847#ifdef DEBUG_DISAS
4910e6e4
RH		 5848 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
5849 && qemu_log_in_addr_range(pc_start)) {
1ee73216 5850 qemu_log_lock();
93fcfe39
AL		 5851 qemu_log("--------------\n");
5852 qemu_log("IN: %s\n", lookup_symbol(pc_start));
d49190c4 5853 log_target_disas(cs, pc_start, last_pc + 4 - pc_start, 0);
93fcfe39 5854 qemu_log("\n");
1ee73216 5855 qemu_log_unlock();
cf495bcf 5856 }
7a3f1944 5857#endif
7a3f1944
FB		 5858}
5859
55c3ceef 5860void sparc_tcg_init(void)
e80cfcfc 5861{
d2dc4069 5862 static const char gregnames[32][4] = {
0ea63844 5863 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
d2dc4069
RH		 5864 "o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7",
5865 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
5866 "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7",
f5069b26 5867 };
0ea63844 5868 static const char fregnames[32][4] = {
30038fd8
RH		 5869 "f0", "f2", "f4", "f6", "f8", "f10", "f12", "f14",
5870 "f16", "f18", "f20", "f22", "f24", "f26", "f28", "f30",
5871 "f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46",
5872 "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62",
714547bb 5873 };
aaed909a 5874
0ea63844 5875 static const struct { TCGv_i32 *ptr; int off; const char *name; } r32[] = {
1a2fb1c0 5876#ifdef TARGET_SPARC64
0ea63844 5877 { &cpu_xcc, offsetof(CPUSPARCState, xcc), "xcc" },
0ea63844 5878 { &cpu_fprs, offsetof(CPUSPARCState, fprs), "fprs" },
255e1fcb 5879#else
0ea63844
RH		 5880 { &cpu_wim, offsetof(CPUSPARCState, wim), "wim" },
5881#endif
5882 { &cpu_cc_op, offsetof(CPUSPARCState, cc_op), "cc_op" },
5883 { &cpu_psr, offsetof(CPUSPARCState, psr), "psr" },
5884 };
5885
5886 static const struct { TCGv *ptr; int off; const char *name; } rtl[] = {
5887#ifdef TARGET_SPARC64
5888 { &cpu_gsr, offsetof(CPUSPARCState, gsr), "gsr" },
5889 { &cpu_tick_cmpr, offsetof(CPUSPARCState, tick_cmpr), "tick_cmpr" },
5890 { &cpu_stick_cmpr, offsetof(CPUSPARCState, stick_cmpr), "stick_cmpr" },
5891 { &cpu_hstick_cmpr, offsetof(CPUSPARCState, hstick_cmpr),
5892 "hstick_cmpr" },
5893 { &cpu_hintp, offsetof(CPUSPARCState, hintp), "hintp" },
5894 { &cpu_htba, offsetof(CPUSPARCState, htba), "htba" },
5895 { &cpu_hver, offsetof(CPUSPARCState, hver), "hver" },
5896 { &cpu_ssr, offsetof(CPUSPARCState, ssr), "ssr" },
5897 { &cpu_ver, offsetof(CPUSPARCState, version), "ver" },
1a2fb1c0 5898#endif
0ea63844
RH		 5899 { &cpu_cond, offsetof(CPUSPARCState, cond), "cond" },
5900 { &cpu_cc_src, offsetof(CPUSPARCState, cc_src), "cc_src" },
5901 { &cpu_cc_src2, offsetof(CPUSPARCState, cc_src2), "cc_src2" },
5902 { &cpu_cc_dst, offsetof(CPUSPARCState, cc_dst), "cc_dst" },
5903 { &cpu_fsr, offsetof(CPUSPARCState, fsr), "fsr" },
5904 { &cpu_pc, offsetof(CPUSPARCState, pc), "pc" },
5905 { &cpu_npc, offsetof(CPUSPARCState, npc), "npc" },
5906 { &cpu_y, offsetof(CPUSPARCState, y), "y" },
255e1fcb 5907#ifndef CONFIG_USER_ONLY
0ea63844 5908 { &cpu_tbr, offsetof(CPUSPARCState, tbr), "tbr" },
255e1fcb 5909#endif
0ea63844
RH		 5910 };
5911
5912 unsigned int i;
5913
0ea63844 5914 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
7c255043 5915 tcg_ctx.tcg_env = cpu_env;
0ea63844
RH		 5916
5917 cpu_regwptr = tcg_global_mem_new_ptr(cpu_env,
5918 offsetof(CPUSPARCState, regwptr),
5919 "regwptr");
5920
5921 for (i = 0; i < ARRAY_SIZE(r32); ++i) {
5922 *r32[i].ptr = tcg_global_mem_new_i32(cpu_env, r32[i].off, r32[i].name);
5923 }
5924
5925 for (i = 0; i < ARRAY_SIZE(rtl); ++i) {
5926 *rtl[i].ptr = tcg_global_mem_new(cpu_env, rtl[i].off, rtl[i].name);
5927 }
5928
d2dc4069 5929 TCGV_UNUSED(cpu_regs[0]);
0ea63844 5930 for (i = 1; i < 8; ++i) {
d2dc4069
RH		 5931 cpu_regs[i] = tcg_global_mem_new(cpu_env,
5932 offsetof(CPUSPARCState, gregs[i]),
5933 gregnames[i]);
5934 }
5935
5936 for (i = 8; i < 32; ++i) {
5937 cpu_regs[i] = tcg_global_mem_new(cpu_regwptr,
5938 (i - 8) * sizeof(target_ulong),
5939 gregnames[i]);
0ea63844
RH		 5940 }
5941
5942 for (i = 0; i < TARGET_DPREGS; i++) {
5943 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
5944 offsetof(CPUSPARCState, fpr[i]),
5945 fregnames[i]);
1a2fb1c0 5946 }
658138bc 5947}
d2856f1a 5948
bad729e2
RH		 5949void restore_state_to_opc(CPUSPARCState *env, TranslationBlock *tb,
5950 target_ulong *data)
d2856f1a 5951{
bad729e2
RH		 5952 target_ulong pc = data[0];
5953 target_ulong npc = data[1];
5954
5955 env->pc = pc;
6c42444f 5956 if (npc == DYNAMIC_PC) {
d2856f1a 5957 /* dynamic NPC: already stored */
6c42444f 5958 } else if (npc & JUMP_PC) {
d7da2a10
BS		 5959 /* jump PC: use 'cond' and the jump targets of the translation */
5960 if (env->cond) {
6c42444f 5961 env->npc = npc & ~3;
d7da2a10 5962 } else {
6c42444f 5963 env->npc = pc + 4;
d7da2a10 5964 }
d2856f1a
AJ		 5965 } else {
5966 env->npc = npc;
5967 }
5968}
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