]>
Commit | Line | Data |
---|---|---|
48e06fe0 BK |
1 | /* |
2 | * TriCore emulation for qemu: main translation routines. | |
3 | * | |
4 | * Copyright (c) 2013-2014 Bastian Koppelmann C-Lab/University Paderborn | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
02754acd | 9 | * version 2.1 of the License, or (at your option) any later version. |
48e06fe0 BK |
10 | * |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | ||
61d9f32b | 21 | #include "qemu/osdep.h" |
48e06fe0 BK |
22 | #include "cpu.h" |
23 | #include "disas/disas.h" | |
63c91552 | 24 | #include "exec/exec-all.h" |
dcb32f1d | 25 | #include "tcg/tcg-op.h" |
48e06fe0 | 26 | #include "exec/cpu_ldst.h" |
90c84c56 | 27 | #include "qemu/qemu-print.h" |
48e06fe0 BK |
28 | |
29 | #include "exec/helper-proto.h" | |
30 | #include "exec/helper-gen.h" | |
31 | ||
7c87d074 | 32 | #include "tricore-opcodes.h" |
6b9f5a42 | 33 | #include "exec/translator.h" |
508127e2 | 34 | #include "exec/log.h" |
0707ec1b | 35 | |
d53106c9 RH |
36 | #define HELPER_H "helper.h" |
37 | #include "exec/helper-info.c.inc" | |
38 | #undef HELPER_H | |
39 | ||
1706e04f | 40 | #define DISAS_EXIT DISAS_TARGET_0 |
2dbd73bf | 41 | #define DISAS_EXIT_UPDATE DISAS_TARGET_1 |
d8f466af | 42 | #define DISAS_JUMP DISAS_TARGET_2 |
d53106c9 | 43 | |
0aaeb118 BK |
44 | /* |
45 | * TCG registers | |
46 | */ | |
47 | static TCGv cpu_PC; | |
48 | static TCGv cpu_PCXI; | |
49 | static TCGv cpu_PSW; | |
50 | static TCGv cpu_ICR; | |
51 | /* GPR registers */ | |
52 | static TCGv cpu_gpr_a[16]; | |
53 | static TCGv cpu_gpr_d[16]; | |
54 | /* PSW Flag cache */ | |
55 | static TCGv cpu_PSW_C; | |
56 | static TCGv cpu_PSW_V; | |
57 | static TCGv cpu_PSW_SV; | |
58 | static TCGv cpu_PSW_AV; | |
59 | static TCGv cpu_PSW_SAV; | |
0aaeb118 | 60 | |
48e06fe0 BK |
61 | static const char *regnames_a[] = { |
62 | "a0" , "a1" , "a2" , "a3" , "a4" , "a5" , | |
63 | "a6" , "a7" , "a8" , "a9" , "sp" , "a11" , | |
64 | "a12" , "a13" , "a14" , "a15", | |
65 | }; | |
66 | ||
67 | static const char *regnames_d[] = { | |
68 | "d0" , "d1" , "d2" , "d3" , "d4" , "d5" , | |
69 | "d6" , "d7" , "d8" , "d9" , "d10" , "d11" , | |
70 | "d12" , "d13" , "d14" , "d15", | |
71 | }; | |
72 | ||
0aaeb118 | 73 | typedef struct DisasContext { |
6b9f5a42 BK |
74 | DisasContextBase base; |
75 | target_ulong pc_succ_insn; | |
0aaeb118 | 76 | uint32_t opcode; |
0aaeb118 BK |
77 | /* Routine used to access memory */ |
78 | int mem_idx; | |
878d1b6a | 79 | int priv; |
44ee3baf | 80 | uint64_t features; |
0b9f9b63 | 81 | uint32_t icr_ie_mask, icr_ie_offset; |
0aaeb118 BK |
82 | } DisasContext; |
83 | ||
44ee3baf BK |
84 | static int has_feature(DisasContext *ctx, int feature) |
85 | { | |
86 | return (ctx->features & (1ULL << feature)) != 0; | |
87 | } | |
88 | ||
2e430e1c BK |
89 | enum { |
90 | MODE_LL = 0, | |
91 | MODE_LU = 1, | |
92 | MODE_UL = 2, | |
93 | MODE_UU = 3, | |
94 | }; | |
95 | ||
90c84c56 | 96 | void tricore_cpu_dump_state(CPUState *cs, FILE *f, int flags) |
48e06fe0 BK |
97 | { |
98 | TriCoreCPU *cpu = TRICORE_CPU(cs); | |
99 | CPUTriCoreState *env = &cpu->env; | |
45820fcc | 100 | uint32_t psw; |
48e06fe0 BK |
101 | int i; |
102 | ||
45820fcc AZ |
103 | psw = psw_read(env); |
104 | ||
90c84c56 MA |
105 | qemu_fprintf(f, "PC: " TARGET_FMT_lx, env->PC); |
106 | qemu_fprintf(f, " PSW: " TARGET_FMT_lx, psw); | |
107 | qemu_fprintf(f, " ICR: " TARGET_FMT_lx, env->ICR); | |
108 | qemu_fprintf(f, "\nPCXI: " TARGET_FMT_lx, env->PCXI); | |
109 | qemu_fprintf(f, " FCX: " TARGET_FMT_lx, env->FCX); | |
110 | qemu_fprintf(f, " LCX: " TARGET_FMT_lx, env->LCX); | |
45820fcc | 111 | |
48e06fe0 BK |
112 | for (i = 0; i < 16; ++i) { |
113 | if ((i & 3) == 0) { | |
90c84c56 | 114 | qemu_fprintf(f, "\nGPR A%02d:", i); |
48e06fe0 | 115 | } |
90c84c56 | 116 | qemu_fprintf(f, " " TARGET_FMT_lx, env->gpr_a[i]); |
48e06fe0 BK |
117 | } |
118 | for (i = 0; i < 16; ++i) { | |
119 | if ((i & 3) == 0) { | |
90c84c56 | 120 | qemu_fprintf(f, "\nGPR D%02d:", i); |
48e06fe0 | 121 | } |
90c84c56 | 122 | qemu_fprintf(f, " " TARGET_FMT_lx, env->gpr_d[i]); |
48e06fe0 | 123 | } |
90c84c56 | 124 | qemu_fprintf(f, "\n"); |
48e06fe0 BK |
125 | } |
126 | ||
0707ec1b BK |
127 | /* |
128 | * Functions to generate micro-ops | |
129 | */ | |
130 | ||
8b81968c | 131 | /* Macros for generating helpers */ |
9a31922b BK |
132 | |
133 | #define gen_helper_1arg(name, arg) do { \ | |
151293c2 | 134 | TCGv_i32 helper_tmp = tcg_constant_i32(arg); \ |
ad75a51e | 135 | gen_helper_##name(tcg_env, helper_tmp); \ |
9a31922b BK |
136 | } while (0) |
137 | ||
9655b932 BK |
138 | #define GEN_HELPER_LL(name, ret, arg0, arg1, n) do { \ |
139 | TCGv arg00 = tcg_temp_new(); \ | |
140 | TCGv arg01 = tcg_temp_new(); \ | |
141 | TCGv arg11 = tcg_temp_new(); \ | |
142 | tcg_gen_sari_tl(arg00, arg0, 16); \ | |
143 | tcg_gen_ext16s_tl(arg01, arg0); \ | |
144 | tcg_gen_ext16s_tl(arg11, arg1); \ | |
145 | gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \ | |
9655b932 BK |
146 | } while (0) |
147 | ||
148 | #define GEN_HELPER_LU(name, ret, arg0, arg1, n) do { \ | |
149 | TCGv arg00 = tcg_temp_new(); \ | |
150 | TCGv arg01 = tcg_temp_new(); \ | |
151 | TCGv arg10 = tcg_temp_new(); \ | |
152 | TCGv arg11 = tcg_temp_new(); \ | |
153 | tcg_gen_sari_tl(arg00, arg0, 16); \ | |
154 | tcg_gen_ext16s_tl(arg01, arg0); \ | |
155 | tcg_gen_sari_tl(arg11, arg1, 16); \ | |
156 | tcg_gen_ext16s_tl(arg10, arg1); \ | |
157 | gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \ | |
9655b932 BK |
158 | } while (0) |
159 | ||
160 | #define GEN_HELPER_UL(name, ret, arg0, arg1, n) do { \ | |
161 | TCGv arg00 = tcg_temp_new(); \ | |
162 | TCGv arg01 = tcg_temp_new(); \ | |
163 | TCGv arg10 = tcg_temp_new(); \ | |
164 | TCGv arg11 = tcg_temp_new(); \ | |
165 | tcg_gen_sari_tl(arg00, arg0, 16); \ | |
166 | tcg_gen_ext16s_tl(arg01, arg0); \ | |
167 | tcg_gen_sari_tl(arg10, arg1, 16); \ | |
168 | tcg_gen_ext16s_tl(arg11, arg1); \ | |
169 | gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \ | |
9655b932 BK |
170 | } while (0) |
171 | ||
172 | #define GEN_HELPER_UU(name, ret, arg0, arg1, n) do { \ | |
173 | TCGv arg00 = tcg_temp_new(); \ | |
174 | TCGv arg01 = tcg_temp_new(); \ | |
175 | TCGv arg11 = tcg_temp_new(); \ | |
176 | tcg_gen_sari_tl(arg01, arg0, 16); \ | |
177 | tcg_gen_ext16s_tl(arg00, arg0); \ | |
178 | tcg_gen_sari_tl(arg11, arg1, 16); \ | |
179 | gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \ | |
9655b932 BK |
180 | } while (0) |
181 | ||
09532255 BK |
182 | #define GEN_HELPER_RRR(name, rl, rh, al1, ah1, arg2) do { \ |
183 | TCGv_i64 ret = tcg_temp_new_i64(); \ | |
184 | TCGv_i64 arg1 = tcg_temp_new_i64(); \ | |
185 | \ | |
186 | tcg_gen_concat_i32_i64(arg1, al1, ah1); \ | |
187 | gen_helper_##name(ret, arg1, arg2); \ | |
188 | tcg_gen_extr_i64_i32(rl, rh, ret); \ | |
09532255 BK |
189 | } while (0) |
190 | ||
93715571 BK |
191 | #define GEN_HELPER_RR(name, rl, rh, arg1, arg2) do { \ |
192 | TCGv_i64 ret = tcg_temp_new_i64(); \ | |
193 | \ | |
ad75a51e | 194 | gen_helper_##name(ret, tcg_env, arg1, arg2); \ |
93715571 | 195 | tcg_gen_extr_i64_i32(rl, rh, ret); \ |
93715571 BK |
196 | } while (0) |
197 | ||
59543d4e | 198 | #define EA_ABS_FORMAT(con) (((con & 0x3C000) << 14) + (con & 0x3FFF)) |
f718b0bb BK |
199 | #define EA_B_ABSOLUT(con) (((offset & 0xf00000) << 8) | \ |
200 | ((offset & 0x0fffff) << 1)) | |
59543d4e | 201 | |
828066c7 BK |
202 | /* For two 32-bit registers used a 64-bit register, the first |
203 | registernumber needs to be even. Otherwise we trap. */ | |
204 | static inline void generate_trap(DisasContext *ctx, int class, int tin); | |
205 | #define CHECK_REG_PAIR(reg) do { \ | |
206 | if (reg & 0x1) { \ | |
207 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_OPD); \ | |
208 | } \ | |
209 | } while (0) | |
210 | ||
d2798210 BK |
211 | /* Functions for load/save to/from memory */ |
212 | ||
213 | static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2, | |
14776ab5 | 214 | int16_t con, MemOp mop) |
d2798210 BK |
215 | { |
216 | TCGv temp = tcg_temp_new(); | |
217 | tcg_gen_addi_tl(temp, r2, con); | |
218 | tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop); | |
d2798210 BK |
219 | } |
220 | ||
221 | static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2, | |
14776ab5 | 222 | int16_t con, MemOp mop) |
d2798210 BK |
223 | { |
224 | TCGv temp = tcg_temp_new(); | |
225 | tcg_gen_addi_tl(temp, r2, con); | |
226 | tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop); | |
d2798210 BK |
227 | } |
228 | ||
59543d4e BK |
229 | static void gen_st_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx) |
230 | { | |
231 | TCGv_i64 temp = tcg_temp_new_i64(); | |
232 | ||
233 | tcg_gen_concat_i32_i64(temp, rl, rh); | |
fc313c64 | 234 | tcg_gen_qemu_st_i64(temp, address, ctx->mem_idx, MO_LEUQ); |
59543d4e BK |
235 | } |
236 | ||
3a16ecb0 BK |
237 | static void gen_offset_st_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con, |
238 | DisasContext *ctx) | |
239 | { | |
240 | TCGv temp = tcg_temp_new(); | |
241 | tcg_gen_addi_tl(temp, base, con); | |
242 | gen_st_2regs_64(rh, rl, temp, ctx); | |
3a16ecb0 BK |
243 | } |
244 | ||
59543d4e BK |
245 | static void gen_ld_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx) |
246 | { | |
247 | TCGv_i64 temp = tcg_temp_new_i64(); | |
248 | ||
fc313c64 | 249 | tcg_gen_qemu_ld_i64(temp, address, ctx->mem_idx, MO_LEUQ); |
59543d4e BK |
250 | /* write back to two 32 bit regs */ |
251 | tcg_gen_extr_i64_i32(rl, rh, temp); | |
59543d4e BK |
252 | } |
253 | ||
3a16ecb0 BK |
254 | static void gen_offset_ld_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con, |
255 | DisasContext *ctx) | |
256 | { | |
257 | TCGv temp = tcg_temp_new(); | |
258 | tcg_gen_addi_tl(temp, base, con); | |
259 | gen_ld_2regs_64(rh, rl, temp, ctx); | |
3a16ecb0 BK |
260 | } |
261 | ||
262 | static void gen_st_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off, | |
14776ab5 | 263 | MemOp mop) |
3a16ecb0 BK |
264 | { |
265 | TCGv temp = tcg_temp_new(); | |
266 | tcg_gen_addi_tl(temp, r2, off); | |
267 | tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop); | |
268 | tcg_gen_mov_tl(r2, temp); | |
3a16ecb0 BK |
269 | } |
270 | ||
271 | static void gen_ld_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off, | |
14776ab5 | 272 | MemOp mop) |
3a16ecb0 BK |
273 | { |
274 | TCGv temp = tcg_temp_new(); | |
275 | tcg_gen_addi_tl(temp, r2, off); | |
276 | tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop); | |
277 | tcg_gen_mov_tl(r2, temp); | |
3a16ecb0 BK |
278 | } |
279 | ||
59543d4e BK |
280 | /* M(EA, word) = (M(EA, word) & ~E[a][63:32]) | (E[a][31:0] & E[a][63:32]); */ |
281 | static void gen_ldmst(DisasContext *ctx, int ereg, TCGv ea) | |
282 | { | |
283 | TCGv temp = tcg_temp_new(); | |
284 | TCGv temp2 = tcg_temp_new(); | |
285 | ||
828066c7 | 286 | CHECK_REG_PAIR(ereg); |
59543d4e BK |
287 | /* temp = (M(EA, word) */ |
288 | tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); | |
289 | /* temp = temp & ~E[a][63:32]) */ | |
290 | tcg_gen_andc_tl(temp, temp, cpu_gpr_d[ereg+1]); | |
291 | /* temp2 = (E[a][31:0] & E[a][63:32]); */ | |
292 | tcg_gen_and_tl(temp2, cpu_gpr_d[ereg], cpu_gpr_d[ereg+1]); | |
293 | /* temp = temp | temp2; */ | |
294 | tcg_gen_or_tl(temp, temp, temp2); | |
295 | /* M(EA, word) = temp; */ | |
296 | tcg_gen_qemu_st_tl(temp, ea, ctx->mem_idx, MO_LEUL); | |
59543d4e BK |
297 | } |
298 | ||
299 | /* tmp = M(EA, word); | |
300 | M(EA, word) = D[a]; | |
301 | D[a] = tmp[31:0];*/ | |
302 | static void gen_swap(DisasContext *ctx, int reg, TCGv ea) | |
303 | { | |
304 | TCGv temp = tcg_temp_new(); | |
305 | ||
306 | tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); | |
307 | tcg_gen_qemu_st_tl(cpu_gpr_d[reg], ea, ctx->mem_idx, MO_LEUL); | |
308 | tcg_gen_mov_tl(cpu_gpr_d[reg], temp); | |
59543d4e BK |
309 | } |
310 | ||
62872ebc BK |
311 | static void gen_cmpswap(DisasContext *ctx, int reg, TCGv ea) |
312 | { | |
313 | TCGv temp = tcg_temp_new(); | |
314 | TCGv temp2 = tcg_temp_new(); | |
6991777e | 315 | CHECK_REG_PAIR(reg); |
62872ebc BK |
316 | tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); |
317 | tcg_gen_movcond_tl(TCG_COND_EQ, temp2, cpu_gpr_d[reg+1], temp, | |
318 | cpu_gpr_d[reg], temp); | |
319 | tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL); | |
320 | tcg_gen_mov_tl(cpu_gpr_d[reg], temp); | |
62872ebc BK |
321 | } |
322 | ||
ddd8cebe BK |
323 | static void gen_swapmsk(DisasContext *ctx, int reg, TCGv ea) |
324 | { | |
325 | TCGv temp = tcg_temp_new(); | |
326 | TCGv temp2 = tcg_temp_new(); | |
327 | TCGv temp3 = tcg_temp_new(); | |
6991777e | 328 | CHECK_REG_PAIR(reg); |
ddd8cebe BK |
329 | tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); |
330 | tcg_gen_and_tl(temp2, cpu_gpr_d[reg], cpu_gpr_d[reg+1]); | |
331 | tcg_gen_andc_tl(temp3, temp, cpu_gpr_d[reg+1]); | |
332 | tcg_gen_or_tl(temp2, temp2, temp3); | |
333 | tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL); | |
334 | tcg_gen_mov_tl(cpu_gpr_d[reg], temp); | |
ddd8cebe BK |
335 | } |
336 | ||
2b2f7d97 BK |
337 | /* We generate loads and store to core special function register (csfr) through |
338 | the function gen_mfcr and gen_mtcr. To handle access permissions, we use 3 | |
8b81968c MT |
339 | macros R, A and E, which allow read-only, all and endinit protected access. |
340 | These macros also specify in which ISA version the csfr was introduced. */ | |
2b2f7d97 BK |
341 | #define R(ADDRESS, REG, FEATURE) \ |
342 | case ADDRESS: \ | |
44ee3baf | 343 | if (has_feature(ctx, FEATURE)) { \ |
ad75a51e | 344 | tcg_gen_ld_tl(ret, tcg_env, offsetof(CPUTriCoreState, REG)); \ |
2b2f7d97 BK |
345 | } \ |
346 | break; | |
347 | #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) | |
348 | #define E(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) | |
2db92a0c | 349 | static inline void gen_mfcr(DisasContext *ctx, TCGv ret, int32_t offset) |
2b2f7d97 BK |
350 | { |
351 | /* since we're caching PSW make this a special case */ | |
352 | if (offset == 0xfe04) { | |
ad75a51e | 353 | gen_helper_psw_read(ret, tcg_env); |
2b2f7d97 BK |
354 | } else { |
355 | switch (offset) { | |
5d756c82 | 356 | #include "csfr.h.inc" |
2b2f7d97 BK |
357 | } |
358 | } | |
359 | } | |
360 | #undef R | |
361 | #undef A | |
362 | #undef E | |
363 | ||
364 | #define R(ADDRESS, REG, FEATURE) /* don't gen writes to read-only reg, | |
8b81968c | 365 | since no exception occurs */ |
2b2f7d97 BK |
366 | #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) \ |
367 | case ADDRESS: \ | |
44ee3baf | 368 | if (has_feature(ctx, FEATURE)) { \ |
ad75a51e | 369 | tcg_gen_st_tl(r1, tcg_env, offsetof(CPUTriCoreState, REG)); \ |
2b2f7d97 BK |
370 | } \ |
371 | break; | |
372 | /* Endinit protected registers | |
373 | TODO: Since the endinit bit is in a register of a not yet implemented | |
374 | watchdog device, we handle endinit protected registers like | |
375 | all-access registers for now. */ | |
376 | #define E(ADDRESS, REG, FEATURE) A(ADDRESS, REG, FEATURE) | |
2db92a0c | 377 | static inline void gen_mtcr(DisasContext *ctx, TCGv r1, |
2b2f7d97 BK |
378 | int32_t offset) |
379 | { | |
878d1b6a | 380 | if (ctx->priv == TRICORE_PRIV_SM) { |
2b2f7d97 BK |
381 | /* since we're caching PSW make this a special case */ |
382 | if (offset == 0xfe04) { | |
ad75a51e | 383 | gen_helper_psw_write(tcg_env, r1); |
19a18edd | 384 | ctx->base.is_jmp = DISAS_EXIT_UPDATE; |
2b2f7d97 BK |
385 | } else { |
386 | switch (offset) { | |
5d756c82 | 387 | #include "csfr.h.inc" |
2b2f7d97 BK |
388 | } |
389 | } | |
390 | } else { | |
57b9c589 | 391 | generate_trap(ctx, TRAPC_PROT, TIN1_PRIV); |
2b2f7d97 BK |
392 | } |
393 | } | |
394 | ||
0707ec1b BK |
395 | /* Functions for arithmetic instructions */ |
396 | ||
397 | static inline void gen_add_d(TCGv ret, TCGv r1, TCGv r2) | |
398 | { | |
399 | TCGv t0 = tcg_temp_new_i32(); | |
400 | TCGv result = tcg_temp_new_i32(); | |
401 | /* Addition and set V/SV bits */ | |
402 | tcg_gen_add_tl(result, r1, r2); | |
403 | /* calc V bit */ | |
404 | tcg_gen_xor_tl(cpu_PSW_V, result, r1); | |
405 | tcg_gen_xor_tl(t0, r1, r2); | |
406 | tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0); | |
407 | /* Calc SV bit */ | |
408 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
409 | /* Calc AV/SAV bits */ | |
410 | tcg_gen_add_tl(cpu_PSW_AV, result, result); | |
411 | tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); | |
412 | /* calc SAV */ | |
413 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
414 | /* write back result */ | |
415 | tcg_gen_mov_tl(ret, result); | |
0707ec1b BK |
416 | } |
417 | ||
2e430e1c BK |
418 | static inline void |
419 | gen_add64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2) | |
420 | { | |
421 | TCGv temp = tcg_temp_new(); | |
422 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
423 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
424 | TCGv_i64 result = tcg_temp_new_i64(); | |
425 | ||
426 | tcg_gen_add_i64(result, r1, r2); | |
427 | /* calc v bit */ | |
428 | tcg_gen_xor_i64(t1, result, r1); | |
429 | tcg_gen_xor_i64(t0, r1, r2); | |
430 | tcg_gen_andc_i64(t1, t1, t0); | |
609ad705 | 431 | tcg_gen_extrh_i64_i32(cpu_PSW_V, t1); |
2e430e1c BK |
432 | /* calc SV bit */ |
433 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
434 | /* calc AV/SAV bits */ | |
609ad705 | 435 | tcg_gen_extrh_i64_i32(temp, result); |
2e430e1c BK |
436 | tcg_gen_add_tl(cpu_PSW_AV, temp, temp); |
437 | tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV); | |
438 | /* calc SAV */ | |
439 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
440 | /* write back result */ | |
441 | tcg_gen_mov_i64(ret, result); | |
2e430e1c BK |
442 | } |
443 | ||
444 | static inline void | |
445 | gen_addsub64_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, | |
446 | TCGv r3, void(*op1)(TCGv, TCGv, TCGv), | |
447 | void(*op2)(TCGv, TCGv, TCGv)) | |
448 | { | |
449 | TCGv temp = tcg_temp_new(); | |
450 | TCGv temp2 = tcg_temp_new(); | |
451 | TCGv temp3 = tcg_temp_new(); | |
452 | TCGv temp4 = tcg_temp_new(); | |
453 | ||
454 | (*op1)(temp, r1_low, r2); | |
455 | /* calc V0 bit */ | |
456 | tcg_gen_xor_tl(temp2, temp, r1_low); | |
457 | tcg_gen_xor_tl(temp3, r1_low, r2); | |
458 | if (op1 == tcg_gen_add_tl) { | |
459 | tcg_gen_andc_tl(temp2, temp2, temp3); | |
460 | } else { | |
461 | tcg_gen_and_tl(temp2, temp2, temp3); | |
462 | } | |
463 | ||
464 | (*op2)(temp3, r1_high, r3); | |
465 | /* calc V1 bit */ | |
466 | tcg_gen_xor_tl(cpu_PSW_V, temp3, r1_high); | |
467 | tcg_gen_xor_tl(temp4, r1_high, r3); | |
468 | if (op2 == tcg_gen_add_tl) { | |
469 | tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, temp4); | |
470 | } else { | |
471 | tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp4); | |
472 | } | |
473 | /* combine V0/V1 bits */ | |
474 | tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp2); | |
475 | /* calc sv bit */ | |
476 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
477 | /* write result */ | |
478 | tcg_gen_mov_tl(ret_low, temp); | |
479 | tcg_gen_mov_tl(ret_high, temp3); | |
480 | /* calc AV bit */ | |
481 | tcg_gen_add_tl(temp, ret_low, ret_low); | |
482 | tcg_gen_xor_tl(temp, temp, ret_low); | |
483 | tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); | |
484 | tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, ret_high); | |
485 | tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp); | |
486 | /* calc SAV bit */ | |
487 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
2e430e1c BK |
488 | } |
489 | ||
328f1f0f BK |
490 | /* ret = r2 + (r1 * r3); */ |
491 | static inline void gen_madd32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3) | |
492 | { | |
493 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
494 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
495 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
496 | ||
497 | tcg_gen_ext_i32_i64(t1, r1); | |
498 | tcg_gen_ext_i32_i64(t2, r2); | |
499 | tcg_gen_ext_i32_i64(t3, r3); | |
500 | ||
501 | tcg_gen_mul_i64(t1, t1, t3); | |
502 | tcg_gen_add_i64(t1, t2, t1); | |
503 | ||
ecc7b3aa | 504 | tcg_gen_extrl_i64_i32(ret, t1); |
328f1f0f BK |
505 | /* calc V |
506 | t1 > 0x7fffffff */ | |
507 | tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL); | |
508 | /* t1 < -0x80000000 */ | |
509 | tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL); | |
510 | tcg_gen_or_i64(t2, t2, t3); | |
ecc7b3aa | 511 | tcg_gen_extrl_i64_i32(cpu_PSW_V, t2); |
328f1f0f BK |
512 | tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); |
513 | /* Calc SV bit */ | |
514 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
515 | /* Calc AV/SAV bits */ | |
516 | tcg_gen_add_tl(cpu_PSW_AV, ret, ret); | |
517 | tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); | |
518 | /* calc SAV */ | |
519 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
328f1f0f BK |
520 | } |
521 | ||
522 | static inline void gen_maddi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con) | |
523 | { | |
151293c2 | 524 | TCGv temp = tcg_constant_i32(con); |
328f1f0f | 525 | gen_madd32_d(ret, r1, r2, temp); |
328f1f0f BK |
526 | } |
527 | ||
528 | static inline void | |
529 | gen_madd64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
530 | TCGv r3) | |
531 | { | |
532 | TCGv t1 = tcg_temp_new(); | |
533 | TCGv t2 = tcg_temp_new(); | |
534 | TCGv t3 = tcg_temp_new(); | |
535 | TCGv t4 = tcg_temp_new(); | |
536 | ||
537 | tcg_gen_muls2_tl(t1, t2, r1, r3); | |
538 | /* only the add can overflow */ | |
539 | tcg_gen_add2_tl(t3, t4, r2_low, r2_high, t1, t2); | |
540 | /* calc V bit */ | |
541 | tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high); | |
542 | tcg_gen_xor_tl(t1, r2_high, t2); | |
543 | tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t1); | |
544 | /* Calc SV bit */ | |
545 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
546 | /* Calc AV/SAV bits */ | |
547 | tcg_gen_add_tl(cpu_PSW_AV, t4, t4); | |
548 | tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV); | |
549 | /* calc SAV */ | |
550 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
551 | /* write back the result */ | |
552 | tcg_gen_mov_tl(ret_low, t3); | |
553 | tcg_gen_mov_tl(ret_high, t4); | |
328f1f0f BK |
554 | } |
555 | ||
556 | static inline void | |
557 | gen_maddu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
558 | TCGv r3) | |
559 | { | |
560 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
561 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
562 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
563 | ||
564 | tcg_gen_extu_i32_i64(t1, r1); | |
565 | tcg_gen_concat_i32_i64(t2, r2_low, r2_high); | |
566 | tcg_gen_extu_i32_i64(t3, r3); | |
567 | ||
568 | tcg_gen_mul_i64(t1, t1, t3); | |
569 | tcg_gen_add_i64(t2, t2, t1); | |
570 | /* write back result */ | |
571 | tcg_gen_extr_i64_i32(ret_low, ret_high, t2); | |
572 | /* only the add overflows, if t2 < t1 | |
573 | calc V bit */ | |
574 | tcg_gen_setcond_i64(TCG_COND_LTU, t2, t2, t1); | |
ecc7b3aa | 575 | tcg_gen_extrl_i64_i32(cpu_PSW_V, t2); |
328f1f0f BK |
576 | tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); |
577 | /* Calc SV bit */ | |
578 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
579 | /* Calc AV/SAV bits */ | |
580 | tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); | |
581 | tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); | |
582 | /* calc SAV */ | |
583 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
328f1f0f BK |
584 | } |
585 | ||
586 | static inline void | |
587 | gen_maddi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
588 | int32_t con) | |
589 | { | |
151293c2 | 590 | TCGv temp = tcg_constant_i32(con); |
328f1f0f | 591 | gen_madd64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); |
328f1f0f BK |
592 | } |
593 | ||
594 | static inline void | |
595 | gen_maddui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
596 | int32_t con) | |
597 | { | |
151293c2 | 598 | TCGv temp = tcg_constant_i32(con); |
328f1f0f | 599 | gen_maddu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); |
328f1f0f BK |
600 | } |
601 | ||
2e430e1c BK |
602 | static inline void |
603 | gen_madd_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, | |
604 | TCGv r3, uint32_t n, uint32_t mode) | |
605 | { | |
bf38ca5c RH |
606 | TCGv t_n = tcg_constant_i32(n); |
607 | TCGv temp = tcg_temp_new(); | |
2e430e1c BK |
608 | TCGv temp2 = tcg_temp_new(); |
609 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
610 | switch (mode) { | |
611 | case MODE_LL: | |
bf38ca5c | 612 | GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); |
2e430e1c BK |
613 | break; |
614 | case MODE_LU: | |
bf38ca5c | 615 | GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); |
2e430e1c BK |
616 | break; |
617 | case MODE_UL: | |
bf38ca5c | 618 | GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); |
2e430e1c BK |
619 | break; |
620 | case MODE_UU: | |
bf38ca5c | 621 | GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); |
2e430e1c BK |
622 | break; |
623 | } | |
624 | tcg_gen_extr_i64_i32(temp, temp2, temp64); | |
625 | gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, | |
626 | tcg_gen_add_tl, tcg_gen_add_tl); | |
2e430e1c BK |
627 | } |
628 | ||
bebe80fc BK |
629 | static inline void |
630 | gen_maddsu_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, | |
631 | TCGv r3, uint32_t n, uint32_t mode) | |
632 | { | |
bf38ca5c RH |
633 | TCGv t_n = tcg_constant_i32(n); |
634 | TCGv temp = tcg_temp_new(); | |
bebe80fc BK |
635 | TCGv temp2 = tcg_temp_new(); |
636 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
637 | switch (mode) { | |
638 | case MODE_LL: | |
bf38ca5c | 639 | GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); |
bebe80fc BK |
640 | break; |
641 | case MODE_LU: | |
bf38ca5c | 642 | GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); |
bebe80fc BK |
643 | break; |
644 | case MODE_UL: | |
bf38ca5c | 645 | GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); |
bebe80fc BK |
646 | break; |
647 | case MODE_UU: | |
bf38ca5c | 648 | GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); |
bebe80fc BK |
649 | break; |
650 | } | |
651 | tcg_gen_extr_i64_i32(temp, temp2, temp64); | |
652 | gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, | |
653 | tcg_gen_sub_tl, tcg_gen_add_tl); | |
bebe80fc BK |
654 | } |
655 | ||
656 | static inline void | |
657 | gen_maddsum_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, | |
658 | TCGv r3, uint32_t n, uint32_t mode) | |
659 | { | |
bf38ca5c | 660 | TCGv t_n = tcg_constant_i32(n); |
bebe80fc BK |
661 | TCGv_i64 temp64 = tcg_temp_new_i64(); |
662 | TCGv_i64 temp64_2 = tcg_temp_new_i64(); | |
663 | TCGv_i64 temp64_3 = tcg_temp_new_i64(); | |
664 | switch (mode) { | |
665 | case MODE_LL: | |
bf38ca5c | 666 | GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); |
bebe80fc BK |
667 | break; |
668 | case MODE_LU: | |
bf38ca5c | 669 | GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); |
bebe80fc BK |
670 | break; |
671 | case MODE_UL: | |
bf38ca5c | 672 | GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); |
bebe80fc BK |
673 | break; |
674 | case MODE_UU: | |
bf38ca5c | 675 | GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); |
bebe80fc BK |
676 | break; |
677 | } | |
678 | tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high); | |
679 | tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ | |
680 | tcg_gen_ext32s_i64(temp64, temp64); /* low */ | |
681 | tcg_gen_sub_i64(temp64, temp64_2, temp64); | |
682 | tcg_gen_shli_i64(temp64, temp64, 16); | |
683 | ||
684 | gen_add64_d(temp64_2, temp64_3, temp64); | |
685 | /* write back result */ | |
686 | tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2); | |
bebe80fc BK |
687 | } |
688 | ||
2e430e1c BK |
689 | static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2); |
690 | ||
691 | static inline void | |
692 | gen_madds_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, | |
693 | TCGv r3, uint32_t n, uint32_t mode) | |
694 | { | |
bf38ca5c RH |
695 | TCGv t_n = tcg_constant_i32(n); |
696 | TCGv temp = tcg_temp_new(); | |
2e430e1c BK |
697 | TCGv temp2 = tcg_temp_new(); |
698 | TCGv temp3 = tcg_temp_new(); | |
699 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
700 | ||
701 | switch (mode) { | |
702 | case MODE_LL: | |
bf38ca5c | 703 | GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); |
2e430e1c BK |
704 | break; |
705 | case MODE_LU: | |
bf38ca5c | 706 | GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); |
2e430e1c BK |
707 | break; |
708 | case MODE_UL: | |
bf38ca5c | 709 | GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); |
2e430e1c BK |
710 | break; |
711 | case MODE_UU: | |
bf38ca5c | 712 | GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); |
2e430e1c BK |
713 | break; |
714 | } | |
715 | tcg_gen_extr_i64_i32(temp, temp2, temp64); | |
716 | gen_adds(ret_low, r1_low, temp); | |
717 | tcg_gen_mov_tl(temp, cpu_PSW_V); | |
718 | tcg_gen_mov_tl(temp3, cpu_PSW_AV); | |
719 | gen_adds(ret_high, r1_high, temp2); | |
720 | /* combine v bits */ | |
721 | tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); | |
722 | /* combine av bits */ | |
723 | tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); | |
2e430e1c BK |
724 | } |
725 | ||
bebe80fc BK |
726 | static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2); |
727 | ||
728 | static inline void | |
729 | gen_maddsus_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, | |
730 | TCGv r3, uint32_t n, uint32_t mode) | |
731 | { | |
bf38ca5c RH |
732 | TCGv t_n = tcg_constant_i32(n); |
733 | TCGv temp = tcg_temp_new(); | |
bebe80fc BK |
734 | TCGv temp2 = tcg_temp_new(); |
735 | TCGv temp3 = tcg_temp_new(); | |
736 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
737 | ||
738 | switch (mode) { | |
739 | case MODE_LL: | |
bf38ca5c | 740 | GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); |
bebe80fc BK |
741 | break; |
742 | case MODE_LU: | |
bf38ca5c | 743 | GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); |
bebe80fc BK |
744 | break; |
745 | case MODE_UL: | |
bf38ca5c | 746 | GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); |
bebe80fc BK |
747 | break; |
748 | case MODE_UU: | |
bf38ca5c | 749 | GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); |
bebe80fc BK |
750 | break; |
751 | } | |
752 | tcg_gen_extr_i64_i32(temp, temp2, temp64); | |
753 | gen_subs(ret_low, r1_low, temp); | |
754 | tcg_gen_mov_tl(temp, cpu_PSW_V); | |
755 | tcg_gen_mov_tl(temp3, cpu_PSW_AV); | |
756 | gen_adds(ret_high, r1_high, temp2); | |
757 | /* combine v bits */ | |
758 | tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); | |
759 | /* combine av bits */ | |
760 | tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); | |
bebe80fc BK |
761 | } |
762 | ||
763 | static inline void | |
764 | gen_maddsums_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, | |
765 | TCGv r3, uint32_t n, uint32_t mode) | |
766 | { | |
bf38ca5c | 767 | TCGv t_n = tcg_constant_i32(n); |
bebe80fc BK |
768 | TCGv_i64 temp64 = tcg_temp_new_i64(); |
769 | TCGv_i64 temp64_2 = tcg_temp_new_i64(); | |
770 | ||
771 | switch (mode) { | |
772 | case MODE_LL: | |
bf38ca5c | 773 | GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); |
bebe80fc BK |
774 | break; |
775 | case MODE_LU: | |
bf38ca5c | 776 | GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); |
bebe80fc BK |
777 | break; |
778 | case MODE_UL: | |
bf38ca5c | 779 | GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); |
bebe80fc BK |
780 | break; |
781 | case MODE_UU: | |
bf38ca5c | 782 | GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); |
bebe80fc BK |
783 | break; |
784 | } | |
785 | tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ | |
786 | tcg_gen_ext32s_i64(temp64, temp64); /* low */ | |
787 | tcg_gen_sub_i64(temp64, temp64_2, temp64); | |
788 | tcg_gen_shli_i64(temp64, temp64, 16); | |
789 | tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); | |
790 | ||
ad75a51e | 791 | gen_helper_add64_ssov(temp64, tcg_env, temp64_2, temp64); |
bebe80fc | 792 | tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); |
bebe80fc BK |
793 | } |
794 | ||
795 | ||
2e430e1c BK |
796 | static inline void |
797 | gen_maddm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, | |
798 | TCGv r3, uint32_t n, uint32_t mode) | |
799 | { | |
bf38ca5c | 800 | TCGv t_n = tcg_constant_i32(n); |
2e430e1c BK |
801 | TCGv_i64 temp64 = tcg_temp_new_i64(); |
802 | TCGv_i64 temp64_2 = tcg_temp_new_i64(); | |
803 | TCGv_i64 temp64_3 = tcg_temp_new_i64(); | |
804 | switch (mode) { | |
805 | case MODE_LL: | |
bf38ca5c | 806 | GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n); |
2e430e1c BK |
807 | break; |
808 | case MODE_LU: | |
bf38ca5c | 809 | GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n); |
2e430e1c BK |
810 | break; |
811 | case MODE_UL: | |
bf38ca5c | 812 | GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n); |
2e430e1c BK |
813 | break; |
814 | case MODE_UU: | |
bf38ca5c | 815 | GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n); |
2e430e1c BK |
816 | break; |
817 | } | |
818 | tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); | |
819 | gen_add64_d(temp64_3, temp64_2, temp64); | |
820 | /* write back result */ | |
821 | tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3); | |
2e430e1c BK |
822 | } |
823 | ||
824 | static inline void | |
825 | gen_maddms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, | |
826 | TCGv r3, uint32_t n, uint32_t mode) | |
827 | { | |
bf38ca5c | 828 | TCGv t_n = tcg_constant_i32(n); |
2e430e1c BK |
829 | TCGv_i64 temp64 = tcg_temp_new_i64(); |
830 | TCGv_i64 temp64_2 = tcg_temp_new_i64(); | |
831 | switch (mode) { | |
832 | case MODE_LL: | |
bf38ca5c | 833 | GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n); |
2e430e1c BK |
834 | break; |
835 | case MODE_LU: | |
bf38ca5c | 836 | GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n); |
2e430e1c BK |
837 | break; |
838 | case MODE_UL: | |
bf38ca5c | 839 | GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n); |
2e430e1c BK |
840 | break; |
841 | case MODE_UU: | |
bf38ca5c | 842 | GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n); |
2e430e1c BK |
843 | break; |
844 | } | |
845 | tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); | |
ad75a51e | 846 | gen_helper_add64_ssov(temp64, tcg_env, temp64_2, temp64); |
2e430e1c | 847 | tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); |
2e430e1c BK |
848 | } |
849 | ||
850 | static inline void | |
851 | gen_maddr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n, | |
852 | uint32_t mode) | |
853 | { | |
bf38ca5c | 854 | TCGv t_n = tcg_constant_i32(n); |
2e430e1c BK |
855 | TCGv_i64 temp64 = tcg_temp_new_i64(); |
856 | switch (mode) { | |
857 | case MODE_LL: | |
bf38ca5c | 858 | GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); |
2e430e1c BK |
859 | break; |
860 | case MODE_LU: | |
bf38ca5c | 861 | GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); |
2e430e1c BK |
862 | break; |
863 | case MODE_UL: | |
bf38ca5c | 864 | GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); |
2e430e1c BK |
865 | break; |
866 | case MODE_UU: | |
bf38ca5c | 867 | GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); |
2e430e1c BK |
868 | break; |
869 | } | |
ad75a51e | 870 | gen_helper_addr_h(ret, tcg_env, temp64, r1_low, r1_high); |
2e430e1c BK |
871 | } |
872 | ||
873 | static inline void | |
874 | gen_maddr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) | |
875 | { | |
876 | TCGv temp = tcg_temp_new(); | |
877 | TCGv temp2 = tcg_temp_new(); | |
878 | ||
879 | tcg_gen_andi_tl(temp2, r1, 0xffff0000); | |
880 | tcg_gen_shli_tl(temp, r1, 16); | |
881 | gen_maddr64_h(ret, temp, temp2, r2, r3, n, mode); | |
2e430e1c BK |
882 | } |
883 | ||
bebe80fc BK |
884 | static inline void |
885 | gen_maddsur32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) | |
886 | { | |
bf38ca5c RH |
887 | TCGv t_n = tcg_constant_i32(n); |
888 | TCGv temp = tcg_temp_new(); | |
bebe80fc BK |
889 | TCGv temp2 = tcg_temp_new(); |
890 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
891 | switch (mode) { | |
892 | case MODE_LL: | |
bf38ca5c | 893 | GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); |
bebe80fc BK |
894 | break; |
895 | case MODE_LU: | |
bf38ca5c | 896 | GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); |
bebe80fc BK |
897 | break; |
898 | case MODE_UL: | |
bf38ca5c | 899 | GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); |
bebe80fc BK |
900 | break; |
901 | case MODE_UU: | |
bf38ca5c | 902 | GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); |
bebe80fc BK |
903 | break; |
904 | } | |
905 | tcg_gen_andi_tl(temp2, r1, 0xffff0000); | |
906 | tcg_gen_shli_tl(temp, r1, 16); | |
ad75a51e | 907 | gen_helper_addsur_h(ret, tcg_env, temp64, temp, temp2); |
bebe80fc BK |
908 | } |
909 | ||
910 | ||
2e430e1c BK |
911 | static inline void |
912 | gen_maddr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, | |
913 | uint32_t n, uint32_t mode) | |
914 | { | |
bf38ca5c | 915 | TCGv t_n = tcg_constant_i32(n); |
2e430e1c BK |
916 | TCGv_i64 temp64 = tcg_temp_new_i64(); |
917 | switch (mode) { | |
918 | case MODE_LL: | |
bf38ca5c | 919 | GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); |
2e430e1c BK |
920 | break; |
921 | case MODE_LU: | |
bf38ca5c | 922 | GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); |
2e430e1c BK |
923 | break; |
924 | case MODE_UL: | |
bf38ca5c | 925 | GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); |
2e430e1c BK |
926 | break; |
927 | case MODE_UU: | |
bf38ca5c | 928 | GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); |
2e430e1c BK |
929 | break; |
930 | } | |
ad75a51e | 931 | gen_helper_addr_h_ssov(ret, tcg_env, temp64, r1_low, r1_high); |
2e430e1c BK |
932 | } |
933 | ||
934 | static inline void | |
935 | gen_maddr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) | |
936 | { | |
937 | TCGv temp = tcg_temp_new(); | |
938 | TCGv temp2 = tcg_temp_new(); | |
939 | ||
940 | tcg_gen_andi_tl(temp2, r1, 0xffff0000); | |
941 | tcg_gen_shli_tl(temp, r1, 16); | |
942 | gen_maddr64s_h(ret, temp, temp2, r2, r3, n, mode); | |
2e430e1c BK |
943 | } |
944 | ||
bebe80fc BK |
945 | static inline void |
946 | gen_maddsur32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) | |
947 | { | |
bf38ca5c RH |
948 | TCGv t_n = tcg_constant_i32(n); |
949 | TCGv temp = tcg_temp_new(); | |
bebe80fc BK |
950 | TCGv temp2 = tcg_temp_new(); |
951 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
952 | switch (mode) { | |
953 | case MODE_LL: | |
bf38ca5c | 954 | GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); |
bebe80fc BK |
955 | break; |
956 | case MODE_LU: | |
bf38ca5c | 957 | GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); |
bebe80fc BK |
958 | break; |
959 | case MODE_UL: | |
bf38ca5c | 960 | GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); |
bebe80fc BK |
961 | break; |
962 | case MODE_UU: | |
bf38ca5c | 963 | GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); |
bebe80fc BK |
964 | break; |
965 | } | |
966 | tcg_gen_andi_tl(temp2, r1, 0xffff0000); | |
967 | tcg_gen_shli_tl(temp, r1, 16); | |
ad75a51e | 968 | gen_helper_addsur_h_ssov(ret, tcg_env, temp64, temp, temp2); |
bebe80fc BK |
969 | } |
970 | ||
b00aa8ec BK |
971 | static inline void |
972 | gen_maddr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) | |
973 | { | |
bf38ca5c | 974 | TCGv t_n = tcg_constant_i32(n); |
ad75a51e | 975 | gen_helper_maddr_q(ret, tcg_env, r1, r2, r3, t_n); |
b00aa8ec BK |
976 | } |
977 | ||
978 | static inline void | |
979 | gen_maddrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) | |
980 | { | |
bf38ca5c | 981 | TCGv t_n = tcg_constant_i32(n); |
ad75a51e | 982 | gen_helper_maddr_q_ssov(ret, tcg_env, r1, r2, r3, t_n); |
b00aa8ec BK |
983 | } |
984 | ||
985 | static inline void | |
986 | gen_madd32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, | |
2db92a0c | 987 | uint32_t up_shift) |
b00aa8ec BK |
988 | { |
989 | TCGv temp = tcg_temp_new(); | |
990 | TCGv temp2 = tcg_temp_new(); | |
991 | TCGv temp3 = tcg_temp_new(); | |
992 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
993 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
994 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
995 | ||
996 | tcg_gen_ext_i32_i64(t2, arg2); | |
997 | tcg_gen_ext_i32_i64(t3, arg3); | |
998 | ||
999 | tcg_gen_mul_i64(t2, t2, t3); | |
1000 | tcg_gen_shli_i64(t2, t2, n); | |
1001 | ||
1002 | tcg_gen_ext_i32_i64(t1, arg1); | |
1003 | tcg_gen_sari_i64(t2, t2, up_shift); | |
1004 | ||
1005 | tcg_gen_add_i64(t3, t1, t2); | |
ecc7b3aa | 1006 | tcg_gen_extrl_i64_i32(temp3, t3); |
b00aa8ec BK |
1007 | /* calc v bit */ |
1008 | tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL); | |
1009 | tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL); | |
1010 | tcg_gen_or_i64(t1, t1, t2); | |
ecc7b3aa | 1011 | tcg_gen_extrl_i64_i32(cpu_PSW_V, t1); |
b00aa8ec BK |
1012 | tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); |
1013 | /* We produce an overflow on the host if the mul before was | |
1014 | (0x80000000 * 0x80000000) << 1). If this is the | |
1015 | case, we negate the ovf. */ | |
1016 | if (n == 1) { | |
1017 | tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000); | |
1018 | tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3); | |
1019 | tcg_gen_and_tl(temp, temp, temp2); | |
1020 | tcg_gen_shli_tl(temp, temp, 31); | |
1021 | /* negate v bit, if special condition */ | |
1022 | tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp); | |
1023 | } | |
1024 | /* Calc SV bit */ | |
1025 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
1026 | /* Calc AV/SAV bits */ | |
1027 | tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3); | |
1028 | tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV); | |
1029 | /* calc SAV */ | |
1030 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
1031 | /* write back result */ | |
1032 | tcg_gen_mov_tl(ret, temp3); | |
b00aa8ec BK |
1033 | } |
1034 | ||
1035 | static inline void | |
1036 | gen_m16add32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n) | |
1037 | { | |
1038 | TCGv temp = tcg_temp_new(); | |
1039 | TCGv temp2 = tcg_temp_new(); | |
1040 | if (n == 0) { | |
1041 | tcg_gen_mul_tl(temp, arg2, arg3); | |
de7ad4ce | 1042 | } else { /* n is expected to be 1 */ |
b00aa8ec BK |
1043 | tcg_gen_mul_tl(temp, arg2, arg3); |
1044 | tcg_gen_shli_tl(temp, temp, 1); | |
1045 | /* catch special case r1 = r2 = 0x8000 */ | |
1046 | tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); | |
1047 | tcg_gen_sub_tl(temp, temp, temp2); | |
1048 | } | |
1049 | gen_add_d(ret, arg1, temp); | |
b00aa8ec BK |
1050 | } |
1051 | ||
1052 | static inline void | |
1053 | gen_m16adds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n) | |
1054 | { | |
1055 | TCGv temp = tcg_temp_new(); | |
1056 | TCGv temp2 = tcg_temp_new(); | |
1057 | if (n == 0) { | |
1058 | tcg_gen_mul_tl(temp, arg2, arg3); | |
de7ad4ce | 1059 | } else { /* n is expected to be 1 */ |
b00aa8ec BK |
1060 | tcg_gen_mul_tl(temp, arg2, arg3); |
1061 | tcg_gen_shli_tl(temp, temp, 1); | |
1062 | /* catch special case r1 = r2 = 0x8000 */ | |
1063 | tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); | |
1064 | tcg_gen_sub_tl(temp, temp, temp2); | |
1065 | } | |
1066 | gen_adds(ret, arg1, temp); | |
b00aa8ec BK |
1067 | } |
1068 | ||
1069 | static inline void | |
1070 | gen_m16add64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, | |
1071 | TCGv arg3, uint32_t n) | |
1072 | { | |
1073 | TCGv temp = tcg_temp_new(); | |
1074 | TCGv temp2 = tcg_temp_new(); | |
1075 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1076 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
1077 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
1078 | ||
1079 | if (n == 0) { | |
1080 | tcg_gen_mul_tl(temp, arg2, arg3); | |
de7ad4ce | 1081 | } else { /* n is expected to be 1 */ |
b00aa8ec BK |
1082 | tcg_gen_mul_tl(temp, arg2, arg3); |
1083 | tcg_gen_shli_tl(temp, temp, 1); | |
1084 | /* catch special case r1 = r2 = 0x8000 */ | |
1085 | tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); | |
1086 | tcg_gen_sub_tl(temp, temp, temp2); | |
1087 | } | |
1088 | tcg_gen_ext_i32_i64(t2, temp); | |
1089 | tcg_gen_shli_i64(t2, t2, 16); | |
1090 | tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); | |
1091 | gen_add64_d(t3, t1, t2); | |
1092 | /* write back result */ | |
1093 | tcg_gen_extr_i64_i32(rl, rh, t3); | |
b00aa8ec BK |
1094 | } |
1095 | ||
1096 | static inline void | |
1097 | gen_m16adds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, | |
1098 | TCGv arg3, uint32_t n) | |
1099 | { | |
1100 | TCGv temp = tcg_temp_new(); | |
1101 | TCGv temp2 = tcg_temp_new(); | |
1102 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1103 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
1104 | ||
1105 | if (n == 0) { | |
1106 | tcg_gen_mul_tl(temp, arg2, arg3); | |
de7ad4ce | 1107 | } else { /* n is expected to be 1 */ |
b00aa8ec BK |
1108 | tcg_gen_mul_tl(temp, arg2, arg3); |
1109 | tcg_gen_shli_tl(temp, temp, 1); | |
1110 | /* catch special case r1 = r2 = 0x8000 */ | |
1111 | tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); | |
1112 | tcg_gen_sub_tl(temp, temp, temp2); | |
1113 | } | |
1114 | tcg_gen_ext_i32_i64(t2, temp); | |
1115 | tcg_gen_shli_i64(t2, t2, 16); | |
1116 | tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); | |
1117 | ||
ad75a51e | 1118 | gen_helper_add64_ssov(t1, tcg_env, t1, t2); |
b00aa8ec | 1119 | tcg_gen_extr_i64_i32(rl, rh, t1); |
b00aa8ec BK |
1120 | } |
1121 | ||
1122 | static inline void | |
1123 | gen_madd64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, | |
2db92a0c | 1124 | TCGv arg3, uint32_t n) |
b00aa8ec BK |
1125 | { |
1126 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1127 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
1128 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
1129 | TCGv_i64 t4 = tcg_temp_new_i64(); | |
1130 | TCGv temp, temp2; | |
1131 | ||
1132 | tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); | |
1133 | tcg_gen_ext_i32_i64(t2, arg2); | |
1134 | tcg_gen_ext_i32_i64(t3, arg3); | |
1135 | ||
1136 | tcg_gen_mul_i64(t2, t2, t3); | |
1137 | if (n != 0) { | |
1138 | tcg_gen_shli_i64(t2, t2, 1); | |
1139 | } | |
1140 | tcg_gen_add_i64(t4, t1, t2); | |
1141 | /* calc v bit */ | |
1142 | tcg_gen_xor_i64(t3, t4, t1); | |
1143 | tcg_gen_xor_i64(t2, t1, t2); | |
1144 | tcg_gen_andc_i64(t3, t3, t2); | |
609ad705 | 1145 | tcg_gen_extrh_i64_i32(cpu_PSW_V, t3); |
b00aa8ec BK |
1146 | /* We produce an overflow on the host if the mul before was |
1147 | (0x80000000 * 0x80000000) << 1). If this is the | |
1148 | case, we negate the ovf. */ | |
1149 | if (n == 1) { | |
1150 | temp = tcg_temp_new(); | |
1151 | temp2 = tcg_temp_new(); | |
1152 | tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000); | |
1153 | tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3); | |
1154 | tcg_gen_and_tl(temp, temp, temp2); | |
1155 | tcg_gen_shli_tl(temp, temp, 31); | |
1156 | /* negate v bit, if special condition */ | |
1157 | tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp); | |
b00aa8ec BK |
1158 | } |
1159 | /* write back result */ | |
1160 | tcg_gen_extr_i64_i32(rl, rh, t4); | |
1161 | /* Calc SV bit */ | |
1162 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
1163 | /* Calc AV/SAV bits */ | |
1164 | tcg_gen_add_tl(cpu_PSW_AV, rh, rh); | |
1165 | tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV); | |
1166 | /* calc SAV */ | |
1167 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
b00aa8ec BK |
1168 | } |
1169 | ||
1170 | static inline void | |
1171 | gen_madds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, | |
1172 | uint32_t up_shift) | |
1173 | { | |
1174 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1175 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
1176 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
1177 | ||
1178 | tcg_gen_ext_i32_i64(t1, arg1); | |
1179 | tcg_gen_ext_i32_i64(t2, arg2); | |
1180 | tcg_gen_ext_i32_i64(t3, arg3); | |
1181 | ||
1182 | tcg_gen_mul_i64(t2, t2, t3); | |
1183 | tcg_gen_sari_i64(t2, t2, up_shift - n); | |
1184 | ||
ad75a51e | 1185 | gen_helper_madd32_q_add_ssov(ret, tcg_env, t1, t2); |
b00aa8ec BK |
1186 | } |
1187 | ||
1188 | static inline void | |
1189 | gen_madds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, | |
1190 | TCGv arg3, uint32_t n) | |
1191 | { | |
1192 | TCGv_i64 r1 = tcg_temp_new_i64(); | |
bf38ca5c | 1193 | TCGv t_n = tcg_constant_i32(n); |
b00aa8ec BK |
1194 | |
1195 | tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high); | |
ad75a51e | 1196 | gen_helper_madd64_q_ssov(r1, tcg_env, r1, arg2, arg3, t_n); |
b00aa8ec | 1197 | tcg_gen_extr_i64_i32(rl, rh, r1); |
b00aa8ec | 1198 | } |
08ee498b | 1199 | |
328f1f0f BK |
1200 | /* ret = r2 - (r1 * r3); */ |
1201 | static inline void gen_msub32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3) | |
1202 | { | |
1203 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1204 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
1205 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
1206 | ||
1207 | tcg_gen_ext_i32_i64(t1, r1); | |
1208 | tcg_gen_ext_i32_i64(t2, r2); | |
1209 | tcg_gen_ext_i32_i64(t3, r3); | |
1210 | ||
1211 | tcg_gen_mul_i64(t1, t1, t3); | |
1212 | tcg_gen_sub_i64(t1, t2, t1); | |
1213 | ||
ecc7b3aa | 1214 | tcg_gen_extrl_i64_i32(ret, t1); |
328f1f0f BK |
1215 | /* calc V |
1216 | t2 > 0x7fffffff */ | |
1217 | tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL); | |
1218 | /* result < -0x80000000 */ | |
1219 | tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL); | |
1220 | tcg_gen_or_i64(t2, t2, t3); | |
ecc7b3aa | 1221 | tcg_gen_extrl_i64_i32(cpu_PSW_V, t2); |
328f1f0f BK |
1222 | tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); |
1223 | ||
1224 | /* Calc SV bit */ | |
1225 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
1226 | /* Calc AV/SAV bits */ | |
1227 | tcg_gen_add_tl(cpu_PSW_AV, ret, ret); | |
1228 | tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); | |
1229 | /* calc SAV */ | |
1230 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
328f1f0f BK |
1231 | } |
1232 | ||
1233 | static inline void gen_msubi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con) | |
1234 | { | |
151293c2 | 1235 | TCGv temp = tcg_constant_i32(con); |
328f1f0f | 1236 | gen_msub32_d(ret, r1, r2, temp); |
328f1f0f BK |
1237 | } |
1238 | ||
1239 | static inline void | |
1240 | gen_msub64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
1241 | TCGv r3) | |
1242 | { | |
1243 | TCGv t1 = tcg_temp_new(); | |
1244 | TCGv t2 = tcg_temp_new(); | |
1245 | TCGv t3 = tcg_temp_new(); | |
1246 | TCGv t4 = tcg_temp_new(); | |
1247 | ||
1248 | tcg_gen_muls2_tl(t1, t2, r1, r3); | |
1249 | /* only the sub can overflow */ | |
1250 | tcg_gen_sub2_tl(t3, t4, r2_low, r2_high, t1, t2); | |
1251 | /* calc V bit */ | |
1252 | tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high); | |
1253 | tcg_gen_xor_tl(t1, r2_high, t2); | |
1254 | tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, t1); | |
1255 | /* Calc SV bit */ | |
1256 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
1257 | /* Calc AV/SAV bits */ | |
1258 | tcg_gen_add_tl(cpu_PSW_AV, t4, t4); | |
1259 | tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV); | |
1260 | /* calc SAV */ | |
1261 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
1262 | /* write back the result */ | |
1263 | tcg_gen_mov_tl(ret_low, t3); | |
1264 | tcg_gen_mov_tl(ret_high, t4); | |
328f1f0f BK |
1265 | } |
1266 | ||
1267 | static inline void | |
1268 | gen_msubi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
1269 | int32_t con) | |
1270 | { | |
151293c2 | 1271 | TCGv temp = tcg_constant_i32(con); |
328f1f0f | 1272 | gen_msub64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); |
328f1f0f BK |
1273 | } |
1274 | ||
1275 | static inline void | |
1276 | gen_msubu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
1277 | TCGv r3) | |
1278 | { | |
1279 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1280 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
1281 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
1282 | ||
1283 | tcg_gen_extu_i32_i64(t1, r1); | |
1284 | tcg_gen_concat_i32_i64(t2, r2_low, r2_high); | |
1285 | tcg_gen_extu_i32_i64(t3, r3); | |
1286 | ||
1287 | tcg_gen_mul_i64(t1, t1, t3); | |
1288 | tcg_gen_sub_i64(t3, t2, t1); | |
1289 | tcg_gen_extr_i64_i32(ret_low, ret_high, t3); | |
1290 | /* calc V bit, only the sub can overflow, if t1 > t2 */ | |
1291 | tcg_gen_setcond_i64(TCG_COND_GTU, t1, t1, t2); | |
ecc7b3aa | 1292 | tcg_gen_extrl_i64_i32(cpu_PSW_V, t1); |
328f1f0f BK |
1293 | tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); |
1294 | /* Calc SV bit */ | |
1295 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
1296 | /* Calc AV/SAV bits */ | |
1297 | tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); | |
1298 | tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); | |
1299 | /* calc SAV */ | |
1300 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
328f1f0f BK |
1301 | } |
1302 | ||
1303 | static inline void | |
1304 | gen_msubui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
1305 | int32_t con) | |
1306 | { | |
151293c2 | 1307 | TCGv temp = tcg_constant_i32(con); |
328f1f0f | 1308 | gen_msubu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); |
328f1f0f BK |
1309 | } |
1310 | ||
0707ec1b BK |
1311 | static inline void gen_addi_d(TCGv ret, TCGv r1, target_ulong r2) |
1312 | { | |
151293c2 | 1313 | TCGv temp = tcg_constant_i32(r2); |
0707ec1b | 1314 | gen_add_d(ret, r1, temp); |
0707ec1b | 1315 | } |
08ee498b | 1316 | |
0974257e BK |
1317 | /* calculate the carry bit too */ |
1318 | static inline void gen_add_CC(TCGv ret, TCGv r1, TCGv r2) | |
1319 | { | |
1320 | TCGv t0 = tcg_temp_new_i32(); | |
1321 | TCGv result = tcg_temp_new_i32(); | |
1322 | ||
1323 | tcg_gen_movi_tl(t0, 0); | |
1324 | /* Addition and set C/V/SV bits */ | |
1325 | tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, r2, t0); | |
1326 | /* calc V bit */ | |
1327 | tcg_gen_xor_tl(cpu_PSW_V, result, r1); | |
1328 | tcg_gen_xor_tl(t0, r1, r2); | |
1329 | tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0); | |
1330 | /* Calc SV bit */ | |
1331 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
1332 | /* Calc AV/SAV bits */ | |
1333 | tcg_gen_add_tl(cpu_PSW_AV, result, result); | |
1334 | tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); | |
1335 | /* calc SAV */ | |
1336 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
1337 | /* write back result */ | |
1338 | tcg_gen_mov_tl(ret, result); | |
0974257e BK |
1339 | } |
1340 | ||
1341 | static inline void gen_addi_CC(TCGv ret, TCGv r1, int32_t con) | |
1342 | { | |
151293c2 | 1343 | TCGv temp = tcg_constant_i32(con); |
0974257e | 1344 | gen_add_CC(ret, r1, temp); |
0974257e BK |
1345 | } |
1346 | ||
1347 | static inline void gen_addc_CC(TCGv ret, TCGv r1, TCGv r2) | |
1348 | { | |
1349 | TCGv carry = tcg_temp_new_i32(); | |
1350 | TCGv t0 = tcg_temp_new_i32(); | |
1351 | TCGv result = tcg_temp_new_i32(); | |
1352 | ||
1353 | tcg_gen_movi_tl(t0, 0); | |
1354 | tcg_gen_setcondi_tl(TCG_COND_NE, carry, cpu_PSW_C, 0); | |
1355 | /* Addition, carry and set C/V/SV bits */ | |
1356 | tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, carry, t0); | |
1357 | tcg_gen_add2_i32(result, cpu_PSW_C, result, cpu_PSW_C, r2, t0); | |
1358 | /* calc V bit */ | |
1359 | tcg_gen_xor_tl(cpu_PSW_V, result, r1); | |
1360 | tcg_gen_xor_tl(t0, r1, r2); | |
1361 | tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0); | |
1362 | /* Calc SV bit */ | |
1363 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
1364 | /* Calc AV/SAV bits */ | |
1365 | tcg_gen_add_tl(cpu_PSW_AV, result, result); | |
1366 | tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); | |
1367 | /* calc SAV */ | |
1368 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
1369 | /* write back result */ | |
1370 | tcg_gen_mov_tl(ret, result); | |
0974257e BK |
1371 | } |
1372 | ||
1373 | static inline void gen_addci_CC(TCGv ret, TCGv r1, int32_t con) | |
1374 | { | |
151293c2 | 1375 | TCGv temp = tcg_constant_i32(con); |
0974257e | 1376 | gen_addc_CC(ret, r1, temp); |
0974257e | 1377 | } |
0707ec1b BK |
1378 | |
1379 | static inline void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3, | |
1380 | TCGv r4) | |
1381 | { | |
1382 | TCGv temp = tcg_temp_new(); | |
1383 | TCGv temp2 = tcg_temp_new(); | |
1384 | TCGv result = tcg_temp_new(); | |
1385 | TCGv mask = tcg_temp_new(); | |
151293c2 | 1386 | TCGv t0 = tcg_constant_i32(0); |
0707ec1b BK |
1387 | |
1388 | /* create mask for sticky bits */ | |
1389 | tcg_gen_setcond_tl(cond, mask, r4, t0); | |
1390 | tcg_gen_shli_tl(mask, mask, 31); | |
1391 | ||
1392 | tcg_gen_add_tl(result, r1, r2); | |
1393 | /* Calc PSW_V */ | |
1394 | tcg_gen_xor_tl(temp, result, r1); | |
1395 | tcg_gen_xor_tl(temp2, r1, r2); | |
1396 | tcg_gen_andc_tl(temp, temp, temp2); | |
1397 | tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V); | |
1398 | /* Set PSW_SV */ | |
1399 | tcg_gen_and_tl(temp, temp, mask); | |
1400 | tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV); | |
1401 | /* calc AV bit */ | |
1402 | tcg_gen_add_tl(temp, result, result); | |
1403 | tcg_gen_xor_tl(temp, temp, result); | |
1404 | tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV); | |
1405 | /* calc SAV bit */ | |
1406 | tcg_gen_and_tl(temp, temp, mask); | |
1407 | tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV); | |
1408 | /* write back result */ | |
5f30046f | 1409 | tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1); |
0707ec1b BK |
1410 | } |
1411 | ||
1412 | static inline void gen_condi_add(TCGCond cond, TCGv r1, int32_t r2, | |
1413 | TCGv r3, TCGv r4) | |
1414 | { | |
151293c2 | 1415 | TCGv temp = tcg_constant_i32(r2); |
0707ec1b | 1416 | gen_cond_add(cond, r1, temp, r3, r4); |
0707ec1b BK |
1417 | } |
1418 | ||
2692802a BK |
1419 | static inline void gen_sub_d(TCGv ret, TCGv r1, TCGv r2) |
1420 | { | |
1421 | TCGv temp = tcg_temp_new_i32(); | |
1422 | TCGv result = tcg_temp_new_i32(); | |
1423 | ||
1424 | tcg_gen_sub_tl(result, r1, r2); | |
1425 | /* calc V bit */ | |
1426 | tcg_gen_xor_tl(cpu_PSW_V, result, r1); | |
1427 | tcg_gen_xor_tl(temp, r1, r2); | |
1428 | tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp); | |
1429 | /* calc SV bit */ | |
1430 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
1431 | /* Calc AV bit */ | |
1432 | tcg_gen_add_tl(cpu_PSW_AV, result, result); | |
1433 | tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); | |
1434 | /* calc SAV bit */ | |
1435 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
1436 | /* write back result */ | |
1437 | tcg_gen_mov_tl(ret, result); | |
2692802a BK |
1438 | } |
1439 | ||
f4aef476 BK |
1440 | static inline void |
1441 | gen_sub64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2) | |
1442 | { | |
1443 | TCGv temp = tcg_temp_new(); | |
1444 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
1445 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1446 | TCGv_i64 result = tcg_temp_new_i64(); | |
1447 | ||
1448 | tcg_gen_sub_i64(result, r1, r2); | |
1449 | /* calc v bit */ | |
1450 | tcg_gen_xor_i64(t1, result, r1); | |
1451 | tcg_gen_xor_i64(t0, r1, r2); | |
1452 | tcg_gen_and_i64(t1, t1, t0); | |
609ad705 | 1453 | tcg_gen_extrh_i64_i32(cpu_PSW_V, t1); |
f4aef476 BK |
1454 | /* calc SV bit */ |
1455 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
1456 | /* calc AV/SAV bits */ | |
609ad705 | 1457 | tcg_gen_extrh_i64_i32(temp, result); |
f4aef476 BK |
1458 | tcg_gen_add_tl(cpu_PSW_AV, temp, temp); |
1459 | tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV); | |
1460 | /* calc SAV */ | |
1461 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
1462 | /* write back result */ | |
1463 | tcg_gen_mov_i64(ret, result); | |
f4aef476 BK |
1464 | } |
1465 | ||
d5de7839 BK |
1466 | static inline void gen_sub_CC(TCGv ret, TCGv r1, TCGv r2) |
1467 | { | |
1468 | TCGv result = tcg_temp_new(); | |
1469 | TCGv temp = tcg_temp_new(); | |
1470 | ||
1471 | tcg_gen_sub_tl(result, r1, r2); | |
1472 | /* calc C bit */ | |
1473 | tcg_gen_setcond_tl(TCG_COND_GEU, cpu_PSW_C, r1, r2); | |
1474 | /* calc V bit */ | |
1475 | tcg_gen_xor_tl(cpu_PSW_V, result, r1); | |
1476 | tcg_gen_xor_tl(temp, r1, r2); | |
1477 | tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp); | |
1478 | /* calc SV bit */ | |
1479 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
1480 | /* Calc AV bit */ | |
1481 | tcg_gen_add_tl(cpu_PSW_AV, result, result); | |
1482 | tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); | |
1483 | /* calc SAV bit */ | |
1484 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
1485 | /* write back result */ | |
1486 | tcg_gen_mov_tl(ret, result); | |
d5de7839 BK |
1487 | } |
1488 | ||
1489 | static inline void gen_subc_CC(TCGv ret, TCGv r1, TCGv r2) | |
1490 | { | |
1491 | TCGv temp = tcg_temp_new(); | |
1492 | tcg_gen_not_tl(temp, r2); | |
1493 | gen_addc_CC(ret, r1, temp); | |
d5de7839 BK |
1494 | } |
1495 | ||
09532255 BK |
1496 | static inline void gen_cond_sub(TCGCond cond, TCGv r1, TCGv r2, TCGv r3, |
1497 | TCGv r4) | |
1498 | { | |
1499 | TCGv temp = tcg_temp_new(); | |
1500 | TCGv temp2 = tcg_temp_new(); | |
1501 | TCGv result = tcg_temp_new(); | |
1502 | TCGv mask = tcg_temp_new(); | |
151293c2 | 1503 | TCGv t0 = tcg_constant_i32(0); |
09532255 BK |
1504 | |
1505 | /* create mask for sticky bits */ | |
1506 | tcg_gen_setcond_tl(cond, mask, r4, t0); | |
1507 | tcg_gen_shli_tl(mask, mask, 31); | |
1508 | ||
1509 | tcg_gen_sub_tl(result, r1, r2); | |
1510 | /* Calc PSW_V */ | |
1511 | tcg_gen_xor_tl(temp, result, r1); | |
1512 | tcg_gen_xor_tl(temp2, r1, r2); | |
1513 | tcg_gen_and_tl(temp, temp, temp2); | |
1514 | tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V); | |
1515 | /* Set PSW_SV */ | |
1516 | tcg_gen_and_tl(temp, temp, mask); | |
1517 | tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV); | |
1518 | /* calc AV bit */ | |
1519 | tcg_gen_add_tl(temp, result, result); | |
1520 | tcg_gen_xor_tl(temp, temp, result); | |
1521 | tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV); | |
1522 | /* calc SAV bit */ | |
1523 | tcg_gen_and_tl(temp, temp, mask); | |
1524 | tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV); | |
1525 | /* write back result */ | |
1526 | tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1); | |
09532255 BK |
1527 | } |
1528 | ||
f4aef476 BK |
1529 | static inline void |
1530 | gen_msub_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, | |
1531 | TCGv r3, uint32_t n, uint32_t mode) | |
1532 | { | |
bf38ca5c RH |
1533 | TCGv t_n = tcg_constant_i32(n); |
1534 | TCGv temp = tcg_temp_new(); | |
f4aef476 BK |
1535 | TCGv temp2 = tcg_temp_new(); |
1536 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
1537 | switch (mode) { | |
1538 | case MODE_LL: | |
bf38ca5c | 1539 | GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); |
f4aef476 BK |
1540 | break; |
1541 | case MODE_LU: | |
bf38ca5c | 1542 | GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); |
f4aef476 BK |
1543 | break; |
1544 | case MODE_UL: | |
bf38ca5c | 1545 | GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); |
f4aef476 BK |
1546 | break; |
1547 | case MODE_UU: | |
bf38ca5c | 1548 | GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); |
f4aef476 BK |
1549 | break; |
1550 | } | |
1551 | tcg_gen_extr_i64_i32(temp, temp2, temp64); | |
1552 | gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, | |
1553 | tcg_gen_sub_tl, tcg_gen_sub_tl); | |
f4aef476 BK |
1554 | } |
1555 | ||
1556 | static inline void | |
1557 | gen_msubs_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, | |
1558 | TCGv r3, uint32_t n, uint32_t mode) | |
1559 | { | |
bf38ca5c RH |
1560 | TCGv t_n = tcg_constant_i32(n); |
1561 | TCGv temp = tcg_temp_new(); | |
f4aef476 BK |
1562 | TCGv temp2 = tcg_temp_new(); |
1563 | TCGv temp3 = tcg_temp_new(); | |
1564 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
1565 | ||
1566 | switch (mode) { | |
1567 | case MODE_LL: | |
bf38ca5c | 1568 | GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); |
f4aef476 BK |
1569 | break; |
1570 | case MODE_LU: | |
bf38ca5c | 1571 | GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); |
f4aef476 BK |
1572 | break; |
1573 | case MODE_UL: | |
bf38ca5c | 1574 | GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); |
f4aef476 BK |
1575 | break; |
1576 | case MODE_UU: | |
bf38ca5c | 1577 | GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); |
f4aef476 BK |
1578 | break; |
1579 | } | |
1580 | tcg_gen_extr_i64_i32(temp, temp2, temp64); | |
1581 | gen_subs(ret_low, r1_low, temp); | |
1582 | tcg_gen_mov_tl(temp, cpu_PSW_V); | |
1583 | tcg_gen_mov_tl(temp3, cpu_PSW_AV); | |
1584 | gen_subs(ret_high, r1_high, temp2); | |
1585 | /* combine v bits */ | |
1586 | tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); | |
1587 | /* combine av bits */ | |
1588 | tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); | |
f4aef476 BK |
1589 | } |
1590 | ||
1591 | static inline void | |
1592 | gen_msubm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, | |
1593 | TCGv r3, uint32_t n, uint32_t mode) | |
1594 | { | |
bf38ca5c | 1595 | TCGv t_n = tcg_constant_i32(n); |
f4aef476 BK |
1596 | TCGv_i64 temp64 = tcg_temp_new_i64(); |
1597 | TCGv_i64 temp64_2 = tcg_temp_new_i64(); | |
1598 | TCGv_i64 temp64_3 = tcg_temp_new_i64(); | |
1599 | switch (mode) { | |
1600 | case MODE_LL: | |
bf38ca5c | 1601 | GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n); |
f4aef476 BK |
1602 | break; |
1603 | case MODE_LU: | |
bf38ca5c | 1604 | GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n); |
f4aef476 BK |
1605 | break; |
1606 | case MODE_UL: | |
bf38ca5c | 1607 | GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n); |
f4aef476 BK |
1608 | break; |
1609 | case MODE_UU: | |
bf38ca5c | 1610 | GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n); |
f4aef476 BK |
1611 | break; |
1612 | } | |
1613 | tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); | |
1614 | gen_sub64_d(temp64_3, temp64_2, temp64); | |
1615 | /* write back result */ | |
1616 | tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3); | |
f4aef476 BK |
1617 | } |
1618 | ||
1619 | static inline void | |
1620 | gen_msubms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, | |
1621 | TCGv r3, uint32_t n, uint32_t mode) | |
1622 | { | |
bf38ca5c | 1623 | TCGv t_n = tcg_constant_i32(n); |
f4aef476 BK |
1624 | TCGv_i64 temp64 = tcg_temp_new_i64(); |
1625 | TCGv_i64 temp64_2 = tcg_temp_new_i64(); | |
1626 | switch (mode) { | |
1627 | case MODE_LL: | |
bf38ca5c | 1628 | GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n); |
f4aef476 BK |
1629 | break; |
1630 | case MODE_LU: | |
bf38ca5c | 1631 | GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n); |
f4aef476 BK |
1632 | break; |
1633 | case MODE_UL: | |
bf38ca5c | 1634 | GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n); |
f4aef476 BK |
1635 | break; |
1636 | case MODE_UU: | |
bf38ca5c | 1637 | GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n); |
f4aef476 BK |
1638 | break; |
1639 | } | |
1640 | tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); | |
ad75a51e | 1641 | gen_helper_sub64_ssov(temp64, tcg_env, temp64_2, temp64); |
f4aef476 | 1642 | tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); |
f4aef476 BK |
1643 | } |
1644 | ||
1645 | static inline void | |
1646 | gen_msubr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n, | |
1647 | uint32_t mode) | |
1648 | { | |
bf38ca5c | 1649 | TCGv t_n = tcg_constant_i32(n); |
f4aef476 BK |
1650 | TCGv_i64 temp64 = tcg_temp_new_i64(); |
1651 | switch (mode) { | |
1652 | case MODE_LL: | |
bf38ca5c | 1653 | GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); |
f4aef476 BK |
1654 | break; |
1655 | case MODE_LU: | |
bf38ca5c | 1656 | GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); |
f4aef476 BK |
1657 | break; |
1658 | case MODE_UL: | |
bf38ca5c | 1659 | GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); |
f4aef476 BK |
1660 | break; |
1661 | case MODE_UU: | |
bf38ca5c | 1662 | GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); |
f4aef476 BK |
1663 | break; |
1664 | } | |
ad75a51e | 1665 | gen_helper_subr_h(ret, tcg_env, temp64, r1_low, r1_high); |
f4aef476 BK |
1666 | } |
1667 | ||
1668 | static inline void | |
1669 | gen_msubr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) | |
1670 | { | |
1671 | TCGv temp = tcg_temp_new(); | |
1672 | TCGv temp2 = tcg_temp_new(); | |
1673 | ||
1674 | tcg_gen_andi_tl(temp2, r1, 0xffff0000); | |
1675 | tcg_gen_shli_tl(temp, r1, 16); | |
1676 | gen_msubr64_h(ret, temp, temp2, r2, r3, n, mode); | |
f4aef476 BK |
1677 | } |
1678 | ||
1679 | static inline void | |
1680 | gen_msubr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, | |
1681 | uint32_t n, uint32_t mode) | |
1682 | { | |
bf38ca5c | 1683 | TCGv t_n = tcg_constant_i32(n); |
f4aef476 BK |
1684 | TCGv_i64 temp64 = tcg_temp_new_i64(); |
1685 | switch (mode) { | |
1686 | case MODE_LL: | |
bf38ca5c | 1687 | GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); |
f4aef476 BK |
1688 | break; |
1689 | case MODE_LU: | |
bf38ca5c | 1690 | GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); |
f4aef476 BK |
1691 | break; |
1692 | case MODE_UL: | |
bf38ca5c | 1693 | GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); |
f4aef476 BK |
1694 | break; |
1695 | case MODE_UU: | |
bf38ca5c | 1696 | GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); |
f4aef476 BK |
1697 | break; |
1698 | } | |
ad75a51e | 1699 | gen_helper_subr_h_ssov(ret, tcg_env, temp64, r1_low, r1_high); |
f4aef476 BK |
1700 | } |
1701 | ||
1702 | static inline void | |
1703 | gen_msubr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) | |
1704 | { | |
1705 | TCGv temp = tcg_temp_new(); | |
1706 | TCGv temp2 = tcg_temp_new(); | |
1707 | ||
1708 | tcg_gen_andi_tl(temp2, r1, 0xffff0000); | |
1709 | tcg_gen_shli_tl(temp, r1, 16); | |
1710 | gen_msubr64s_h(ret, temp, temp2, r2, r3, n, mode); | |
f4aef476 BK |
1711 | } |
1712 | ||
62e47b2e BK |
1713 | static inline void |
1714 | gen_msubr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) | |
1715 | { | |
151293c2 | 1716 | TCGv temp = tcg_constant_i32(n); |
ad75a51e | 1717 | gen_helper_msubr_q(ret, tcg_env, r1, r2, r3, temp); |
62e47b2e BK |
1718 | } |
1719 | ||
1720 | static inline void | |
1721 | gen_msubrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) | |
1722 | { | |
151293c2 | 1723 | TCGv temp = tcg_constant_i32(n); |
ad75a51e | 1724 | gen_helper_msubr_q_ssov(ret, tcg_env, r1, r2, r3, temp); |
62e47b2e BK |
1725 | } |
1726 | ||
1727 | static inline void | |
1728 | gen_msub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, | |
2db92a0c | 1729 | uint32_t up_shift) |
62e47b2e | 1730 | { |
62e47b2e BK |
1731 | TCGv temp3 = tcg_temp_new(); |
1732 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1733 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
1734 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
1735 | TCGv_i64 t4 = tcg_temp_new_i64(); | |
1736 | ||
1737 | tcg_gen_ext_i32_i64(t2, arg2); | |
1738 | tcg_gen_ext_i32_i64(t3, arg3); | |
1739 | ||
1740 | tcg_gen_mul_i64(t2, t2, t3); | |
1741 | ||
1742 | tcg_gen_ext_i32_i64(t1, arg1); | |
1743 | /* if we shift part of the fraction out, we need to round up */ | |
1744 | tcg_gen_andi_i64(t4, t2, (1ll << (up_shift - n)) - 1); | |
1745 | tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0); | |
1746 | tcg_gen_sari_i64(t2, t2, up_shift - n); | |
1747 | tcg_gen_add_i64(t2, t2, t4); | |
1748 | ||
1749 | tcg_gen_sub_i64(t3, t1, t2); | |
ecc7b3aa | 1750 | tcg_gen_extrl_i64_i32(temp3, t3); |
62e47b2e BK |
1751 | /* calc v bit */ |
1752 | tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL); | |
1753 | tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL); | |
1754 | tcg_gen_or_i64(t1, t1, t2); | |
ecc7b3aa | 1755 | tcg_gen_extrl_i64_i32(cpu_PSW_V, t1); |
62e47b2e | 1756 | tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); |
62e47b2e BK |
1757 | /* Calc SV bit */ |
1758 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
1759 | /* Calc AV/SAV bits */ | |
1760 | tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3); | |
1761 | tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV); | |
1762 | /* calc SAV */ | |
1763 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
1764 | /* write back result */ | |
1765 | tcg_gen_mov_tl(ret, temp3); | |
62e47b2e BK |
1766 | } |
1767 | ||
1768 | static inline void | |
1769 | gen_m16sub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n) | |
1770 | { | |
1771 | TCGv temp = tcg_temp_new(); | |
1772 | TCGv temp2 = tcg_temp_new(); | |
1773 | if (n == 0) { | |
1774 | tcg_gen_mul_tl(temp, arg2, arg3); | |
de7ad4ce | 1775 | } else { /* n is expected to be 1 */ |
62e47b2e BK |
1776 | tcg_gen_mul_tl(temp, arg2, arg3); |
1777 | tcg_gen_shli_tl(temp, temp, 1); | |
1778 | /* catch special case r1 = r2 = 0x8000 */ | |
1779 | tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); | |
1780 | tcg_gen_sub_tl(temp, temp, temp2); | |
1781 | } | |
1782 | gen_sub_d(ret, arg1, temp); | |
62e47b2e BK |
1783 | } |
1784 | ||
1785 | static inline void | |
1786 | gen_m16subs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n) | |
1787 | { | |
1788 | TCGv temp = tcg_temp_new(); | |
1789 | TCGv temp2 = tcg_temp_new(); | |
1790 | if (n == 0) { | |
1791 | tcg_gen_mul_tl(temp, arg2, arg3); | |
de7ad4ce | 1792 | } else { /* n is expected to be 1 */ |
62e47b2e BK |
1793 | tcg_gen_mul_tl(temp, arg2, arg3); |
1794 | tcg_gen_shli_tl(temp, temp, 1); | |
1795 | /* catch special case r1 = r2 = 0x8000 */ | |
1796 | tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); | |
1797 | tcg_gen_sub_tl(temp, temp, temp2); | |
1798 | } | |
1799 | gen_subs(ret, arg1, temp); | |
62e47b2e BK |
1800 | } |
1801 | ||
1802 | static inline void | |
1803 | gen_m16sub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, | |
1804 | TCGv arg3, uint32_t n) | |
1805 | { | |
1806 | TCGv temp = tcg_temp_new(); | |
1807 | TCGv temp2 = tcg_temp_new(); | |
1808 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1809 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
1810 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
1811 | ||
1812 | if (n == 0) { | |
1813 | tcg_gen_mul_tl(temp, arg2, arg3); | |
de7ad4ce | 1814 | } else { /* n is expected to be 1 */ |
62e47b2e BK |
1815 | tcg_gen_mul_tl(temp, arg2, arg3); |
1816 | tcg_gen_shli_tl(temp, temp, 1); | |
1817 | /* catch special case r1 = r2 = 0x8000 */ | |
1818 | tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); | |
1819 | tcg_gen_sub_tl(temp, temp, temp2); | |
1820 | } | |
1821 | tcg_gen_ext_i32_i64(t2, temp); | |
1822 | tcg_gen_shli_i64(t2, t2, 16); | |
1823 | tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); | |
1824 | gen_sub64_d(t3, t1, t2); | |
1825 | /* write back result */ | |
1826 | tcg_gen_extr_i64_i32(rl, rh, t3); | |
62e47b2e BK |
1827 | } |
1828 | ||
1829 | static inline void | |
1830 | gen_m16subs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, | |
1831 | TCGv arg3, uint32_t n) | |
1832 | { | |
1833 | TCGv temp = tcg_temp_new(); | |
1834 | TCGv temp2 = tcg_temp_new(); | |
1835 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1836 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
1837 | ||
1838 | if (n == 0) { | |
1839 | tcg_gen_mul_tl(temp, arg2, arg3); | |
de7ad4ce | 1840 | } else { /* n is expected to be 1 */ |
62e47b2e BK |
1841 | tcg_gen_mul_tl(temp, arg2, arg3); |
1842 | tcg_gen_shli_tl(temp, temp, 1); | |
1843 | /* catch special case r1 = r2 = 0x8000 */ | |
1844 | tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); | |
1845 | tcg_gen_sub_tl(temp, temp, temp2); | |
1846 | } | |
1847 | tcg_gen_ext_i32_i64(t2, temp); | |
1848 | tcg_gen_shli_i64(t2, t2, 16); | |
1849 | tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); | |
1850 | ||
ad75a51e | 1851 | gen_helper_sub64_ssov(t1, tcg_env, t1, t2); |
62e47b2e | 1852 | tcg_gen_extr_i64_i32(rl, rh, t1); |
62e47b2e BK |
1853 | } |
1854 | ||
1855 | static inline void | |
1856 | gen_msub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, | |
2db92a0c | 1857 | TCGv arg3, uint32_t n) |
62e47b2e BK |
1858 | { |
1859 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1860 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
1861 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
1862 | TCGv_i64 t4 = tcg_temp_new_i64(); | |
1863 | TCGv temp, temp2; | |
1864 | ||
1865 | tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); | |
1866 | tcg_gen_ext_i32_i64(t2, arg2); | |
1867 | tcg_gen_ext_i32_i64(t3, arg3); | |
1868 | ||
1869 | tcg_gen_mul_i64(t2, t2, t3); | |
1870 | if (n != 0) { | |
1871 | tcg_gen_shli_i64(t2, t2, 1); | |
1872 | } | |
1873 | tcg_gen_sub_i64(t4, t1, t2); | |
1874 | /* calc v bit */ | |
1875 | tcg_gen_xor_i64(t3, t4, t1); | |
1876 | tcg_gen_xor_i64(t2, t1, t2); | |
1877 | tcg_gen_and_i64(t3, t3, t2); | |
609ad705 | 1878 | tcg_gen_extrh_i64_i32(cpu_PSW_V, t3); |
62e47b2e BK |
1879 | /* We produce an overflow on the host if the mul before was |
1880 | (0x80000000 * 0x80000000) << 1). If this is the | |
1881 | case, we negate the ovf. */ | |
1882 | if (n == 1) { | |
1883 | temp = tcg_temp_new(); | |
1884 | temp2 = tcg_temp_new(); | |
1885 | tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000); | |
1886 | tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3); | |
1887 | tcg_gen_and_tl(temp, temp, temp2); | |
1888 | tcg_gen_shli_tl(temp, temp, 31); | |
1889 | /* negate v bit, if special condition */ | |
1890 | tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp); | |
62e47b2e BK |
1891 | } |
1892 | /* write back result */ | |
1893 | tcg_gen_extr_i64_i32(rl, rh, t4); | |
1894 | /* Calc SV bit */ | |
1895 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
1896 | /* Calc AV/SAV bits */ | |
1897 | tcg_gen_add_tl(cpu_PSW_AV, rh, rh); | |
1898 | tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV); | |
1899 | /* calc SAV */ | |
1900 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
62e47b2e BK |
1901 | } |
1902 | ||
1903 | static inline void | |
1904 | gen_msubs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, | |
1905 | uint32_t up_shift) | |
1906 | { | |
1907 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1908 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
1909 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
1910 | TCGv_i64 t4 = tcg_temp_new_i64(); | |
1911 | ||
1912 | tcg_gen_ext_i32_i64(t1, arg1); | |
1913 | tcg_gen_ext_i32_i64(t2, arg2); | |
1914 | tcg_gen_ext_i32_i64(t3, arg3); | |
1915 | ||
1916 | tcg_gen_mul_i64(t2, t2, t3); | |
1917 | /* if we shift part of the fraction out, we need to round up */ | |
1918 | tcg_gen_andi_i64(t4, t2, (1ll << (up_shift - n)) - 1); | |
1919 | tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0); | |
1920 | tcg_gen_sari_i64(t3, t2, up_shift - n); | |
1921 | tcg_gen_add_i64(t3, t3, t4); | |
1922 | ||
ad75a51e | 1923 | gen_helper_msub32_q_sub_ssov(ret, tcg_env, t1, t3); |
62e47b2e BK |
1924 | } |
1925 | ||
1926 | static inline void | |
1927 | gen_msubs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, | |
1928 | TCGv arg3, uint32_t n) | |
1929 | { | |
1930 | TCGv_i64 r1 = tcg_temp_new_i64(); | |
bf38ca5c | 1931 | TCGv t_n = tcg_constant_i32(n); |
62e47b2e BK |
1932 | |
1933 | tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high); | |
ad75a51e | 1934 | gen_helper_msub64_q_ssov(r1, tcg_env, r1, arg2, arg3, t_n); |
62e47b2e | 1935 | tcg_gen_extr_i64_i32(rl, rh, r1); |
62e47b2e BK |
1936 | } |
1937 | ||
068fac77 BK |
1938 | static inline void |
1939 | gen_msubad_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, | |
1940 | TCGv r3, uint32_t n, uint32_t mode) | |
1941 | { | |
bf38ca5c RH |
1942 | TCGv t_n = tcg_constant_i32(n); |
1943 | TCGv temp = tcg_temp_new(); | |
068fac77 BK |
1944 | TCGv temp2 = tcg_temp_new(); |
1945 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
1946 | switch (mode) { | |
1947 | case MODE_LL: | |
bf38ca5c | 1948 | GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); |
068fac77 BK |
1949 | break; |
1950 | case MODE_LU: | |
bf38ca5c | 1951 | GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); |
068fac77 BK |
1952 | break; |
1953 | case MODE_UL: | |
bf38ca5c | 1954 | GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); |
068fac77 BK |
1955 | break; |
1956 | case MODE_UU: | |
bf38ca5c | 1957 | GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); |
068fac77 BK |
1958 | break; |
1959 | } | |
1960 | tcg_gen_extr_i64_i32(temp, temp2, temp64); | |
1961 | gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, | |
1962 | tcg_gen_add_tl, tcg_gen_sub_tl); | |
068fac77 BK |
1963 | } |
1964 | ||
1965 | static inline void | |
1966 | gen_msubadm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, | |
1967 | TCGv r3, uint32_t n, uint32_t mode) | |
1968 | { | |
bf38ca5c | 1969 | TCGv t_n = tcg_constant_i32(n); |
068fac77 BK |
1970 | TCGv_i64 temp64 = tcg_temp_new_i64(); |
1971 | TCGv_i64 temp64_2 = tcg_temp_new_i64(); | |
1972 | TCGv_i64 temp64_3 = tcg_temp_new_i64(); | |
1973 | switch (mode) { | |
1974 | case MODE_LL: | |
bf38ca5c | 1975 | GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); |
068fac77 BK |
1976 | break; |
1977 | case MODE_LU: | |
bf38ca5c | 1978 | GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); |
068fac77 BK |
1979 | break; |
1980 | case MODE_UL: | |
bf38ca5c | 1981 | GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); |
068fac77 BK |
1982 | break; |
1983 | case MODE_UU: | |
bf38ca5c | 1984 | GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); |
068fac77 BK |
1985 | break; |
1986 | } | |
1987 | tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high); | |
1988 | tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ | |
1989 | tcg_gen_ext32s_i64(temp64, temp64); /* low */ | |
1990 | tcg_gen_sub_i64(temp64, temp64_2, temp64); | |
1991 | tcg_gen_shli_i64(temp64, temp64, 16); | |
1992 | ||
1993 | gen_sub64_d(temp64_2, temp64_3, temp64); | |
1994 | /* write back result */ | |
1995 | tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2); | |
068fac77 BK |
1996 | } |
1997 | ||
1998 | static inline void | |
1999 | gen_msubadr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) | |
2000 | { | |
bf38ca5c RH |
2001 | TCGv t_n = tcg_constant_i32(n); |
2002 | TCGv temp = tcg_temp_new(); | |
068fac77 BK |
2003 | TCGv temp2 = tcg_temp_new(); |
2004 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
2005 | switch (mode) { | |
2006 | case MODE_LL: | |
bf38ca5c | 2007 | GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); |
068fac77 BK |
2008 | break; |
2009 | case MODE_LU: | |
bf38ca5c | 2010 | GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); |
068fac77 BK |
2011 | break; |
2012 | case MODE_UL: | |
bf38ca5c | 2013 | GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); |
068fac77 BK |
2014 | break; |
2015 | case MODE_UU: | |
bf38ca5c | 2016 | GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); |
068fac77 BK |
2017 | break; |
2018 | } | |
2019 | tcg_gen_andi_tl(temp2, r1, 0xffff0000); | |
2020 | tcg_gen_shli_tl(temp, r1, 16); | |
ad75a51e | 2021 | gen_helper_subadr_h(ret, tcg_env, temp64, temp, temp2); |
068fac77 BK |
2022 | } |
2023 | ||
2024 | static inline void | |
2025 | gen_msubads_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, | |
2026 | TCGv r3, uint32_t n, uint32_t mode) | |
2027 | { | |
bf38ca5c RH |
2028 | TCGv t_n = tcg_constant_i32(n); |
2029 | TCGv temp = tcg_temp_new(); | |
068fac77 BK |
2030 | TCGv temp2 = tcg_temp_new(); |
2031 | TCGv temp3 = tcg_temp_new(); | |
2032 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
2033 | ||
2034 | switch (mode) { | |
2035 | case MODE_LL: | |
bf38ca5c | 2036 | GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); |
068fac77 BK |
2037 | break; |
2038 | case MODE_LU: | |
bf38ca5c | 2039 | GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); |
068fac77 BK |
2040 | break; |
2041 | case MODE_UL: | |
bf38ca5c | 2042 | GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); |
068fac77 BK |
2043 | break; |
2044 | case MODE_UU: | |
bf38ca5c | 2045 | GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); |
068fac77 BK |
2046 | break; |
2047 | } | |
2048 | tcg_gen_extr_i64_i32(temp, temp2, temp64); | |
2049 | gen_adds(ret_low, r1_low, temp); | |
2050 | tcg_gen_mov_tl(temp, cpu_PSW_V); | |
2051 | tcg_gen_mov_tl(temp3, cpu_PSW_AV); | |
2052 | gen_subs(ret_high, r1_high, temp2); | |
2053 | /* combine v bits */ | |
2054 | tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); | |
2055 | /* combine av bits */ | |
2056 | tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); | |
068fac77 BK |
2057 | } |
2058 | ||
2059 | static inline void | |
2060 | gen_msubadms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, | |
2061 | TCGv r3, uint32_t n, uint32_t mode) | |
2062 | { | |
bf38ca5c | 2063 | TCGv t_n = tcg_constant_i32(n); |
068fac77 BK |
2064 | TCGv_i64 temp64 = tcg_temp_new_i64(); |
2065 | TCGv_i64 temp64_2 = tcg_temp_new_i64(); | |
2066 | ||
2067 | switch (mode) { | |
2068 | case MODE_LL: | |
bf38ca5c | 2069 | GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); |
068fac77 BK |
2070 | break; |
2071 | case MODE_LU: | |
bf38ca5c | 2072 | GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); |
068fac77 BK |
2073 | break; |
2074 | case MODE_UL: | |
bf38ca5c | 2075 | GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); |
068fac77 BK |
2076 | break; |
2077 | case MODE_UU: | |
bf38ca5c | 2078 | GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); |
068fac77 BK |
2079 | break; |
2080 | } | |
2081 | tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ | |
2082 | tcg_gen_ext32s_i64(temp64, temp64); /* low */ | |
2083 | tcg_gen_sub_i64(temp64, temp64_2, temp64); | |
2084 | tcg_gen_shli_i64(temp64, temp64, 16); | |
2085 | tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); | |
2086 | ||
ad75a51e | 2087 | gen_helper_sub64_ssov(temp64, tcg_env, temp64_2, temp64); |
068fac77 | 2088 | tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); |
068fac77 BK |
2089 | } |
2090 | ||
2091 | static inline void | |
2092 | gen_msubadr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) | |
2093 | { | |
bf38ca5c RH |
2094 | TCGv t_n = tcg_constant_i32(n); |
2095 | TCGv temp = tcg_temp_new(); | |
068fac77 BK |
2096 | TCGv temp2 = tcg_temp_new(); |
2097 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
2098 | switch (mode) { | |
2099 | case MODE_LL: | |
bf38ca5c | 2100 | GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); |
068fac77 BK |
2101 | break; |
2102 | case MODE_LU: | |
bf38ca5c | 2103 | GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); |
068fac77 BK |
2104 | break; |
2105 | case MODE_UL: | |
bf38ca5c | 2106 | GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); |
068fac77 BK |
2107 | break; |
2108 | case MODE_UU: | |
bf38ca5c | 2109 | GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); |
068fac77 BK |
2110 | break; |
2111 | } | |
2112 | tcg_gen_andi_tl(temp2, r1, 0xffff0000); | |
2113 | tcg_gen_shli_tl(temp, r1, 16); | |
ad75a51e | 2114 | gen_helper_subadr_h_ssov(ret, tcg_env, temp64, temp, temp2); |
068fac77 BK |
2115 | } |
2116 | ||
d5de7839 BK |
2117 | static inline void gen_abs(TCGv ret, TCGv r1) |
2118 | { | |
2f8036d2 | 2119 | tcg_gen_abs_tl(ret, r1); |
d5de7839 BK |
2120 | /* overflow can only happen, if r1 = 0x80000000 */ |
2121 | tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, r1, 0x80000000); | |
2122 | tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); | |
2123 | /* calc SV bit */ | |
2124 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
2125 | /* Calc AV bit */ | |
2126 | tcg_gen_add_tl(cpu_PSW_AV, ret, ret); | |
2127 | tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); | |
2128 | /* calc SAV bit */ | |
2129 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
d5de7839 BK |
2130 | } |
2131 | ||
0974257e BK |
2132 | static inline void gen_absdif(TCGv ret, TCGv r1, TCGv r2) |
2133 | { | |
2134 | TCGv temp = tcg_temp_new_i32(); | |
2135 | TCGv result = tcg_temp_new_i32(); | |
2136 | ||
2137 | tcg_gen_sub_tl(result, r1, r2); | |
2138 | tcg_gen_sub_tl(temp, r2, r1); | |
2139 | tcg_gen_movcond_tl(TCG_COND_GT, result, r1, r2, result, temp); | |
2140 | ||
2141 | /* calc V bit */ | |
2142 | tcg_gen_xor_tl(cpu_PSW_V, result, r1); | |
2143 | tcg_gen_xor_tl(temp, result, r2); | |
2144 | tcg_gen_movcond_tl(TCG_COND_GT, cpu_PSW_V, r1, r2, cpu_PSW_V, temp); | |
2145 | tcg_gen_xor_tl(temp, r1, r2); | |
2146 | tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp); | |
2147 | /* calc SV bit */ | |
2148 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
2149 | /* Calc AV bit */ | |
2150 | tcg_gen_add_tl(cpu_PSW_AV, result, result); | |
2151 | tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); | |
2152 | /* calc SAV bit */ | |
2153 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
2154 | /* write back result */ | |
2155 | tcg_gen_mov_tl(ret, result); | |
0974257e BK |
2156 | } |
2157 | ||
2158 | static inline void gen_absdifi(TCGv ret, TCGv r1, int32_t con) | |
2159 | { | |
151293c2 | 2160 | TCGv temp = tcg_constant_i32(con); |
0974257e | 2161 | gen_absdif(ret, r1, temp); |
0974257e BK |
2162 | } |
2163 | ||
2164 | static inline void gen_absdifsi(TCGv ret, TCGv r1, int32_t con) | |
2165 | { | |
151293c2 | 2166 | TCGv temp = tcg_constant_i32(con); |
ad75a51e | 2167 | gen_helper_absdif_ssov(ret, tcg_env, r1, temp); |
0974257e BK |
2168 | } |
2169 | ||
2692802a BK |
2170 | static inline void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2) |
2171 | { | |
2172 | TCGv high = tcg_temp_new(); | |
2173 | TCGv low = tcg_temp_new(); | |
2174 | ||
2175 | tcg_gen_muls2_tl(low, high, r1, r2); | |
2176 | tcg_gen_mov_tl(ret, low); | |
2177 | /* calc V bit */ | |
2178 | tcg_gen_sari_tl(low, low, 31); | |
2179 | tcg_gen_setcond_tl(TCG_COND_NE, cpu_PSW_V, high, low); | |
2180 | tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); | |
2181 | /* calc SV bit */ | |
2182 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
2183 | /* Calc AV bit */ | |
2184 | tcg_gen_add_tl(cpu_PSW_AV, ret, ret); | |
2185 | tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); | |
2186 | /* calc SAV bit */ | |
2187 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
2692802a BK |
2188 | } |
2189 | ||
0974257e BK |
2190 | static inline void gen_muli_i32s(TCGv ret, TCGv r1, int32_t con) |
2191 | { | |
151293c2 | 2192 | TCGv temp = tcg_constant_i32(con); |
0974257e | 2193 | gen_mul_i32s(ret, r1, temp); |
0974257e BK |
2194 | } |
2195 | ||
2196 | static inline void gen_mul_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2) | |
2197 | { | |
2198 | tcg_gen_muls2_tl(ret_low, ret_high, r1, r2); | |
2199 | /* clear V bit */ | |
2200 | tcg_gen_movi_tl(cpu_PSW_V, 0); | |
2201 | /* calc SV bit */ | |
2202 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
2203 | /* Calc AV bit */ | |
2204 | tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); | |
2205 | tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); | |
2206 | /* calc SAV bit */ | |
2207 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
2208 | } | |
2209 | ||
2210 | static inline void gen_muli_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, | |
2211 | int32_t con) | |
2212 | { | |
151293c2 | 2213 | TCGv temp = tcg_constant_i32(con); |
0974257e | 2214 | gen_mul_i64s(ret_low, ret_high, r1, temp); |
0974257e BK |
2215 | } |
2216 | ||
2217 | static inline void gen_mul_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2) | |
2218 | { | |
2219 | tcg_gen_mulu2_tl(ret_low, ret_high, r1, r2); | |
2220 | /* clear V bit */ | |
2221 | tcg_gen_movi_tl(cpu_PSW_V, 0); | |
2222 | /* calc SV bit */ | |
2223 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
2224 | /* Calc AV bit */ | |
2225 | tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); | |
2226 | tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); | |
2227 | /* calc SAV bit */ | |
2228 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
2229 | } | |
2230 | ||
2231 | static inline void gen_muli_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, | |
2232 | int32_t con) | |
2233 | { | |
151293c2 | 2234 | TCGv temp = tcg_constant_i32(con); |
0974257e | 2235 | gen_mul_i64u(ret_low, ret_high, r1, temp); |
0974257e BK |
2236 | } |
2237 | ||
2238 | static inline void gen_mulsi_i32(TCGv ret, TCGv r1, int32_t con) | |
2239 | { | |
151293c2 | 2240 | TCGv temp = tcg_constant_i32(con); |
ad75a51e | 2241 | gen_helper_mul_ssov(ret, tcg_env, r1, temp); |
0974257e BK |
2242 | } |
2243 | ||
2244 | static inline void gen_mulsui_i32(TCGv ret, TCGv r1, int32_t con) | |
2245 | { | |
151293c2 | 2246 | TCGv temp = tcg_constant_i32(con); |
ad75a51e | 2247 | gen_helper_mul_suov(ret, tcg_env, r1, temp); |
0974257e | 2248 | } |
151293c2 | 2249 | |
328f1f0f BK |
2250 | /* gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); */ |
2251 | static inline void gen_maddsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) | |
2252 | { | |
151293c2 | 2253 | TCGv temp = tcg_constant_i32(con); |
ad75a51e | 2254 | gen_helper_madd32_ssov(ret, tcg_env, r1, r2, temp); |
328f1f0f BK |
2255 | } |
2256 | ||
2257 | static inline void gen_maddsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) | |
2258 | { | |
151293c2 | 2259 | TCGv temp = tcg_constant_i32(con); |
ad75a51e | 2260 | gen_helper_madd32_suov(ret, tcg_env, r1, r2, temp); |
328f1f0f BK |
2261 | } |
2262 | ||
f1cc6eaf BK |
2263 | static void |
2264 | gen_mul_q(TCGv rl, TCGv rh, TCGv arg1, TCGv arg2, uint32_t n, uint32_t up_shift) | |
2265 | { | |
f1cc6eaf BK |
2266 | TCGv_i64 temp_64 = tcg_temp_new_i64(); |
2267 | TCGv_i64 temp2_64 = tcg_temp_new_i64(); | |
2268 | ||
2269 | if (n == 0) { | |
2270 | if (up_shift == 32) { | |
2271 | tcg_gen_muls2_tl(rh, rl, arg1, arg2); | |
2272 | } else if (up_shift == 16) { | |
2273 | tcg_gen_ext_i32_i64(temp_64, arg1); | |
2274 | tcg_gen_ext_i32_i64(temp2_64, arg2); | |
2275 | ||
2276 | tcg_gen_mul_i64(temp_64, temp_64, temp2_64); | |
2277 | tcg_gen_shri_i64(temp_64, temp_64, up_shift); | |
2278 | tcg_gen_extr_i64_i32(rl, rh, temp_64); | |
2279 | } else { | |
2280 | tcg_gen_muls2_tl(rl, rh, arg1, arg2); | |
2281 | } | |
2282 | /* reset v bit */ | |
2283 | tcg_gen_movi_tl(cpu_PSW_V, 0); | |
de7ad4ce | 2284 | } else { /* n is expected to be 1 */ |
f1cc6eaf BK |
2285 | tcg_gen_ext_i32_i64(temp_64, arg1); |
2286 | tcg_gen_ext_i32_i64(temp2_64, arg2); | |
2287 | ||
2288 | tcg_gen_mul_i64(temp_64, temp_64, temp2_64); | |
2289 | ||
2290 | if (up_shift == 0) { | |
2291 | tcg_gen_shli_i64(temp_64, temp_64, 1); | |
2292 | } else { | |
2293 | tcg_gen_shri_i64(temp_64, temp_64, up_shift - 1); | |
2294 | } | |
2295 | tcg_gen_extr_i64_i32(rl, rh, temp_64); | |
de7ad4ce | 2296 | /* overflow only occurs if r1 = r2 = 0x8000 */ |
f1cc6eaf BK |
2297 | if (up_shift == 0) {/* result is 64 bit */ |
2298 | tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rh, | |
2299 | 0x80000000); | |
2300 | } else { /* result is 32 bit */ | |
2301 | tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rl, | |
2302 | 0x80000000); | |
2303 | } | |
2304 | tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); | |
2305 | /* calc sv overflow bit */ | |
2306 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
2307 | } | |
2308 | /* calc av overflow bit */ | |
2309 | if (up_shift == 0) { | |
2310 | tcg_gen_add_tl(cpu_PSW_AV, rh, rh); | |
2311 | tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV); | |
2312 | } else { | |
2313 | tcg_gen_add_tl(cpu_PSW_AV, rl, rl); | |
2314 | tcg_gen_xor_tl(cpu_PSW_AV, rl, cpu_PSW_AV); | |
2315 | } | |
2316 | /* calc sav overflow bit */ | |
2317 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
f1cc6eaf BK |
2318 | } |
2319 | ||
2320 | static void | |
2321 | gen_mul_q_16(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n) | |
2322 | { | |
2323 | TCGv temp = tcg_temp_new(); | |
2324 | if (n == 0) { | |
2325 | tcg_gen_mul_tl(ret, arg1, arg2); | |
de7ad4ce | 2326 | } else { /* n is expected to be 1 */ |
f1cc6eaf BK |
2327 | tcg_gen_mul_tl(ret, arg1, arg2); |
2328 | tcg_gen_shli_tl(ret, ret, 1); | |
2329 | /* catch special case r1 = r2 = 0x8000 */ | |
2330 | tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80000000); | |
2331 | tcg_gen_sub_tl(ret, ret, temp); | |
2332 | } | |
2333 | /* reset v bit */ | |
2334 | tcg_gen_movi_tl(cpu_PSW_V, 0); | |
2335 | /* calc av overflow bit */ | |
2336 | tcg_gen_add_tl(cpu_PSW_AV, ret, ret); | |
2337 | tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); | |
2338 | /* calc sav overflow bit */ | |
2339 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
f1cc6eaf BK |
2340 | } |
2341 | ||
2342 | static void gen_mulr_q(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n) | |
2343 | { | |
2344 | TCGv temp = tcg_temp_new(); | |
2345 | if (n == 0) { | |
2346 | tcg_gen_mul_tl(ret, arg1, arg2); | |
2347 | tcg_gen_addi_tl(ret, ret, 0x8000); | |
2348 | } else { | |
2349 | tcg_gen_mul_tl(ret, arg1, arg2); | |
2350 | tcg_gen_shli_tl(ret, ret, 1); | |
2351 | tcg_gen_addi_tl(ret, ret, 0x8000); | |
2352 | /* catch special case r1 = r2 = 0x8000 */ | |
2353 | tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80008000); | |
2354 | tcg_gen_muli_tl(temp, temp, 0x8001); | |
2355 | tcg_gen_sub_tl(ret, ret, temp); | |
2356 | } | |
2357 | /* reset v bit */ | |
2358 | tcg_gen_movi_tl(cpu_PSW_V, 0); | |
2359 | /* calc av overflow bit */ | |
2360 | tcg_gen_add_tl(cpu_PSW_AV, ret, ret); | |
2361 | tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); | |
2362 | /* calc sav overflow bit */ | |
2363 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
2364 | /* cut halfword off */ | |
2365 | tcg_gen_andi_tl(ret, ret, 0xffff0000); | |
f1cc6eaf BK |
2366 | } |
2367 | ||
2984cfbd BK |
2368 | static inline void |
2369 | gen_madds_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
2370 | TCGv r3) | |
2371 | { | |
2372 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
2373 | tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); | |
ad75a51e | 2374 | gen_helper_madd64_ssov(temp64, tcg_env, r1, temp64, r3); |
2984cfbd | 2375 | tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); |
2984cfbd BK |
2376 | } |
2377 | ||
328f1f0f BK |
2378 | static inline void |
2379 | gen_maddsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
2380 | int32_t con) | |
2381 | { | |
151293c2 | 2382 | TCGv temp = tcg_constant_i32(con); |
2984cfbd | 2383 | gen_madds_64(ret_low, ret_high, r1, r2_low, r2_high, temp); |
2984cfbd BK |
2384 | } |
2385 | ||
2386 | static inline void | |
2387 | gen_maddsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
2388 | TCGv r3) | |
2389 | { | |
328f1f0f BK |
2390 | TCGv_i64 temp64 = tcg_temp_new_i64(); |
2391 | tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); | |
ad75a51e | 2392 | gen_helper_madd64_suov(temp64, tcg_env, r1, temp64, r3); |
328f1f0f | 2393 | tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); |
328f1f0f BK |
2394 | } |
2395 | ||
2396 | static inline void | |
2397 | gen_maddsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
2398 | int32_t con) | |
2399 | { | |
151293c2 | 2400 | TCGv temp = tcg_constant_i32(con); |
2984cfbd | 2401 | gen_maddsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp); |
328f1f0f BK |
2402 | } |
2403 | ||
2404 | static inline void gen_msubsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) | |
2405 | { | |
151293c2 | 2406 | TCGv temp = tcg_constant_i32(con); |
ad75a51e | 2407 | gen_helper_msub32_ssov(ret, tcg_env, r1, r2, temp); |
328f1f0f BK |
2408 | } |
2409 | ||
2410 | static inline void gen_msubsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) | |
2411 | { | |
151293c2 | 2412 | TCGv temp = tcg_constant_i32(con); |
ad75a51e | 2413 | gen_helper_msub32_suov(ret, tcg_env, r1, r2, temp); |
328f1f0f BK |
2414 | } |
2415 | ||
2984cfbd BK |
2416 | static inline void |
2417 | gen_msubs_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
2418 | TCGv r3) | |
2419 | { | |
2420 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
2421 | tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); | |
ad75a51e | 2422 | gen_helper_msub64_ssov(temp64, tcg_env, r1, temp64, r3); |
2984cfbd | 2423 | tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); |
2984cfbd BK |
2424 | } |
2425 | ||
328f1f0f BK |
2426 | static inline void |
2427 | gen_msubsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
2428 | int32_t con) | |
2429 | { | |
151293c2 | 2430 | TCGv temp = tcg_constant_i32(con); |
2984cfbd | 2431 | gen_msubs_64(ret_low, ret_high, r1, r2_low, r2_high, temp); |
2984cfbd BK |
2432 | } |
2433 | ||
2434 | static inline void | |
2435 | gen_msubsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
2436 | TCGv r3) | |
2437 | { | |
328f1f0f BK |
2438 | TCGv_i64 temp64 = tcg_temp_new_i64(); |
2439 | tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); | |
ad75a51e | 2440 | gen_helper_msub64_suov(temp64, tcg_env, r1, temp64, r3); |
328f1f0f | 2441 | tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); |
328f1f0f BK |
2442 | } |
2443 | ||
2444 | static inline void | |
2445 | gen_msubsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
2446 | int32_t con) | |
2447 | { | |
151293c2 | 2448 | TCGv temp = tcg_constant_i32(con); |
2984cfbd | 2449 | gen_msubsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp); |
328f1f0f | 2450 | } |
0974257e | 2451 | |
44ea3430 BK |
2452 | static void gen_saturate(TCGv ret, TCGv arg, int32_t up, int32_t low) |
2453 | { | |
5a48476e RH |
2454 | tcg_gen_smax_tl(ret, arg, tcg_constant_i32(low)); |
2455 | tcg_gen_smin_tl(ret, ret, tcg_constant_i32(up)); | |
44ea3430 BK |
2456 | } |
2457 | ||
2458 | static void gen_saturate_u(TCGv ret, TCGv arg, int32_t up) | |
2459 | { | |
5a48476e | 2460 | tcg_gen_umin_tl(ret, arg, tcg_constant_i32(up)); |
44ea3430 BK |
2461 | } |
2462 | ||
0707ec1b BK |
2463 | static void gen_shi(TCGv ret, TCGv r1, int32_t shift_count) |
2464 | { | |
2465 | if (shift_count == -32) { | |
2466 | tcg_gen_movi_tl(ret, 0); | |
2467 | } else if (shift_count >= 0) { | |
2468 | tcg_gen_shli_tl(ret, r1, shift_count); | |
2469 | } else { | |
2470 | tcg_gen_shri_tl(ret, r1, -shift_count); | |
2471 | } | |
2472 | } | |
2473 | ||
0974257e BK |
2474 | static void gen_sh_hi(TCGv ret, TCGv r1, int32_t shiftcount) |
2475 | { | |
2476 | TCGv temp_low, temp_high; | |
2477 | ||
2478 | if (shiftcount == -16) { | |
2479 | tcg_gen_movi_tl(ret, 0); | |
2480 | } else { | |
2481 | temp_high = tcg_temp_new(); | |
2482 | temp_low = tcg_temp_new(); | |
2483 | ||
2484 | tcg_gen_andi_tl(temp_low, r1, 0xffff); | |
2485 | tcg_gen_andi_tl(temp_high, r1, 0xffff0000); | |
2486 | gen_shi(temp_low, temp_low, shiftcount); | |
2487 | gen_shi(ret, temp_high, shiftcount); | |
2488 | tcg_gen_deposit_tl(ret, ret, temp_low, 0, 16); | |
0974257e BK |
2489 | } |
2490 | } | |
2491 | ||
0707ec1b BK |
2492 | static void gen_shaci(TCGv ret, TCGv r1, int32_t shift_count) |
2493 | { | |
2494 | uint32_t msk, msk_start; | |
2495 | TCGv temp = tcg_temp_new(); | |
2496 | TCGv temp2 = tcg_temp_new(); | |
0707ec1b BK |
2497 | |
2498 | if (shift_count == 0) { | |
2499 | /* Clear PSW.C and PSW.V */ | |
2500 | tcg_gen_movi_tl(cpu_PSW_C, 0); | |
2501 | tcg_gen_mov_tl(cpu_PSW_V, cpu_PSW_C); | |
2502 | tcg_gen_mov_tl(ret, r1); | |
2503 | } else if (shift_count == -32) { | |
2504 | /* set PSW.C */ | |
2505 | tcg_gen_mov_tl(cpu_PSW_C, r1); | |
cb8d4c8f | 2506 | /* fill ret completely with sign bit */ |
0707ec1b BK |
2507 | tcg_gen_sari_tl(ret, r1, 31); |
2508 | /* clear PSW.V */ | |
2509 | tcg_gen_movi_tl(cpu_PSW_V, 0); | |
2510 | } else if (shift_count > 0) { | |
151293c2 RH |
2511 | TCGv t_max = tcg_constant_i32(0x7FFFFFFF >> shift_count); |
2512 | TCGv t_min = tcg_constant_i32(((int32_t) -0x80000000) >> shift_count); | |
0707ec1b BK |
2513 | |
2514 | /* calc carry */ | |
2515 | msk_start = 32 - shift_count; | |
2516 | msk = ((1 << shift_count) - 1) << msk_start; | |
2517 | tcg_gen_andi_tl(cpu_PSW_C, r1, msk); | |
2518 | /* calc v/sv bits */ | |
2519 | tcg_gen_setcond_tl(TCG_COND_GT, temp, r1, t_max); | |
2520 | tcg_gen_setcond_tl(TCG_COND_LT, temp2, r1, t_min); | |
2521 | tcg_gen_or_tl(cpu_PSW_V, temp, temp2); | |
2522 | tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); | |
2523 | /* calc sv */ | |
2524 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_V, cpu_PSW_SV); | |
2525 | /* do shift */ | |
2526 | tcg_gen_shli_tl(ret, r1, shift_count); | |
0707ec1b BK |
2527 | } else { |
2528 | /* clear PSW.V */ | |
2529 | tcg_gen_movi_tl(cpu_PSW_V, 0); | |
2530 | /* calc carry */ | |
2531 | msk = (1 << -shift_count) - 1; | |
2532 | tcg_gen_andi_tl(cpu_PSW_C, r1, msk); | |
2533 | /* do shift */ | |
2534 | tcg_gen_sari_tl(ret, r1, -shift_count); | |
2535 | } | |
2536 | /* calc av overflow bit */ | |
2537 | tcg_gen_add_tl(cpu_PSW_AV, ret, ret); | |
2538 | tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); | |
2539 | /* calc sav overflow bit */ | |
2540 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
0707ec1b BK |
2541 | } |
2542 | ||
0974257e BK |
2543 | static void gen_shas(TCGv ret, TCGv r1, TCGv r2) |
2544 | { | |
ad75a51e | 2545 | gen_helper_sha_ssov(ret, tcg_env, r1, r2); |
0974257e BK |
2546 | } |
2547 | ||
2548 | static void gen_shasi(TCGv ret, TCGv r1, int32_t con) | |
2549 | { | |
151293c2 | 2550 | TCGv temp = tcg_constant_i32(con); |
0974257e | 2551 | gen_shas(ret, r1, temp); |
0974257e BK |
2552 | } |
2553 | ||
2554 | static void gen_sha_hi(TCGv ret, TCGv r1, int32_t shift_count) | |
2555 | { | |
2556 | TCGv low, high; | |
2557 | ||
2558 | if (shift_count == 0) { | |
2559 | tcg_gen_mov_tl(ret, r1); | |
2560 | } else if (shift_count > 0) { | |
2561 | low = tcg_temp_new(); | |
2562 | high = tcg_temp_new(); | |
2563 | ||
2564 | tcg_gen_andi_tl(high, r1, 0xffff0000); | |
2565 | tcg_gen_shli_tl(low, r1, shift_count); | |
2566 | tcg_gen_shli_tl(ret, high, shift_count); | |
2567 | tcg_gen_deposit_tl(ret, ret, low, 0, 16); | |
0974257e BK |
2568 | } else { |
2569 | low = tcg_temp_new(); | |
2570 | high = tcg_temp_new(); | |
2571 | ||
2572 | tcg_gen_ext16s_tl(low, r1); | |
2573 | tcg_gen_sari_tl(low, low, -shift_count); | |
2574 | tcg_gen_sari_tl(ret, r1, -shift_count); | |
2575 | tcg_gen_deposit_tl(ret, ret, low, 0, 16); | |
0974257e | 2576 | } |
0974257e BK |
2577 | } |
2578 | ||
2579 | /* ret = {ret[30:0], (r1 cond r2)}; */ | |
2580 | static void gen_sh_cond(int cond, TCGv ret, TCGv r1, TCGv r2) | |
2581 | { | |
2582 | TCGv temp = tcg_temp_new(); | |
2583 | TCGv temp2 = tcg_temp_new(); | |
2584 | ||
2585 | tcg_gen_shli_tl(temp, ret, 1); | |
2586 | tcg_gen_setcond_tl(cond, temp2, r1, r2); | |
2587 | tcg_gen_or_tl(ret, temp, temp2); | |
0974257e BK |
2588 | } |
2589 | ||
2590 | static void gen_sh_condi(int cond, TCGv ret, TCGv r1, int32_t con) | |
2591 | { | |
151293c2 | 2592 | TCGv temp = tcg_constant_i32(con); |
0974257e | 2593 | gen_sh_cond(cond, ret, r1, temp); |
0974257e BK |
2594 | } |
2595 | ||
2692802a BK |
2596 | static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2) |
2597 | { | |
ad75a51e | 2598 | gen_helper_add_ssov(ret, tcg_env, r1, r2); |
2692802a BK |
2599 | } |
2600 | ||
0974257e BK |
2601 | static inline void gen_addsi(TCGv ret, TCGv r1, int32_t con) |
2602 | { | |
151293c2 | 2603 | TCGv temp = tcg_constant_i32(con); |
ad75a51e | 2604 | gen_helper_add_ssov(ret, tcg_env, r1, temp); |
0974257e BK |
2605 | } |
2606 | ||
2607 | static inline void gen_addsui(TCGv ret, TCGv r1, int32_t con) | |
2608 | { | |
151293c2 | 2609 | TCGv temp = tcg_constant_i32(con); |
ad75a51e | 2610 | gen_helper_add_suov(ret, tcg_env, r1, temp); |
0974257e BK |
2611 | } |
2612 | ||
2692802a BK |
2613 | static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2) |
2614 | { | |
ad75a51e | 2615 | gen_helper_sub_ssov(ret, tcg_env, r1, r2); |
2692802a BK |
2616 | } |
2617 | ||
0974257e BK |
2618 | static inline void gen_subsu(TCGv ret, TCGv r1, TCGv r2) |
2619 | { | |
ad75a51e | 2620 | gen_helper_sub_suov(ret, tcg_env, r1, r2); |
0974257e BK |
2621 | } |
2622 | ||
b74f2b5b BK |
2623 | static inline void gen_bit_2op(TCGv ret, TCGv r1, TCGv r2, |
2624 | int pos1, int pos2, | |
2625 | void(*op1)(TCGv, TCGv, TCGv), | |
2626 | void(*op2)(TCGv, TCGv, TCGv)) | |
2627 | { | |
2628 | TCGv temp1, temp2; | |
2629 | ||
2630 | temp1 = tcg_temp_new(); | |
2631 | temp2 = tcg_temp_new(); | |
2632 | ||
2633 | tcg_gen_shri_tl(temp2, r2, pos2); | |
2634 | tcg_gen_shri_tl(temp1, r1, pos1); | |
2635 | ||
2636 | (*op1)(temp1, temp1, temp2); | |
2637 | (*op2)(temp1 , ret, temp1); | |
2638 | ||
2639 | tcg_gen_deposit_tl(ret, ret, temp1, 0, 1); | |
b74f2b5b BK |
2640 | } |
2641 | ||
2642 | /* ret = r1[pos1] op1 r2[pos2]; */ | |
2643 | static inline void gen_bit_1op(TCGv ret, TCGv r1, TCGv r2, | |
2644 | int pos1, int pos2, | |
2645 | void(*op1)(TCGv, TCGv, TCGv)) | |
2646 | { | |
2647 | TCGv temp1, temp2; | |
2648 | ||
2649 | temp1 = tcg_temp_new(); | |
2650 | temp2 = tcg_temp_new(); | |
2651 | ||
2652 | tcg_gen_shri_tl(temp2, r2, pos2); | |
2653 | tcg_gen_shri_tl(temp1, r1, pos1); | |
2654 | ||
2655 | (*op1)(ret, temp1, temp2); | |
2656 | ||
2657 | tcg_gen_andi_tl(ret, ret, 0x1); | |
b74f2b5b BK |
2658 | } |
2659 | ||
0974257e BK |
2660 | static inline void gen_accumulating_cond(int cond, TCGv ret, TCGv r1, TCGv r2, |
2661 | void(*op)(TCGv, TCGv, TCGv)) | |
2662 | { | |
2663 | TCGv temp = tcg_temp_new(); | |
2664 | TCGv temp2 = tcg_temp_new(); | |
2665 | /* temp = (arg1 cond arg2 )*/ | |
2666 | tcg_gen_setcond_tl(cond, temp, r1, r2); | |
2667 | /* temp2 = ret[0]*/ | |
2668 | tcg_gen_andi_tl(temp2, ret, 0x1); | |
2669 | /* temp = temp insn temp2 */ | |
2670 | (*op)(temp, temp, temp2); | |
2671 | /* ret = {ret[31:1], temp} */ | |
2672 | tcg_gen_deposit_tl(ret, ret, temp, 0, 1); | |
0974257e BK |
2673 | } |
2674 | ||
2675 | static inline void | |
2676 | gen_accumulating_condi(int cond, TCGv ret, TCGv r1, int32_t con, | |
2677 | void(*op)(TCGv, TCGv, TCGv)) | |
2678 | { | |
151293c2 | 2679 | TCGv temp = tcg_constant_i32(con); |
0974257e | 2680 | gen_accumulating_cond(cond, ret, r1, temp, op); |
0974257e BK |
2681 | } |
2682 | ||
2683 | static inline void gen_eqany_bi(TCGv ret, TCGv r1, int32_t con) | |
2684 | { | |
2685 | TCGv b0 = tcg_temp_new(); | |
2686 | TCGv b1 = tcg_temp_new(); | |
2687 | TCGv b2 = tcg_temp_new(); | |
2688 | TCGv b3 = tcg_temp_new(); | |
2689 | ||
2690 | /* byte 0 */ | |
2691 | tcg_gen_andi_tl(b0, r1, 0xff); | |
2692 | tcg_gen_setcondi_tl(TCG_COND_EQ, b0, b0, con & 0xff); | |
2693 | ||
2694 | /* byte 1 */ | |
2695 | tcg_gen_andi_tl(b1, r1, 0xff00); | |
2696 | tcg_gen_setcondi_tl(TCG_COND_EQ, b1, b1, con & 0xff00); | |
2697 | ||
2698 | /* byte 2 */ | |
2699 | tcg_gen_andi_tl(b2, r1, 0xff0000); | |
2700 | tcg_gen_setcondi_tl(TCG_COND_EQ, b2, b2, con & 0xff0000); | |
2701 | ||
2702 | /* byte 3 */ | |
2703 | tcg_gen_andi_tl(b3, r1, 0xff000000); | |
2704 | tcg_gen_setcondi_tl(TCG_COND_EQ, b3, b3, con & 0xff000000); | |
2705 | ||
2706 | /* combine them */ | |
2707 | tcg_gen_or_tl(ret, b0, b1); | |
2708 | tcg_gen_or_tl(ret, ret, b2); | |
2709 | tcg_gen_or_tl(ret, ret, b3); | |
0974257e BK |
2710 | } |
2711 | ||
2712 | static inline void gen_eqany_hi(TCGv ret, TCGv r1, int32_t con) | |
2713 | { | |
2714 | TCGv h0 = tcg_temp_new(); | |
2715 | TCGv h1 = tcg_temp_new(); | |
2716 | ||
2717 | /* halfword 0 */ | |
2718 | tcg_gen_andi_tl(h0, r1, 0xffff); | |
2719 | tcg_gen_setcondi_tl(TCG_COND_EQ, h0, h0, con & 0xffff); | |
2720 | ||
2721 | /* halfword 1 */ | |
2722 | tcg_gen_andi_tl(h1, r1, 0xffff0000); | |
2723 | tcg_gen_setcondi_tl(TCG_COND_EQ, h1, h1, con & 0xffff0000); | |
2724 | ||
2725 | /* combine them */ | |
2726 | tcg_gen_or_tl(ret, h0, h1); | |
0974257e | 2727 | } |
08ee498b | 2728 | |
ed516260 BK |
2729 | /* mask = ((1 << width) -1) << pos; |
2730 | ret = (r1 & ~mask) | (r2 << pos) & mask); */ | |
2731 | static inline void gen_insert(TCGv ret, TCGv r1, TCGv r2, TCGv width, TCGv pos) | |
2732 | { | |
2733 | TCGv mask = tcg_temp_new(); | |
2734 | TCGv temp = tcg_temp_new(); | |
2735 | TCGv temp2 = tcg_temp_new(); | |
0974257e | 2736 | |
ed516260 BK |
2737 | tcg_gen_movi_tl(mask, 1); |
2738 | tcg_gen_shl_tl(mask, mask, width); | |
2739 | tcg_gen_subi_tl(mask, mask, 1); | |
2740 | tcg_gen_shl_tl(mask, mask, pos); | |
2741 | ||
2742 | tcg_gen_shl_tl(temp, r2, pos); | |
2743 | tcg_gen_and_tl(temp, temp, mask); | |
2744 | tcg_gen_andc_tl(temp2, r1, mask); | |
2745 | tcg_gen_or_tl(ret, temp, temp2); | |
ed516260 | 2746 | } |
0974257e | 2747 | |
e2bed107 BK |
2748 | static inline void gen_bsplit(TCGv rl, TCGv rh, TCGv r1) |
2749 | { | |
2750 | TCGv_i64 temp = tcg_temp_new_i64(); | |
2751 | ||
2752 | gen_helper_bsplit(temp, r1); | |
2753 | tcg_gen_extr_i64_i32(rl, rh, temp); | |
e2bed107 BK |
2754 | } |
2755 | ||
2756 | static inline void gen_unpack(TCGv rl, TCGv rh, TCGv r1) | |
2757 | { | |
2758 | TCGv_i64 temp = tcg_temp_new_i64(); | |
2759 | ||
2760 | gen_helper_unpack(temp, r1); | |
2761 | tcg_gen_extr_i64_i32(rl, rh, temp); | |
e2bed107 BK |
2762 | } |
2763 | ||
2764 | static inline void | |
2db92a0c | 2765 | gen_dvinit_b(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2) |
e2bed107 BK |
2766 | { |
2767 | TCGv_i64 ret = tcg_temp_new_i64(); | |
2768 | ||
44ee3baf | 2769 | if (!has_feature(ctx, TRICORE_FEATURE_131)) { |
ad75a51e | 2770 | gen_helper_dvinit_b_13(ret, tcg_env, r1, r2); |
e2bed107 | 2771 | } else { |
ad75a51e | 2772 | gen_helper_dvinit_b_131(ret, tcg_env, r1, r2); |
e2bed107 BK |
2773 | } |
2774 | tcg_gen_extr_i64_i32(rl, rh, ret); | |
e2bed107 BK |
2775 | } |
2776 | ||
2777 | static inline void | |
2db92a0c | 2778 | gen_dvinit_h(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2) |
e2bed107 BK |
2779 | { |
2780 | TCGv_i64 ret = tcg_temp_new_i64(); | |
2781 | ||
44ee3baf | 2782 | if (!has_feature(ctx, TRICORE_FEATURE_131)) { |
ad75a51e | 2783 | gen_helper_dvinit_h_13(ret, tcg_env, r1, r2); |
e2bed107 | 2784 | } else { |
ad75a51e | 2785 | gen_helper_dvinit_h_131(ret, tcg_env, r1, r2); |
e2bed107 BK |
2786 | } |
2787 | tcg_gen_extr_i64_i32(rl, rh, ret); | |
e2bed107 BK |
2788 | } |
2789 | ||
9655b932 BK |
2790 | static void gen_calc_usb_mul_h(TCGv arg_low, TCGv arg_high) |
2791 | { | |
2792 | TCGv temp = tcg_temp_new(); | |
2793 | /* calc AV bit */ | |
2794 | tcg_gen_add_tl(temp, arg_low, arg_low); | |
2795 | tcg_gen_xor_tl(temp, temp, arg_low); | |
2796 | tcg_gen_add_tl(cpu_PSW_AV, arg_high, arg_high); | |
2797 | tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, arg_high); | |
2798 | tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp); | |
2799 | /* calc SAV bit */ | |
2800 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
2801 | tcg_gen_movi_tl(cpu_PSW_V, 0); | |
9655b932 BK |
2802 | } |
2803 | ||
2804 | static void gen_calc_usb_mulr_h(TCGv arg) | |
2805 | { | |
2806 | TCGv temp = tcg_temp_new(); | |
2807 | /* calc AV bit */ | |
2808 | tcg_gen_add_tl(temp, arg, arg); | |
2809 | tcg_gen_xor_tl(temp, temp, arg); | |
2810 | tcg_gen_shli_tl(cpu_PSW_AV, temp, 16); | |
2811 | tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp); | |
2812 | /* calc SAV bit */ | |
2813 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
2814 | /* clear V bit */ | |
2815 | tcg_gen_movi_tl(cpu_PSW_V, 0); | |
9655b932 BK |
2816 | } |
2817 | ||
9a31922b BK |
2818 | /* helpers for generating program flow micro-ops */ |
2819 | ||
2820 | static inline void gen_save_pc(target_ulong pc) | |
2821 | { | |
2822 | tcg_gen_movi_tl(cpu_PC, pc); | |
2823 | } | |
2824 | ||
d6b6f261 | 2825 | static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) |
9a31922b | 2826 | { |
d6b6f261 | 2827 | if (translator_use_goto_tb(&ctx->base, dest)) { |
9a31922b BK |
2828 | tcg_gen_goto_tb(n); |
2829 | gen_save_pc(dest); | |
6b9f5a42 | 2830 | tcg_gen_exit_tb(ctx->base.tb, n); |
9a31922b BK |
2831 | } else { |
2832 | gen_save_pc(dest); | |
1b55c52d | 2833 | tcg_gen_lookup_and_goto_ptr(); |
9a31922b | 2834 | } |
1706e04f | 2835 | ctx->base.is_jmp = DISAS_NORETURN; |
9a31922b BK |
2836 | } |
2837 | ||
518d7fd2 BK |
2838 | static void generate_trap(DisasContext *ctx, int class, int tin) |
2839 | { | |
151293c2 RH |
2840 | TCGv_i32 classtemp = tcg_constant_i32(class); |
2841 | TCGv_i32 tintemp = tcg_constant_i32(tin); | |
518d7fd2 | 2842 | |
6b9f5a42 | 2843 | gen_save_pc(ctx->base.pc_next); |
ad75a51e | 2844 | gen_helper_raise_exception_sync(tcg_env, classtemp, tintemp); |
6b9f5a42 | 2845 | ctx->base.is_jmp = DISAS_NORETURN; |
518d7fd2 BK |
2846 | } |
2847 | ||
9a31922b BK |
2848 | static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1, |
2849 | TCGv r2, int16_t address) | |
2850 | { | |
42a268c2 | 2851 | TCGLabel *jumpLabel = gen_new_label(); |
9a31922b BK |
2852 | tcg_gen_brcond_tl(cond, r1, r2, jumpLabel); |
2853 | ||
6b9f5a42 | 2854 | gen_goto_tb(ctx, 1, ctx->pc_succ_insn); |
9a31922b BK |
2855 | |
2856 | gen_set_label(jumpLabel); | |
6b9f5a42 | 2857 | gen_goto_tb(ctx, 0, ctx->base.pc_next + address * 2); |
9a31922b BK |
2858 | } |
2859 | ||
2860 | static inline void gen_branch_condi(DisasContext *ctx, TCGCond cond, TCGv r1, | |
2861 | int r2, int16_t address) | |
2862 | { | |
151293c2 | 2863 | TCGv temp = tcg_constant_i32(r2); |
9a31922b | 2864 | gen_branch_cond(ctx, cond, r1, temp, address); |
9a31922b BK |
2865 | } |
2866 | ||
a47b50db BK |
2867 | static void gen_loop(DisasContext *ctx, int r1, int32_t offset) |
2868 | { | |
42a268c2 | 2869 | TCGLabel *l1 = gen_new_label(); |
a47b50db BK |
2870 | |
2871 | tcg_gen_subi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], 1); | |
2872 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr_a[r1], -1, l1); | |
6b9f5a42 | 2873 | gen_goto_tb(ctx, 1, ctx->base.pc_next + offset); |
a47b50db | 2874 | gen_set_label(l1); |
6b9f5a42 | 2875 | gen_goto_tb(ctx, 0, ctx->pc_succ_insn); |
a47b50db BK |
2876 | } |
2877 | ||
9e14a7b2 BK |
2878 | static void gen_fcall_save_ctx(DisasContext *ctx) |
2879 | { | |
2880 | TCGv temp = tcg_temp_new(); | |
2881 | ||
2882 | tcg_gen_addi_tl(temp, cpu_gpr_a[10], -4); | |
2883 | tcg_gen_qemu_st_tl(cpu_gpr_a[11], temp, ctx->mem_idx, MO_LESL); | |
6b9f5a42 | 2884 | tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); |
9e14a7b2 | 2885 | tcg_gen_mov_tl(cpu_gpr_a[10], temp); |
9e14a7b2 BK |
2886 | } |
2887 | ||
0e045f43 BK |
2888 | static void gen_fret(DisasContext *ctx) |
2889 | { | |
2890 | TCGv temp = tcg_temp_new(); | |
2891 | ||
2892 | tcg_gen_andi_tl(temp, cpu_gpr_a[11], ~0x1); | |
2893 | tcg_gen_qemu_ld_tl(cpu_gpr_a[11], cpu_gpr_a[10], ctx->mem_idx, MO_LESL); | |
2894 | tcg_gen_addi_tl(cpu_gpr_a[10], cpu_gpr_a[10], 4); | |
2895 | tcg_gen_mov_tl(cpu_PC, temp); | |
1706e04f | 2896 | ctx->base.is_jmp = DISAS_EXIT; |
0e045f43 BK |
2897 | } |
2898 | ||
9a31922b BK |
2899 | static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, |
2900 | int r2 , int32_t constant , int32_t offset) | |
2901 | { | |
a68e0d54 | 2902 | TCGv temp, temp2; |
83c1bb18 | 2903 | int n; |
70b02262 | 2904 | |
9a31922b BK |
2905 | switch (opc) { |
2906 | /* SB-format jumps */ | |
2907 | case OPC1_16_SB_J: | |
2908 | case OPC1_32_B_J: | |
6b9f5a42 | 2909 | gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); |
9a31922b | 2910 | break; |
f718b0bb | 2911 | case OPC1_32_B_CALL: |
9a31922b | 2912 | case OPC1_16_SB_CALL: |
6b9f5a42 BK |
2913 | gen_helper_1arg(call, ctx->pc_succ_insn); |
2914 | gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); | |
9a31922b BK |
2915 | break; |
2916 | case OPC1_16_SB_JZ: | |
2917 | gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], 0, offset); | |
2918 | break; | |
2919 | case OPC1_16_SB_JNZ: | |
2920 | gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 0, offset); | |
2921 | break; | |
70b02262 BK |
2922 | /* SBC-format jumps */ |
2923 | case OPC1_16_SBC_JEQ: | |
2924 | gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, offset); | |
2925 | break; | |
dedd8c9c PA |
2926 | case OPC1_16_SBC_JEQ2: |
2927 | gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, | |
2928 | offset + 16); | |
2929 | break; | |
70b02262 BK |
2930 | case OPC1_16_SBC_JNE: |
2931 | gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset); | |
2932 | break; | |
dedd8c9c PA |
2933 | case OPC1_16_SBC_JNE2: |
2934 | gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], | |
2935 | constant, offset + 16); | |
2936 | break; | |
70b02262 BK |
2937 | /* SBRN-format jumps */ |
2938 | case OPC1_16_SBRN_JZ_T: | |
2939 | temp = tcg_temp_new(); | |
2940 | tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant); | |
2941 | gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset); | |
70b02262 BK |
2942 | break; |
2943 | case OPC1_16_SBRN_JNZ_T: | |
2944 | temp = tcg_temp_new(); | |
2945 | tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant); | |
2946 | gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset); | |
70b02262 | 2947 | break; |
a47b50db BK |
2948 | /* SBR-format jumps */ |
2949 | case OPC1_16_SBR_JEQ: | |
2950 | gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], | |
2951 | offset); | |
2952 | break; | |
defda2d4 DB |
2953 | case OPC1_16_SBR_JEQ2: |
2954 | gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], | |
2955 | offset + 16); | |
2956 | break; | |
a47b50db BK |
2957 | case OPC1_16_SBR_JNE: |
2958 | gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], | |
2959 | offset); | |
2960 | break; | |
defda2d4 DB |
2961 | case OPC1_16_SBR_JNE2: |
2962 | gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], | |
2963 | offset + 16); | |
2964 | break; | |
a47b50db BK |
2965 | case OPC1_16_SBR_JNZ: |
2966 | gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], 0, offset); | |
2967 | break; | |
2968 | case OPC1_16_SBR_JNZ_A: | |
2969 | gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset); | |
2970 | break; | |
2971 | case OPC1_16_SBR_JGEZ: | |
2972 | gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], 0, offset); | |
2973 | break; | |
2974 | case OPC1_16_SBR_JGTZ: | |
2975 | gen_branch_condi(ctx, TCG_COND_GT, cpu_gpr_d[r1], 0, offset); | |
2976 | break; | |
2977 | case OPC1_16_SBR_JLEZ: | |
2978 | gen_branch_condi(ctx, TCG_COND_LE, cpu_gpr_d[r1], 0, offset); | |
2979 | break; | |
2980 | case OPC1_16_SBR_JLTZ: | |
2981 | gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], 0, offset); | |
2982 | break; | |
2983 | case OPC1_16_SBR_JZ: | |
2984 | gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], 0, offset); | |
2985 | break; | |
2986 | case OPC1_16_SBR_JZ_A: | |
2987 | gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset); | |
2988 | break; | |
2989 | case OPC1_16_SBR_LOOP: | |
2990 | gen_loop(ctx, r1, offset * 2 - 32); | |
2991 | break; | |
44ea3430 BK |
2992 | /* SR-format jumps */ |
2993 | case OPC1_16_SR_JI: | |
2994 | tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], 0xfffffffe); | |
1706e04f | 2995 | ctx->base.is_jmp = DISAS_EXIT; |
44ea3430 | 2996 | break; |
b724b012 | 2997 | case OPC2_32_SYS_RET: |
44ea3430 | 2998 | case OPC2_16_SR_RET: |
ad75a51e | 2999 | gen_helper_ret(tcg_env); |
1706e04f | 3000 | ctx->base.is_jmp = DISAS_EXIT; |
44ea3430 | 3001 | break; |
f718b0bb BK |
3002 | /* B-format */ |
3003 | case OPC1_32_B_CALLA: | |
6b9f5a42 | 3004 | gen_helper_1arg(call, ctx->pc_succ_insn); |
f718b0bb BK |
3005 | gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); |
3006 | break; | |
9e14a7b2 BK |
3007 | case OPC1_32_B_FCALL: |
3008 | gen_fcall_save_ctx(ctx); | |
6b9f5a42 | 3009 | gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); |
9e14a7b2 BK |
3010 | break; |
3011 | case OPC1_32_B_FCALLA: | |
3012 | gen_fcall_save_ctx(ctx); | |
3013 | gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); | |
3014 | break; | |
f718b0bb | 3015 | case OPC1_32_B_JLA: |
6b9f5a42 | 3016 | tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); |
40a1f64b | 3017 | /* fall through */ |
f718b0bb BK |
3018 | case OPC1_32_B_JA: |
3019 | gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); | |
3020 | break; | |
3021 | case OPC1_32_B_JL: | |
6b9f5a42 BK |
3022 | tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); |
3023 | gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); | |
f718b0bb | 3024 | break; |
fc2ef4a3 BK |
3025 | /* BOL format */ |
3026 | case OPCM_32_BRC_EQ_NEQ: | |
3027 | if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JEQ) { | |
3028 | gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], constant, offset); | |
3029 | } else { | |
3030 | gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], constant, offset); | |
3031 | } | |
3032 | break; | |
3033 | case OPCM_32_BRC_GE: | |
3034 | if (MASK_OP_BRC_OP2(ctx->opcode) == OP2_32_BRC_JGE) { | |
3035 | gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], constant, offset); | |
3036 | } else { | |
3037 | constant = MASK_OP_BRC_CONST4(ctx->opcode); | |
3038 | gen_branch_condi(ctx, TCG_COND_GEU, cpu_gpr_d[r1], constant, | |
3039 | offset); | |
3040 | } | |
3041 | break; | |
3042 | case OPCM_32_BRC_JLT: | |
3043 | if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JLT) { | |
3044 | gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], constant, offset); | |
3045 | } else { | |
3046 | constant = MASK_OP_BRC_CONST4(ctx->opcode); | |
3047 | gen_branch_condi(ctx, TCG_COND_LTU, cpu_gpr_d[r1], constant, | |
3048 | offset); | |
3049 | } | |
3050 | break; | |
3051 | case OPCM_32_BRC_JNE: | |
3052 | temp = tcg_temp_new(); | |
3053 | if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JNED) { | |
3054 | tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); | |
3055 | /* subi is unconditional */ | |
3056 | tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); | |
3057 | gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset); | |
3058 | } else { | |
3059 | tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); | |
3060 | /* addi is unconditional */ | |
3061 | tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); | |
3062 | gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset); | |
3063 | } | |
fc2ef4a3 | 3064 | break; |
83c1bb18 BK |
3065 | /* BRN format */ |
3066 | case OPCM_32_BRN_JTT: | |
3067 | n = MASK_OP_BRN_N(ctx->opcode); | |
3068 | ||
3069 | temp = tcg_temp_new(); | |
3070 | tcg_gen_andi_tl(temp, cpu_gpr_d[r1], (1 << n)); | |
3071 | ||
3072 | if (MASK_OP_BRN_OP2(ctx->opcode) == OPC2_32_BRN_JNZ_T) { | |
3073 | gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset); | |
3074 | } else { | |
3075 | gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset); | |
3076 | } | |
83c1bb18 | 3077 | break; |
a68e0d54 BK |
3078 | /* BRR Format */ |
3079 | case OPCM_32_BRR_EQ_NEQ: | |
3080 | if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ) { | |
3081 | gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], | |
3082 | offset); | |
3083 | } else { | |
3084 | gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], | |
3085 | offset); | |
3086 | } | |
3087 | break; | |
3088 | case OPCM_32_BRR_ADDR_EQ_NEQ: | |
3089 | if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ_A) { | |
3090 | gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_a[r1], cpu_gpr_a[r2], | |
3091 | offset); | |
3092 | } else { | |
3093 | gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_a[r1], cpu_gpr_a[r2], | |
3094 | offset); | |
3095 | } | |
3096 | break; | |
3097 | case OPCM_32_BRR_GE: | |
3098 | if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JGE) { | |
3099 | gen_branch_cond(ctx, TCG_COND_GE, cpu_gpr_d[r1], cpu_gpr_d[r2], | |
3100 | offset); | |
3101 | } else { | |
3102 | gen_branch_cond(ctx, TCG_COND_GEU, cpu_gpr_d[r1], cpu_gpr_d[r2], | |
3103 | offset); | |
3104 | } | |
3105 | break; | |
3106 | case OPCM_32_BRR_JLT: | |
3107 | if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JLT) { | |
3108 | gen_branch_cond(ctx, TCG_COND_LT, cpu_gpr_d[r1], cpu_gpr_d[r2], | |
3109 | offset); | |
3110 | } else { | |
3111 | gen_branch_cond(ctx, TCG_COND_LTU, cpu_gpr_d[r1], cpu_gpr_d[r2], | |
3112 | offset); | |
3113 | } | |
3114 | break; | |
3115 | case OPCM_32_BRR_LOOP: | |
3116 | if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_LOOP) { | |
250ef8c7 | 3117 | gen_loop(ctx, r2, offset * 2); |
a68e0d54 BK |
3118 | } else { |
3119 | /* OPC2_32_BRR_LOOPU */ | |
6b9f5a42 | 3120 | gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); |
a68e0d54 BK |
3121 | } |
3122 | break; | |
3123 | case OPCM_32_BRR_JNE: | |
3124 | temp = tcg_temp_new(); | |
3125 | temp2 = tcg_temp_new(); | |
3126 | if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRR_JNED) { | |
3127 | tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); | |
3128 | /* also save r2, in case of r1 == r2, so r2 is not decremented */ | |
3129 | tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]); | |
3130 | /* subi is unconditional */ | |
3131 | tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); | |
3132 | gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset); | |
3133 | } else { | |
3134 | tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); | |
3135 | /* also save r2, in case of r1 == r2, so r2 is not decremented */ | |
3136 | tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]); | |
3137 | /* addi is unconditional */ | |
3138 | tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); | |
3139 | gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset); | |
3140 | } | |
a68e0d54 BK |
3141 | break; |
3142 | case OPCM_32_BRR_JNZ: | |
3143 | if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JNZ_A) { | |
3144 | gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset); | |
3145 | } else { | |
3146 | gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset); | |
3147 | } | |
3148 | break; | |
9a31922b | 3149 | default: |
f678f671 | 3150 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); |
9a31922b | 3151 | } |
9a31922b BK |
3152 | } |
3153 | ||
3154 | ||
0707ec1b BK |
3155 | /* |
3156 | * Functions for decoding instructions | |
3157 | */ | |
3158 | ||
2db92a0c | 3159 | static void decode_src_opc(DisasContext *ctx, int op1) |
0707ec1b BK |
3160 | { |
3161 | int r1; | |
3162 | int32_t const4; | |
3163 | TCGv temp, temp2; | |
3164 | ||
3165 | r1 = MASK_OP_SRC_S1D(ctx->opcode); | |
3166 | const4 = MASK_OP_SRC_CONST4_SEXT(ctx->opcode); | |
3167 | ||
3168 | switch (op1) { | |
3169 | case OPC1_16_SRC_ADD: | |
3170 | gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[r1], const4); | |
3171 | break; | |
3172 | case OPC1_16_SRC_ADD_A15: | |
3173 | gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[15], const4); | |
3174 | break; | |
3175 | case OPC1_16_SRC_ADD_15A: | |
3176 | gen_addi_d(cpu_gpr_d[15], cpu_gpr_d[r1], const4); | |
3177 | break; | |
3178 | case OPC1_16_SRC_ADD_A: | |
3179 | tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], const4); | |
3180 | break; | |
3181 | case OPC1_16_SRC_CADD: | |
3182 | gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const4, cpu_gpr_d[r1], | |
3183 | cpu_gpr_d[15]); | |
3184 | break; | |
3185 | case OPC1_16_SRC_CADDN: | |
3186 | gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const4, cpu_gpr_d[r1], | |
3187 | cpu_gpr_d[15]); | |
3188 | break; | |
3189 | case OPC1_16_SRC_CMOV: | |
151293c2 RH |
3190 | temp = tcg_constant_tl(0); |
3191 | temp2 = tcg_constant_tl(const4); | |
0707ec1b BK |
3192 | tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp, |
3193 | temp2, cpu_gpr_d[r1]); | |
0707ec1b BK |
3194 | break; |
3195 | case OPC1_16_SRC_CMOVN: | |
151293c2 RH |
3196 | temp = tcg_constant_tl(0); |
3197 | temp2 = tcg_constant_tl(const4); | |
0707ec1b BK |
3198 | tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp, |
3199 | temp2, cpu_gpr_d[r1]); | |
0707ec1b BK |
3200 | break; |
3201 | case OPC1_16_SRC_EQ: | |
3202 | tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1], | |
3203 | const4); | |
3204 | break; | |
3205 | case OPC1_16_SRC_LT: | |
3206 | tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1], | |
3207 | const4); | |
3208 | break; | |
3209 | case OPC1_16_SRC_MOV: | |
3210 | tcg_gen_movi_tl(cpu_gpr_d[r1], const4); | |
3211 | break; | |
3212 | case OPC1_16_SRC_MOV_A: | |
3213 | const4 = MASK_OP_SRC_CONST4(ctx->opcode); | |
3214 | tcg_gen_movi_tl(cpu_gpr_a[r1], const4); | |
3215 | break; | |
fcecf126 | 3216 | case OPC1_16_SRC_MOV_E: |
44ee3baf | 3217 | if (has_feature(ctx, TRICORE_FEATURE_16)) { |
6991777e | 3218 | CHECK_REG_PAIR(r1); |
fcecf126 BK |
3219 | tcg_gen_movi_tl(cpu_gpr_d[r1], const4); |
3220 | tcg_gen_sari_tl(cpu_gpr_d[r1+1], cpu_gpr_d[r1], 31); | |
f678f671 BK |
3221 | } else { |
3222 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
3223 | } | |
fcecf126 | 3224 | break; |
0707ec1b BK |
3225 | case OPC1_16_SRC_SH: |
3226 | gen_shi(cpu_gpr_d[r1], cpu_gpr_d[r1], const4); | |
3227 | break; | |
3228 | case OPC1_16_SRC_SHA: | |
3229 | gen_shaci(cpu_gpr_d[r1], cpu_gpr_d[r1], const4); | |
3230 | break; | |
f678f671 BK |
3231 | default: |
3232 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
0707ec1b BK |
3233 | } |
3234 | } | |
3235 | ||
2692802a BK |
3236 | static void decode_srr_opc(DisasContext *ctx, int op1) |
3237 | { | |
3238 | int r1, r2; | |
3239 | TCGv temp; | |
3240 | ||
3241 | r1 = MASK_OP_SRR_S1D(ctx->opcode); | |
3242 | r2 = MASK_OP_SRR_S2(ctx->opcode); | |
3243 | ||
3244 | switch (op1) { | |
3245 | case OPC1_16_SRR_ADD: | |
3246 | gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
3247 | break; | |
3248 | case OPC1_16_SRR_ADD_A15: | |
3249 | gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]); | |
3250 | break; | |
3251 | case OPC1_16_SRR_ADD_15A: | |
3252 | gen_add_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
3253 | break; | |
3254 | case OPC1_16_SRR_ADD_A: | |
3255 | tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], cpu_gpr_a[r2]); | |
3256 | break; | |
3257 | case OPC1_16_SRR_ADDS: | |
3258 | gen_adds(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
3259 | break; | |
3260 | case OPC1_16_SRR_AND: | |
3261 | tcg_gen_and_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
3262 | break; | |
3263 | case OPC1_16_SRR_CMOV: | |
151293c2 | 3264 | temp = tcg_constant_tl(0); |
2692802a BK |
3265 | tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp, |
3266 | cpu_gpr_d[r2], cpu_gpr_d[r1]); | |
2692802a BK |
3267 | break; |
3268 | case OPC1_16_SRR_CMOVN: | |
151293c2 | 3269 | temp = tcg_constant_tl(0); |
2692802a BK |
3270 | tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp, |
3271 | cpu_gpr_d[r2], cpu_gpr_d[r1]); | |
2692802a BK |
3272 | break; |
3273 | case OPC1_16_SRR_EQ: | |
3274 | tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1], | |
3275 | cpu_gpr_d[r2]); | |
3276 | break; | |
3277 | case OPC1_16_SRR_LT: | |
3278 | tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1], | |
3279 | cpu_gpr_d[r2]); | |
3280 | break; | |
3281 | case OPC1_16_SRR_MOV: | |
3282 | tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
3283 | break; | |
3284 | case OPC1_16_SRR_MOV_A: | |
3285 | tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_d[r2]); | |
3286 | break; | |
3287 | case OPC1_16_SRR_MOV_AA: | |
3288 | tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_a[r2]); | |
3289 | break; | |
3290 | case OPC1_16_SRR_MOV_D: | |
3291 | tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_a[r2]); | |
3292 | break; | |
3293 | case OPC1_16_SRR_MUL: | |
3294 | gen_mul_i32s(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
3295 | break; | |
3296 | case OPC1_16_SRR_OR: | |
3297 | tcg_gen_or_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
3298 | break; | |
3299 | case OPC1_16_SRR_SUB: | |
3300 | gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
3301 | break; | |
3302 | case OPC1_16_SRR_SUB_A15B: | |
3303 | gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]); | |
3304 | break; | |
3305 | case OPC1_16_SRR_SUB_15AB: | |
3306 | gen_sub_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
3307 | break; | |
3308 | case OPC1_16_SRR_SUBS: | |
3309 | gen_subs(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
3310 | break; | |
3311 | case OPC1_16_SRR_XOR: | |
3312 | tcg_gen_xor_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
3313 | break; | |
f678f671 BK |
3314 | default: |
3315 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
2692802a BK |
3316 | } |
3317 | } | |
3318 | ||
46aa848f BK |
3319 | static void decode_ssr_opc(DisasContext *ctx, int op1) |
3320 | { | |
3321 | int r1, r2; | |
3322 | ||
3323 | r1 = MASK_OP_SSR_S1(ctx->opcode); | |
3324 | r2 = MASK_OP_SSR_S2(ctx->opcode); | |
3325 | ||
3326 | switch (op1) { | |
3327 | case OPC1_16_SSR_ST_A: | |
3328 | tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); | |
3329 | break; | |
3330 | case OPC1_16_SSR_ST_A_POSTINC: | |
3331 | tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); | |
3332 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); | |
3333 | break; | |
3334 | case OPC1_16_SSR_ST_B: | |
3335 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); | |
3336 | break; | |
3337 | case OPC1_16_SSR_ST_B_POSTINC: | |
3338 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); | |
3339 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1); | |
3340 | break; | |
3341 | case OPC1_16_SSR_ST_H: | |
3342 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW); | |
3343 | break; | |
3344 | case OPC1_16_SSR_ST_H_POSTINC: | |
3345 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW); | |
3346 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2); | |
3347 | break; | |
3348 | case OPC1_16_SSR_ST_W: | |
3349 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); | |
3350 | break; | |
3351 | case OPC1_16_SSR_ST_W_POSTINC: | |
3352 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); | |
3353 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); | |
3354 | break; | |
f678f671 BK |
3355 | default: |
3356 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
46aa848f BK |
3357 | } |
3358 | } | |
3359 | ||
5de93515 BK |
3360 | static void decode_sc_opc(DisasContext *ctx, int op1) |
3361 | { | |
3362 | int32_t const16; | |
3363 | ||
3364 | const16 = MASK_OP_SC_CONST8(ctx->opcode); | |
3365 | ||
3366 | switch (op1) { | |
3367 | case OPC1_16_SC_AND: | |
3368 | tcg_gen_andi_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16); | |
3369 | break; | |
3370 | case OPC1_16_SC_BISR: | |
57b9c589 BK |
3371 | if (ctx->priv == TRICORE_PRIV_SM) { |
3372 | gen_helper_1arg(bisr, const16 & 0xff); | |
3373 | } else { | |
3374 | generate_trap(ctx, TRAPC_PROT, TIN1_PRIV); | |
3375 | } | |
5de93515 BK |
3376 | break; |
3377 | case OPC1_16_SC_LD_A: | |
3378 | gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL); | |
3379 | break; | |
3380 | case OPC1_16_SC_LD_W: | |
3381 | gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL); | |
3382 | break; | |
3383 | case OPC1_16_SC_MOV: | |
3384 | tcg_gen_movi_tl(cpu_gpr_d[15], const16); | |
3385 | break; | |
3386 | case OPC1_16_SC_OR: | |
3387 | tcg_gen_ori_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16); | |
3388 | break; | |
3389 | case OPC1_16_SC_ST_A: | |
3390 | gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL); | |
3391 | break; | |
3392 | case OPC1_16_SC_ST_W: | |
3393 | gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL); | |
3394 | break; | |
3395 | case OPC1_16_SC_SUB_A: | |
3396 | tcg_gen_subi_tl(cpu_gpr_a[10], cpu_gpr_a[10], const16); | |
3397 | break; | |
f678f671 BK |
3398 | default: |
3399 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
5de93515 BK |
3400 | } |
3401 | } | |
5a7634a2 BK |
3402 | |
3403 | static void decode_slr_opc(DisasContext *ctx, int op1) | |
3404 | { | |
3405 | int r1, r2; | |
3406 | ||
3407 | r1 = MASK_OP_SLR_D(ctx->opcode); | |
3408 | r2 = MASK_OP_SLR_S2(ctx->opcode); | |
3409 | ||
3410 | switch (op1) { | |
3411 | /* SLR-format */ | |
3412 | case OPC1_16_SLR_LD_A: | |
3413 | tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); | |
3414 | break; | |
3415 | case OPC1_16_SLR_LD_A_POSTINC: | |
3416 | tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); | |
3417 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); | |
3418 | break; | |
3419 | case OPC1_16_SLR_LD_BU: | |
3420 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); | |
3421 | break; | |
3422 | case OPC1_16_SLR_LD_BU_POSTINC: | |
3423 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); | |
3424 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1); | |
3425 | break; | |
3426 | case OPC1_16_SLR_LD_H: | |
3427 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW); | |
3428 | break; | |
3429 | case OPC1_16_SLR_LD_H_POSTINC: | |
3430 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW); | |
3431 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2); | |
3432 | break; | |
3433 | case OPC1_16_SLR_LD_W: | |
7bd0eaec | 3434 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); |
5a7634a2 BK |
3435 | break; |
3436 | case OPC1_16_SLR_LD_W_POSTINC: | |
7bd0eaec | 3437 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); |
5a7634a2 BK |
3438 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); |
3439 | break; | |
f678f671 BK |
3440 | default: |
3441 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
5a7634a2 BK |
3442 | } |
3443 | } | |
3444 | ||
3445 | static void decode_sro_opc(DisasContext *ctx, int op1) | |
3446 | { | |
3447 | int r2; | |
3448 | int32_t address; | |
3449 | ||
3450 | r2 = MASK_OP_SRO_S2(ctx->opcode); | |
3451 | address = MASK_OP_SRO_OFF4(ctx->opcode); | |
3452 | ||
3453 | /* SRO-format */ | |
3454 | switch (op1) { | |
3455 | case OPC1_16_SRO_LD_A: | |
3456 | gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL); | |
3457 | break; | |
3458 | case OPC1_16_SRO_LD_BU: | |
3459 | gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB); | |
3460 | break; | |
3461 | case OPC1_16_SRO_LD_H: | |
77eb0085 | 3462 | gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW); |
5a7634a2 BK |
3463 | break; |
3464 | case OPC1_16_SRO_LD_W: | |
3465 | gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL); | |
3466 | break; | |
3467 | case OPC1_16_SRO_ST_A: | |
3468 | gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL); | |
3469 | break; | |
3470 | case OPC1_16_SRO_ST_B: | |
3471 | gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB); | |
3472 | break; | |
3473 | case OPC1_16_SRO_ST_H: | |
3474 | gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW); | |
3475 | break; | |
3476 | case OPC1_16_SRO_ST_W: | |
3477 | gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL); | |
3478 | break; | |
f678f671 BK |
3479 | default: |
3480 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
5a7634a2 BK |
3481 | } |
3482 | } | |
3483 | ||
2db92a0c | 3484 | static void decode_sr_system(DisasContext *ctx) |
44ea3430 BK |
3485 | { |
3486 | uint32_t op2; | |
3487 | op2 = MASK_OP_SR_OP2(ctx->opcode); | |
3488 | ||
3489 | switch (op2) { | |
3490 | case OPC2_16_SR_NOP: | |
3491 | break; | |
3492 | case OPC2_16_SR_RET: | |
3493 | gen_compute_branch(ctx, op2, 0, 0, 0, 0); | |
3494 | break; | |
3495 | case OPC2_16_SR_RFE: | |
ad75a51e | 3496 | gen_helper_rfe(tcg_env); |
1706e04f | 3497 | ctx->base.is_jmp = DISAS_EXIT; |
44ea3430 BK |
3498 | break; |
3499 | case OPC2_16_SR_DEBUG: | |
3500 | /* raise EXCP_DEBUG */ | |
3501 | break; | |
0e045f43 BK |
3502 | case OPC2_16_SR_FRET: |
3503 | gen_fret(ctx); | |
f678f671 BK |
3504 | break; |
3505 | default: | |
3506 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
44ea3430 BK |
3507 | } |
3508 | } | |
3509 | ||
2db92a0c | 3510 | static void decode_sr_accu(DisasContext *ctx) |
44ea3430 BK |
3511 | { |
3512 | uint32_t op2; | |
3513 | uint32_t r1; | |
44ea3430 BK |
3514 | |
3515 | r1 = MASK_OP_SR_S1D(ctx->opcode); | |
3516 | op2 = MASK_OP_SR_OP2(ctx->opcode); | |
3517 | ||
3518 | switch (op2) { | |
3519 | case OPC2_16_SR_RSUB: | |
0a476786 RH |
3520 | /* calc V bit -- overflow only if r1 = -0x80000000 */ |
3521 | tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r1], -0x80000000); | |
44ea3430 BK |
3522 | tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); |
3523 | /* calc SV bit */ | |
3524 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
3525 | /* sub */ | |
3526 | tcg_gen_neg_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]); | |
3527 | /* calc av */ | |
3528 | tcg_gen_add_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_gpr_d[r1]); | |
3529 | tcg_gen_xor_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_PSW_AV); | |
3530 | /* calc sav */ | |
3531 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
44ea3430 BK |
3532 | break; |
3533 | case OPC2_16_SR_SAT_B: | |
3534 | gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7f, -0x80); | |
3535 | break; | |
3536 | case OPC2_16_SR_SAT_BU: | |
3537 | gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xff); | |
3538 | break; | |
3539 | case OPC2_16_SR_SAT_H: | |
3540 | gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7fff, -0x8000); | |
3541 | break; | |
3542 | case OPC2_16_SR_SAT_HU: | |
3543 | gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xffff); | |
3544 | break; | |
f678f671 BK |
3545 | default: |
3546 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
44ea3430 BK |
3547 | } |
3548 | } | |
3549 | ||
2db92a0c | 3550 | static void decode_16Bit_opc(DisasContext *ctx) |
0aaeb118 | 3551 | { |
0707ec1b | 3552 | int op1; |
d2798210 BK |
3553 | int r1, r2; |
3554 | int32_t const16; | |
9a31922b | 3555 | int32_t address; |
d2798210 | 3556 | TCGv temp; |
0707ec1b BK |
3557 | |
3558 | op1 = MASK_OP_MAJOR(ctx->opcode); | |
3559 | ||
d2798210 BK |
3560 | /* handle ADDSC.A opcode only being 6 bit long */ |
3561 | if (unlikely((op1 & 0x3f) == OPC1_16_SRRS_ADDSC_A)) { | |
3562 | op1 = OPC1_16_SRRS_ADDSC_A; | |
3563 | } | |
3564 | ||
0707ec1b BK |
3565 | switch (op1) { |
3566 | case OPC1_16_SRC_ADD: | |
3567 | case OPC1_16_SRC_ADD_A15: | |
3568 | case OPC1_16_SRC_ADD_15A: | |
3569 | case OPC1_16_SRC_ADD_A: | |
3570 | case OPC1_16_SRC_CADD: | |
3571 | case OPC1_16_SRC_CADDN: | |
3572 | case OPC1_16_SRC_CMOV: | |
3573 | case OPC1_16_SRC_CMOVN: | |
3574 | case OPC1_16_SRC_EQ: | |
3575 | case OPC1_16_SRC_LT: | |
3576 | case OPC1_16_SRC_MOV: | |
3577 | case OPC1_16_SRC_MOV_A: | |
fcecf126 | 3578 | case OPC1_16_SRC_MOV_E: |
0707ec1b BK |
3579 | case OPC1_16_SRC_SH: |
3580 | case OPC1_16_SRC_SHA: | |
2db92a0c | 3581 | decode_src_opc(ctx, op1); |
0707ec1b | 3582 | break; |
2692802a BK |
3583 | /* SRR-format */ |
3584 | case OPC1_16_SRR_ADD: | |
3585 | case OPC1_16_SRR_ADD_A15: | |
3586 | case OPC1_16_SRR_ADD_15A: | |
3587 | case OPC1_16_SRR_ADD_A: | |
3588 | case OPC1_16_SRR_ADDS: | |
3589 | case OPC1_16_SRR_AND: | |
3590 | case OPC1_16_SRR_CMOV: | |
3591 | case OPC1_16_SRR_CMOVN: | |
3592 | case OPC1_16_SRR_EQ: | |
3593 | case OPC1_16_SRR_LT: | |
3594 | case OPC1_16_SRR_MOV: | |
3595 | case OPC1_16_SRR_MOV_A: | |
3596 | case OPC1_16_SRR_MOV_AA: | |
3597 | case OPC1_16_SRR_MOV_D: | |
3598 | case OPC1_16_SRR_MUL: | |
3599 | case OPC1_16_SRR_OR: | |
3600 | case OPC1_16_SRR_SUB: | |
3601 | case OPC1_16_SRR_SUB_A15B: | |
3602 | case OPC1_16_SRR_SUB_15AB: | |
3603 | case OPC1_16_SRR_SUBS: | |
3604 | case OPC1_16_SRR_XOR: | |
3605 | decode_srr_opc(ctx, op1); | |
3606 | break; | |
46aa848f BK |
3607 | /* SSR-format */ |
3608 | case OPC1_16_SSR_ST_A: | |
3609 | case OPC1_16_SSR_ST_A_POSTINC: | |
3610 | case OPC1_16_SSR_ST_B: | |
3611 | case OPC1_16_SSR_ST_B_POSTINC: | |
3612 | case OPC1_16_SSR_ST_H: | |
3613 | case OPC1_16_SSR_ST_H_POSTINC: | |
3614 | case OPC1_16_SSR_ST_W: | |
3615 | case OPC1_16_SSR_ST_W_POSTINC: | |
3616 | decode_ssr_opc(ctx, op1); | |
3617 | break; | |
d2798210 BK |
3618 | /* SRRS-format */ |
3619 | case OPC1_16_SRRS_ADDSC_A: | |
3620 | r2 = MASK_OP_SRRS_S2(ctx->opcode); | |
3621 | r1 = MASK_OP_SRRS_S1D(ctx->opcode); | |
3622 | const16 = MASK_OP_SRRS_N(ctx->opcode); | |
3623 | temp = tcg_temp_new(); | |
3624 | tcg_gen_shli_tl(temp, cpu_gpr_d[15], const16); | |
3625 | tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], temp); | |
d2798210 BK |
3626 | break; |
3627 | /* SLRO-format */ | |
3628 | case OPC1_16_SLRO_LD_A: | |
3629 | r1 = MASK_OP_SLRO_D(ctx->opcode); | |
3630 | const16 = MASK_OP_SLRO_OFF4(ctx->opcode); | |
3631 | gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); | |
3632 | break; | |
3633 | case OPC1_16_SLRO_LD_BU: | |
3634 | r1 = MASK_OP_SLRO_D(ctx->opcode); | |
3635 | const16 = MASK_OP_SLRO_OFF4(ctx->opcode); | |
3636 | gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB); | |
3637 | break; | |
3638 | case OPC1_16_SLRO_LD_H: | |
3639 | r1 = MASK_OP_SLRO_D(ctx->opcode); | |
3640 | const16 = MASK_OP_SLRO_OFF4(ctx->opcode); | |
3641 | gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW); | |
3642 | break; | |
3643 | case OPC1_16_SLRO_LD_W: | |
3644 | r1 = MASK_OP_SLRO_D(ctx->opcode); | |
3645 | const16 = MASK_OP_SLRO_OFF4(ctx->opcode); | |
3646 | gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); | |
3647 | break; | |
9a31922b BK |
3648 | /* SB-format */ |
3649 | case OPC1_16_SB_CALL: | |
3650 | case OPC1_16_SB_J: | |
3651 | case OPC1_16_SB_JNZ: | |
3652 | case OPC1_16_SB_JZ: | |
3653 | address = MASK_OP_SB_DISP8_SEXT(ctx->opcode); | |
3654 | gen_compute_branch(ctx, op1, 0, 0, 0, address); | |
3655 | break; | |
70b02262 BK |
3656 | /* SBC-format */ |
3657 | case OPC1_16_SBC_JEQ: | |
3658 | case OPC1_16_SBC_JNE: | |
3659 | address = MASK_OP_SBC_DISP4(ctx->opcode); | |
3660 | const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode); | |
3661 | gen_compute_branch(ctx, op1, 0, 0, const16, address); | |
3662 | break; | |
dedd8c9c PA |
3663 | case OPC1_16_SBC_JEQ2: |
3664 | case OPC1_16_SBC_JNE2: | |
44ee3baf | 3665 | if (has_feature(ctx, TRICORE_FEATURE_16)) { |
dedd8c9c PA |
3666 | address = MASK_OP_SBC_DISP4(ctx->opcode); |
3667 | const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode); | |
3668 | gen_compute_branch(ctx, op1, 0, 0, const16, address); | |
3669 | } else { | |
3670 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
3671 | } | |
3672 | break; | |
70b02262 BK |
3673 | /* SBRN-format */ |
3674 | case OPC1_16_SBRN_JNZ_T: | |
3675 | case OPC1_16_SBRN_JZ_T: | |
3676 | address = MASK_OP_SBRN_DISP4(ctx->opcode); | |
3677 | const16 = MASK_OP_SBRN_N(ctx->opcode); | |
3678 | gen_compute_branch(ctx, op1, 0, 0, const16, address); | |
3679 | break; | |
a47b50db | 3680 | /* SBR-format */ |
defda2d4 DB |
3681 | case OPC1_16_SBR_JEQ2: |
3682 | case OPC1_16_SBR_JNE2: | |
44ee3baf | 3683 | if (has_feature(ctx, TRICORE_FEATURE_16)) { |
defda2d4 DB |
3684 | r1 = MASK_OP_SBR_S2(ctx->opcode); |
3685 | address = MASK_OP_SBR_DISP4(ctx->opcode); | |
3686 | gen_compute_branch(ctx, op1, r1, 0, 0, address); | |
3687 | } else { | |
3688 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
3689 | } | |
3690 | break; | |
a47b50db BK |
3691 | case OPC1_16_SBR_JEQ: |
3692 | case OPC1_16_SBR_JGEZ: | |
3693 | case OPC1_16_SBR_JGTZ: | |
3694 | case OPC1_16_SBR_JLEZ: | |
3695 | case OPC1_16_SBR_JLTZ: | |
3696 | case OPC1_16_SBR_JNE: | |
3697 | case OPC1_16_SBR_JNZ: | |
3698 | case OPC1_16_SBR_JNZ_A: | |
3699 | case OPC1_16_SBR_JZ: | |
3700 | case OPC1_16_SBR_JZ_A: | |
3701 | case OPC1_16_SBR_LOOP: | |
3702 | r1 = MASK_OP_SBR_S2(ctx->opcode); | |
3703 | address = MASK_OP_SBR_DISP4(ctx->opcode); | |
3704 | gen_compute_branch(ctx, op1, r1, 0, 0, address); | |
3705 | break; | |
5de93515 BK |
3706 | /* SC-format */ |
3707 | case OPC1_16_SC_AND: | |
3708 | case OPC1_16_SC_BISR: | |
3709 | case OPC1_16_SC_LD_A: | |
3710 | case OPC1_16_SC_LD_W: | |
3711 | case OPC1_16_SC_MOV: | |
3712 | case OPC1_16_SC_OR: | |
3713 | case OPC1_16_SC_ST_A: | |
3714 | case OPC1_16_SC_ST_W: | |
3715 | case OPC1_16_SC_SUB_A: | |
3716 | decode_sc_opc(ctx, op1); | |
3717 | break; | |
5a7634a2 BK |
3718 | /* SLR-format */ |
3719 | case OPC1_16_SLR_LD_A: | |
3720 | case OPC1_16_SLR_LD_A_POSTINC: | |
3721 | case OPC1_16_SLR_LD_BU: | |
3722 | case OPC1_16_SLR_LD_BU_POSTINC: | |
3723 | case OPC1_16_SLR_LD_H: | |
3724 | case OPC1_16_SLR_LD_H_POSTINC: | |
3725 | case OPC1_16_SLR_LD_W: | |
3726 | case OPC1_16_SLR_LD_W_POSTINC: | |
3727 | decode_slr_opc(ctx, op1); | |
3728 | break; | |
3729 | /* SRO-format */ | |
3730 | case OPC1_16_SRO_LD_A: | |
3731 | case OPC1_16_SRO_LD_BU: | |
3732 | case OPC1_16_SRO_LD_H: | |
3733 | case OPC1_16_SRO_LD_W: | |
3734 | case OPC1_16_SRO_ST_A: | |
3735 | case OPC1_16_SRO_ST_B: | |
3736 | case OPC1_16_SRO_ST_H: | |
3737 | case OPC1_16_SRO_ST_W: | |
3738 | decode_sro_opc(ctx, op1); | |
3739 | break; | |
3740 | /* SSRO-format */ | |
3741 | case OPC1_16_SSRO_ST_A: | |
3742 | r1 = MASK_OP_SSRO_S1(ctx->opcode); | |
3743 | const16 = MASK_OP_SSRO_OFF4(ctx->opcode); | |
3744 | gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); | |
3745 | break; | |
3746 | case OPC1_16_SSRO_ST_B: | |
3747 | r1 = MASK_OP_SSRO_S1(ctx->opcode); | |
3748 | const16 = MASK_OP_SSRO_OFF4(ctx->opcode); | |
3749 | gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB); | |
3750 | break; | |
3751 | case OPC1_16_SSRO_ST_H: | |
3752 | r1 = MASK_OP_SSRO_S1(ctx->opcode); | |
3753 | const16 = MASK_OP_SSRO_OFF4(ctx->opcode); | |
3754 | gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW); | |
3755 | break; | |
3756 | case OPC1_16_SSRO_ST_W: | |
3757 | r1 = MASK_OP_SSRO_S1(ctx->opcode); | |
3758 | const16 = MASK_OP_SSRO_OFF4(ctx->opcode); | |
3759 | gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); | |
3760 | break; | |
44ea3430 BK |
3761 | /* SR-format */ |
3762 | case OPCM_16_SR_SYSTEM: | |
2db92a0c | 3763 | decode_sr_system(ctx); |
44ea3430 BK |
3764 | break; |
3765 | case OPCM_16_SR_ACCU: | |
2db92a0c | 3766 | decode_sr_accu(ctx); |
44ea3430 BK |
3767 | break; |
3768 | case OPC1_16_SR_JI: | |
3769 | r1 = MASK_OP_SR_S1D(ctx->opcode); | |
3770 | gen_compute_branch(ctx, op1, r1, 0, 0, 0); | |
3771 | break; | |
3772 | case OPC1_16_SR_NOT: | |
3773 | r1 = MASK_OP_SR_S1D(ctx->opcode); | |
3774 | tcg_gen_not_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]); | |
3775 | break; | |
f678f671 BK |
3776 | default: |
3777 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
0707ec1b | 3778 | } |
0aaeb118 BK |
3779 | } |
3780 | ||
59543d4e BK |
3781 | /* |
3782 | * 32 bit instructions | |
3783 | */ | |
3784 | ||
3785 | /* ABS-format */ | |
2db92a0c | 3786 | static void decode_abs_ldw(DisasContext *ctx) |
59543d4e BK |
3787 | { |
3788 | int32_t op2; | |
3789 | int32_t r1; | |
3790 | uint32_t address; | |
3791 | TCGv temp; | |
3792 | ||
3793 | r1 = MASK_OP_ABS_S1D(ctx->opcode); | |
3794 | address = MASK_OP_ABS_OFF18(ctx->opcode); | |
3795 | op2 = MASK_OP_ABS_OP2(ctx->opcode); | |
3796 | ||
151293c2 | 3797 | temp = tcg_constant_i32(EA_ABS_FORMAT(address)); |
59543d4e BK |
3798 | |
3799 | switch (op2) { | |
3800 | case OPC2_32_ABS_LD_A: | |
3801 | tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL); | |
3802 | break; | |
3803 | case OPC2_32_ABS_LD_D: | |
828066c7 | 3804 | CHECK_REG_PAIR(r1); |
59543d4e BK |
3805 | gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); |
3806 | break; | |
3807 | case OPC2_32_ABS_LD_DA: | |
828066c7 | 3808 | CHECK_REG_PAIR(r1); |
59543d4e BK |
3809 | gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); |
3810 | break; | |
3811 | case OPC2_32_ABS_LD_W: | |
3812 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL); | |
3813 | break; | |
f678f671 BK |
3814 | default: |
3815 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
59543d4e | 3816 | } |
59543d4e BK |
3817 | } |
3818 | ||
2db92a0c | 3819 | static void decode_abs_ldb(DisasContext *ctx) |
59543d4e BK |
3820 | { |
3821 | int32_t op2; | |
3822 | int32_t r1; | |
3823 | uint32_t address; | |
3824 | TCGv temp; | |
3825 | ||
3826 | r1 = MASK_OP_ABS_S1D(ctx->opcode); | |
3827 | address = MASK_OP_ABS_OFF18(ctx->opcode); | |
3828 | op2 = MASK_OP_ABS_OP2(ctx->opcode); | |
3829 | ||
151293c2 | 3830 | temp = tcg_constant_i32(EA_ABS_FORMAT(address)); |
59543d4e BK |
3831 | |
3832 | switch (op2) { | |
3833 | case OPC2_32_ABS_LD_B: | |
3834 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_SB); | |
3835 | break; | |
3836 | case OPC2_32_ABS_LD_BU: | |
3837 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB); | |
3838 | break; | |
3839 | case OPC2_32_ABS_LD_H: | |
3840 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESW); | |
3841 | break; | |
3842 | case OPC2_32_ABS_LD_HU: | |
3843 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW); | |
3844 | break; | |
f678f671 BK |
3845 | default: |
3846 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
59543d4e | 3847 | } |
59543d4e BK |
3848 | } |
3849 | ||
2db92a0c | 3850 | static void decode_abs_ldst_swap(DisasContext *ctx) |
59543d4e BK |
3851 | { |
3852 | int32_t op2; | |
3853 | int32_t r1; | |
3854 | uint32_t address; | |
3855 | TCGv temp; | |
3856 | ||
3857 | r1 = MASK_OP_ABS_S1D(ctx->opcode); | |
3858 | address = MASK_OP_ABS_OFF18(ctx->opcode); | |
3859 | op2 = MASK_OP_ABS_OP2(ctx->opcode); | |
3860 | ||
151293c2 | 3861 | temp = tcg_constant_i32(EA_ABS_FORMAT(address)); |
59543d4e BK |
3862 | |
3863 | switch (op2) { | |
3864 | case OPC2_32_ABS_LDMST: | |
3865 | gen_ldmst(ctx, r1, temp); | |
3866 | break; | |
3867 | case OPC2_32_ABS_SWAP_W: | |
3868 | gen_swap(ctx, r1, temp); | |
3869 | break; | |
f678f671 BK |
3870 | default: |
3871 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
59543d4e | 3872 | } |
59543d4e BK |
3873 | } |
3874 | ||
2db92a0c | 3875 | static void decode_abs_ldst_context(DisasContext *ctx) |
59543d4e BK |
3876 | { |
3877 | uint32_t op2; | |
3878 | int32_t off18; | |
3879 | ||
3880 | off18 = MASK_OP_ABS_OFF18(ctx->opcode); | |
3881 | op2 = MASK_OP_ABS_OP2(ctx->opcode); | |
3882 | ||
3883 | switch (op2) { | |
3884 | case OPC2_32_ABS_LDLCX: | |
3885 | gen_helper_1arg(ldlcx, EA_ABS_FORMAT(off18)); | |
3886 | break; | |
3887 | case OPC2_32_ABS_LDUCX: | |
3888 | gen_helper_1arg(lducx, EA_ABS_FORMAT(off18)); | |
3889 | break; | |
3890 | case OPC2_32_ABS_STLCX: | |
3891 | gen_helper_1arg(stlcx, EA_ABS_FORMAT(off18)); | |
3892 | break; | |
3893 | case OPC2_32_ABS_STUCX: | |
3894 | gen_helper_1arg(stucx, EA_ABS_FORMAT(off18)); | |
3895 | break; | |
f678f671 BK |
3896 | default: |
3897 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
59543d4e BK |
3898 | } |
3899 | } | |
3900 | ||
2db92a0c | 3901 | static void decode_abs_store(DisasContext *ctx) |
59543d4e BK |
3902 | { |
3903 | int32_t op2; | |
3904 | int32_t r1; | |
3905 | uint32_t address; | |
3906 | TCGv temp; | |
3907 | ||
3908 | r1 = MASK_OP_ABS_S1D(ctx->opcode); | |
3909 | address = MASK_OP_ABS_OFF18(ctx->opcode); | |
3910 | op2 = MASK_OP_ABS_OP2(ctx->opcode); | |
3911 | ||
151293c2 | 3912 | temp = tcg_constant_i32(EA_ABS_FORMAT(address)); |
59543d4e BK |
3913 | |
3914 | switch (op2) { | |
3915 | case OPC2_32_ABS_ST_A: | |
3916 | tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL); | |
3917 | break; | |
3918 | case OPC2_32_ABS_ST_D: | |
828066c7 | 3919 | CHECK_REG_PAIR(r1); |
59543d4e BK |
3920 | gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); |
3921 | break; | |
3922 | case OPC2_32_ABS_ST_DA: | |
828066c7 | 3923 | CHECK_REG_PAIR(r1); |
59543d4e BK |
3924 | gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); |
3925 | break; | |
3926 | case OPC2_32_ABS_ST_W: | |
3927 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL); | |
3928 | break; | |
f678f671 BK |
3929 | default: |
3930 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
59543d4e | 3931 | } |
59543d4e BK |
3932 | } |
3933 | ||
2db92a0c | 3934 | static void decode_abs_storeb_h(DisasContext *ctx) |
59543d4e BK |
3935 | { |
3936 | int32_t op2; | |
3937 | int32_t r1; | |
3938 | uint32_t address; | |
3939 | TCGv temp; | |
3940 | ||
3941 | r1 = MASK_OP_ABS_S1D(ctx->opcode); | |
3942 | address = MASK_OP_ABS_OFF18(ctx->opcode); | |
3943 | op2 = MASK_OP_ABS_OP2(ctx->opcode); | |
3944 | ||
151293c2 | 3945 | temp = tcg_constant_i32(EA_ABS_FORMAT(address)); |
59543d4e BK |
3946 | |
3947 | switch (op2) { | |
3948 | case OPC2_32_ABS_ST_B: | |
3949 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB); | |
3950 | break; | |
3951 | case OPC2_32_ABS_ST_H: | |
3952 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW); | |
3953 | break; | |
f678f671 BK |
3954 | default: |
3955 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
59543d4e | 3956 | } |
59543d4e BK |
3957 | } |
3958 | ||
b74f2b5b BK |
3959 | /* Bit-format */ |
3960 | ||
2db92a0c | 3961 | static void decode_bit_andacc(DisasContext *ctx) |
b74f2b5b BK |
3962 | { |
3963 | uint32_t op2; | |
3964 | int r1, r2, r3; | |
3965 | int pos1, pos2; | |
3966 | ||
3967 | r1 = MASK_OP_BIT_S1(ctx->opcode); | |
3968 | r2 = MASK_OP_BIT_S2(ctx->opcode); | |
3969 | r3 = MASK_OP_BIT_D(ctx->opcode); | |
3970 | pos1 = MASK_OP_BIT_POS1(ctx->opcode); | |
3971 | pos2 = MASK_OP_BIT_POS2(ctx->opcode); | |
3972 | op2 = MASK_OP_BIT_OP2(ctx->opcode); | |
3973 | ||
3974 | ||
3975 | switch (op2) { | |
3976 | case OPC2_32_BIT_AND_AND_T: | |
3977 | gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
3978 | pos1, pos2, &tcg_gen_and_tl, &tcg_gen_and_tl); | |
3979 | break; | |
3980 | case OPC2_32_BIT_AND_ANDN_T: | |
3981 | gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
3982 | pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_and_tl); | |
3983 | break; | |
3984 | case OPC2_32_BIT_AND_NOR_T: | |
3985 | if (TCG_TARGET_HAS_andc_i32) { | |
3986 | gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
3987 | pos1, pos2, &tcg_gen_or_tl, &tcg_gen_andc_tl); | |
3988 | } else { | |
3989 | gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
3990 | pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_and_tl); | |
3991 | } | |
3992 | break; | |
3993 | case OPC2_32_BIT_AND_OR_T: | |
3994 | gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
3995 | pos1, pos2, &tcg_gen_or_tl, &tcg_gen_and_tl); | |
3996 | break; | |
f678f671 BK |
3997 | default: |
3998 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
b74f2b5b BK |
3999 | } |
4000 | } | |
4001 | ||
2db92a0c | 4002 | static void decode_bit_logical_t(DisasContext *ctx) |
b74f2b5b BK |
4003 | { |
4004 | uint32_t op2; | |
4005 | int r1, r2, r3; | |
4006 | int pos1, pos2; | |
4007 | r1 = MASK_OP_BIT_S1(ctx->opcode); | |
4008 | r2 = MASK_OP_BIT_S2(ctx->opcode); | |
4009 | r3 = MASK_OP_BIT_D(ctx->opcode); | |
4010 | pos1 = MASK_OP_BIT_POS1(ctx->opcode); | |
4011 | pos2 = MASK_OP_BIT_POS2(ctx->opcode); | |
4012 | op2 = MASK_OP_BIT_OP2(ctx->opcode); | |
4013 | ||
4014 | switch (op2) { | |
4015 | case OPC2_32_BIT_AND_T: | |
4016 | gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
4017 | pos1, pos2, &tcg_gen_and_tl); | |
4018 | break; | |
4019 | case OPC2_32_BIT_ANDN_T: | |
4020 | gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
4021 | pos1, pos2, &tcg_gen_andc_tl); | |
4022 | break; | |
4023 | case OPC2_32_BIT_NOR_T: | |
4024 | gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
4025 | pos1, pos2, &tcg_gen_nor_tl); | |
4026 | break; | |
4027 | case OPC2_32_BIT_OR_T: | |
4028 | gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
4029 | pos1, pos2, &tcg_gen_or_tl); | |
4030 | break; | |
f678f671 BK |
4031 | default: |
4032 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
b74f2b5b BK |
4033 | } |
4034 | } | |
4035 | ||
2db92a0c | 4036 | static void decode_bit_insert(DisasContext *ctx) |
b74f2b5b BK |
4037 | { |
4038 | uint32_t op2; | |
4039 | int r1, r2, r3; | |
4040 | int pos1, pos2; | |
4041 | TCGv temp; | |
4042 | op2 = MASK_OP_BIT_OP2(ctx->opcode); | |
4043 | r1 = MASK_OP_BIT_S1(ctx->opcode); | |
4044 | r2 = MASK_OP_BIT_S2(ctx->opcode); | |
4045 | r3 = MASK_OP_BIT_D(ctx->opcode); | |
4046 | pos1 = MASK_OP_BIT_POS1(ctx->opcode); | |
4047 | pos2 = MASK_OP_BIT_POS2(ctx->opcode); | |
4048 | ||
4049 | temp = tcg_temp_new(); | |
4050 | ||
4051 | tcg_gen_shri_tl(temp, cpu_gpr_d[r2], pos2); | |
4052 | if (op2 == OPC2_32_BIT_INSN_T) { | |
4053 | tcg_gen_not_tl(temp, temp); | |
4054 | } | |
4055 | tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, pos1, 1); | |
b74f2b5b BK |
4056 | } |
4057 | ||
2db92a0c | 4058 | static void decode_bit_logical_t2(DisasContext *ctx) |
b74f2b5b BK |
4059 | { |
4060 | uint32_t op2; | |
4061 | ||
4062 | int r1, r2, r3; | |
4063 | int pos1, pos2; | |
4064 | ||
4065 | op2 = MASK_OP_BIT_OP2(ctx->opcode); | |
4066 | r1 = MASK_OP_BIT_S1(ctx->opcode); | |
4067 | r2 = MASK_OP_BIT_S2(ctx->opcode); | |
4068 | r3 = MASK_OP_BIT_D(ctx->opcode); | |
4069 | pos1 = MASK_OP_BIT_POS1(ctx->opcode); | |
4070 | pos2 = MASK_OP_BIT_POS2(ctx->opcode); | |
4071 | ||
4072 | switch (op2) { | |
4073 | case OPC2_32_BIT_NAND_T: | |
4074 | gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
4075 | pos1, pos2, &tcg_gen_nand_tl); | |
4076 | break; | |
4077 | case OPC2_32_BIT_ORN_T: | |
4078 | gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
4079 | pos1, pos2, &tcg_gen_orc_tl); | |
4080 | break; | |
4081 | case OPC2_32_BIT_XNOR_T: | |
4082 | gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
4083 | pos1, pos2, &tcg_gen_eqv_tl); | |
4084 | break; | |
4085 | case OPC2_32_BIT_XOR_T: | |
4086 | gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
4087 | pos1, pos2, &tcg_gen_xor_tl); | |
4088 | break; | |
f678f671 BK |
4089 | default: |
4090 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
b74f2b5b BK |
4091 | } |
4092 | } | |
4093 | ||
2db92a0c | 4094 | static void decode_bit_orand(DisasContext *ctx) |
b74f2b5b BK |
4095 | { |
4096 | uint32_t op2; | |
4097 | ||
4098 | int r1, r2, r3; | |
4099 | int pos1, pos2; | |
4100 | ||
4101 | op2 = MASK_OP_BIT_OP2(ctx->opcode); | |
4102 | r1 = MASK_OP_BIT_S1(ctx->opcode); | |
4103 | r2 = MASK_OP_BIT_S2(ctx->opcode); | |
4104 | r3 = MASK_OP_BIT_D(ctx->opcode); | |
4105 | pos1 = MASK_OP_BIT_POS1(ctx->opcode); | |
4106 | pos2 = MASK_OP_BIT_POS2(ctx->opcode); | |
4107 | ||
4108 | switch (op2) { | |
4109 | case OPC2_32_BIT_OR_AND_T: | |
4110 | gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
4111 | pos1, pos2, &tcg_gen_and_tl, &tcg_gen_or_tl); | |
4112 | break; | |
4113 | case OPC2_32_BIT_OR_ANDN_T: | |
4114 | gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
4115 | pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_or_tl); | |
4116 | break; | |
4117 | case OPC2_32_BIT_OR_NOR_T: | |
4118 | if (TCG_TARGET_HAS_orc_i32) { | |
4119 | gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
4120 | pos1, pos2, &tcg_gen_or_tl, &tcg_gen_orc_tl); | |
4121 | } else { | |
4122 | gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
4123 | pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_or_tl); | |
4124 | } | |
4125 | break; | |
4126 | case OPC2_32_BIT_OR_OR_T: | |
4127 | gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
4128 | pos1, pos2, &tcg_gen_or_tl, &tcg_gen_or_tl); | |
4129 | break; | |
f678f671 BK |
4130 | default: |
4131 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
b74f2b5b BK |
4132 | } |
4133 | } | |
4134 | ||
2db92a0c | 4135 | static void decode_bit_sh_logic1(DisasContext *ctx) |
b74f2b5b BK |
4136 | { |
4137 | uint32_t op2; | |
4138 | int r1, r2, r3; | |
4139 | int pos1, pos2; | |
4140 | TCGv temp; | |
4141 | ||
4142 | op2 = MASK_OP_BIT_OP2(ctx->opcode); | |
4143 | r1 = MASK_OP_BIT_S1(ctx->opcode); | |
4144 | r2 = MASK_OP_BIT_S2(ctx->opcode); | |
4145 | r3 = MASK_OP_BIT_D(ctx->opcode); | |
4146 | pos1 = MASK_OP_BIT_POS1(ctx->opcode); | |
4147 | pos2 = MASK_OP_BIT_POS2(ctx->opcode); | |
4148 | ||
4149 | temp = tcg_temp_new(); | |
4150 | ||
4151 | switch (op2) { | |
4152 | case OPC2_32_BIT_SH_AND_T: | |
4153 | gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], | |
4154 | pos1, pos2, &tcg_gen_and_tl); | |
4155 | break; | |
4156 | case OPC2_32_BIT_SH_ANDN_T: | |
4157 | gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], | |
4158 | pos1, pos2, &tcg_gen_andc_tl); | |
4159 | break; | |
4160 | case OPC2_32_BIT_SH_NOR_T: | |
4161 | gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], | |
4162 | pos1, pos2, &tcg_gen_nor_tl); | |
4163 | break; | |
4164 | case OPC2_32_BIT_SH_OR_T: | |
4165 | gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], | |
4166 | pos1, pos2, &tcg_gen_or_tl); | |
4167 | break; | |
f678f671 BK |
4168 | default: |
4169 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
b74f2b5b BK |
4170 | } |
4171 | tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1); | |
4172 | tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp); | |
b74f2b5b BK |
4173 | } |
4174 | ||
2db92a0c | 4175 | static void decode_bit_sh_logic2(DisasContext *ctx) |
b74f2b5b BK |
4176 | { |
4177 | uint32_t op2; | |
4178 | int r1, r2, r3; | |
4179 | int pos1, pos2; | |
4180 | TCGv temp; | |
4181 | ||
4182 | op2 = MASK_OP_BIT_OP2(ctx->opcode); | |
4183 | r1 = MASK_OP_BIT_S1(ctx->opcode); | |
4184 | r2 = MASK_OP_BIT_S2(ctx->opcode); | |
4185 | r3 = MASK_OP_BIT_D(ctx->opcode); | |
4186 | pos1 = MASK_OP_BIT_POS1(ctx->opcode); | |
4187 | pos2 = MASK_OP_BIT_POS2(ctx->opcode); | |
4188 | ||
4189 | temp = tcg_temp_new(); | |
4190 | ||
4191 | switch (op2) { | |
4192 | case OPC2_32_BIT_SH_NAND_T: | |
4193 | gen_bit_1op(temp, cpu_gpr_d[r1] , cpu_gpr_d[r2] , | |
4194 | pos1, pos2, &tcg_gen_nand_tl); | |
4195 | break; | |
4196 | case OPC2_32_BIT_SH_ORN_T: | |
4197 | gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], | |
4198 | pos1, pos2, &tcg_gen_orc_tl); | |
4199 | break; | |
4200 | case OPC2_32_BIT_SH_XNOR_T: | |
4201 | gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], | |
4202 | pos1, pos2, &tcg_gen_eqv_tl); | |
4203 | break; | |
4204 | case OPC2_32_BIT_SH_XOR_T: | |
4205 | gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], | |
4206 | pos1, pos2, &tcg_gen_xor_tl); | |
4207 | break; | |
f678f671 BK |
4208 | default: |
4209 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
b74f2b5b BK |
4210 | } |
4211 | tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1); | |
4212 | tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp); | |
b74f2b5b BK |
4213 | } |
4214 | ||
3a16ecb0 BK |
4215 | /* BO-format */ |
4216 | ||
4217 | ||
2db92a0c | 4218 | static void decode_bo_addrmode_post_pre_base(DisasContext *ctx) |
3a16ecb0 BK |
4219 | { |
4220 | uint32_t op2; | |
4221 | uint32_t off10; | |
4222 | int32_t r1, r2; | |
4223 | TCGv temp; | |
4224 | ||
4225 | r1 = MASK_OP_BO_S1D(ctx->opcode); | |
4226 | r2 = MASK_OP_BO_S2(ctx->opcode); | |
4227 | off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); | |
4228 | op2 = MASK_OP_BO_OP2(ctx->opcode); | |
4229 | ||
4230 | switch (op2) { | |
4231 | case OPC2_32_BO_CACHEA_WI_SHORTOFF: | |
4232 | case OPC2_32_BO_CACHEA_W_SHORTOFF: | |
4233 | case OPC2_32_BO_CACHEA_I_SHORTOFF: | |
4234 | /* instruction to access the cache */ | |
4235 | break; | |
4236 | case OPC2_32_BO_CACHEA_WI_POSTINC: | |
4237 | case OPC2_32_BO_CACHEA_W_POSTINC: | |
4238 | case OPC2_32_BO_CACHEA_I_POSTINC: | |
4239 | /* instruction to access the cache, but we still need to handle | |
4240 | the addressing mode */ | |
f1fdaf55 | 4241 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); |
3a16ecb0 BK |
4242 | break; |
4243 | case OPC2_32_BO_CACHEA_WI_PREINC: | |
4244 | case OPC2_32_BO_CACHEA_W_PREINC: | |
4245 | case OPC2_32_BO_CACHEA_I_PREINC: | |
4246 | /* instruction to access the cache, but we still need to handle | |
4247 | the addressing mode */ | |
f1fdaf55 | 4248 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); |
3a16ecb0 BK |
4249 | break; |
4250 | case OPC2_32_BO_CACHEI_WI_SHORTOFF: | |
4251 | case OPC2_32_BO_CACHEI_W_SHORTOFF: | |
44ee3baf | 4252 | if (!has_feature(ctx, TRICORE_FEATURE_131)) { |
f678f671 BK |
4253 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); |
4254 | } | |
3a16ecb0 BK |
4255 | break; |
4256 | case OPC2_32_BO_CACHEI_W_POSTINC: | |
4257 | case OPC2_32_BO_CACHEI_WI_POSTINC: | |
44ee3baf | 4258 | if (has_feature(ctx, TRICORE_FEATURE_131)) { |
f1fdaf55 | 4259 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); |
f678f671 BK |
4260 | } else { |
4261 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
4262 | } | |
3a16ecb0 BK |
4263 | break; |
4264 | case OPC2_32_BO_CACHEI_W_PREINC: | |
4265 | case OPC2_32_BO_CACHEI_WI_PREINC: | |
44ee3baf | 4266 | if (has_feature(ctx, TRICORE_FEATURE_131)) { |
f1fdaf55 | 4267 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); |
f678f671 BK |
4268 | } else { |
4269 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
4270 | } | |
3a16ecb0 BK |
4271 | break; |
4272 | case OPC2_32_BO_ST_A_SHORTOFF: | |
4273 | gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL); | |
4274 | break; | |
4275 | case OPC2_32_BO_ST_A_POSTINC: | |
4276 | tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, | |
4277 | MO_LESL); | |
4278 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4279 | break; | |
4280 | case OPC2_32_BO_ST_A_PREINC: | |
4281 | gen_st_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL); | |
4282 | break; | |
4283 | case OPC2_32_BO_ST_B_SHORTOFF: | |
4284 | gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); | |
4285 | break; | |
4286 | case OPC2_32_BO_ST_B_POSTINC: | |
4287 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, | |
4288 | MO_UB); | |
4289 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4290 | break; | |
4291 | case OPC2_32_BO_ST_B_PREINC: | |
4292 | gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); | |
4293 | break; | |
4294 | case OPC2_32_BO_ST_D_SHORTOFF: | |
828066c7 | 4295 | CHECK_REG_PAIR(r1); |
3a16ecb0 BK |
4296 | gen_offset_st_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], |
4297 | off10, ctx); | |
4298 | break; | |
4299 | case OPC2_32_BO_ST_D_POSTINC: | |
828066c7 | 4300 | CHECK_REG_PAIR(r1); |
3a16ecb0 BK |
4301 | gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx); |
4302 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4303 | break; | |
4304 | case OPC2_32_BO_ST_D_PREINC: | |
828066c7 | 4305 | CHECK_REG_PAIR(r1); |
3a16ecb0 BK |
4306 | temp = tcg_temp_new(); |
4307 | tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); | |
4308 | gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); | |
4309 | tcg_gen_mov_tl(cpu_gpr_a[r2], temp); | |
3a16ecb0 BK |
4310 | break; |
4311 | case OPC2_32_BO_ST_DA_SHORTOFF: | |
828066c7 | 4312 | CHECK_REG_PAIR(r1); |
3a16ecb0 BK |
4313 | gen_offset_st_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], |
4314 | off10, ctx); | |
4315 | break; | |
4316 | case OPC2_32_BO_ST_DA_POSTINC: | |
828066c7 | 4317 | CHECK_REG_PAIR(r1); |
3a16ecb0 BK |
4318 | gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx); |
4319 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4320 | break; | |
4321 | case OPC2_32_BO_ST_DA_PREINC: | |
828066c7 | 4322 | CHECK_REG_PAIR(r1); |
3a16ecb0 BK |
4323 | temp = tcg_temp_new(); |
4324 | tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); | |
4325 | gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); | |
4326 | tcg_gen_mov_tl(cpu_gpr_a[r2], temp); | |
3a16ecb0 BK |
4327 | break; |
4328 | case OPC2_32_BO_ST_H_SHORTOFF: | |
4329 | gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); | |
4330 | break; | |
4331 | case OPC2_32_BO_ST_H_POSTINC: | |
4332 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, | |
4333 | MO_LEUW); | |
4334 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4335 | break; | |
4336 | case OPC2_32_BO_ST_H_PREINC: | |
4337 | gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); | |
4338 | break; | |
4339 | case OPC2_32_BO_ST_Q_SHORTOFF: | |
4340 | temp = tcg_temp_new(); | |
4341 | tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); | |
4342 | gen_offset_st(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW); | |
3a16ecb0 BK |
4343 | break; |
4344 | case OPC2_32_BO_ST_Q_POSTINC: | |
4345 | temp = tcg_temp_new(); | |
4346 | tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); | |
4347 | tcg_gen_qemu_st_tl(temp, cpu_gpr_a[r2], ctx->mem_idx, | |
4348 | MO_LEUW); | |
4349 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
3a16ecb0 BK |
4350 | break; |
4351 | case OPC2_32_BO_ST_Q_PREINC: | |
4352 | temp = tcg_temp_new(); | |
4353 | tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); | |
4354 | gen_st_preincr(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW); | |
3a16ecb0 BK |
4355 | break; |
4356 | case OPC2_32_BO_ST_W_SHORTOFF: | |
4357 | gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); | |
4358 | break; | |
4359 | case OPC2_32_BO_ST_W_POSTINC: | |
4360 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, | |
4361 | MO_LEUL); | |
4362 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4363 | break; | |
4364 | case OPC2_32_BO_ST_W_PREINC: | |
4365 | gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); | |
4366 | break; | |
f678f671 BK |
4367 | default: |
4368 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
3a16ecb0 BK |
4369 | } |
4370 | } | |
4371 | ||
2db92a0c | 4372 | static void decode_bo_addrmode_bitreverse_circular(DisasContext *ctx) |
3a16ecb0 BK |
4373 | { |
4374 | uint32_t op2; | |
4375 | uint32_t off10; | |
4376 | int32_t r1, r2; | |
5c48ad75 | 4377 | TCGv temp, temp2, t_off10; |
3a16ecb0 BK |
4378 | |
4379 | r1 = MASK_OP_BO_S1D(ctx->opcode); | |
4380 | r2 = MASK_OP_BO_S2(ctx->opcode); | |
4381 | off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); | |
4382 | op2 = MASK_OP_BO_OP2(ctx->opcode); | |
4383 | ||
4384 | temp = tcg_temp_new(); | |
4385 | temp2 = tcg_temp_new(); | |
5c48ad75 | 4386 | t_off10 = tcg_constant_i32(off10); |
828066c7 | 4387 | CHECK_REG_PAIR(r2); |
3a16ecb0 BK |
4388 | tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]); |
4389 | tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); | |
4390 | ||
4391 | switch (op2) { | |
4392 | case OPC2_32_BO_CACHEA_WI_BR: | |
4393 | case OPC2_32_BO_CACHEA_W_BR: | |
4394 | case OPC2_32_BO_CACHEA_I_BR: | |
4395 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
4396 | break; | |
4397 | case OPC2_32_BO_CACHEA_WI_CIRC: | |
4398 | case OPC2_32_BO_CACHEA_W_CIRC: | |
4399 | case OPC2_32_BO_CACHEA_I_CIRC: | |
5c48ad75 | 4400 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); |
3a16ecb0 BK |
4401 | break; |
4402 | case OPC2_32_BO_ST_A_BR: | |
4403 | tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); | |
4404 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
4405 | break; | |
4406 | case OPC2_32_BO_ST_A_CIRC: | |
4407 | tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); | |
5c48ad75 | 4408 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); |
3a16ecb0 BK |
4409 | break; |
4410 | case OPC2_32_BO_ST_B_BR: | |
4411 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); | |
4412 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
4413 | break; | |
4414 | case OPC2_32_BO_ST_B_CIRC: | |
4415 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); | |
5c48ad75 | 4416 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); |
3a16ecb0 BK |
4417 | break; |
4418 | case OPC2_32_BO_ST_D_BR: | |
828066c7 | 4419 | CHECK_REG_PAIR(r1); |
3a16ecb0 BK |
4420 | gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx); |
4421 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
4422 | break; | |
4423 | case OPC2_32_BO_ST_D_CIRC: | |
828066c7 | 4424 | CHECK_REG_PAIR(r1); |
3a16ecb0 BK |
4425 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); |
4426 | tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); | |
4427 | tcg_gen_addi_tl(temp, temp, 4); | |
4428 | tcg_gen_rem_tl(temp, temp, temp2); | |
4429 | tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); | |
4430 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL); | |
5c48ad75 | 4431 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); |
3a16ecb0 BK |
4432 | break; |
4433 | case OPC2_32_BO_ST_DA_BR: | |
828066c7 | 4434 | CHECK_REG_PAIR(r1); |
3a16ecb0 BK |
4435 | gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx); |
4436 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
4437 | break; | |
4438 | case OPC2_32_BO_ST_DA_CIRC: | |
828066c7 | 4439 | CHECK_REG_PAIR(r1); |
3a16ecb0 BK |
4440 | tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); |
4441 | tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); | |
4442 | tcg_gen_addi_tl(temp, temp, 4); | |
4443 | tcg_gen_rem_tl(temp, temp, temp2); | |
4444 | tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); | |
4445 | tcg_gen_qemu_st_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL); | |
5c48ad75 | 4446 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); |
3a16ecb0 BK |
4447 | break; |
4448 | case OPC2_32_BO_ST_H_BR: | |
4449 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); | |
4450 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
4451 | break; | |
4452 | case OPC2_32_BO_ST_H_CIRC: | |
4453 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); | |
5c48ad75 | 4454 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); |
3a16ecb0 BK |
4455 | break; |
4456 | case OPC2_32_BO_ST_Q_BR: | |
4457 | tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); | |
4458 | tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW); | |
4459 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
4460 | break; | |
4461 | case OPC2_32_BO_ST_Q_CIRC: | |
4462 | tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); | |
4463 | tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW); | |
5c48ad75 | 4464 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); |
3a16ecb0 BK |
4465 | break; |
4466 | case OPC2_32_BO_ST_W_BR: | |
4467 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); | |
4468 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
4469 | break; | |
4470 | case OPC2_32_BO_ST_W_CIRC: | |
4471 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); | |
5c48ad75 | 4472 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); |
3a16ecb0 | 4473 | break; |
f678f671 BK |
4474 | default: |
4475 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
3a16ecb0 | 4476 | } |
3a16ecb0 BK |
4477 | } |
4478 | ||
2db92a0c | 4479 | static void decode_bo_addrmode_ld_post_pre_base(DisasContext *ctx) |
3a16ecb0 BK |
4480 | { |
4481 | uint32_t op2; | |
4482 | uint32_t off10; | |
4483 | int32_t r1, r2; | |
4484 | TCGv temp; | |
4485 | ||
4486 | r1 = MASK_OP_BO_S1D(ctx->opcode); | |
4487 | r2 = MASK_OP_BO_S2(ctx->opcode); | |
4488 | off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); | |
4489 | op2 = MASK_OP_BO_OP2(ctx->opcode); | |
4490 | ||
4491 | switch (op2) { | |
4492 | case OPC2_32_BO_LD_A_SHORTOFF: | |
4493 | gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL); | |
4494 | break; | |
4495 | case OPC2_32_BO_LD_A_POSTINC: | |
4496 | tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, | |
4497 | MO_LEUL); | |
4498 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4499 | break; | |
4500 | case OPC2_32_BO_LD_A_PREINC: | |
4501 | gen_ld_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL); | |
4502 | break; | |
4503 | case OPC2_32_BO_LD_B_SHORTOFF: | |
4504 | gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB); | |
4505 | break; | |
4506 | case OPC2_32_BO_LD_B_POSTINC: | |
4507 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, | |
4508 | MO_SB); | |
4509 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4510 | break; | |
4511 | case OPC2_32_BO_LD_B_PREINC: | |
4512 | gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB); | |
4513 | break; | |
4514 | case OPC2_32_BO_LD_BU_SHORTOFF: | |
4515 | gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); | |
4516 | break; | |
4517 | case OPC2_32_BO_LD_BU_POSTINC: | |
4518 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, | |
4519 | MO_UB); | |
4520 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4521 | break; | |
4522 | case OPC2_32_BO_LD_BU_PREINC: | |
d8b33554 | 4523 | gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); |
3a16ecb0 BK |
4524 | break; |
4525 | case OPC2_32_BO_LD_D_SHORTOFF: | |
828066c7 | 4526 | CHECK_REG_PAIR(r1); |
3a16ecb0 BK |
4527 | gen_offset_ld_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], |
4528 | off10, ctx); | |
4529 | break; | |
4530 | case OPC2_32_BO_LD_D_POSTINC: | |
828066c7 | 4531 | CHECK_REG_PAIR(r1); |
3a16ecb0 BK |
4532 | gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx); |
4533 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4534 | break; | |
4535 | case OPC2_32_BO_LD_D_PREINC: | |
828066c7 | 4536 | CHECK_REG_PAIR(r1); |
3a16ecb0 BK |
4537 | temp = tcg_temp_new(); |
4538 | tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); | |
4539 | gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); | |
4540 | tcg_gen_mov_tl(cpu_gpr_a[r2], temp); | |
3a16ecb0 BK |
4541 | break; |
4542 | case OPC2_32_BO_LD_DA_SHORTOFF: | |
828066c7 | 4543 | CHECK_REG_PAIR(r1); |
3a16ecb0 BK |
4544 | gen_offset_ld_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], |
4545 | off10, ctx); | |
4546 | break; | |
4547 | case OPC2_32_BO_LD_DA_POSTINC: | |
828066c7 | 4548 | CHECK_REG_PAIR(r1); |
3a16ecb0 BK |
4549 | gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx); |
4550 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4551 | break; | |
4552 | case OPC2_32_BO_LD_DA_PREINC: | |
828066c7 | 4553 | CHECK_REG_PAIR(r1); |
3a16ecb0 BK |
4554 | temp = tcg_temp_new(); |
4555 | tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); | |
4556 | gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); | |
4557 | tcg_gen_mov_tl(cpu_gpr_a[r2], temp); | |
3a16ecb0 BK |
4558 | break; |
4559 | case OPC2_32_BO_LD_H_SHORTOFF: | |
4560 | gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW); | |
4561 | break; | |
4562 | case OPC2_32_BO_LD_H_POSTINC: | |
4563 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, | |
4564 | MO_LESW); | |
4565 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4566 | break; | |
4567 | case OPC2_32_BO_LD_H_PREINC: | |
4568 | gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW); | |
4569 | break; | |
4570 | case OPC2_32_BO_LD_HU_SHORTOFF: | |
4571 | gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); | |
4572 | break; | |
4573 | case OPC2_32_BO_LD_HU_POSTINC: | |
4574 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, | |
4575 | MO_LEUW); | |
4576 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4577 | break; | |
4578 | case OPC2_32_BO_LD_HU_PREINC: | |
4579 | gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); | |
4580 | break; | |
4581 | case OPC2_32_BO_LD_Q_SHORTOFF: | |
4582 | gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); | |
4583 | tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); | |
4584 | break; | |
4585 | case OPC2_32_BO_LD_Q_POSTINC: | |
4586 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, | |
4587 | MO_LEUW); | |
4588 | tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); | |
4589 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4590 | break; | |
4591 | case OPC2_32_BO_LD_Q_PREINC: | |
4592 | gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); | |
4593 | tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); | |
4594 | break; | |
4595 | case OPC2_32_BO_LD_W_SHORTOFF: | |
4596 | gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); | |
4597 | break; | |
4598 | case OPC2_32_BO_LD_W_POSTINC: | |
4599 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, | |
4600 | MO_LEUL); | |
4601 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4602 | break; | |
4603 | case OPC2_32_BO_LD_W_PREINC: | |
4604 | gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); | |
4605 | break; | |
f678f671 BK |
4606 | default: |
4607 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
3a16ecb0 BK |
4608 | } |
4609 | } | |
4610 | ||
2db92a0c | 4611 | static void decode_bo_addrmode_ld_bitreverse_circular(DisasContext *ctx) |
3a16ecb0 BK |
4612 | { |
4613 | uint32_t op2; | |
4614 | uint32_t off10; | |
4615 | int r1, r2; | |
5c48ad75 | 4616 | TCGv temp, temp2, t_off10; |
3a16ecb0 BK |
4617 | |
4618 | r1 = MASK_OP_BO_S1D(ctx->opcode); | |
4619 | r2 = MASK_OP_BO_S2(ctx->opcode); | |
4620 | off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); | |
4621 | op2 = MASK_OP_BO_OP2(ctx->opcode); | |
4622 | ||
4623 | temp = tcg_temp_new(); | |
4624 | temp2 = tcg_temp_new(); | |
5c48ad75 | 4625 | t_off10 = tcg_constant_i32(off10); |
828066c7 | 4626 | CHECK_REG_PAIR(r2); |
3a16ecb0 BK |
4627 | tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]); |
4628 | tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); | |
4629 | ||
4630 | ||
4631 | switch (op2) { | |
4632 | case OPC2_32_BO_LD_A_BR: | |
4633 | tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); | |
4634 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
4635 | break; | |
4636 | case OPC2_32_BO_LD_A_CIRC: | |
4637 | tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); | |
5c48ad75 | 4638 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); |
3a16ecb0 BK |
4639 | break; |
4640 | case OPC2_32_BO_LD_B_BR: | |
4641 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB); | |
4642 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
4643 | break; | |
4644 | case OPC2_32_BO_LD_B_CIRC: | |
4645 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB); | |
5c48ad75 | 4646 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); |
3a16ecb0 BK |
4647 | break; |
4648 | case OPC2_32_BO_LD_BU_BR: | |
4649 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); | |
4650 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
4651 | break; | |
4652 | case OPC2_32_BO_LD_BU_CIRC: | |
4653 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); | |
5c48ad75 | 4654 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); |
3a16ecb0 BK |
4655 | break; |
4656 | case OPC2_32_BO_LD_D_BR: | |
828066c7 | 4657 | CHECK_REG_PAIR(r1); |
3a16ecb0 BK |
4658 | gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx); |
4659 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
4660 | break; | |
4661 | case OPC2_32_BO_LD_D_CIRC: | |
828066c7 | 4662 | CHECK_REG_PAIR(r1); |
3a16ecb0 BK |
4663 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); |
4664 | tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); | |
4665 | tcg_gen_addi_tl(temp, temp, 4); | |
4666 | tcg_gen_rem_tl(temp, temp, temp2); | |
4667 | tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); | |
4668 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL); | |
5c48ad75 | 4669 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); |
3a16ecb0 BK |
4670 | break; |
4671 | case OPC2_32_BO_LD_DA_BR: | |
828066c7 | 4672 | CHECK_REG_PAIR(r1); |
3a16ecb0 BK |
4673 | gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx); |
4674 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
4675 | break; | |
4676 | case OPC2_32_BO_LD_DA_CIRC: | |
828066c7 | 4677 | CHECK_REG_PAIR(r1); |
3a16ecb0 BK |
4678 | tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); |
4679 | tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); | |
4680 | tcg_gen_addi_tl(temp, temp, 4); | |
4681 | tcg_gen_rem_tl(temp, temp, temp2); | |
4682 | tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); | |
4683 | tcg_gen_qemu_ld_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL); | |
5c48ad75 | 4684 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); |
3a16ecb0 BK |
4685 | break; |
4686 | case OPC2_32_BO_LD_H_BR: | |
4687 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW); | |
4688 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
4689 | break; | |
4690 | case OPC2_32_BO_LD_H_CIRC: | |
4691 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW); | |
5c48ad75 | 4692 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); |
3a16ecb0 BK |
4693 | break; |
4694 | case OPC2_32_BO_LD_HU_BR: | |
4695 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); | |
4696 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
4697 | break; | |
4698 | case OPC2_32_BO_LD_HU_CIRC: | |
4699 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); | |
5c48ad75 | 4700 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); |
3a16ecb0 BK |
4701 | break; |
4702 | case OPC2_32_BO_LD_Q_BR: | |
4703 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); | |
4704 | tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); | |
4705 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
4706 | break; | |
4707 | case OPC2_32_BO_LD_Q_CIRC: | |
4708 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); | |
4709 | tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); | |
5c48ad75 | 4710 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); |
3a16ecb0 BK |
4711 | break; |
4712 | case OPC2_32_BO_LD_W_BR: | |
4713 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); | |
4714 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
4715 | break; | |
4716 | case OPC2_32_BO_LD_W_CIRC: | |
4717 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); | |
5c48ad75 | 4718 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); |
3a16ecb0 | 4719 | break; |
f678f671 BK |
4720 | default: |
4721 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
3a16ecb0 | 4722 | } |
3a16ecb0 BK |
4723 | } |
4724 | ||
2db92a0c | 4725 | static void decode_bo_addrmode_stctx_post_pre_base(DisasContext *ctx) |
3a16ecb0 BK |
4726 | { |
4727 | uint32_t op2; | |
4728 | uint32_t off10; | |
4729 | int r1, r2; | |
4730 | ||
08ee498b | 4731 | TCGv temp; |
3a16ecb0 BK |
4732 | |
4733 | r1 = MASK_OP_BO_S1D(ctx->opcode); | |
4734 | r2 = MASK_OP_BO_S2(ctx->opcode); | |
4735 | off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); | |
4736 | op2 = MASK_OP_BO_OP2(ctx->opcode); | |
4737 | ||
4738 | ||
4739 | temp = tcg_temp_new(); | |
3a16ecb0 BK |
4740 | |
4741 | switch (op2) { | |
4742 | case OPC2_32_BO_LDLCX_SHORTOFF: | |
4743 | tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); | |
ad75a51e | 4744 | gen_helper_ldlcx(tcg_env, temp); |
3a16ecb0 BK |
4745 | break; |
4746 | case OPC2_32_BO_LDMST_SHORTOFF: | |
4747 | tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); | |
4748 | gen_ldmst(ctx, r1, temp); | |
4749 | break; | |
4750 | case OPC2_32_BO_LDMST_POSTINC: | |
4751 | gen_ldmst(ctx, r1, cpu_gpr_a[r2]); | |
4752 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4753 | break; | |
4754 | case OPC2_32_BO_LDMST_PREINC: | |
4755 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4756 | gen_ldmst(ctx, r1, cpu_gpr_a[r2]); | |
4757 | break; | |
4758 | case OPC2_32_BO_LDUCX_SHORTOFF: | |
4759 | tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); | |
ad75a51e | 4760 | gen_helper_lducx(tcg_env, temp); |
3a16ecb0 BK |
4761 | break; |
4762 | case OPC2_32_BO_LEA_SHORTOFF: | |
4763 | tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], off10); | |
4764 | break; | |
4765 | case OPC2_32_BO_STLCX_SHORTOFF: | |
4766 | tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); | |
ad75a51e | 4767 | gen_helper_stlcx(tcg_env, temp); |
3a16ecb0 BK |
4768 | break; |
4769 | case OPC2_32_BO_STUCX_SHORTOFF: | |
4770 | tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); | |
ad75a51e | 4771 | gen_helper_stucx(tcg_env, temp); |
3a16ecb0 BK |
4772 | break; |
4773 | case OPC2_32_BO_SWAP_W_SHORTOFF: | |
4774 | tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); | |
4775 | gen_swap(ctx, r1, temp); | |
4776 | break; | |
4777 | case OPC2_32_BO_SWAP_W_POSTINC: | |
4778 | gen_swap(ctx, r1, cpu_gpr_a[r2]); | |
4779 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4780 | break; | |
4781 | case OPC2_32_BO_SWAP_W_PREINC: | |
4782 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4783 | gen_swap(ctx, r1, cpu_gpr_a[r2]); | |
4784 | break; | |
62872ebc BK |
4785 | case OPC2_32_BO_CMPSWAP_W_SHORTOFF: |
4786 | tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); | |
4787 | gen_cmpswap(ctx, r1, temp); | |
4788 | break; | |
4789 | case OPC2_32_BO_CMPSWAP_W_POSTINC: | |
4790 | gen_cmpswap(ctx, r1, cpu_gpr_a[r2]); | |
4791 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4792 | break; | |
4793 | case OPC2_32_BO_CMPSWAP_W_PREINC: | |
4794 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4795 | gen_cmpswap(ctx, r1, cpu_gpr_a[r2]); | |
4796 | break; | |
ddd8cebe BK |
4797 | case OPC2_32_BO_SWAPMSK_W_SHORTOFF: |
4798 | tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); | |
4799 | gen_swapmsk(ctx, r1, temp); | |
4800 | break; | |
4801 | case OPC2_32_BO_SWAPMSK_W_POSTINC: | |
4802 | gen_swapmsk(ctx, r1, cpu_gpr_a[r2]); | |
4803 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4804 | break; | |
4805 | case OPC2_32_BO_SWAPMSK_W_PREINC: | |
4806 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4807 | gen_swapmsk(ctx, r1, cpu_gpr_a[r2]); | |
4808 | break; | |
f678f671 BK |
4809 | default: |
4810 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
3a16ecb0 | 4811 | } |
3a16ecb0 BK |
4812 | } |
4813 | ||
2db92a0c | 4814 | static void decode_bo_addrmode_ldmst_bitreverse_circular(DisasContext *ctx) |
3a16ecb0 BK |
4815 | { |
4816 | uint32_t op2; | |
4817 | uint32_t off10; | |
4818 | int r1, r2; | |
5c48ad75 | 4819 | TCGv temp, temp2, t_off10; |
3a16ecb0 BK |
4820 | |
4821 | r1 = MASK_OP_BO_S1D(ctx->opcode); | |
4822 | r2 = MASK_OP_BO_S2(ctx->opcode); | |
4823 | off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); | |
4824 | op2 = MASK_OP_BO_OP2(ctx->opcode); | |
4825 | ||
4826 | temp = tcg_temp_new(); | |
4827 | temp2 = tcg_temp_new(); | |
5c48ad75 | 4828 | t_off10 = tcg_constant_i32(off10); |
828066c7 | 4829 | CHECK_REG_PAIR(r2); |
3a16ecb0 BK |
4830 | tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]); |
4831 | tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); | |
4832 | ||
4833 | switch (op2) { | |
4834 | case OPC2_32_BO_LDMST_BR: | |
4835 | gen_ldmst(ctx, r1, temp2); | |
4836 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
4837 | break; | |
4838 | case OPC2_32_BO_LDMST_CIRC: | |
4839 | gen_ldmst(ctx, r1, temp2); | |
5c48ad75 | 4840 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); |
3a16ecb0 BK |
4841 | break; |
4842 | case OPC2_32_BO_SWAP_W_BR: | |
4843 | gen_swap(ctx, r1, temp2); | |
4844 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
4845 | break; | |
4846 | case OPC2_32_BO_SWAP_W_CIRC: | |
4847 | gen_swap(ctx, r1, temp2); | |
5c48ad75 | 4848 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); |
3a16ecb0 | 4849 | break; |
62872ebc BK |
4850 | case OPC2_32_BO_CMPSWAP_W_BR: |
4851 | gen_cmpswap(ctx, r1, temp2); | |
4852 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
4853 | break; | |
4854 | case OPC2_32_BO_CMPSWAP_W_CIRC: | |
4855 | gen_cmpswap(ctx, r1, temp2); | |
5c48ad75 | 4856 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); |
62872ebc | 4857 | break; |
ddd8cebe BK |
4858 | case OPC2_32_BO_SWAPMSK_W_BR: |
4859 | gen_swapmsk(ctx, r1, temp2); | |
4860 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
4861 | break; | |
4862 | case OPC2_32_BO_SWAPMSK_W_CIRC: | |
4863 | gen_swapmsk(ctx, r1, temp2); | |
5c48ad75 | 4864 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); |
ddd8cebe | 4865 | break; |
f678f671 BK |
4866 | default: |
4867 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
3a16ecb0 | 4868 | } |
3a16ecb0 BK |
4869 | } |
4870 | ||
2db92a0c | 4871 | static void decode_bol_opc(DisasContext *ctx, int32_t op1) |
3fb763cb BK |
4872 | { |
4873 | int r1, r2; | |
4874 | int32_t address; | |
4875 | TCGv temp; | |
4876 | ||
4877 | r1 = MASK_OP_BOL_S1D(ctx->opcode); | |
4878 | r2 = MASK_OP_BOL_S2(ctx->opcode); | |
4879 | address = MASK_OP_BOL_OFF16_SEXT(ctx->opcode); | |
4880 | ||
4881 | switch (op1) { | |
4882 | case OPC1_32_BOL_LD_A_LONGOFF: | |
4883 | temp = tcg_temp_new(); | |
4884 | tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address); | |
4885 | tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LEUL); | |
3fb763cb | 4886 | break; |
af715d98 | 4887 | case OPC1_32_BOL_LD_W_LONGOFF: |
3fb763cb BK |
4888 | temp = tcg_temp_new(); |
4889 | tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address); | |
4890 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUL); | |
3fb763cb BK |
4891 | break; |
4892 | case OPC1_32_BOL_LEA_LONGOFF: | |
4893 | tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], address); | |
4894 | break; | |
4895 | case OPC1_32_BOL_ST_A_LONGOFF: | |
44ee3baf | 4896 | if (has_feature(ctx, TRICORE_FEATURE_16)) { |
3fb763cb BK |
4897 | gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], address, MO_LEUL); |
4898 | } else { | |
f678f671 | 4899 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); |
3fb763cb BK |
4900 | } |
4901 | break; | |
4902 | case OPC1_32_BOL_ST_W_LONGOFF: | |
4903 | gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUL); | |
4904 | break; | |
b5fd8fa3 | 4905 | case OPC1_32_BOL_LD_B_LONGOFF: |
44ee3baf | 4906 | if (has_feature(ctx, TRICORE_FEATURE_16)) { |
b5fd8fa3 BK |
4907 | gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB); |
4908 | } else { | |
f678f671 | 4909 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); |
b5fd8fa3 BK |
4910 | } |
4911 | break; | |
4912 | case OPC1_32_BOL_LD_BU_LONGOFF: | |
44ee3baf | 4913 | if (has_feature(ctx, TRICORE_FEATURE_16)) { |
b5fd8fa3 BK |
4914 | gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_UB); |
4915 | } else { | |
f678f671 | 4916 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); |
b5fd8fa3 BK |
4917 | } |
4918 | break; | |
4919 | case OPC1_32_BOL_LD_H_LONGOFF: | |
44ee3baf | 4920 | if (has_feature(ctx, TRICORE_FEATURE_16)) { |
b5fd8fa3 BK |
4921 | gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW); |
4922 | } else { | |
f678f671 | 4923 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); |
b5fd8fa3 BK |
4924 | } |
4925 | break; | |
4926 | case OPC1_32_BOL_LD_HU_LONGOFF: | |
44ee3baf | 4927 | if (has_feature(ctx, TRICORE_FEATURE_16)) { |
b5fd8fa3 BK |
4928 | gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUW); |
4929 | } else { | |
f678f671 | 4930 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); |
b5fd8fa3 BK |
4931 | } |
4932 | break; | |
4933 | case OPC1_32_BOL_ST_B_LONGOFF: | |
44ee3baf | 4934 | if (has_feature(ctx, TRICORE_FEATURE_16)) { |
b5fd8fa3 BK |
4935 | gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB); |
4936 | } else { | |
f678f671 | 4937 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); |
b5fd8fa3 BK |
4938 | } |
4939 | break; | |
4940 | case OPC1_32_BOL_ST_H_LONGOFF: | |
44ee3baf | 4941 | if (has_feature(ctx, TRICORE_FEATURE_16)) { |
07e15486 | 4942 | gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW); |
b5fd8fa3 | 4943 | } else { |
f678f671 | 4944 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); |
b5fd8fa3 BK |
4945 | } |
4946 | break; | |
f678f671 BK |
4947 | default: |
4948 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
3fb763cb | 4949 | } |
3fb763cb BK |
4950 | } |
4951 | ||
0974257e | 4952 | /* RC format */ |
2db92a0c | 4953 | static void decode_rc_logical_shift(DisasContext *ctx) |
0974257e BK |
4954 | { |
4955 | uint32_t op2; | |
4956 | int r1, r2; | |
4957 | int32_t const9; | |
4958 | TCGv temp; | |
4959 | ||
4960 | r2 = MASK_OP_RC_D(ctx->opcode); | |
4961 | r1 = MASK_OP_RC_S1(ctx->opcode); | |
4962 | const9 = MASK_OP_RC_CONST9(ctx->opcode); | |
4963 | op2 = MASK_OP_RC_OP2(ctx->opcode); | |
4964 | ||
0974257e BK |
4965 | switch (op2) { |
4966 | case OPC2_32_RC_AND: | |
4967 | tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
4968 | break; | |
4969 | case OPC2_32_RC_ANDN: | |
4970 | tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9); | |
4971 | break; | |
4972 | case OPC2_32_RC_NAND: | |
81b8056a | 4973 | temp = tcg_temp_new(); |
0974257e BK |
4974 | tcg_gen_movi_tl(temp, const9); |
4975 | tcg_gen_nand_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp); | |
4976 | break; | |
4977 | case OPC2_32_RC_NOR: | |
81b8056a | 4978 | temp = tcg_temp_new(); |
0974257e BK |
4979 | tcg_gen_movi_tl(temp, const9); |
4980 | tcg_gen_nor_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp); | |
4981 | break; | |
4982 | case OPC2_32_RC_OR: | |
4983 | tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
4984 | break; | |
4985 | case OPC2_32_RC_ORN: | |
4986 | tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9); | |
4987 | break; | |
4988 | case OPC2_32_RC_SH: | |
4989 | const9 = sextract32(const9, 0, 6); | |
4990 | gen_shi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
4991 | break; | |
4992 | case OPC2_32_RC_SH_H: | |
4993 | const9 = sextract32(const9, 0, 5); | |
4994 | gen_sh_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
4995 | break; | |
4996 | case OPC2_32_RC_SHA: | |
4997 | const9 = sextract32(const9, 0, 6); | |
4998 | gen_shaci(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
4999 | break; | |
5000 | case OPC2_32_RC_SHA_H: | |
5001 | const9 = sextract32(const9, 0, 5); | |
5002 | gen_sha_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5003 | break; | |
5004 | case OPC2_32_RC_SHAS: | |
5005 | gen_shasi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5006 | break; | |
5007 | case OPC2_32_RC_XNOR: | |
5008 | tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5009 | tcg_gen_not_tl(cpu_gpr_d[r2], cpu_gpr_d[r2]); | |
5010 | break; | |
5011 | case OPC2_32_RC_XOR: | |
5012 | tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5013 | break; | |
4e3377bb BK |
5014 | case OPC2_32_RC_SHUFFLE: |
5015 | if (has_feature(ctx, TRICORE_FEATURE_162)) { | |
81b8056a | 5016 | temp = tcg_constant_i32(const9); |
4e3377bb BK |
5017 | gen_helper_shuffle(cpu_gpr_d[r2], cpu_gpr_d[r1], temp); |
5018 | } else { | |
5019 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
5020 | } | |
5021 | break; | |
f678f671 BK |
5022 | default: |
5023 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
0974257e | 5024 | } |
0974257e BK |
5025 | } |
5026 | ||
2db92a0c | 5027 | static void decode_rc_accumulator(DisasContext *ctx) |
0974257e BK |
5028 | { |
5029 | uint32_t op2; | |
5030 | int r1, r2; | |
5031 | int16_t const9; | |
5032 | ||
5033 | TCGv temp; | |
5034 | ||
5035 | r2 = MASK_OP_RC_D(ctx->opcode); | |
5036 | r1 = MASK_OP_RC_S1(ctx->opcode); | |
5037 | const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode); | |
5038 | ||
5039 | op2 = MASK_OP_RC_OP2(ctx->opcode); | |
5040 | ||
5041 | temp = tcg_temp_new(); | |
5042 | ||
5043 | switch (op2) { | |
5044 | case OPC2_32_RC_ABSDIF: | |
5045 | gen_absdifi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5046 | break; | |
5047 | case OPC2_32_RC_ABSDIFS: | |
5048 | gen_absdifsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5049 | break; | |
5050 | case OPC2_32_RC_ADD: | |
5051 | gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5052 | break; | |
5053 | case OPC2_32_RC_ADDC: | |
5054 | gen_addci_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5055 | break; | |
5056 | case OPC2_32_RC_ADDS: | |
5057 | gen_addsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5058 | break; | |
5059 | case OPC2_32_RC_ADDS_U: | |
5060 | gen_addsui(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5061 | break; | |
5062 | case OPC2_32_RC_ADDX: | |
5063 | gen_addi_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5064 | break; | |
5065 | case OPC2_32_RC_AND_EQ: | |
5066 | gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
5067 | const9, &tcg_gen_and_tl); | |
5068 | break; | |
5069 | case OPC2_32_RC_AND_GE: | |
5070 | gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
5071 | const9, &tcg_gen_and_tl); | |
5072 | break; | |
5073 | case OPC2_32_RC_AND_GE_U: | |
5074 | const9 = MASK_OP_RC_CONST9(ctx->opcode); | |
5075 | gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
5076 | const9, &tcg_gen_and_tl); | |
5077 | break; | |
5078 | case OPC2_32_RC_AND_LT: | |
5079 | gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
5080 | const9, &tcg_gen_and_tl); | |
5081 | break; | |
5082 | case OPC2_32_RC_AND_LT_U: | |
5083 | const9 = MASK_OP_RC_CONST9(ctx->opcode); | |
5084 | gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
5085 | const9, &tcg_gen_and_tl); | |
5086 | break; | |
5087 | case OPC2_32_RC_AND_NE: | |
5088 | gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
5089 | const9, &tcg_gen_and_tl); | |
5090 | break; | |
5091 | case OPC2_32_RC_EQ: | |
5092 | tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5093 | break; | |
5094 | case OPC2_32_RC_EQANY_B: | |
5095 | gen_eqany_bi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5096 | break; | |
5097 | case OPC2_32_RC_EQANY_H: | |
5098 | gen_eqany_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5099 | break; | |
5100 | case OPC2_32_RC_GE: | |
5101 | tcg_gen_setcondi_tl(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5102 | break; | |
5103 | case OPC2_32_RC_GE_U: | |
5104 | const9 = MASK_OP_RC_CONST9(ctx->opcode); | |
5105 | tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5106 | break; | |
5107 | case OPC2_32_RC_LT: | |
5108 | tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5109 | break; | |
5110 | case OPC2_32_RC_LT_U: | |
5111 | const9 = MASK_OP_RC_CONST9(ctx->opcode); | |
5112 | tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5113 | break; | |
5114 | case OPC2_32_RC_MAX: | |
5115 | tcg_gen_movi_tl(temp, const9); | |
5116 | tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, | |
5117 | cpu_gpr_d[r1], temp); | |
5118 | break; | |
5119 | case OPC2_32_RC_MAX_U: | |
5120 | tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode)); | |
5121 | tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, | |
5122 | cpu_gpr_d[r1], temp); | |
5123 | break; | |
5124 | case OPC2_32_RC_MIN: | |
5125 | tcg_gen_movi_tl(temp, const9); | |
5126 | tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, | |
5127 | cpu_gpr_d[r1], temp); | |
5128 | break; | |
5129 | case OPC2_32_RC_MIN_U: | |
5130 | tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode)); | |
5131 | tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, | |
5132 | cpu_gpr_d[r1], temp); | |
5133 | break; | |
5134 | case OPC2_32_RC_NE: | |
5135 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5136 | break; | |
5137 | case OPC2_32_RC_OR_EQ: | |
5138 | gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
5139 | const9, &tcg_gen_or_tl); | |
5140 | break; | |
5141 | case OPC2_32_RC_OR_GE: | |
5142 | gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
5143 | const9, &tcg_gen_or_tl); | |
5144 | break; | |
5145 | case OPC2_32_RC_OR_GE_U: | |
5146 | const9 = MASK_OP_RC_CONST9(ctx->opcode); | |
5147 | gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
5148 | const9, &tcg_gen_or_tl); | |
5149 | break; | |
5150 | case OPC2_32_RC_OR_LT: | |
5151 | gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
5152 | const9, &tcg_gen_or_tl); | |
5153 | break; | |
5154 | case OPC2_32_RC_OR_LT_U: | |
5155 | const9 = MASK_OP_RC_CONST9(ctx->opcode); | |
5156 | gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
5157 | const9, &tcg_gen_or_tl); | |
5158 | break; | |
5159 | case OPC2_32_RC_OR_NE: | |
5160 | gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
5161 | const9, &tcg_gen_or_tl); | |
5162 | break; | |
5163 | case OPC2_32_RC_RSUB: | |
5164 | tcg_gen_movi_tl(temp, const9); | |
5165 | gen_sub_d(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]); | |
5166 | break; | |
5167 | case OPC2_32_RC_RSUBS: | |
5168 | tcg_gen_movi_tl(temp, const9); | |
5169 | gen_subs(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]); | |
5170 | break; | |
5171 | case OPC2_32_RC_RSUBS_U: | |
5172 | tcg_gen_movi_tl(temp, const9); | |
5173 | gen_subsu(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]); | |
5174 | break; | |
5175 | case OPC2_32_RC_SH_EQ: | |
5176 | gen_sh_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5177 | break; | |
5178 | case OPC2_32_RC_SH_GE: | |
5179 | gen_sh_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5180 | break; | |
5181 | case OPC2_32_RC_SH_GE_U: | |
5182 | const9 = MASK_OP_RC_CONST9(ctx->opcode); | |
5183 | gen_sh_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5184 | break; | |
5185 | case OPC2_32_RC_SH_LT: | |
5186 | gen_sh_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5187 | break; | |
5188 | case OPC2_32_RC_SH_LT_U: | |
5189 | const9 = MASK_OP_RC_CONST9(ctx->opcode); | |
5190 | gen_sh_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5191 | break; | |
5192 | case OPC2_32_RC_SH_NE: | |
5193 | gen_sh_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5194 | break; | |
5195 | case OPC2_32_RC_XOR_EQ: | |
5196 | gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
5197 | const9, &tcg_gen_xor_tl); | |
5198 | break; | |
5199 | case OPC2_32_RC_XOR_GE: | |
5200 | gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
5201 | const9, &tcg_gen_xor_tl); | |
5202 | break; | |
5203 | case OPC2_32_RC_XOR_GE_U: | |
5204 | const9 = MASK_OP_RC_CONST9(ctx->opcode); | |
5205 | gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
5206 | const9, &tcg_gen_xor_tl); | |
5207 | break; | |
5208 | case OPC2_32_RC_XOR_LT: | |
5209 | gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
5210 | const9, &tcg_gen_xor_tl); | |
5211 | break; | |
5212 | case OPC2_32_RC_XOR_LT_U: | |
5213 | const9 = MASK_OP_RC_CONST9(ctx->opcode); | |
5214 | gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
5215 | const9, &tcg_gen_xor_tl); | |
5216 | break; | |
5217 | case OPC2_32_RC_XOR_NE: | |
5218 | gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
5219 | const9, &tcg_gen_xor_tl); | |
5220 | break; | |
f678f671 BK |
5221 | default: |
5222 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
0974257e | 5223 | } |
0974257e BK |
5224 | } |
5225 | ||
2db92a0c | 5226 | static void decode_rc_serviceroutine(DisasContext *ctx) |
0974257e BK |
5227 | { |
5228 | uint32_t op2; | |
5229 | uint32_t const9; | |
5230 | ||
5231 | op2 = MASK_OP_RC_OP2(ctx->opcode); | |
5232 | const9 = MASK_OP_RC_CONST9(ctx->opcode); | |
5233 | ||
5234 | switch (op2) { | |
5235 | case OPC2_32_RC_BISR: | |
57b9c589 BK |
5236 | if (ctx->priv == TRICORE_PRIV_SM) { |
5237 | gen_helper_1arg(bisr, const9); | |
5238 | } else { | |
5239 | generate_trap(ctx, TRAPC_PROT, TIN1_PRIV); | |
5240 | } | |
0974257e BK |
5241 | break; |
5242 | case OPC2_32_RC_SYSCALL: | |
3b5d136d | 5243 | generate_trap(ctx, TRAPC_SYSCALL, const9 & 0xff); |
0974257e | 5244 | break; |
f678f671 BK |
5245 | default: |
5246 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
0974257e BK |
5247 | } |
5248 | } | |
5249 | ||
2db92a0c | 5250 | static void decode_rc_mul(DisasContext *ctx) |
0974257e BK |
5251 | { |
5252 | uint32_t op2; | |
5253 | int r1, r2; | |
5254 | int16_t const9; | |
5255 | ||
5256 | r2 = MASK_OP_RC_D(ctx->opcode); | |
5257 | r1 = MASK_OP_RC_S1(ctx->opcode); | |
5258 | const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode); | |
5259 | ||
5260 | op2 = MASK_OP_RC_OP2(ctx->opcode); | |
5261 | ||
5262 | switch (op2) { | |
5263 | case OPC2_32_RC_MUL_32: | |
5264 | gen_muli_i32s(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5265 | break; | |
5266 | case OPC2_32_RC_MUL_64: | |
828066c7 | 5267 | CHECK_REG_PAIR(r2); |
0974257e BK |
5268 | gen_muli_i64s(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9); |
5269 | break; | |
5270 | case OPC2_32_RC_MULS_32: | |
5271 | gen_mulsi_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5272 | break; | |
5273 | case OPC2_32_RC_MUL_U_64: | |
5274 | const9 = MASK_OP_RC_CONST9(ctx->opcode); | |
828066c7 | 5275 | CHECK_REG_PAIR(r2); |
0974257e BK |
5276 | gen_muli_i64u(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9); |
5277 | break; | |
5278 | case OPC2_32_RC_MULS_U_32: | |
5279 | const9 = MASK_OP_RC_CONST9(ctx->opcode); | |
5280 | gen_mulsui_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5281 | break; | |
f678f671 BK |
5282 | default: |
5283 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
0974257e BK |
5284 | } |
5285 | } | |
5286 | ||
ed516260 | 5287 | /* RCPW format */ |
2db92a0c | 5288 | static void decode_rcpw_insert(DisasContext *ctx) |
ed516260 BK |
5289 | { |
5290 | uint32_t op2; | |
5291 | int r1, r2; | |
5292 | int32_t pos, width, const4; | |
5293 | ||
5294 | TCGv temp; | |
5295 | ||
5296 | op2 = MASK_OP_RCPW_OP2(ctx->opcode); | |
5297 | r1 = MASK_OP_RCPW_S1(ctx->opcode); | |
5298 | r2 = MASK_OP_RCPW_D(ctx->opcode); | |
5299 | const4 = MASK_OP_RCPW_CONST4(ctx->opcode); | |
5300 | width = MASK_OP_RCPW_WIDTH(ctx->opcode); | |
5301 | pos = MASK_OP_RCPW_POS(ctx->opcode); | |
5302 | ||
5303 | switch (op2) { | |
5304 | case OPC2_32_RCPW_IMASK: | |
828066c7 | 5305 | CHECK_REG_PAIR(r2); |
9b620609 AK |
5306 | /* if pos + width > 32 undefined result */ |
5307 | if (pos + width <= 32) { | |
ed516260 BK |
5308 | tcg_gen_movi_tl(cpu_gpr_d[r2+1], ((1u << width) - 1) << pos); |
5309 | tcg_gen_movi_tl(cpu_gpr_d[r2], (const4 << pos)); | |
5310 | } | |
5311 | break; | |
5312 | case OPC2_32_RCPW_INSERT: | |
23fa6f56 BK |
5313 | /* tcg_gen_deposit_tl() does not handle the case of width = 0 */ |
5314 | if (width == 0) { | |
5315 | tcg_gen_mov_tl(cpu_gpr_d[r2], cpu_gpr_d[r1]); | |
ed516260 | 5316 | /* if pos + width > 32 undefined result */ |
23fa6f56 | 5317 | } else if (pos + width <= 32) { |
151293c2 | 5318 | temp = tcg_constant_i32(const4); |
ed516260 | 5319 | tcg_gen_deposit_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, pos, width); |
ed516260 BK |
5320 | } |
5321 | break; | |
f678f671 BK |
5322 | default: |
5323 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
ed516260 BK |
5324 | } |
5325 | } | |
5326 | ||
5327 | /* RCRW format */ | |
5328 | ||
2db92a0c | 5329 | static void decode_rcrw_insert(DisasContext *ctx) |
ed516260 BK |
5330 | { |
5331 | uint32_t op2; | |
5332 | int r1, r3, r4; | |
5333 | int32_t width, const4; | |
5334 | ||
5335 | TCGv temp, temp2, temp3; | |
5336 | ||
5337 | op2 = MASK_OP_RCRW_OP2(ctx->opcode); | |
5338 | r1 = MASK_OP_RCRW_S1(ctx->opcode); | |
5339 | r3 = MASK_OP_RCRW_S3(ctx->opcode); | |
5340 | r4 = MASK_OP_RCRW_D(ctx->opcode); | |
5341 | width = MASK_OP_RCRW_WIDTH(ctx->opcode); | |
5342 | const4 = MASK_OP_RCRW_CONST4(ctx->opcode); | |
5343 | ||
5344 | temp = tcg_temp_new(); | |
5345 | temp2 = tcg_temp_new(); | |
5346 | ||
5347 | switch (op2) { | |
5348 | case OPC2_32_RCRW_IMASK: | |
d34b092c | 5349 | CHECK_REG_PAIR(r4); |
65e57fdb | 5350 | tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f); |
ed516260 | 5351 | tcg_gen_movi_tl(temp2, (1 << width) - 1); |
65e57fdb | 5352 | tcg_gen_shl_tl(cpu_gpr_d[r4 + 1], temp2, temp); |
ed516260 | 5353 | tcg_gen_movi_tl(temp2, const4); |
65e57fdb | 5354 | tcg_gen_shl_tl(cpu_gpr_d[r4], temp2, temp); |
ed516260 BK |
5355 | break; |
5356 | case OPC2_32_RCRW_INSERT: | |
5357 | temp3 = tcg_temp_new(); | |
5358 | ||
5359 | tcg_gen_movi_tl(temp, width); | |
5360 | tcg_gen_movi_tl(temp2, const4); | |
1c6b2e4b BK |
5361 | tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f); |
5362 | gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], temp2, temp, temp3); | |
ed516260 | 5363 | break; |
f678f671 BK |
5364 | default: |
5365 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
ed516260 | 5366 | } |
ed516260 BK |
5367 | } |
5368 | ||
328f1f0f BK |
5369 | /* RCR format */ |
5370 | ||
2db92a0c | 5371 | static void decode_rcr_cond_select(DisasContext *ctx) |
328f1f0f BK |
5372 | { |
5373 | uint32_t op2; | |
5374 | int r1, r3, r4; | |
5375 | int32_t const9; | |
5376 | ||
5377 | TCGv temp, temp2; | |
5378 | ||
5379 | op2 = MASK_OP_RCR_OP2(ctx->opcode); | |
5380 | r1 = MASK_OP_RCR_S1(ctx->opcode); | |
5381 | const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode); | |
5382 | r3 = MASK_OP_RCR_S3(ctx->opcode); | |
5383 | r4 = MASK_OP_RCR_D(ctx->opcode); | |
5384 | ||
5385 | switch (op2) { | |
5386 | case OPC2_32_RCR_CADD: | |
a00585ee DB |
5387 | gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const9, cpu_gpr_d[r4], |
5388 | cpu_gpr_d[r3]); | |
328f1f0f BK |
5389 | break; |
5390 | case OPC2_32_RCR_CADDN: | |
d1c1d88c DB |
5391 | gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const9, cpu_gpr_d[r4], |
5392 | cpu_gpr_d[r3]); | |
328f1f0f BK |
5393 | break; |
5394 | case OPC2_32_RCR_SEL: | |
151293c2 RH |
5395 | temp = tcg_constant_i32(0); |
5396 | temp2 = tcg_constant_i32(const9); | |
5f30046f | 5397 | tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, |
328f1f0f | 5398 | cpu_gpr_d[r1], temp2); |
328f1f0f BK |
5399 | break; |
5400 | case OPC2_32_RCR_SELN: | |
151293c2 RH |
5401 | temp = tcg_constant_i32(0); |
5402 | temp2 = tcg_constant_i32(const9); | |
5f30046f | 5403 | tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, |
328f1f0f | 5404 | cpu_gpr_d[r1], temp2); |
328f1f0f | 5405 | break; |
f678f671 BK |
5406 | default: |
5407 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
328f1f0f BK |
5408 | } |
5409 | } | |
5410 | ||
2db92a0c | 5411 | static void decode_rcr_madd(DisasContext *ctx) |
328f1f0f BK |
5412 | { |
5413 | uint32_t op2; | |
5414 | int r1, r3, r4; | |
5415 | int32_t const9; | |
5416 | ||
5417 | ||
5418 | op2 = MASK_OP_RCR_OP2(ctx->opcode); | |
5419 | r1 = MASK_OP_RCR_S1(ctx->opcode); | |
5420 | const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode); | |
5421 | r3 = MASK_OP_RCR_S3(ctx->opcode); | |
5422 | r4 = MASK_OP_RCR_D(ctx->opcode); | |
5423 | ||
5424 | switch (op2) { | |
5425 | case OPC2_32_RCR_MADD_32: | |
5426 | gen_maddi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); | |
5427 | break; | |
5428 | case OPC2_32_RCR_MADD_64: | |
828066c7 BK |
5429 | CHECK_REG_PAIR(r4); |
5430 | CHECK_REG_PAIR(r3); | |
328f1f0f BK |
5431 | gen_maddi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], |
5432 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); | |
5433 | break; | |
5434 | case OPC2_32_RCR_MADDS_32: | |
5435 | gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); | |
5436 | break; | |
5437 | case OPC2_32_RCR_MADDS_64: | |
828066c7 BK |
5438 | CHECK_REG_PAIR(r4); |
5439 | CHECK_REG_PAIR(r3); | |
328f1f0f BK |
5440 | gen_maddsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], |
5441 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); | |
5442 | break; | |
5443 | case OPC2_32_RCR_MADD_U_64: | |
828066c7 BK |
5444 | CHECK_REG_PAIR(r4); |
5445 | CHECK_REG_PAIR(r3); | |
328f1f0f BK |
5446 | const9 = MASK_OP_RCR_CONST9(ctx->opcode); |
5447 | gen_maddui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], | |
5448 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); | |
5449 | break; | |
5450 | case OPC2_32_RCR_MADDS_U_32: | |
5451 | const9 = MASK_OP_RCR_CONST9(ctx->opcode); | |
5452 | gen_maddsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); | |
5453 | break; | |
5454 | case OPC2_32_RCR_MADDS_U_64: | |
828066c7 BK |
5455 | CHECK_REG_PAIR(r4); |
5456 | CHECK_REG_PAIR(r3); | |
328f1f0f BK |
5457 | const9 = MASK_OP_RCR_CONST9(ctx->opcode); |
5458 | gen_maddsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], | |
5459 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); | |
5460 | break; | |
f678f671 BK |
5461 | default: |
5462 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
328f1f0f BK |
5463 | } |
5464 | } | |
5465 | ||
2db92a0c | 5466 | static void decode_rcr_msub(DisasContext *ctx) |
328f1f0f BK |
5467 | { |
5468 | uint32_t op2; | |
5469 | int r1, r3, r4; | |
5470 | int32_t const9; | |
5471 | ||
5472 | ||
5473 | op2 = MASK_OP_RCR_OP2(ctx->opcode); | |
5474 | r1 = MASK_OP_RCR_S1(ctx->opcode); | |
5475 | const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode); | |
5476 | r3 = MASK_OP_RCR_S3(ctx->opcode); | |
5477 | r4 = MASK_OP_RCR_D(ctx->opcode); | |
5478 | ||
5479 | switch (op2) { | |
5480 | case OPC2_32_RCR_MSUB_32: | |
5481 | gen_msubi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); | |
5482 | break; | |
5483 | case OPC2_32_RCR_MSUB_64: | |
828066c7 BK |
5484 | CHECK_REG_PAIR(r4); |
5485 | CHECK_REG_PAIR(r3); | |
328f1f0f BK |
5486 | gen_msubi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], |
5487 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); | |
5488 | break; | |
5489 | case OPC2_32_RCR_MSUBS_32: | |
5490 | gen_msubsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); | |
5491 | break; | |
5492 | case OPC2_32_RCR_MSUBS_64: | |
828066c7 BK |
5493 | CHECK_REG_PAIR(r4); |
5494 | CHECK_REG_PAIR(r3); | |
328f1f0f BK |
5495 | gen_msubsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], |
5496 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); | |
5497 | break; | |
5498 | case OPC2_32_RCR_MSUB_U_64: | |
828066c7 BK |
5499 | CHECK_REG_PAIR(r4); |
5500 | CHECK_REG_PAIR(r3); | |
328f1f0f BK |
5501 | const9 = MASK_OP_RCR_CONST9(ctx->opcode); |
5502 | gen_msubui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], | |
5503 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); | |
5504 | break; | |
5505 | case OPC2_32_RCR_MSUBS_U_32: | |
5506 | const9 = MASK_OP_RCR_CONST9(ctx->opcode); | |
5507 | gen_msubsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); | |
5508 | break; | |
5509 | case OPC2_32_RCR_MSUBS_U_64: | |
828066c7 BK |
5510 | CHECK_REG_PAIR(r4); |
5511 | CHECK_REG_PAIR(r3); | |
328f1f0f BK |
5512 | const9 = MASK_OP_RCR_CONST9(ctx->opcode); |
5513 | gen_msubsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], | |
5514 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); | |
5515 | break; | |
f678f671 BK |
5516 | default: |
5517 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
328f1f0f BK |
5518 | } |
5519 | } | |
5520 | ||
2b2f7d97 BK |
5521 | /* RLC format */ |
5522 | ||
2db92a0c | 5523 | static void decode_rlc_opc(DisasContext *ctx, |
2b2f7d97 BK |
5524 | uint32_t op1) |
5525 | { | |
5526 | int32_t const16; | |
5527 | int r1, r2; | |
5528 | ||
5529 | const16 = MASK_OP_RLC_CONST16_SEXT(ctx->opcode); | |
5530 | r1 = MASK_OP_RLC_S1(ctx->opcode); | |
5531 | r2 = MASK_OP_RLC_D(ctx->opcode); | |
5532 | ||
5533 | switch (op1) { | |
5534 | case OPC1_32_RLC_ADDI: | |
f0cab01b | 5535 | gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16); |
2b2f7d97 BK |
5536 | break; |
5537 | case OPC1_32_RLC_ADDIH: | |
f0cab01b | 5538 | gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16 << 16); |
2b2f7d97 BK |
5539 | break; |
5540 | case OPC1_32_RLC_ADDIH_A: | |
5541 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r1], const16 << 16); | |
5542 | break; | |
5543 | case OPC1_32_RLC_MFCR: | |
436d63ff | 5544 | const16 = MASK_OP_RLC_CONST16(ctx->opcode); |
2db92a0c | 5545 | gen_mfcr(ctx, cpu_gpr_d[r2], const16); |
2b2f7d97 BK |
5546 | break; |
5547 | case OPC1_32_RLC_MOV: | |
5548 | tcg_gen_movi_tl(cpu_gpr_d[r2], const16); | |
5549 | break; | |
4b5b4435 | 5550 | case OPC1_32_RLC_MOV_64: |
44ee3baf | 5551 | if (has_feature(ctx, TRICORE_FEATURE_16)) { |
828066c7 | 5552 | CHECK_REG_PAIR(r2); |
4b5b4435 AZ |
5553 | tcg_gen_movi_tl(cpu_gpr_d[r2], const16); |
5554 | tcg_gen_movi_tl(cpu_gpr_d[r2+1], const16 >> 15); | |
5555 | } else { | |
f678f671 | 5556 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); |
4b5b4435 AZ |
5557 | } |
5558 | break; | |
2b2f7d97 BK |
5559 | case OPC1_32_RLC_MOV_U: |
5560 | const16 = MASK_OP_RLC_CONST16(ctx->opcode); | |
5561 | tcg_gen_movi_tl(cpu_gpr_d[r2], const16); | |
5562 | break; | |
5563 | case OPC1_32_RLC_MOV_H: | |
5564 | tcg_gen_movi_tl(cpu_gpr_d[r2], const16 << 16); | |
5565 | break; | |
5566 | case OPC1_32_RLC_MOVH_A: | |
5567 | tcg_gen_movi_tl(cpu_gpr_a[r2], const16 << 16); | |
5568 | break; | |
5569 | case OPC1_32_RLC_MTCR: | |
436d63ff | 5570 | const16 = MASK_OP_RLC_CONST16(ctx->opcode); |
2db92a0c | 5571 | gen_mtcr(ctx, cpu_gpr_d[r1], const16); |
2b2f7d97 | 5572 | break; |
f678f671 BK |
5573 | default: |
5574 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
2b2f7d97 BK |
5575 | } |
5576 | } | |
5577 | ||
d5de7839 | 5578 | /* RR format */ |
2db92a0c | 5579 | static void decode_rr_accumulator(DisasContext *ctx) |
d5de7839 BK |
5580 | { |
5581 | uint32_t op2; | |
5582 | int r3, r2, r1; | |
5583 | ||
550929dd PA |
5584 | TCGv temp; |
5585 | ||
d5de7839 BK |
5586 | r3 = MASK_OP_RR_D(ctx->opcode); |
5587 | r2 = MASK_OP_RR_S2(ctx->opcode); | |
5588 | r1 = MASK_OP_RR_S1(ctx->opcode); | |
5589 | op2 = MASK_OP_RR_OP2(ctx->opcode); | |
5590 | ||
5591 | switch (op2) { | |
5592 | case OPC2_32_RR_ABS: | |
5593 | gen_abs(cpu_gpr_d[r3], cpu_gpr_d[r2]); | |
5594 | break; | |
5595 | case OPC2_32_RR_ABS_B: | |
ad75a51e | 5596 | gen_helper_abs_b(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r2]); |
d5de7839 BK |
5597 | break; |
5598 | case OPC2_32_RR_ABS_H: | |
ad75a51e | 5599 | gen_helper_abs_h(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r2]); |
d5de7839 BK |
5600 | break; |
5601 | case OPC2_32_RR_ABSDIF: | |
5602 | gen_absdif(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5603 | break; | |
5604 | case OPC2_32_RR_ABSDIF_B: | |
ad75a51e | 5605 | gen_helper_absdif_b(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], |
d5de7839 BK |
5606 | cpu_gpr_d[r2]); |
5607 | break; | |
5608 | case OPC2_32_RR_ABSDIF_H: | |
ad75a51e | 5609 | gen_helper_absdif_h(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], |
d5de7839 BK |
5610 | cpu_gpr_d[r2]); |
5611 | break; | |
5612 | case OPC2_32_RR_ABSDIFS: | |
ad75a51e | 5613 | gen_helper_absdif_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], |
d5de7839 BK |
5614 | cpu_gpr_d[r2]); |
5615 | break; | |
5616 | case OPC2_32_RR_ABSDIFS_H: | |
ad75a51e | 5617 | gen_helper_absdif_h_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], |
d5de7839 BK |
5618 | cpu_gpr_d[r2]); |
5619 | break; | |
5620 | case OPC2_32_RR_ABSS: | |
ad75a51e | 5621 | gen_helper_abs_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r2]); |
d5de7839 BK |
5622 | break; |
5623 | case OPC2_32_RR_ABSS_H: | |
ad75a51e | 5624 | gen_helper_abs_h_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r2]); |
d5de7839 BK |
5625 | break; |
5626 | case OPC2_32_RR_ADD: | |
5627 | gen_add_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5628 | break; | |
5629 | case OPC2_32_RR_ADD_B: | |
ad75a51e | 5630 | gen_helper_add_b(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); |
d5de7839 BK |
5631 | break; |
5632 | case OPC2_32_RR_ADD_H: | |
ad75a51e | 5633 | gen_helper_add_h(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); |
d5de7839 BK |
5634 | break; |
5635 | case OPC2_32_RR_ADDC: | |
5636 | gen_addc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5637 | break; | |
5638 | case OPC2_32_RR_ADDS: | |
5639 | gen_adds(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5640 | break; | |
5641 | case OPC2_32_RR_ADDS_H: | |
ad75a51e | 5642 | gen_helper_add_h_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], |
d5de7839 BK |
5643 | cpu_gpr_d[r2]); |
5644 | break; | |
5645 | case OPC2_32_RR_ADDS_HU: | |
ad75a51e | 5646 | gen_helper_add_h_suov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], |
d5de7839 BK |
5647 | cpu_gpr_d[r2]); |
5648 | break; | |
5649 | case OPC2_32_RR_ADDS_U: | |
ad75a51e | 5650 | gen_helper_add_suov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], |
d5de7839 BK |
5651 | cpu_gpr_d[r2]); |
5652 | break; | |
5653 | case OPC2_32_RR_ADDX: | |
5654 | gen_add_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5655 | break; | |
5656 | case OPC2_32_RR_AND_EQ: | |
5657 | gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5658 | cpu_gpr_d[r2], &tcg_gen_and_tl); | |
5659 | break; | |
5660 | case OPC2_32_RR_AND_GE: | |
5661 | gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5662 | cpu_gpr_d[r2], &tcg_gen_and_tl); | |
5663 | break; | |
5664 | case OPC2_32_RR_AND_GE_U: | |
5665 | gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5666 | cpu_gpr_d[r2], &tcg_gen_and_tl); | |
5667 | break; | |
5668 | case OPC2_32_RR_AND_LT: | |
5669 | gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5670 | cpu_gpr_d[r2], &tcg_gen_and_tl); | |
5671 | break; | |
5672 | case OPC2_32_RR_AND_LT_U: | |
5673 | gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5674 | cpu_gpr_d[r2], &tcg_gen_and_tl); | |
5675 | break; | |
5676 | case OPC2_32_RR_AND_NE: | |
5677 | gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5678 | cpu_gpr_d[r2], &tcg_gen_and_tl); | |
5679 | break; | |
5680 | case OPC2_32_RR_EQ: | |
5681 | tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5682 | cpu_gpr_d[r2]); | |
5683 | break; | |
5684 | case OPC2_32_RR_EQ_B: | |
5685 | gen_helper_eq_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5686 | break; | |
5687 | case OPC2_32_RR_EQ_H: | |
5688 | gen_helper_eq_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5689 | break; | |
5690 | case OPC2_32_RR_EQ_W: | |
b0a433be RH |
5691 | tcg_gen_negsetcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], |
5692 | cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
d5de7839 BK |
5693 | break; |
5694 | case OPC2_32_RR_EQANY_B: | |
5695 | gen_helper_eqany_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5696 | break; | |
5697 | case OPC2_32_RR_EQANY_H: | |
5698 | gen_helper_eqany_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5699 | break; | |
5700 | case OPC2_32_RR_GE: | |
5701 | tcg_gen_setcond_tl(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5702 | cpu_gpr_d[r2]); | |
5703 | break; | |
5704 | case OPC2_32_RR_GE_U: | |
5705 | tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5706 | cpu_gpr_d[r2]); | |
5707 | break; | |
5708 | case OPC2_32_RR_LT: | |
5709 | tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5710 | cpu_gpr_d[r2]); | |
5711 | break; | |
5712 | case OPC2_32_RR_LT_U: | |
5713 | tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5714 | cpu_gpr_d[r2]); | |
5715 | break; | |
5716 | case OPC2_32_RR_LT_B: | |
5717 | gen_helper_lt_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5718 | break; | |
5719 | case OPC2_32_RR_LT_BU: | |
5720 | gen_helper_lt_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5721 | break; | |
5722 | case OPC2_32_RR_LT_H: | |
5723 | gen_helper_lt_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5724 | break; | |
5725 | case OPC2_32_RR_LT_HU: | |
5726 | gen_helper_lt_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5727 | break; | |
5728 | case OPC2_32_RR_LT_W: | |
b0a433be RH |
5729 | tcg_gen_negsetcond_tl(TCG_COND_LT, cpu_gpr_d[r3], |
5730 | cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
d5de7839 BK |
5731 | break; |
5732 | case OPC2_32_RR_LT_WU: | |
b0a433be RH |
5733 | tcg_gen_negsetcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], |
5734 | cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
d5de7839 BK |
5735 | break; |
5736 | case OPC2_32_RR_MAX: | |
5737 | tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5738 | cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5739 | break; | |
5740 | case OPC2_32_RR_MAX_U: | |
5741 | tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5742 | cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5743 | break; | |
5744 | case OPC2_32_RR_MAX_B: | |
5745 | gen_helper_max_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5746 | break; | |
5747 | case OPC2_32_RR_MAX_BU: | |
5748 | gen_helper_max_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5749 | break; | |
5750 | case OPC2_32_RR_MAX_H: | |
5751 | gen_helper_max_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5752 | break; | |
5753 | case OPC2_32_RR_MAX_HU: | |
5754 | gen_helper_max_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5755 | break; | |
5756 | case OPC2_32_RR_MIN: | |
5757 | tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5758 | cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5759 | break; | |
5760 | case OPC2_32_RR_MIN_U: | |
5761 | tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5762 | cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5763 | break; | |
5764 | case OPC2_32_RR_MIN_B: | |
5765 | gen_helper_min_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5766 | break; | |
5767 | case OPC2_32_RR_MIN_BU: | |
5768 | gen_helper_min_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5769 | break; | |
5770 | case OPC2_32_RR_MIN_H: | |
5771 | gen_helper_min_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5772 | break; | |
5773 | case OPC2_32_RR_MIN_HU: | |
5774 | gen_helper_min_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5775 | break; | |
5776 | case OPC2_32_RR_MOV: | |
5777 | tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); | |
5778 | break; | |
550929dd | 5779 | case OPC2_32_RR_MOV_64: |
44ee3baf | 5780 | if (has_feature(ctx, TRICORE_FEATURE_16)) { |
550929dd PA |
5781 | temp = tcg_temp_new(); |
5782 | ||
5783 | CHECK_REG_PAIR(r3); | |
5784 | tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); | |
5785 | tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); | |
5786 | tcg_gen_mov_tl(cpu_gpr_d[r3 + 1], temp); | |
550929dd PA |
5787 | } else { |
5788 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
5789 | } | |
5790 | break; | |
defda2d4 | 5791 | case OPC2_32_RR_MOVS_64: |
44ee3baf | 5792 | if (has_feature(ctx, TRICORE_FEATURE_16)) { |
defda2d4 DB |
5793 | CHECK_REG_PAIR(r3); |
5794 | tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); | |
5795 | tcg_gen_sari_tl(cpu_gpr_d[r3 + 1], cpu_gpr_d[r2], 31); | |
5796 | } else { | |
5797 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
5798 | } | |
5799 | break; | |
d5de7839 BK |
5800 | case OPC2_32_RR_NE: |
5801 | tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5802 | cpu_gpr_d[r2]); | |
5803 | break; | |
5804 | case OPC2_32_RR_OR_EQ: | |
5805 | gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5806 | cpu_gpr_d[r2], &tcg_gen_or_tl); | |
5807 | break; | |
5808 | case OPC2_32_RR_OR_GE: | |
5809 | gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5810 | cpu_gpr_d[r2], &tcg_gen_or_tl); | |
5811 | break; | |
5812 | case OPC2_32_RR_OR_GE_U: | |
5813 | gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5814 | cpu_gpr_d[r2], &tcg_gen_or_tl); | |
5815 | break; | |
5816 | case OPC2_32_RR_OR_LT: | |
5817 | gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5818 | cpu_gpr_d[r2], &tcg_gen_or_tl); | |
5819 | break; | |
5820 | case OPC2_32_RR_OR_LT_U: | |
5821 | gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5822 | cpu_gpr_d[r2], &tcg_gen_or_tl); | |
5823 | break; | |
5824 | case OPC2_32_RR_OR_NE: | |
5825 | gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5826 | cpu_gpr_d[r2], &tcg_gen_or_tl); | |
5827 | break; | |
5828 | case OPC2_32_RR_SAT_B: | |
5829 | gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7f, -0x80); | |
5830 | break; | |
5831 | case OPC2_32_RR_SAT_BU: | |
5832 | gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xff); | |
5833 | break; | |
5834 | case OPC2_32_RR_SAT_H: | |
5835 | gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7fff, -0x8000); | |
5836 | break; | |
5837 | case OPC2_32_RR_SAT_HU: | |
5838 | gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xffff); | |
5839 | break; | |
5840 | case OPC2_32_RR_SH_EQ: | |
5841 | gen_sh_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5842 | cpu_gpr_d[r2]); | |
5843 | break; | |
5844 | case OPC2_32_RR_SH_GE: | |
5845 | gen_sh_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5846 | cpu_gpr_d[r2]); | |
5847 | break; | |
5848 | case OPC2_32_RR_SH_GE_U: | |
5849 | gen_sh_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5850 | cpu_gpr_d[r2]); | |
5851 | break; | |
5852 | case OPC2_32_RR_SH_LT: | |
5853 | gen_sh_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5854 | cpu_gpr_d[r2]); | |
5855 | break; | |
5856 | case OPC2_32_RR_SH_LT_U: | |
5857 | gen_sh_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5858 | cpu_gpr_d[r2]); | |
5859 | break; | |
5860 | case OPC2_32_RR_SH_NE: | |
5861 | gen_sh_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5862 | cpu_gpr_d[r2]); | |
5863 | break; | |
5864 | case OPC2_32_RR_SUB: | |
5865 | gen_sub_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5866 | break; | |
5867 | case OPC2_32_RR_SUB_B: | |
ad75a51e | 5868 | gen_helper_sub_b(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); |
d5de7839 BK |
5869 | break; |
5870 | case OPC2_32_RR_SUB_H: | |
ad75a51e | 5871 | gen_helper_sub_h(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); |
d5de7839 BK |
5872 | break; |
5873 | case OPC2_32_RR_SUBC: | |
5874 | gen_subc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5875 | break; | |
5876 | case OPC2_32_RR_SUBS: | |
5877 | gen_subs(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5878 | break; | |
5879 | case OPC2_32_RR_SUBS_U: | |
5880 | gen_subsu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5881 | break; | |
5882 | case OPC2_32_RR_SUBS_H: | |
ad75a51e | 5883 | gen_helper_sub_h_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], |
d5de7839 BK |
5884 | cpu_gpr_d[r2]); |
5885 | break; | |
5886 | case OPC2_32_RR_SUBS_HU: | |
ad75a51e | 5887 | gen_helper_sub_h_suov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], |
d5de7839 BK |
5888 | cpu_gpr_d[r2]); |
5889 | break; | |
5890 | case OPC2_32_RR_SUBX: | |
5891 | gen_sub_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5892 | break; | |
5893 | case OPC2_32_RR_XOR_EQ: | |
5894 | gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5895 | cpu_gpr_d[r2], &tcg_gen_xor_tl); | |
5896 | break; | |
5897 | case OPC2_32_RR_XOR_GE: | |
5898 | gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5899 | cpu_gpr_d[r2], &tcg_gen_xor_tl); | |
5900 | break; | |
5901 | case OPC2_32_RR_XOR_GE_U: | |
5902 | gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5903 | cpu_gpr_d[r2], &tcg_gen_xor_tl); | |
5904 | break; | |
5905 | case OPC2_32_RR_XOR_LT: | |
5906 | gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5907 | cpu_gpr_d[r2], &tcg_gen_xor_tl); | |
5908 | break; | |
5909 | case OPC2_32_RR_XOR_LT_U: | |
5910 | gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5911 | cpu_gpr_d[r2], &tcg_gen_xor_tl); | |
5912 | break; | |
5913 | case OPC2_32_RR_XOR_NE: | |
5914 | gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
5915 | cpu_gpr_d[r2], &tcg_gen_xor_tl); | |
5916 | break; | |
f678f671 BK |
5917 | default: |
5918 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
d5de7839 BK |
5919 | } |
5920 | } | |
5921 | ||
2db92a0c | 5922 | static void decode_rr_logical_shift(DisasContext *ctx) |
0b79a781 BK |
5923 | { |
5924 | uint32_t op2; | |
5925 | int r3, r2, r1; | |
0b79a781 BK |
5926 | |
5927 | r3 = MASK_OP_RR_D(ctx->opcode); | |
5928 | r2 = MASK_OP_RR_S2(ctx->opcode); | |
5929 | r1 = MASK_OP_RR_S1(ctx->opcode); | |
0b79a781 BK |
5930 | op2 = MASK_OP_RR_OP2(ctx->opcode); |
5931 | ||
5932 | switch (op2) { | |
5933 | case OPC2_32_RR_AND: | |
5934 | tcg_gen_and_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5935 | break; | |
5936 | case OPC2_32_RR_ANDN: | |
5937 | tcg_gen_andc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5938 | break; | |
5939 | case OPC2_32_RR_CLO: | |
0efa8208 RH |
5940 | tcg_gen_not_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); |
5941 | tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], TARGET_LONG_BITS); | |
0b79a781 BK |
5942 | break; |
5943 | case OPC2_32_RR_CLO_H: | |
5944 | gen_helper_clo_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); | |
5945 | break; | |
5946 | case OPC2_32_RR_CLS: | |
16256947 | 5947 | tcg_gen_clrsb_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); |
0b79a781 BK |
5948 | break; |
5949 | case OPC2_32_RR_CLS_H: | |
5950 | gen_helper_cls_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); | |
5951 | break; | |
5952 | case OPC2_32_RR_CLZ: | |
0efa8208 | 5953 | tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], TARGET_LONG_BITS); |
0b79a781 BK |
5954 | break; |
5955 | case OPC2_32_RR_CLZ_H: | |
5956 | gen_helper_clz_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); | |
5957 | break; | |
5958 | case OPC2_32_RR_NAND: | |
5959 | tcg_gen_nand_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5960 | break; | |
5961 | case OPC2_32_RR_NOR: | |
5962 | tcg_gen_nor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5963 | break; | |
5964 | case OPC2_32_RR_OR: | |
5965 | tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5966 | break; | |
5967 | case OPC2_32_RR_ORN: | |
5968 | tcg_gen_orc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5969 | break; | |
5970 | case OPC2_32_RR_SH: | |
5971 | gen_helper_sh(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5972 | break; | |
5973 | case OPC2_32_RR_SH_H: | |
5974 | gen_helper_sh_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5975 | break; | |
5976 | case OPC2_32_RR_SHA: | |
ad75a51e | 5977 | gen_helper_sha(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); |
0b79a781 BK |
5978 | break; |
5979 | case OPC2_32_RR_SHA_H: | |
5980 | gen_helper_sha_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5981 | break; | |
5982 | case OPC2_32_RR_SHAS: | |
5983 | gen_shas(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5984 | break; | |
5985 | case OPC2_32_RR_XNOR: | |
5986 | tcg_gen_eqv_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5987 | break; | |
5988 | case OPC2_32_RR_XOR: | |
5989 | tcg_gen_xor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
5990 | break; | |
f678f671 BK |
5991 | default: |
5992 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
0b79a781 | 5993 | } |
0b79a781 BK |
5994 | } |
5995 | ||
2db92a0c | 5996 | static void decode_rr_address(DisasContext *ctx) |
f2f1585f BK |
5997 | { |
5998 | uint32_t op2, n; | |
5999 | int r1, r2, r3; | |
6000 | TCGv temp; | |
6001 | ||
6002 | op2 = MASK_OP_RR_OP2(ctx->opcode); | |
6003 | r3 = MASK_OP_RR_D(ctx->opcode); | |
6004 | r2 = MASK_OP_RR_S2(ctx->opcode); | |
6005 | r1 = MASK_OP_RR_S1(ctx->opcode); | |
6006 | n = MASK_OP_RR_N(ctx->opcode); | |
6007 | ||
6008 | switch (op2) { | |
6009 | case OPC2_32_RR_ADD_A: | |
6010 | tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]); | |
6011 | break; | |
6012 | case OPC2_32_RR_ADDSC_A: | |
6013 | temp = tcg_temp_new(); | |
6014 | tcg_gen_shli_tl(temp, cpu_gpr_d[r1], n); | |
6015 | tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r2], temp); | |
f2f1585f BK |
6016 | break; |
6017 | case OPC2_32_RR_ADDSC_AT: | |
6018 | temp = tcg_temp_new(); | |
6019 | tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 3); | |
6020 | tcg_gen_add_tl(temp, cpu_gpr_a[r2], temp); | |
6021 | tcg_gen_andi_tl(cpu_gpr_a[r3], temp, 0xFFFFFFFC); | |
f2f1585f BK |
6022 | break; |
6023 | case OPC2_32_RR_EQ_A: | |
6024 | tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1], | |
6025 | cpu_gpr_a[r2]); | |
6026 | break; | |
6027 | case OPC2_32_RR_EQZ: | |
6028 | tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1], 0); | |
6029 | break; | |
6030 | case OPC2_32_RR_GE_A: | |
6031 | tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_a[r1], | |
6032 | cpu_gpr_a[r2]); | |
6033 | break; | |
6034 | case OPC2_32_RR_LT_A: | |
6035 | tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_a[r1], | |
6036 | cpu_gpr_a[r2]); | |
6037 | break; | |
6038 | case OPC2_32_RR_MOV_A: | |
6039 | tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_d[r2]); | |
6040 | break; | |
6041 | case OPC2_32_RR_MOV_AA: | |
6042 | tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_a[r2]); | |
6043 | break; | |
6044 | case OPC2_32_RR_MOV_D: | |
6045 | tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_a[r2]); | |
6046 | break; | |
6047 | case OPC2_32_RR_NE_A: | |
6048 | tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1], | |
6049 | cpu_gpr_a[r2]); | |
6050 | break; | |
6051 | case OPC2_32_RR_NEZ_A: | |
6052 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1], 0); | |
6053 | break; | |
6054 | case OPC2_32_RR_SUB_A: | |
6055 | tcg_gen_sub_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]); | |
6056 | break; | |
f678f671 BK |
6057 | default: |
6058 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
f2f1585f BK |
6059 | } |
6060 | } | |
6061 | ||
2db92a0c | 6062 | static void decode_rr_idirect(DisasContext *ctx) |
f2f1585f BK |
6063 | { |
6064 | uint32_t op2; | |
6065 | int r1; | |
6066 | ||
6067 | op2 = MASK_OP_RR_OP2(ctx->opcode); | |
6068 | r1 = MASK_OP_RR_S1(ctx->opcode); | |
6069 | ||
6070 | switch (op2) { | |
6071 | case OPC2_32_RR_JI: | |
6072 | tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); | |
6073 | break; | |
6074 | case OPC2_32_RR_JLI: | |
f2f1585f | 6075 | tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); |
8da70480 | 6076 | tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); |
f2f1585f BK |
6077 | break; |
6078 | case OPC2_32_RR_CALLI: | |
6b9f5a42 | 6079 | gen_helper_1arg(call, ctx->pc_succ_insn); |
f2f1585f BK |
6080 | tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); |
6081 | break; | |
9e14a7b2 BK |
6082 | case OPC2_32_RR_FCALLI: |
6083 | gen_fcall_save_ctx(ctx); | |
6084 | tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); | |
6085 | break; | |
f678f671 BK |
6086 | default: |
6087 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
d8f466af | 6088 | return; |
f2f1585f | 6089 | } |
d8f466af | 6090 | ctx->base.is_jmp = DISAS_JUMP; |
f2f1585f BK |
6091 | } |
6092 | ||
2db92a0c | 6093 | static void decode_rr_divide(DisasContext *ctx) |
e2bed107 BK |
6094 | { |
6095 | uint32_t op2; | |
6096 | int r1, r2, r3; | |
6097 | ||
2b9d09bb | 6098 | TCGv temp, temp2, temp3; |
e2bed107 BK |
6099 | |
6100 | op2 = MASK_OP_RR_OP2(ctx->opcode); | |
6101 | r3 = MASK_OP_RR_D(ctx->opcode); | |
6102 | r2 = MASK_OP_RR_S2(ctx->opcode); | |
6103 | r1 = MASK_OP_RR_S1(ctx->opcode); | |
6104 | ||
6105 | switch (op2) { | |
6106 | case OPC2_32_RR_BMERGE: | |
6107 | gen_helper_bmerge(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6108 | break; | |
6109 | case OPC2_32_RR_BSPLIT: | |
828066c7 | 6110 | CHECK_REG_PAIR(r3); |
e2bed107 BK |
6111 | gen_bsplit(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]); |
6112 | break; | |
6113 | case OPC2_32_RR_DVINIT_B: | |
828066c7 | 6114 | CHECK_REG_PAIR(r3); |
2db92a0c | 6115 | gen_dvinit_b(ctx, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], |
e2bed107 BK |
6116 | cpu_gpr_d[r2]); |
6117 | break; | |
6118 | case OPC2_32_RR_DVINIT_BU: | |
6119 | temp = tcg_temp_new(); | |
6120 | temp2 = tcg_temp_new(); | |
2b9d09bb | 6121 | temp3 = tcg_temp_new(); |
828066c7 | 6122 | CHECK_REG_PAIR(r3); |
2b9d09bb | 6123 | tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 8); |
e2bed107 BK |
6124 | /* reset av */ |
6125 | tcg_gen_movi_tl(cpu_PSW_AV, 0); | |
44ee3baf | 6126 | if (!has_feature(ctx, TRICORE_FEATURE_131)) { |
e2bed107 | 6127 | /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */ |
2f8036d2 PMD |
6128 | tcg_gen_abs_tl(temp, temp3); |
6129 | tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]); | |
e2bed107 BK |
6130 | tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2); |
6131 | } else { | |
6132 | /* overflow = (D[b] == 0) */ | |
6133 | tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0); | |
6134 | } | |
6135 | tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); | |
6136 | /* sv */ | |
6137 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
6138 | /* write result */ | |
e2bed107 | 6139 | tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 24); |
2b9d09bb | 6140 | tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3); |
e2bed107 BK |
6141 | break; |
6142 | case OPC2_32_RR_DVINIT_H: | |
828066c7 | 6143 | CHECK_REG_PAIR(r3); |
2db92a0c | 6144 | gen_dvinit_h(ctx, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], |
e2bed107 BK |
6145 | cpu_gpr_d[r2]); |
6146 | break; | |
6147 | case OPC2_32_RR_DVINIT_HU: | |
6148 | temp = tcg_temp_new(); | |
6149 | temp2 = tcg_temp_new(); | |
2b9d09bb | 6150 | temp3 = tcg_temp_new(); |
828066c7 | 6151 | CHECK_REG_PAIR(r3); |
2b9d09bb | 6152 | tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 16); |
e2bed107 BK |
6153 | /* reset av */ |
6154 | tcg_gen_movi_tl(cpu_PSW_AV, 0); | |
44ee3baf | 6155 | if (!has_feature(ctx, TRICORE_FEATURE_131)) { |
e2bed107 | 6156 | /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */ |
2f8036d2 PMD |
6157 | tcg_gen_abs_tl(temp, temp3); |
6158 | tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]); | |
e2bed107 BK |
6159 | tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2); |
6160 | } else { | |
6161 | /* overflow = (D[b] == 0) */ | |
6162 | tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0); | |
6163 | } | |
6164 | tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); | |
6165 | /* sv */ | |
6166 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
6167 | /* write result */ | |
2b9d09bb | 6168 | tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 16); |
05b6ca9b | 6169 | tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3); |
e2bed107 BK |
6170 | break; |
6171 | case OPC2_32_RR_DVINIT: | |
6172 | temp = tcg_temp_new(); | |
6173 | temp2 = tcg_temp_new(); | |
828066c7 | 6174 | CHECK_REG_PAIR(r3); |
e2bed107 BK |
6175 | /* overflow = ((D[b] == 0) || |
6176 | ((D[b] == 0xFFFFFFFF) && (D[a] == 0x80000000))) */ | |
6177 | tcg_gen_setcondi_tl(TCG_COND_EQ, temp, cpu_gpr_d[r2], 0xffffffff); | |
6178 | tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r1], 0x80000000); | |
6179 | tcg_gen_and_tl(temp, temp, temp2); | |
6180 | tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r2], 0); | |
6181 | tcg_gen_or_tl(cpu_PSW_V, temp, temp2); | |
6182 | tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); | |
6183 | /* sv */ | |
6184 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
6185 | /* reset av */ | |
6186 | tcg_gen_movi_tl(cpu_PSW_AV, 0); | |
6187 | /* write result */ | |
6188 | tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); | |
6189 | /* sign extend to high reg */ | |
6190 | tcg_gen_sari_tl(cpu_gpr_d[r3+1], cpu_gpr_d[r1], 31); | |
e2bed107 BK |
6191 | break; |
6192 | case OPC2_32_RR_DVINIT_U: | |
6991777e | 6193 | CHECK_REG_PAIR(r3); |
e2bed107 BK |
6194 | /* overflow = (D[b] == 0) */ |
6195 | tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0); | |
6196 | tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); | |
6197 | /* sv */ | |
6198 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
6199 | /* reset av */ | |
6200 | tcg_gen_movi_tl(cpu_PSW_AV, 0); | |
6201 | /* write result */ | |
6202 | tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); | |
6203 | /* zero extend to high reg*/ | |
6204 | tcg_gen_movi_tl(cpu_gpr_d[r3+1], 0); | |
6205 | break; | |
6206 | case OPC2_32_RR_PARITY: | |
6207 | gen_helper_parity(cpu_gpr_d[r3], cpu_gpr_d[r1]); | |
6208 | break; | |
6209 | case OPC2_32_RR_UNPACK: | |
828066c7 | 6210 | CHECK_REG_PAIR(r3); |
e2bed107 BK |
6211 | gen_unpack(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]); |
6212 | break; | |
0eaafe33 BK |
6213 | case OPC2_32_RR_CRC32_B: |
6214 | if (has_feature(ctx, TRICORE_FEATURE_162)) { | |
6215 | gen_helper_crc32b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6216 | } else { | |
6217 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
6218 | } | |
6219 | break; | |
dc0b4368 | 6220 | case OPC2_32_RR_CRC32: /* CRC32B.W in 1.6.2 */ |
44ee3baf | 6221 | if (has_feature(ctx, TRICORE_FEATURE_161)) { |
dc0b4368 | 6222 | gen_helper_crc32_be(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); |
f678f671 BK |
6223 | } else { |
6224 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
6225 | } | |
e5c96c82 | 6226 | break; |
dc0b4368 BK |
6227 | case OPC2_32_RR_CRC32L_W: |
6228 | if (has_feature(ctx, TRICORE_FEATURE_162)) { | |
6229 | gen_helper_crc32_le(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6230 | } else { | |
6231 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
6232 | } | |
6233 | break; | |
6234 | ||
fd6f446a BK |
6235 | case OPC2_32_RR_POPCNT_W: |
6236 | if (has_feature(ctx, TRICORE_FEATURE_162)) { | |
6237 | tcg_gen_ctpop_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); | |
6238 | } else { | |
6239 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
6240 | } | |
6241 | break; | |
93715571 | 6242 | case OPC2_32_RR_DIV: |
44ee3baf | 6243 | if (has_feature(ctx, TRICORE_FEATURE_16)) { |
6991777e | 6244 | CHECK_REG_PAIR(r3); |
93715571 BK |
6245 | GEN_HELPER_RR(divide, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], |
6246 | cpu_gpr_d[r2]); | |
f678f671 BK |
6247 | } else { |
6248 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
6249 | } | |
93715571 BK |
6250 | break; |
6251 | case OPC2_32_RR_DIV_U: | |
44ee3baf | 6252 | if (has_feature(ctx, TRICORE_FEATURE_16)) { |
6991777e | 6253 | CHECK_REG_PAIR(r3); |
93715571 BK |
6254 | GEN_HELPER_RR(divide_u, cpu_gpr_d[r3], cpu_gpr_d[r3+1], |
6255 | cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
f678f671 BK |
6256 | } else { |
6257 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
6258 | } | |
93715571 | 6259 | break; |
daab3f7f | 6260 | case OPC2_32_RR_MUL_F: |
ad75a51e | 6261 | gen_helper_fmul(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); |
daab3f7f | 6262 | break; |
446ee5b2 | 6263 | case OPC2_32_RR_DIV_F: |
ad75a51e | 6264 | gen_helper_fdiv(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); |
446ee5b2 | 6265 | break; |
815061b9 BK |
6266 | case OPC2_32_RR_FTOHP: |
6267 | if (has_feature(ctx, TRICORE_FEATURE_162)) { | |
ad75a51e | 6268 | gen_helper_ftohp(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); |
815061b9 BK |
6269 | } else { |
6270 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
6271 | } | |
6272 | break; | |
5e0e06d9 BK |
6273 | case OPC2_32_RR_HPTOF: |
6274 | if (has_feature(ctx, TRICORE_FEATURE_162)) { | |
ad75a51e | 6275 | gen_helper_hptof(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); |
5e0e06d9 BK |
6276 | } else { |
6277 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
6278 | } | |
6279 | break; | |
743cd09d | 6280 | case OPC2_32_RR_CMP_F: |
ad75a51e | 6281 | gen_helper_fcmp(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); |
743cd09d | 6282 | break; |
0d4c3b80 | 6283 | case OPC2_32_RR_FTOI: |
ad75a51e | 6284 | gen_helper_ftoi(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); |
0d4c3b80 BK |
6285 | break; |
6286 | case OPC2_32_RR_ITOF: | |
ad75a51e | 6287 | gen_helper_itof(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); |
0d4c3b80 | 6288 | break; |
2bdbe356 | 6289 | case OPC2_32_RR_FTOU: |
ad75a51e | 6290 | gen_helper_ftou(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); |
2bdbe356 | 6291 | break; |
8f75983d | 6292 | case OPC2_32_RR_FTOUZ: |
4f79db47 | 6293 | if (has_feature(ctx, TRICORE_FEATURE_131)) { |
ad75a51e | 6294 | gen_helper_ftouz(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); |
4f79db47 BK |
6295 | } else { |
6296 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
6297 | } | |
8f75983d | 6298 | break; |
50788a3f | 6299 | case OPC2_32_RR_UPDFL: |
ad75a51e | 6300 | gen_helper_updfl(tcg_env, cpu_gpr_d[r1]); |
50788a3f | 6301 | break; |
4e6fd2e3 | 6302 | case OPC2_32_RR_UTOF: |
ad75a51e | 6303 | gen_helper_utof(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); |
4e6fd2e3 | 6304 | break; |
1fa79fb0 | 6305 | case OPC2_32_RR_FTOIZ: |
ad75a51e | 6306 | gen_helper_ftoiz(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); |
1fa79fb0 | 6307 | break; |
8317ea06 | 6308 | case OPC2_32_RR_QSEED_F: |
ad75a51e | 6309 | gen_helper_qseed(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); |
8317ea06 | 6310 | break; |
f678f671 BK |
6311 | default: |
6312 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
e2bed107 BK |
6313 | } |
6314 | } | |
6315 | ||
9655b932 | 6316 | /* RR1 Format */ |
2db92a0c | 6317 | static void decode_rr1_mul(DisasContext *ctx) |
9655b932 BK |
6318 | { |
6319 | uint32_t op2; | |
6320 | ||
6321 | int r1, r2, r3; | |
6322 | TCGv n; | |
6323 | TCGv_i64 temp64; | |
6324 | ||
6325 | r1 = MASK_OP_RR1_S1(ctx->opcode); | |
6326 | r2 = MASK_OP_RR1_S2(ctx->opcode); | |
6327 | r3 = MASK_OP_RR1_D(ctx->opcode); | |
151293c2 | 6328 | n = tcg_constant_i32(MASK_OP_RR1_N(ctx->opcode)); |
9655b932 BK |
6329 | op2 = MASK_OP_RR1_OP2(ctx->opcode); |
6330 | ||
6331 | switch (op2) { | |
6332 | case OPC2_32_RR1_MUL_H_32_LL: | |
6333 | temp64 = tcg_temp_new_i64(); | |
828066c7 | 6334 | CHECK_REG_PAIR(r3); |
9655b932 BK |
6335 | GEN_HELPER_LL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); |
6336 | tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); | |
6337 | gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); | |
9655b932 BK |
6338 | break; |
6339 | case OPC2_32_RR1_MUL_H_32_LU: | |
6340 | temp64 = tcg_temp_new_i64(); | |
828066c7 | 6341 | CHECK_REG_PAIR(r3); |
9655b932 BK |
6342 | GEN_HELPER_LU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); |
6343 | tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); | |
6344 | gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); | |
9655b932 BK |
6345 | break; |
6346 | case OPC2_32_RR1_MUL_H_32_UL: | |
6347 | temp64 = tcg_temp_new_i64(); | |
828066c7 | 6348 | CHECK_REG_PAIR(r3); |
9655b932 BK |
6349 | GEN_HELPER_UL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); |
6350 | tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); | |
6351 | gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); | |
9655b932 BK |
6352 | break; |
6353 | case OPC2_32_RR1_MUL_H_32_UU: | |
6354 | temp64 = tcg_temp_new_i64(); | |
828066c7 | 6355 | CHECK_REG_PAIR(r3); |
9655b932 BK |
6356 | GEN_HELPER_UU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); |
6357 | tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); | |
6358 | gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); | |
9655b932 BK |
6359 | break; |
6360 | case OPC2_32_RR1_MULM_H_64_LL: | |
6361 | temp64 = tcg_temp_new_i64(); | |
828066c7 | 6362 | CHECK_REG_PAIR(r3); |
9655b932 BK |
6363 | GEN_HELPER_LL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); |
6364 | tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); | |
6365 | /* reset V bit */ | |
6366 | tcg_gen_movi_tl(cpu_PSW_V, 0); | |
6367 | /* reset AV bit */ | |
6368 | tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); | |
9655b932 BK |
6369 | break; |
6370 | case OPC2_32_RR1_MULM_H_64_LU: | |
6371 | temp64 = tcg_temp_new_i64(); | |
828066c7 | 6372 | CHECK_REG_PAIR(r3); |
9655b932 BK |
6373 | GEN_HELPER_LU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); |
6374 | tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); | |
6375 | /* reset V bit */ | |
6376 | tcg_gen_movi_tl(cpu_PSW_V, 0); | |
6377 | /* reset AV bit */ | |
6378 | tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); | |
9655b932 BK |
6379 | break; |
6380 | case OPC2_32_RR1_MULM_H_64_UL: | |
6381 | temp64 = tcg_temp_new_i64(); | |
828066c7 | 6382 | CHECK_REG_PAIR(r3); |
9655b932 BK |
6383 | GEN_HELPER_UL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); |
6384 | tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); | |
6385 | /* reset V bit */ | |
6386 | tcg_gen_movi_tl(cpu_PSW_V, 0); | |
6387 | /* reset AV bit */ | |
6388 | tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); | |
9655b932 BK |
6389 | break; |
6390 | case OPC2_32_RR1_MULM_H_64_UU: | |
6391 | temp64 = tcg_temp_new_i64(); | |
828066c7 | 6392 | CHECK_REG_PAIR(r3); |
9655b932 BK |
6393 | GEN_HELPER_UU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); |
6394 | tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); | |
6395 | /* reset V bit */ | |
6396 | tcg_gen_movi_tl(cpu_PSW_V, 0); | |
6397 | /* reset AV bit */ | |
6398 | tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); | |
9655b932 BK |
6399 | break; |
6400 | case OPC2_32_RR1_MULR_H_16_LL: | |
6401 | GEN_HELPER_LL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); | |
6402 | gen_calc_usb_mulr_h(cpu_gpr_d[r3]); | |
6403 | break; | |
6404 | case OPC2_32_RR1_MULR_H_16_LU: | |
6405 | GEN_HELPER_LU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); | |
6406 | gen_calc_usb_mulr_h(cpu_gpr_d[r3]); | |
6407 | break; | |
6408 | case OPC2_32_RR1_MULR_H_16_UL: | |
6409 | GEN_HELPER_UL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); | |
6410 | gen_calc_usb_mulr_h(cpu_gpr_d[r3]); | |
6411 | break; | |
6412 | case OPC2_32_RR1_MULR_H_16_UU: | |
6413 | GEN_HELPER_UU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); | |
6414 | gen_calc_usb_mulr_h(cpu_gpr_d[r3]); | |
6415 | break; | |
f678f671 BK |
6416 | default: |
6417 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
9655b932 | 6418 | } |
9655b932 BK |
6419 | } |
6420 | ||
2db92a0c | 6421 | static void decode_rr1_mulq(DisasContext *ctx) |
f1cc6eaf BK |
6422 | { |
6423 | uint32_t op2; | |
6424 | int r1, r2, r3; | |
6425 | uint32_t n; | |
6426 | ||
6427 | TCGv temp, temp2; | |
6428 | ||
6429 | r1 = MASK_OP_RR1_S1(ctx->opcode); | |
6430 | r2 = MASK_OP_RR1_S2(ctx->opcode); | |
6431 | r3 = MASK_OP_RR1_D(ctx->opcode); | |
6432 | n = MASK_OP_RR1_N(ctx->opcode); | |
6433 | op2 = MASK_OP_RR1_OP2(ctx->opcode); | |
6434 | ||
6435 | temp = tcg_temp_new(); | |
6436 | temp2 = tcg_temp_new(); | |
6437 | ||
6438 | switch (op2) { | |
6439 | case OPC2_32_RR1_MUL_Q_32: | |
6440 | gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], cpu_gpr_d[r2], n, 32); | |
6441 | break; | |
6442 | case OPC2_32_RR1_MUL_Q_64: | |
828066c7 | 6443 | CHECK_REG_PAIR(r3); |
f1cc6eaf BK |
6444 | gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], |
6445 | n, 0); | |
6446 | break; | |
6447 | case OPC2_32_RR1_MUL_Q_32_L: | |
6448 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); | |
6449 | gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16); | |
6450 | break; | |
6451 | case OPC2_32_RR1_MUL_Q_64_L: | |
828066c7 | 6452 | CHECK_REG_PAIR(r3); |
f1cc6eaf BK |
6453 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); |
6454 | gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0); | |
6455 | break; | |
6456 | case OPC2_32_RR1_MUL_Q_32_U: | |
6457 | tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); | |
6458 | gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16); | |
6459 | break; | |
6460 | case OPC2_32_RR1_MUL_Q_64_U: | |
828066c7 | 6461 | CHECK_REG_PAIR(r3); |
f1cc6eaf BK |
6462 | tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); |
6463 | gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0); | |
6464 | break; | |
6465 | case OPC2_32_RR1_MUL_Q_32_LL: | |
6466 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); | |
6467 | tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); | |
6468 | gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n); | |
6469 | break; | |
6470 | case OPC2_32_RR1_MUL_Q_32_UU: | |
6471 | tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); | |
6472 | tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); | |
6473 | gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n); | |
6474 | break; | |
6475 | case OPC2_32_RR1_MULR_Q_32_L: | |
6476 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); | |
6477 | tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); | |
6478 | gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n); | |
6479 | break; | |
6480 | case OPC2_32_RR1_MULR_Q_32_U: | |
6481 | tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); | |
6482 | tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); | |
6483 | gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n); | |
6484 | break; | |
f678f671 BK |
6485 | default: |
6486 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
f1cc6eaf | 6487 | } |
f1cc6eaf BK |
6488 | } |
6489 | ||
12f323e6 | 6490 | /* RR2 format */ |
2db92a0c | 6491 | static void decode_rr2_mul(DisasContext *ctx) |
12f323e6 BK |
6492 | { |
6493 | uint32_t op2; | |
6494 | int r1, r2, r3; | |
6495 | ||
6496 | op2 = MASK_OP_RR2_OP2(ctx->opcode); | |
6497 | r1 = MASK_OP_RR2_S1(ctx->opcode); | |
6498 | r2 = MASK_OP_RR2_S2(ctx->opcode); | |
6499 | r3 = MASK_OP_RR2_D(ctx->opcode); | |
6500 | switch (op2) { | |
6501 | case OPC2_32_RR2_MUL_32: | |
6502 | gen_mul_i32s(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6503 | break; | |
6504 | case OPC2_32_RR2_MUL_64: | |
828066c7 | 6505 | CHECK_REG_PAIR(r3); |
12f323e6 BK |
6506 | gen_mul_i64s(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], |
6507 | cpu_gpr_d[r2]); | |
6508 | break; | |
6509 | case OPC2_32_RR2_MULS_32: | |
ad75a51e | 6510 | gen_helper_mul_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], |
12f323e6 BK |
6511 | cpu_gpr_d[r2]); |
6512 | break; | |
6513 | case OPC2_32_RR2_MUL_U_64: | |
828066c7 | 6514 | CHECK_REG_PAIR(r3); |
12f323e6 BK |
6515 | gen_mul_i64u(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], |
6516 | cpu_gpr_d[r2]); | |
6517 | break; | |
6518 | case OPC2_32_RR2_MULS_U_32: | |
ad75a51e | 6519 | gen_helper_mul_suov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], |
12f323e6 BK |
6520 | cpu_gpr_d[r2]); |
6521 | break; | |
f678f671 BK |
6522 | default: |
6523 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
12f323e6 BK |
6524 | } |
6525 | } | |
6526 | ||
8fb9d0eb | 6527 | /* RRPW format */ |
2db92a0c | 6528 | static void decode_rrpw_extract_insert(DisasContext *ctx) |
8fb9d0eb BK |
6529 | { |
6530 | uint32_t op2; | |
6531 | int r1, r2, r3; | |
6532 | int32_t pos, width; | |
00747984 | 6533 | TCGv temp; |
8fb9d0eb BK |
6534 | |
6535 | op2 = MASK_OP_RRPW_OP2(ctx->opcode); | |
6536 | r1 = MASK_OP_RRPW_S1(ctx->opcode); | |
6537 | r2 = MASK_OP_RRPW_S2(ctx->opcode); | |
6538 | r3 = MASK_OP_RRPW_D(ctx->opcode); | |
6539 | pos = MASK_OP_RRPW_POS(ctx->opcode); | |
6540 | width = MASK_OP_RRPW_WIDTH(ctx->opcode); | |
6541 | ||
6542 | switch (op2) { | |
6543 | case OPC2_32_RRPW_EXTR: | |
a21993c7 | 6544 | if (width == 0) { |
8b8bb295 RH |
6545 | tcg_gen_movi_tl(cpu_gpr_d[r3], 0); |
6546 | } else if (pos + width <= 32) { | |
6547 | tcg_gen_sextract_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], pos, width); | |
8fb9d0eb BK |
6548 | } |
6549 | break; | |
6550 | case OPC2_32_RRPW_EXTR_U: | |
6551 | if (width == 0) { | |
6552 | tcg_gen_movi_tl(cpu_gpr_d[r3], 0); | |
6553 | } else { | |
8b8bb295 | 6554 | tcg_gen_extract_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], pos, width); |
8fb9d0eb BK |
6555 | } |
6556 | break; | |
6557 | case OPC2_32_RRPW_IMASK: | |
828066c7 | 6558 | CHECK_REG_PAIR(r3); |
00747984 | 6559 | |
9b620609 | 6560 | if (pos + width <= 32) { |
00747984 BK |
6561 | temp = tcg_temp_new(); |
6562 | tcg_gen_movi_tl(temp, ((1u << width) - 1) << pos); | |
8fb9d0eb | 6563 | tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], pos); |
00747984 | 6564 | tcg_gen_mov_tl(cpu_gpr_d[r3 + 1], temp); |
8fb9d0eb | 6565 | } |
00747984 | 6566 | |
8fb9d0eb BK |
6567 | break; |
6568 | case OPC2_32_RRPW_INSERT: | |
23fa6f56 BK |
6569 | /* tcg_gen_deposit_tl() does not handle the case of width = 0 */ |
6570 | if (width == 0) { | |
6571 | tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); | |
6572 | } else if (pos + width <= 32) { | |
8fb9d0eb | 6573 | tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], |
61b26250 | 6574 | pos, width); |
8fb9d0eb BK |
6575 | } |
6576 | break; | |
f678f671 BK |
6577 | default: |
6578 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
8fb9d0eb BK |
6579 | } |
6580 | } | |
6581 | ||
09532255 | 6582 | /* RRR format */ |
2db92a0c | 6583 | static void decode_rrr_cond_select(DisasContext *ctx) |
09532255 BK |
6584 | { |
6585 | uint32_t op2; | |
6586 | int r1, r2, r3, r4; | |
6587 | TCGv temp; | |
6588 | ||
6589 | op2 = MASK_OP_RRR_OP2(ctx->opcode); | |
6590 | r1 = MASK_OP_RRR_S1(ctx->opcode); | |
6591 | r2 = MASK_OP_RRR_S2(ctx->opcode); | |
6592 | r3 = MASK_OP_RRR_S3(ctx->opcode); | |
6593 | r4 = MASK_OP_RRR_D(ctx->opcode); | |
6594 | ||
6595 | switch (op2) { | |
6596 | case OPC2_32_RRR_CADD: | |
6597 | gen_cond_add(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], | |
6598 | cpu_gpr_d[r4], cpu_gpr_d[r3]); | |
6599 | break; | |
6600 | case OPC2_32_RRR_CADDN: | |
6601 | gen_cond_add(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4], | |
6602 | cpu_gpr_d[r3]); | |
6603 | break; | |
6604 | case OPC2_32_RRR_CSUB: | |
6605 | gen_cond_sub(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4], | |
6606 | cpu_gpr_d[r3]); | |
6607 | break; | |
6608 | case OPC2_32_RRR_CSUBN: | |
6609 | gen_cond_sub(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4], | |
6610 | cpu_gpr_d[r3]); | |
6611 | break; | |
6612 | case OPC2_32_RRR_SEL: | |
151293c2 | 6613 | temp = tcg_constant_i32(0); |
09532255 BK |
6614 | tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, |
6615 | cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
09532255 BK |
6616 | break; |
6617 | case OPC2_32_RRR_SELN: | |
151293c2 | 6618 | temp = tcg_constant_i32(0); |
09532255 BK |
6619 | tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, |
6620 | cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
09532255 | 6621 | break; |
f678f671 BK |
6622 | default: |
6623 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
09532255 BK |
6624 | } |
6625 | } | |
6626 | ||
2db92a0c | 6627 | static void decode_rrr_divide(DisasContext *ctx) |
09532255 BK |
6628 | { |
6629 | uint32_t op2; | |
6630 | ||
6631 | int r1, r2, r3, r4; | |
6632 | ||
6633 | op2 = MASK_OP_RRR_OP2(ctx->opcode); | |
6634 | r1 = MASK_OP_RRR_S1(ctx->opcode); | |
6635 | r2 = MASK_OP_RRR_S2(ctx->opcode); | |
6636 | r3 = MASK_OP_RRR_S3(ctx->opcode); | |
6637 | r4 = MASK_OP_RRR_D(ctx->opcode); | |
6638 | ||
6639 | switch (op2) { | |
6640 | case OPC2_32_RRR_DVADJ: | |
c433a171 | 6641 | CHECK_REG_PAIR(r3); |
828066c7 | 6642 | CHECK_REG_PAIR(r4); |
09532255 BK |
6643 | GEN_HELPER_RRR(dvadj, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
6644 | cpu_gpr_d[r3+1], cpu_gpr_d[r2]); | |
6645 | break; | |
6646 | case OPC2_32_RRR_DVSTEP: | |
c433a171 | 6647 | CHECK_REG_PAIR(r3); |
828066c7 | 6648 | CHECK_REG_PAIR(r4); |
09532255 BK |
6649 | GEN_HELPER_RRR(dvstep, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
6650 | cpu_gpr_d[r3+1], cpu_gpr_d[r2]); | |
6651 | break; | |
6652 | case OPC2_32_RRR_DVSTEP_U: | |
c433a171 | 6653 | CHECK_REG_PAIR(r3); |
828066c7 | 6654 | CHECK_REG_PAIR(r4); |
09532255 BK |
6655 | GEN_HELPER_RRR(dvstep_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
6656 | cpu_gpr_d[r3+1], cpu_gpr_d[r2]); | |
6657 | break; | |
6658 | case OPC2_32_RRR_IXMAX: | |
c433a171 | 6659 | CHECK_REG_PAIR(r3); |
828066c7 | 6660 | CHECK_REG_PAIR(r4); |
09532255 BK |
6661 | GEN_HELPER_RRR(ixmax, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
6662 | cpu_gpr_d[r3+1], cpu_gpr_d[r2]); | |
6663 | break; | |
6664 | case OPC2_32_RRR_IXMAX_U: | |
c433a171 | 6665 | CHECK_REG_PAIR(r3); |
828066c7 | 6666 | CHECK_REG_PAIR(r4); |
09532255 BK |
6667 | GEN_HELPER_RRR(ixmax_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
6668 | cpu_gpr_d[r3+1], cpu_gpr_d[r2]); | |
6669 | break; | |
6670 | case OPC2_32_RRR_IXMIN: | |
c433a171 | 6671 | CHECK_REG_PAIR(r3); |
828066c7 | 6672 | CHECK_REG_PAIR(r4); |
09532255 BK |
6673 | GEN_HELPER_RRR(ixmin, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
6674 | cpu_gpr_d[r3+1], cpu_gpr_d[r2]); | |
6675 | break; | |
6676 | case OPC2_32_RRR_IXMIN_U: | |
c433a171 | 6677 | CHECK_REG_PAIR(r3); |
828066c7 | 6678 | CHECK_REG_PAIR(r4); |
09532255 BK |
6679 | GEN_HELPER_RRR(ixmin_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
6680 | cpu_gpr_d[r3+1], cpu_gpr_d[r2]); | |
6681 | break; | |
6682 | case OPC2_32_RRR_PACK: | |
c433a171 | 6683 | CHECK_REG_PAIR(r3); |
09532255 BK |
6684 | gen_helper_pack(cpu_gpr_d[r4], cpu_PSW_C, cpu_gpr_d[r3], |
6685 | cpu_gpr_d[r3+1], cpu_gpr_d[r1]); | |
6686 | break; | |
3e2a5107 BK |
6687 | case OPC2_32_RRR_CRCN: |
6688 | if (has_feature(ctx, TRICORE_FEATURE_162)) { | |
6689 | gen_helper_crcn(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
6690 | cpu_gpr_d[r3]); | |
6691 | } else { | |
6692 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
6693 | } | |
6694 | break; | |
baf410dc | 6695 | case OPC2_32_RRR_ADD_F: |
ad75a51e | 6696 | gen_helper_fadd(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r3]); |
baf410dc BK |
6697 | break; |
6698 | case OPC2_32_RRR_SUB_F: | |
ad75a51e | 6699 | gen_helper_fsub(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r3]); |
baf410dc | 6700 | break; |
ddd7fead | 6701 | case OPC2_32_RRR_MADD_F: |
ad75a51e | 6702 | gen_helper_fmadd(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], |
ddd7fead BK |
6703 | cpu_gpr_d[r2], cpu_gpr_d[r3]); |
6704 | break; | |
6705 | case OPC2_32_RRR_MSUB_F: | |
ad75a51e | 6706 | gen_helper_fmsub(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], |
ddd7fead BK |
6707 | cpu_gpr_d[r2], cpu_gpr_d[r3]); |
6708 | break; | |
f678f671 BK |
6709 | default: |
6710 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
09532255 BK |
6711 | } |
6712 | } | |
6713 | ||
2984cfbd | 6714 | /* RRR2 format */ |
2db92a0c | 6715 | static void decode_rrr2_madd(DisasContext *ctx) |
2984cfbd BK |
6716 | { |
6717 | uint32_t op2; | |
6718 | uint32_t r1, r2, r3, r4; | |
6719 | ||
6720 | op2 = MASK_OP_RRR2_OP2(ctx->opcode); | |
6721 | r1 = MASK_OP_RRR2_S1(ctx->opcode); | |
6722 | r2 = MASK_OP_RRR2_S2(ctx->opcode); | |
6723 | r3 = MASK_OP_RRR2_S3(ctx->opcode); | |
6724 | r4 = MASK_OP_RRR2_D(ctx->opcode); | |
6725 | switch (op2) { | |
6726 | case OPC2_32_RRR2_MADD_32: | |
6727 | gen_madd32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], | |
6728 | cpu_gpr_d[r2]); | |
6729 | break; | |
6730 | case OPC2_32_RRR2_MADD_64: | |
828066c7 BK |
6731 | CHECK_REG_PAIR(r4); |
6732 | CHECK_REG_PAIR(r3); | |
2984cfbd BK |
6733 | gen_madd64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], |
6734 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); | |
6735 | break; | |
6736 | case OPC2_32_RRR2_MADDS_32: | |
ad75a51e | 6737 | gen_helper_madd32_ssov(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], |
2984cfbd BK |
6738 | cpu_gpr_d[r3], cpu_gpr_d[r2]); |
6739 | break; | |
6740 | case OPC2_32_RRR2_MADDS_64: | |
828066c7 BK |
6741 | CHECK_REG_PAIR(r4); |
6742 | CHECK_REG_PAIR(r3); | |
2984cfbd BK |
6743 | gen_madds_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], |
6744 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); | |
6745 | break; | |
6746 | case OPC2_32_RRR2_MADD_U_64: | |
828066c7 BK |
6747 | CHECK_REG_PAIR(r4); |
6748 | CHECK_REG_PAIR(r3); | |
2984cfbd BK |
6749 | gen_maddu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], |
6750 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); | |
6751 | break; | |
6752 | case OPC2_32_RRR2_MADDS_U_32: | |
ad75a51e | 6753 | gen_helper_madd32_suov(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], |
2984cfbd BK |
6754 | cpu_gpr_d[r3], cpu_gpr_d[r2]); |
6755 | break; | |
6756 | case OPC2_32_RRR2_MADDS_U_64: | |
828066c7 BK |
6757 | CHECK_REG_PAIR(r4); |
6758 | CHECK_REG_PAIR(r3); | |
2984cfbd BK |
6759 | gen_maddsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], |
6760 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); | |
6761 | break; | |
f678f671 BK |
6762 | default: |
6763 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
2984cfbd BK |
6764 | } |
6765 | } | |
6766 | ||
2db92a0c | 6767 | static void decode_rrr2_msub(DisasContext *ctx) |
2984cfbd BK |
6768 | { |
6769 | uint32_t op2; | |
6770 | uint32_t r1, r2, r3, r4; | |
6771 | ||
6772 | op2 = MASK_OP_RRR2_OP2(ctx->opcode); | |
6773 | r1 = MASK_OP_RRR2_S1(ctx->opcode); | |
6774 | r2 = MASK_OP_RRR2_S2(ctx->opcode); | |
6775 | r3 = MASK_OP_RRR2_S3(ctx->opcode); | |
6776 | r4 = MASK_OP_RRR2_D(ctx->opcode); | |
6777 | ||
6778 | switch (op2) { | |
6779 | case OPC2_32_RRR2_MSUB_32: | |
6780 | gen_msub32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], | |
6781 | cpu_gpr_d[r2]); | |
6782 | break; | |
6783 | case OPC2_32_RRR2_MSUB_64: | |
828066c7 BK |
6784 | CHECK_REG_PAIR(r4); |
6785 | CHECK_REG_PAIR(r3); | |
2984cfbd BK |
6786 | gen_msub64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], |
6787 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); | |
6788 | break; | |
6789 | case OPC2_32_RRR2_MSUBS_32: | |
ad75a51e | 6790 | gen_helper_msub32_ssov(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], |
2984cfbd BK |
6791 | cpu_gpr_d[r3], cpu_gpr_d[r2]); |
6792 | break; | |
6793 | case OPC2_32_RRR2_MSUBS_64: | |
828066c7 BK |
6794 | CHECK_REG_PAIR(r4); |
6795 | CHECK_REG_PAIR(r3); | |
2984cfbd BK |
6796 | gen_msubs_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], |
6797 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); | |
6798 | break; | |
6799 | case OPC2_32_RRR2_MSUB_U_64: | |
6991777e BK |
6800 | CHECK_REG_PAIR(r4); |
6801 | CHECK_REG_PAIR(r3); | |
2984cfbd BK |
6802 | gen_msubu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], |
6803 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); | |
6804 | break; | |
6805 | case OPC2_32_RRR2_MSUBS_U_32: | |
ad75a51e | 6806 | gen_helper_msub32_suov(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], |
2984cfbd BK |
6807 | cpu_gpr_d[r3], cpu_gpr_d[r2]); |
6808 | break; | |
6809 | case OPC2_32_RRR2_MSUBS_U_64: | |
828066c7 BK |
6810 | CHECK_REG_PAIR(r4); |
6811 | CHECK_REG_PAIR(r3); | |
2984cfbd BK |
6812 | gen_msubsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], |
6813 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); | |
6814 | break; | |
f678f671 BK |
6815 | default: |
6816 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
2984cfbd BK |
6817 | } |
6818 | } | |
6819 | ||
2e430e1c | 6820 | /* RRR1 format */ |
2db92a0c | 6821 | static void decode_rrr1_madd(DisasContext *ctx) |
2e430e1c BK |
6822 | { |
6823 | uint32_t op2; | |
6824 | uint32_t r1, r2, r3, r4, n; | |
6825 | ||
6826 | op2 = MASK_OP_RRR1_OP2(ctx->opcode); | |
6827 | r1 = MASK_OP_RRR1_S1(ctx->opcode); | |
6828 | r2 = MASK_OP_RRR1_S2(ctx->opcode); | |
6829 | r3 = MASK_OP_RRR1_S3(ctx->opcode); | |
6830 | r4 = MASK_OP_RRR1_D(ctx->opcode); | |
6831 | n = MASK_OP_RRR1_N(ctx->opcode); | |
6832 | ||
6833 | switch (op2) { | |
6834 | case OPC2_32_RRR1_MADD_H_LL: | |
828066c7 BK |
6835 | CHECK_REG_PAIR(r4); |
6836 | CHECK_REG_PAIR(r3); | |
2e430e1c BK |
6837 | gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
6838 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); | |
6839 | break; | |
6840 | case OPC2_32_RRR1_MADD_H_LU: | |
828066c7 BK |
6841 | CHECK_REG_PAIR(r4); |
6842 | CHECK_REG_PAIR(r3); | |
2e430e1c BK |
6843 | gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
6844 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); | |
6845 | break; | |
6846 | case OPC2_32_RRR1_MADD_H_UL: | |
828066c7 BK |
6847 | CHECK_REG_PAIR(r4); |
6848 | CHECK_REG_PAIR(r3); | |
2e430e1c BK |
6849 | gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
6850 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); | |
6851 | break; | |
6852 | case OPC2_32_RRR1_MADD_H_UU: | |
828066c7 BK |
6853 | CHECK_REG_PAIR(r4); |
6854 | CHECK_REG_PAIR(r3); | |
2e430e1c BK |
6855 | gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
6856 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); | |
6857 | break; | |
6858 | case OPC2_32_RRR1_MADDS_H_LL: | |
828066c7 BK |
6859 | CHECK_REG_PAIR(r4); |
6860 | CHECK_REG_PAIR(r3); | |
2e430e1c BK |
6861 | gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
6862 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); | |
6863 | break; | |
6864 | case OPC2_32_RRR1_MADDS_H_LU: | |
828066c7 BK |
6865 | CHECK_REG_PAIR(r4); |
6866 | CHECK_REG_PAIR(r3); | |
2e430e1c BK |
6867 | gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
6868 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); | |
6869 | break; | |
6870 | case OPC2_32_RRR1_MADDS_H_UL: | |
828066c7 BK |
6871 | CHECK_REG_PAIR(r4); |
6872 | CHECK_REG_PAIR(r3); | |
2e430e1c BK |
6873 | gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
6874 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); | |
6875 | break; | |
6876 | case OPC2_32_RRR1_MADDS_H_UU: | |
828066c7 BK |
6877 | CHECK_REG_PAIR(r4); |
6878 | CHECK_REG_PAIR(r3); | |
2e430e1c BK |
6879 | gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
6880 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); | |
6881 | break; | |
6882 | case OPC2_32_RRR1_MADDM_H_LL: | |
828066c7 BK |
6883 | CHECK_REG_PAIR(r4); |
6884 | CHECK_REG_PAIR(r3); | |
2e430e1c BK |
6885 | gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
6886 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); | |
6887 | break; | |
6888 | case OPC2_32_RRR1_MADDM_H_LU: | |
828066c7 BK |
6889 | CHECK_REG_PAIR(r4); |
6890 | CHECK_REG_PAIR(r3); | |
2e430e1c BK |
6891 | gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
6892 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); | |
6893 | break; | |
6894 | case OPC2_32_RRR1_MADDM_H_UL: | |
828066c7 BK |
6895 | CHECK_REG_PAIR(r4); |
6896 | CHECK_REG_PAIR(r3); | |
2e430e1c BK |
6897 | gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
6898 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); | |
6899 | break; | |
6900 | case OPC2_32_RRR1_MADDM_H_UU: | |
828066c7 BK |
6901 | CHECK_REG_PAIR(r4); |
6902 | CHECK_REG_PAIR(r3); | |
2e430e1c BK |
6903 | gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
6904 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); | |
6905 | break; | |
6906 | case OPC2_32_RRR1_MADDMS_H_LL: | |
828066c7 BK |
6907 | CHECK_REG_PAIR(r4); |
6908 | CHECK_REG_PAIR(r3); | |
2e430e1c BK |
6909 | gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
6910 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); | |
6911 | break; | |
6912 | case OPC2_32_RRR1_MADDMS_H_LU: | |
828066c7 BK |
6913 | CHECK_REG_PAIR(r4); |
6914 | CHECK_REG_PAIR(r3); | |
2e430e1c BK |
6915 | gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
6916 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); | |
6917 | break; | |
6918 | case OPC2_32_RRR1_MADDMS_H_UL: | |
828066c7 BK |
6919 | CHECK_REG_PAIR(r4); |
6920 | CHECK_REG_PAIR(r3); | |
2e430e1c BK |
6921 | gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
6922 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); | |
6923 | break; | |
6924 | case OPC2_32_RRR1_MADDMS_H_UU: | |
828066c7 BK |
6925 | CHECK_REG_PAIR(r4); |
6926 | CHECK_REG_PAIR(r3); | |
2e430e1c BK |
6927 | gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
6928 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); | |
6929 | break; | |
6930 | case OPC2_32_RRR1_MADDR_H_LL: | |
6931 | gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6932 | cpu_gpr_d[r2], n, MODE_LL); | |
6933 | break; | |
6934 | case OPC2_32_RRR1_MADDR_H_LU: | |
6935 | gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6936 | cpu_gpr_d[r2], n, MODE_LU); | |
6937 | break; | |
6938 | case OPC2_32_RRR1_MADDR_H_UL: | |
6939 | gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6940 | cpu_gpr_d[r2], n, MODE_UL); | |
6941 | break; | |
6942 | case OPC2_32_RRR1_MADDR_H_UU: | |
6943 | gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6944 | cpu_gpr_d[r2], n, MODE_UU); | |
6945 | break; | |
6946 | case OPC2_32_RRR1_MADDRS_H_LL: | |
6947 | gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6948 | cpu_gpr_d[r2], n, MODE_LL); | |
6949 | break; | |
6950 | case OPC2_32_RRR1_MADDRS_H_LU: | |
6951 | gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6952 | cpu_gpr_d[r2], n, MODE_LU); | |
6953 | break; | |
6954 | case OPC2_32_RRR1_MADDRS_H_UL: | |
6955 | gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6956 | cpu_gpr_d[r2], n, MODE_UL); | |
6957 | break; | |
6958 | case OPC2_32_RRR1_MADDRS_H_UU: | |
6959 | gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6960 | cpu_gpr_d[r2], n, MODE_UU); | |
6961 | break; | |
f678f671 BK |
6962 | default: |
6963 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
2e430e1c BK |
6964 | } |
6965 | } | |
6966 | ||
2db92a0c | 6967 | static void decode_rrr1_maddq_h(DisasContext *ctx) |
b00aa8ec BK |
6968 | { |
6969 | uint32_t op2; | |
6970 | uint32_t r1, r2, r3, r4, n; | |
6971 | TCGv temp, temp2; | |
6972 | ||
6973 | op2 = MASK_OP_RRR1_OP2(ctx->opcode); | |
6974 | r1 = MASK_OP_RRR1_S1(ctx->opcode); | |
6975 | r2 = MASK_OP_RRR1_S2(ctx->opcode); | |
6976 | r3 = MASK_OP_RRR1_S3(ctx->opcode); | |
6977 | r4 = MASK_OP_RRR1_D(ctx->opcode); | |
6978 | n = MASK_OP_RRR1_N(ctx->opcode); | |
6979 | ||
32f948af | 6980 | temp = tcg_temp_new(); |
b00aa8ec BK |
6981 | temp2 = tcg_temp_new(); |
6982 | ||
6983 | switch (op2) { | |
6984 | case OPC2_32_RRR1_MADD_Q_32: | |
6985 | gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
2db92a0c | 6986 | cpu_gpr_d[r2], n, 32); |
b00aa8ec BK |
6987 | break; |
6988 | case OPC2_32_RRR1_MADD_Q_64: | |
828066c7 BK |
6989 | CHECK_REG_PAIR(r4); |
6990 | CHECK_REG_PAIR(r3); | |
b00aa8ec BK |
6991 | gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
6992 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
2db92a0c | 6993 | n); |
b00aa8ec BK |
6994 | break; |
6995 | case OPC2_32_RRR1_MADD_Q_32_L: | |
6996 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); | |
6997 | gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
2db92a0c | 6998 | temp, n, 16); |
b00aa8ec BK |
6999 | break; |
7000 | case OPC2_32_RRR1_MADD_Q_64_L: | |
828066c7 BK |
7001 | CHECK_REG_PAIR(r4); |
7002 | CHECK_REG_PAIR(r3); | |
b00aa8ec BK |
7003 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); |
7004 | gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
7005 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, | |
2db92a0c | 7006 | n); |
b00aa8ec BK |
7007 | break; |
7008 | case OPC2_32_RRR1_MADD_Q_32_U: | |
7009 | tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); | |
7010 | gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
2db92a0c | 7011 | temp, n, 16); |
b00aa8ec BK |
7012 | break; |
7013 | case OPC2_32_RRR1_MADD_Q_64_U: | |
828066c7 BK |
7014 | CHECK_REG_PAIR(r4); |
7015 | CHECK_REG_PAIR(r3); | |
b00aa8ec BK |
7016 | tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); |
7017 | gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
7018 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, | |
2db92a0c | 7019 | n); |
b00aa8ec BK |
7020 | break; |
7021 | case OPC2_32_RRR1_MADD_Q_32_LL: | |
7022 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); | |
7023 | tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); | |
7024 | gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); | |
7025 | break; | |
7026 | case OPC2_32_RRR1_MADD_Q_64_LL: | |
828066c7 BK |
7027 | CHECK_REG_PAIR(r4); |
7028 | CHECK_REG_PAIR(r3); | |
b00aa8ec BK |
7029 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); |
7030 | tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); | |
7031 | gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
7032 | cpu_gpr_d[r3+1], temp, temp2, n); | |
7033 | break; | |
7034 | case OPC2_32_RRR1_MADD_Q_32_UU: | |
7035 | tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); | |
7036 | tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); | |
7037 | gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); | |
7038 | break; | |
7039 | case OPC2_32_RRR1_MADD_Q_64_UU: | |
828066c7 BK |
7040 | CHECK_REG_PAIR(r4); |
7041 | CHECK_REG_PAIR(r3); | |
b00aa8ec BK |
7042 | tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); |
7043 | tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); | |
7044 | gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
7045 | cpu_gpr_d[r3+1], temp, temp2, n); | |
7046 | break; | |
7047 | case OPC2_32_RRR1_MADDS_Q_32: | |
7048 | gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7049 | cpu_gpr_d[r2], n, 32); | |
7050 | break; | |
7051 | case OPC2_32_RRR1_MADDS_Q_64: | |
828066c7 BK |
7052 | CHECK_REG_PAIR(r4); |
7053 | CHECK_REG_PAIR(r3); | |
b00aa8ec BK |
7054 | gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7055 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
7056 | n); | |
7057 | break; | |
7058 | case OPC2_32_RRR1_MADDS_Q_32_L: | |
7059 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); | |
7060 | gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7061 | temp, n, 16); | |
7062 | break; | |
7063 | case OPC2_32_RRR1_MADDS_Q_64_L: | |
828066c7 BK |
7064 | CHECK_REG_PAIR(r4); |
7065 | CHECK_REG_PAIR(r3); | |
b00aa8ec BK |
7066 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); |
7067 | gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
7068 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, | |
7069 | n); | |
7070 | break; | |
7071 | case OPC2_32_RRR1_MADDS_Q_32_U: | |
7072 | tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); | |
7073 | gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7074 | temp, n, 16); | |
7075 | break; | |
7076 | case OPC2_32_RRR1_MADDS_Q_64_U: | |
828066c7 BK |
7077 | CHECK_REG_PAIR(r4); |
7078 | CHECK_REG_PAIR(r3); | |
b00aa8ec BK |
7079 | tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); |
7080 | gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
7081 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, | |
7082 | n); | |
7083 | break; | |
7084 | case OPC2_32_RRR1_MADDS_Q_32_LL: | |
7085 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); | |
7086 | tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); | |
7087 | gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); | |
7088 | break; | |
7089 | case OPC2_32_RRR1_MADDS_Q_64_LL: | |
828066c7 BK |
7090 | CHECK_REG_PAIR(r4); |
7091 | CHECK_REG_PAIR(r3); | |
b00aa8ec BK |
7092 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); |
7093 | tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); | |
7094 | gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
7095 | cpu_gpr_d[r3+1], temp, temp2, n); | |
7096 | break; | |
7097 | case OPC2_32_RRR1_MADDS_Q_32_UU: | |
7098 | tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); | |
7099 | tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); | |
7100 | gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); | |
7101 | break; | |
7102 | case OPC2_32_RRR1_MADDS_Q_64_UU: | |
828066c7 BK |
7103 | CHECK_REG_PAIR(r4); |
7104 | CHECK_REG_PAIR(r3); | |
b00aa8ec BK |
7105 | tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); |
7106 | tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); | |
7107 | gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
7108 | cpu_gpr_d[r3+1], temp, temp2, n); | |
7109 | break; | |
7110 | case OPC2_32_RRR1_MADDR_H_64_UL: | |
828066c7 | 7111 | CHECK_REG_PAIR(r3); |
b00aa8ec BK |
7112 | gen_maddr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1], |
7113 | cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); | |
7114 | break; | |
7115 | case OPC2_32_RRR1_MADDRS_H_64_UL: | |
828066c7 | 7116 | CHECK_REG_PAIR(r3); |
b00aa8ec BK |
7117 | gen_maddr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1], |
7118 | cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); | |
7119 | break; | |
7120 | case OPC2_32_RRR1_MADDR_Q_32_LL: | |
7121 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); | |
7122 | tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); | |
7123 | gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); | |
7124 | break; | |
7125 | case OPC2_32_RRR1_MADDR_Q_32_UU: | |
7126 | tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); | |
7127 | tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); | |
7128 | gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); | |
7129 | break; | |
7130 | case OPC2_32_RRR1_MADDRS_Q_32_LL: | |
7131 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); | |
7132 | tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); | |
7133 | gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); | |
7134 | break; | |
7135 | case OPC2_32_RRR1_MADDRS_Q_32_UU: | |
7136 | tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); | |
7137 | tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); | |
7138 | gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); | |
7139 | break; | |
f678f671 BK |
7140 | default: |
7141 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
b00aa8ec | 7142 | } |
b00aa8ec BK |
7143 | } |
7144 | ||
2db92a0c | 7145 | static void decode_rrr1_maddsu_h(DisasContext *ctx) |
bebe80fc BK |
7146 | { |
7147 | uint32_t op2; | |
7148 | uint32_t r1, r2, r3, r4, n; | |
7149 | ||
7150 | op2 = MASK_OP_RRR1_OP2(ctx->opcode); | |
7151 | r1 = MASK_OP_RRR1_S1(ctx->opcode); | |
7152 | r2 = MASK_OP_RRR1_S2(ctx->opcode); | |
7153 | r3 = MASK_OP_RRR1_S3(ctx->opcode); | |
7154 | r4 = MASK_OP_RRR1_D(ctx->opcode); | |
7155 | n = MASK_OP_RRR1_N(ctx->opcode); | |
7156 | ||
7157 | switch (op2) { | |
7158 | case OPC2_32_RRR1_MADDSU_H_32_LL: | |
828066c7 BK |
7159 | CHECK_REG_PAIR(r4); |
7160 | CHECK_REG_PAIR(r3); | |
bebe80fc BK |
7161 | gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7162 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); | |
7163 | break; | |
7164 | case OPC2_32_RRR1_MADDSU_H_32_LU: | |
828066c7 BK |
7165 | CHECK_REG_PAIR(r4); |
7166 | CHECK_REG_PAIR(r3); | |
bebe80fc BK |
7167 | gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7168 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); | |
7169 | break; | |
7170 | case OPC2_32_RRR1_MADDSU_H_32_UL: | |
828066c7 BK |
7171 | CHECK_REG_PAIR(r4); |
7172 | CHECK_REG_PAIR(r3); | |
bebe80fc BK |
7173 | gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7174 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); | |
7175 | break; | |
7176 | case OPC2_32_RRR1_MADDSU_H_32_UU: | |
828066c7 BK |
7177 | CHECK_REG_PAIR(r4); |
7178 | CHECK_REG_PAIR(r3); | |
bebe80fc BK |
7179 | gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7180 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); | |
7181 | break; | |
7182 | case OPC2_32_RRR1_MADDSUS_H_32_LL: | |
828066c7 BK |
7183 | CHECK_REG_PAIR(r4); |
7184 | CHECK_REG_PAIR(r3); | |
bebe80fc BK |
7185 | gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7186 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
7187 | n, MODE_LL); | |
7188 | break; | |
7189 | case OPC2_32_RRR1_MADDSUS_H_32_LU: | |
828066c7 BK |
7190 | CHECK_REG_PAIR(r4); |
7191 | CHECK_REG_PAIR(r3); | |
bebe80fc BK |
7192 | gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7193 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
7194 | n, MODE_LU); | |
7195 | break; | |
7196 | case OPC2_32_RRR1_MADDSUS_H_32_UL: | |
828066c7 BK |
7197 | CHECK_REG_PAIR(r4); |
7198 | CHECK_REG_PAIR(r3); | |
bebe80fc BK |
7199 | gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7200 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
7201 | n, MODE_UL); | |
7202 | break; | |
7203 | case OPC2_32_RRR1_MADDSUS_H_32_UU: | |
828066c7 BK |
7204 | CHECK_REG_PAIR(r4); |
7205 | CHECK_REG_PAIR(r3); | |
bebe80fc BK |
7206 | gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7207 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
7208 | n, MODE_UU); | |
7209 | break; | |
7210 | case OPC2_32_RRR1_MADDSUM_H_64_LL: | |
828066c7 BK |
7211 | CHECK_REG_PAIR(r4); |
7212 | CHECK_REG_PAIR(r3); | |
bebe80fc BK |
7213 | gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7214 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
7215 | n, MODE_LL); | |
7216 | break; | |
7217 | case OPC2_32_RRR1_MADDSUM_H_64_LU: | |
828066c7 BK |
7218 | CHECK_REG_PAIR(r4); |
7219 | CHECK_REG_PAIR(r3); | |
bebe80fc BK |
7220 | gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7221 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
7222 | n, MODE_LU); | |
7223 | break; | |
7224 | case OPC2_32_RRR1_MADDSUM_H_64_UL: | |
828066c7 BK |
7225 | CHECK_REG_PAIR(r4); |
7226 | CHECK_REG_PAIR(r3); | |
bebe80fc BK |
7227 | gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7228 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
7229 | n, MODE_UL); | |
7230 | break; | |
7231 | case OPC2_32_RRR1_MADDSUM_H_64_UU: | |
828066c7 BK |
7232 | CHECK_REG_PAIR(r4); |
7233 | CHECK_REG_PAIR(r3); | |
bebe80fc BK |
7234 | gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7235 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
7236 | n, MODE_UU); | |
7237 | break; | |
7238 | case OPC2_32_RRR1_MADDSUMS_H_64_LL: | |
828066c7 BK |
7239 | CHECK_REG_PAIR(r4); |
7240 | CHECK_REG_PAIR(r3); | |
bebe80fc BK |
7241 | gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7242 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
7243 | n, MODE_LL); | |
7244 | break; | |
7245 | case OPC2_32_RRR1_MADDSUMS_H_64_LU: | |
828066c7 BK |
7246 | CHECK_REG_PAIR(r4); |
7247 | CHECK_REG_PAIR(r3); | |
bebe80fc BK |
7248 | gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7249 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
7250 | n, MODE_LU); | |
7251 | break; | |
7252 | case OPC2_32_RRR1_MADDSUMS_H_64_UL: | |
828066c7 BK |
7253 | CHECK_REG_PAIR(r4); |
7254 | CHECK_REG_PAIR(r3); | |
bebe80fc BK |
7255 | gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7256 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
7257 | n, MODE_UL); | |
7258 | break; | |
7259 | case OPC2_32_RRR1_MADDSUMS_H_64_UU: | |
828066c7 BK |
7260 | CHECK_REG_PAIR(r4); |
7261 | CHECK_REG_PAIR(r3); | |
bebe80fc BK |
7262 | gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7263 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
7264 | n, MODE_UU); | |
7265 | break; | |
7266 | case OPC2_32_RRR1_MADDSUR_H_16_LL: | |
7267 | gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7268 | cpu_gpr_d[r2], n, MODE_LL); | |
7269 | break; | |
7270 | case OPC2_32_RRR1_MADDSUR_H_16_LU: | |
7271 | gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7272 | cpu_gpr_d[r2], n, MODE_LU); | |
7273 | break; | |
7274 | case OPC2_32_RRR1_MADDSUR_H_16_UL: | |
7275 | gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7276 | cpu_gpr_d[r2], n, MODE_UL); | |
7277 | break; | |
7278 | case OPC2_32_RRR1_MADDSUR_H_16_UU: | |
7279 | gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7280 | cpu_gpr_d[r2], n, MODE_UU); | |
7281 | break; | |
7282 | case OPC2_32_RRR1_MADDSURS_H_16_LL: | |
7283 | gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7284 | cpu_gpr_d[r2], n, MODE_LL); | |
7285 | break; | |
7286 | case OPC2_32_RRR1_MADDSURS_H_16_LU: | |
7287 | gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7288 | cpu_gpr_d[r2], n, MODE_LU); | |
7289 | break; | |
7290 | case OPC2_32_RRR1_MADDSURS_H_16_UL: | |
7291 | gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7292 | cpu_gpr_d[r2], n, MODE_UL); | |
7293 | break; | |
7294 | case OPC2_32_RRR1_MADDSURS_H_16_UU: | |
7295 | gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7296 | cpu_gpr_d[r2], n, MODE_UU); | |
7297 | break; | |
f678f671 BK |
7298 | default: |
7299 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
bebe80fc BK |
7300 | } |
7301 | } | |
7302 | ||
2db92a0c | 7303 | static void decode_rrr1_msub(DisasContext *ctx) |
f4aef476 BK |
7304 | { |
7305 | uint32_t op2; | |
7306 | uint32_t r1, r2, r3, r4, n; | |
7307 | ||
7308 | op2 = MASK_OP_RRR1_OP2(ctx->opcode); | |
7309 | r1 = MASK_OP_RRR1_S1(ctx->opcode); | |
7310 | r2 = MASK_OP_RRR1_S2(ctx->opcode); | |
7311 | r3 = MASK_OP_RRR1_S3(ctx->opcode); | |
7312 | r4 = MASK_OP_RRR1_D(ctx->opcode); | |
7313 | n = MASK_OP_RRR1_N(ctx->opcode); | |
7314 | ||
7315 | switch (op2) { | |
7316 | case OPC2_32_RRR1_MSUB_H_LL: | |
828066c7 BK |
7317 | CHECK_REG_PAIR(r4); |
7318 | CHECK_REG_PAIR(r3); | |
f4aef476 BK |
7319 | gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7320 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); | |
7321 | break; | |
7322 | case OPC2_32_RRR1_MSUB_H_LU: | |
828066c7 BK |
7323 | CHECK_REG_PAIR(r4); |
7324 | CHECK_REG_PAIR(r3); | |
f4aef476 BK |
7325 | gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7326 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); | |
7327 | break; | |
7328 | case OPC2_32_RRR1_MSUB_H_UL: | |
828066c7 BK |
7329 | CHECK_REG_PAIR(r4); |
7330 | CHECK_REG_PAIR(r3); | |
f4aef476 BK |
7331 | gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7332 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); | |
7333 | break; | |
7334 | case OPC2_32_RRR1_MSUB_H_UU: | |
828066c7 BK |
7335 | CHECK_REG_PAIR(r4); |
7336 | CHECK_REG_PAIR(r3); | |
f4aef476 BK |
7337 | gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7338 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); | |
7339 | break; | |
7340 | case OPC2_32_RRR1_MSUBS_H_LL: | |
828066c7 BK |
7341 | CHECK_REG_PAIR(r4); |
7342 | CHECK_REG_PAIR(r3); | |
f4aef476 BK |
7343 | gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7344 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); | |
7345 | break; | |
7346 | case OPC2_32_RRR1_MSUBS_H_LU: | |
828066c7 BK |
7347 | CHECK_REG_PAIR(r4); |
7348 | CHECK_REG_PAIR(r3); | |
f4aef476 BK |
7349 | gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7350 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); | |
7351 | break; | |
7352 | case OPC2_32_RRR1_MSUBS_H_UL: | |
828066c7 BK |
7353 | CHECK_REG_PAIR(r4); |
7354 | CHECK_REG_PAIR(r3); | |
f4aef476 BK |
7355 | gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7356 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); | |
7357 | break; | |
7358 | case OPC2_32_RRR1_MSUBS_H_UU: | |
828066c7 BK |
7359 | CHECK_REG_PAIR(r4); |
7360 | CHECK_REG_PAIR(r3); | |
f4aef476 BK |
7361 | gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7362 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); | |
7363 | break; | |
7364 | case OPC2_32_RRR1_MSUBM_H_LL: | |
828066c7 BK |
7365 | CHECK_REG_PAIR(r4); |
7366 | CHECK_REG_PAIR(r3); | |
f4aef476 BK |
7367 | gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7368 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); | |
7369 | break; | |
7370 | case OPC2_32_RRR1_MSUBM_H_LU: | |
828066c7 BK |
7371 | CHECK_REG_PAIR(r4); |
7372 | CHECK_REG_PAIR(r3); | |
f4aef476 BK |
7373 | gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7374 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); | |
7375 | break; | |
7376 | case OPC2_32_RRR1_MSUBM_H_UL: | |
828066c7 BK |
7377 | CHECK_REG_PAIR(r4); |
7378 | CHECK_REG_PAIR(r3); | |
f4aef476 BK |
7379 | gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7380 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); | |
7381 | break; | |
7382 | case OPC2_32_RRR1_MSUBM_H_UU: | |
828066c7 BK |
7383 | CHECK_REG_PAIR(r4); |
7384 | CHECK_REG_PAIR(r3); | |
f4aef476 BK |
7385 | gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7386 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); | |
7387 | break; | |
7388 | case OPC2_32_RRR1_MSUBMS_H_LL: | |
828066c7 BK |
7389 | CHECK_REG_PAIR(r4); |
7390 | CHECK_REG_PAIR(r3); | |
f4aef476 BK |
7391 | gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7392 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); | |
7393 | break; | |
7394 | case OPC2_32_RRR1_MSUBMS_H_LU: | |
828066c7 BK |
7395 | CHECK_REG_PAIR(r4); |
7396 | CHECK_REG_PAIR(r3); | |
f4aef476 BK |
7397 | gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7398 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); | |
7399 | break; | |
7400 | case OPC2_32_RRR1_MSUBMS_H_UL: | |
828066c7 BK |
7401 | CHECK_REG_PAIR(r4); |
7402 | CHECK_REG_PAIR(r3); | |
f4aef476 BK |
7403 | gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7404 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); | |
7405 | break; | |
7406 | case OPC2_32_RRR1_MSUBMS_H_UU: | |
828066c7 BK |
7407 | CHECK_REG_PAIR(r4); |
7408 | CHECK_REG_PAIR(r3); | |
f4aef476 BK |
7409 | gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7410 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); | |
7411 | break; | |
7412 | case OPC2_32_RRR1_MSUBR_H_LL: | |
7413 | gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7414 | cpu_gpr_d[r2], n, MODE_LL); | |
7415 | break; | |
7416 | case OPC2_32_RRR1_MSUBR_H_LU: | |
7417 | gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7418 | cpu_gpr_d[r2], n, MODE_LU); | |
7419 | break; | |
7420 | case OPC2_32_RRR1_MSUBR_H_UL: | |
7421 | gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7422 | cpu_gpr_d[r2], n, MODE_UL); | |
7423 | break; | |
7424 | case OPC2_32_RRR1_MSUBR_H_UU: | |
7425 | gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7426 | cpu_gpr_d[r2], n, MODE_UU); | |
7427 | break; | |
7428 | case OPC2_32_RRR1_MSUBRS_H_LL: | |
7429 | gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7430 | cpu_gpr_d[r2], n, MODE_LL); | |
7431 | break; | |
7432 | case OPC2_32_RRR1_MSUBRS_H_LU: | |
7433 | gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7434 | cpu_gpr_d[r2], n, MODE_LU); | |
7435 | break; | |
7436 | case OPC2_32_RRR1_MSUBRS_H_UL: | |
7437 | gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7438 | cpu_gpr_d[r2], n, MODE_UL); | |
7439 | break; | |
7440 | case OPC2_32_RRR1_MSUBRS_H_UU: | |
7441 | gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7442 | cpu_gpr_d[r2], n, MODE_UU); | |
7443 | break; | |
f678f671 BK |
7444 | default: |
7445 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
f4aef476 BK |
7446 | } |
7447 | } | |
7448 | ||
2db92a0c | 7449 | static void decode_rrr1_msubq_h(DisasContext *ctx) |
62e47b2e BK |
7450 | { |
7451 | uint32_t op2; | |
7452 | uint32_t r1, r2, r3, r4, n; | |
7453 | TCGv temp, temp2; | |
7454 | ||
7455 | op2 = MASK_OP_RRR1_OP2(ctx->opcode); | |
7456 | r1 = MASK_OP_RRR1_S1(ctx->opcode); | |
7457 | r2 = MASK_OP_RRR1_S2(ctx->opcode); | |
7458 | r3 = MASK_OP_RRR1_S3(ctx->opcode); | |
7459 | r4 = MASK_OP_RRR1_D(ctx->opcode); | |
7460 | n = MASK_OP_RRR1_N(ctx->opcode); | |
7461 | ||
32f948af | 7462 | temp = tcg_temp_new(); |
62e47b2e BK |
7463 | temp2 = tcg_temp_new(); |
7464 | ||
7465 | switch (op2) { | |
7466 | case OPC2_32_RRR1_MSUB_Q_32: | |
7467 | gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
2db92a0c | 7468 | cpu_gpr_d[r2], n, 32); |
62e47b2e BK |
7469 | break; |
7470 | case OPC2_32_RRR1_MSUB_Q_64: | |
828066c7 BK |
7471 | CHECK_REG_PAIR(r4); |
7472 | CHECK_REG_PAIR(r3); | |
62e47b2e BK |
7473 | gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7474 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
2db92a0c | 7475 | n); |
62e47b2e BK |
7476 | break; |
7477 | case OPC2_32_RRR1_MSUB_Q_32_L: | |
7478 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); | |
7479 | gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
2db92a0c | 7480 | temp, n, 16); |
62e47b2e BK |
7481 | break; |
7482 | case OPC2_32_RRR1_MSUB_Q_64_L: | |
828066c7 BK |
7483 | CHECK_REG_PAIR(r4); |
7484 | CHECK_REG_PAIR(r3); | |
62e47b2e BK |
7485 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); |
7486 | gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
7487 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, | |
2db92a0c | 7488 | n); |
62e47b2e BK |
7489 | break; |
7490 | case OPC2_32_RRR1_MSUB_Q_32_U: | |
7491 | tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); | |
7492 | gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
2db92a0c | 7493 | temp, n, 16); |
62e47b2e BK |
7494 | break; |
7495 | case OPC2_32_RRR1_MSUB_Q_64_U: | |
828066c7 BK |
7496 | CHECK_REG_PAIR(r4); |
7497 | CHECK_REG_PAIR(r3); | |
62e47b2e BK |
7498 | tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); |
7499 | gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
7500 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, | |
2db92a0c | 7501 | n); |
62e47b2e BK |
7502 | break; |
7503 | case OPC2_32_RRR1_MSUB_Q_32_LL: | |
7504 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); | |
7505 | tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); | |
7506 | gen_m16sub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); | |
7507 | break; | |
7508 | case OPC2_32_RRR1_MSUB_Q_64_LL: | |
828066c7 BK |
7509 | CHECK_REG_PAIR(r4); |
7510 | CHECK_REG_PAIR(r3); | |
62e47b2e BK |
7511 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); |
7512 | tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); | |
7513 | gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
7514 | cpu_gpr_d[r3+1], temp, temp2, n); | |
7515 | break; | |
7516 | case OPC2_32_RRR1_MSUB_Q_32_UU: | |
7517 | tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); | |
7518 | tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); | |
7519 | gen_m16sub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); | |
7520 | break; | |
7521 | case OPC2_32_RRR1_MSUB_Q_64_UU: | |
828066c7 BK |
7522 | CHECK_REG_PAIR(r4); |
7523 | CHECK_REG_PAIR(r3); | |
62e47b2e BK |
7524 | tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); |
7525 | tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); | |
7526 | gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
7527 | cpu_gpr_d[r3+1], temp, temp2, n); | |
7528 | break; | |
7529 | case OPC2_32_RRR1_MSUBS_Q_32: | |
7530 | gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7531 | cpu_gpr_d[r2], n, 32); | |
7532 | break; | |
7533 | case OPC2_32_RRR1_MSUBS_Q_64: | |
828066c7 BK |
7534 | CHECK_REG_PAIR(r4); |
7535 | CHECK_REG_PAIR(r3); | |
62e47b2e BK |
7536 | gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7537 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
7538 | n); | |
7539 | break; | |
7540 | case OPC2_32_RRR1_MSUBS_Q_32_L: | |
7541 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); | |
7542 | gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7543 | temp, n, 16); | |
7544 | break; | |
7545 | case OPC2_32_RRR1_MSUBS_Q_64_L: | |
828066c7 BK |
7546 | CHECK_REG_PAIR(r4); |
7547 | CHECK_REG_PAIR(r3); | |
62e47b2e BK |
7548 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); |
7549 | gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
7550 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, | |
7551 | n); | |
7552 | break; | |
7553 | case OPC2_32_RRR1_MSUBS_Q_32_U: | |
7554 | tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); | |
7555 | gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7556 | temp, n, 16); | |
7557 | break; | |
7558 | case OPC2_32_RRR1_MSUBS_Q_64_U: | |
828066c7 BK |
7559 | CHECK_REG_PAIR(r4); |
7560 | CHECK_REG_PAIR(r3); | |
62e47b2e BK |
7561 | tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); |
7562 | gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
7563 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, | |
7564 | n); | |
7565 | break; | |
7566 | case OPC2_32_RRR1_MSUBS_Q_32_LL: | |
7567 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); | |
7568 | tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); | |
7569 | gen_m16subs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); | |
7570 | break; | |
7571 | case OPC2_32_RRR1_MSUBS_Q_64_LL: | |
828066c7 BK |
7572 | CHECK_REG_PAIR(r4); |
7573 | CHECK_REG_PAIR(r3); | |
62e47b2e BK |
7574 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); |
7575 | tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); | |
7576 | gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
7577 | cpu_gpr_d[r3+1], temp, temp2, n); | |
7578 | break; | |
7579 | case OPC2_32_RRR1_MSUBS_Q_32_UU: | |
7580 | tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); | |
7581 | tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); | |
7582 | gen_m16subs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); | |
7583 | break; | |
7584 | case OPC2_32_RRR1_MSUBS_Q_64_UU: | |
828066c7 BK |
7585 | CHECK_REG_PAIR(r4); |
7586 | CHECK_REG_PAIR(r3); | |
62e47b2e BK |
7587 | tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); |
7588 | tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); | |
7589 | gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
7590 | cpu_gpr_d[r3+1], temp, temp2, n); | |
7591 | break; | |
7592 | case OPC2_32_RRR1_MSUBR_H_64_UL: | |
828066c7 | 7593 | CHECK_REG_PAIR(r3); |
62e47b2e BK |
7594 | gen_msubr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1], |
7595 | cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); | |
7596 | break; | |
7597 | case OPC2_32_RRR1_MSUBRS_H_64_UL: | |
828066c7 | 7598 | CHECK_REG_PAIR(r3); |
62e47b2e BK |
7599 | gen_msubr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1], |
7600 | cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); | |
7601 | break; | |
7602 | case OPC2_32_RRR1_MSUBR_Q_32_LL: | |
7603 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); | |
7604 | tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); | |
7605 | gen_msubr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); | |
7606 | break; | |
7607 | case OPC2_32_RRR1_MSUBR_Q_32_UU: | |
7608 | tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); | |
7609 | tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); | |
7610 | gen_msubr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); | |
7611 | break; | |
7612 | case OPC2_32_RRR1_MSUBRS_Q_32_LL: | |
7613 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); | |
7614 | tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); | |
7615 | gen_msubrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); | |
7616 | break; | |
7617 | case OPC2_32_RRR1_MSUBRS_Q_32_UU: | |
7618 | tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); | |
7619 | tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); | |
7620 | gen_msubrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); | |
7621 | break; | |
f678f671 BK |
7622 | default: |
7623 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
62e47b2e | 7624 | } |
62e47b2e BK |
7625 | } |
7626 | ||
2db92a0c | 7627 | static void decode_rrr1_msubad_h(DisasContext *ctx) |
068fac77 BK |
7628 | { |
7629 | uint32_t op2; | |
7630 | uint32_t r1, r2, r3, r4, n; | |
7631 | ||
7632 | op2 = MASK_OP_RRR1_OP2(ctx->opcode); | |
7633 | r1 = MASK_OP_RRR1_S1(ctx->opcode); | |
7634 | r2 = MASK_OP_RRR1_S2(ctx->opcode); | |
7635 | r3 = MASK_OP_RRR1_S3(ctx->opcode); | |
7636 | r4 = MASK_OP_RRR1_D(ctx->opcode); | |
7637 | n = MASK_OP_RRR1_N(ctx->opcode); | |
7638 | ||
7639 | switch (op2) { | |
7640 | case OPC2_32_RRR1_MSUBAD_H_32_LL: | |
828066c7 BK |
7641 | CHECK_REG_PAIR(r4); |
7642 | CHECK_REG_PAIR(r3); | |
068fac77 BK |
7643 | gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7644 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); | |
7645 | break; | |
7646 | case OPC2_32_RRR1_MSUBAD_H_32_LU: | |
828066c7 BK |
7647 | CHECK_REG_PAIR(r4); |
7648 | CHECK_REG_PAIR(r3); | |
068fac77 BK |
7649 | gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7650 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); | |
7651 | break; | |
7652 | case OPC2_32_RRR1_MSUBAD_H_32_UL: | |
828066c7 BK |
7653 | CHECK_REG_PAIR(r4); |
7654 | CHECK_REG_PAIR(r3); | |
068fac77 BK |
7655 | gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7656 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); | |
7657 | break; | |
7658 | case OPC2_32_RRR1_MSUBAD_H_32_UU: | |
828066c7 BK |
7659 | CHECK_REG_PAIR(r4); |
7660 | CHECK_REG_PAIR(r3); | |
068fac77 BK |
7661 | gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7662 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); | |
7663 | break; | |
7664 | case OPC2_32_RRR1_MSUBADS_H_32_LL: | |
828066c7 BK |
7665 | CHECK_REG_PAIR(r4); |
7666 | CHECK_REG_PAIR(r3); | |
068fac77 BK |
7667 | gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7668 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
7669 | n, MODE_LL); | |
7670 | break; | |
7671 | case OPC2_32_RRR1_MSUBADS_H_32_LU: | |
828066c7 BK |
7672 | CHECK_REG_PAIR(r4); |
7673 | CHECK_REG_PAIR(r3); | |
068fac77 BK |
7674 | gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7675 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
7676 | n, MODE_LU); | |
7677 | break; | |
7678 | case OPC2_32_RRR1_MSUBADS_H_32_UL: | |
828066c7 BK |
7679 | CHECK_REG_PAIR(r4); |
7680 | CHECK_REG_PAIR(r3); | |
068fac77 BK |
7681 | gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7682 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
7683 | n, MODE_UL); | |
7684 | break; | |
7685 | case OPC2_32_RRR1_MSUBADS_H_32_UU: | |
828066c7 BK |
7686 | CHECK_REG_PAIR(r4); |
7687 | CHECK_REG_PAIR(r3); | |
068fac77 BK |
7688 | gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7689 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
7690 | n, MODE_UU); | |
7691 | break; | |
7692 | case OPC2_32_RRR1_MSUBADM_H_64_LL: | |
828066c7 BK |
7693 | CHECK_REG_PAIR(r4); |
7694 | CHECK_REG_PAIR(r3); | |
068fac77 BK |
7695 | gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7696 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
7697 | n, MODE_LL); | |
7698 | break; | |
7699 | case OPC2_32_RRR1_MSUBADM_H_64_LU: | |
828066c7 BK |
7700 | CHECK_REG_PAIR(r4); |
7701 | CHECK_REG_PAIR(r3); | |
068fac77 BK |
7702 | gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7703 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
7704 | n, MODE_LU); | |
7705 | break; | |
7706 | case OPC2_32_RRR1_MSUBADM_H_64_UL: | |
828066c7 BK |
7707 | CHECK_REG_PAIR(r4); |
7708 | CHECK_REG_PAIR(r3); | |
068fac77 BK |
7709 | gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7710 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
7711 | n, MODE_UL); | |
7712 | break; | |
7713 | case OPC2_32_RRR1_MSUBADM_H_64_UU: | |
828066c7 BK |
7714 | CHECK_REG_PAIR(r4); |
7715 | CHECK_REG_PAIR(r3); | |
068fac77 BK |
7716 | gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7717 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
7718 | n, MODE_UU); | |
7719 | break; | |
7720 | case OPC2_32_RRR1_MSUBADMS_H_64_LL: | |
828066c7 BK |
7721 | CHECK_REG_PAIR(r4); |
7722 | CHECK_REG_PAIR(r3); | |
068fac77 BK |
7723 | gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7724 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
7725 | n, MODE_LL); | |
7726 | break; | |
7727 | case OPC2_32_RRR1_MSUBADMS_H_64_LU: | |
828066c7 BK |
7728 | CHECK_REG_PAIR(r4); |
7729 | CHECK_REG_PAIR(r3); | |
068fac77 BK |
7730 | gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7731 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
7732 | n, MODE_LU); | |
7733 | break; | |
7734 | case OPC2_32_RRR1_MSUBADMS_H_64_UL: | |
828066c7 BK |
7735 | CHECK_REG_PAIR(r4); |
7736 | CHECK_REG_PAIR(r3); | |
068fac77 BK |
7737 | gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7738 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
7739 | n, MODE_UL); | |
7740 | break; | |
7741 | case OPC2_32_RRR1_MSUBADMS_H_64_UU: | |
828066c7 BK |
7742 | CHECK_REG_PAIR(r4); |
7743 | CHECK_REG_PAIR(r3); | |
068fac77 BK |
7744 | gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7745 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
7746 | n, MODE_UU); | |
7747 | break; | |
7748 | case OPC2_32_RRR1_MSUBADR_H_16_LL: | |
7749 | gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7750 | cpu_gpr_d[r2], n, MODE_LL); | |
7751 | break; | |
7752 | case OPC2_32_RRR1_MSUBADR_H_16_LU: | |
7753 | gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7754 | cpu_gpr_d[r2], n, MODE_LU); | |
7755 | break; | |
7756 | case OPC2_32_RRR1_MSUBADR_H_16_UL: | |
7757 | gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7758 | cpu_gpr_d[r2], n, MODE_UL); | |
7759 | break; | |
7760 | case OPC2_32_RRR1_MSUBADR_H_16_UU: | |
7761 | gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7762 | cpu_gpr_d[r2], n, MODE_UU); | |
7763 | break; | |
7764 | case OPC2_32_RRR1_MSUBADRS_H_16_LL: | |
7765 | gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7766 | cpu_gpr_d[r2], n, MODE_LL); | |
7767 | break; | |
7768 | case OPC2_32_RRR1_MSUBADRS_H_16_LU: | |
7769 | gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7770 | cpu_gpr_d[r2], n, MODE_LU); | |
7771 | break; | |
7772 | case OPC2_32_RRR1_MSUBADRS_H_16_UL: | |
7773 | gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7774 | cpu_gpr_d[r2], n, MODE_UL); | |
7775 | break; | |
7776 | case OPC2_32_RRR1_MSUBADRS_H_16_UU: | |
7777 | gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7778 | cpu_gpr_d[r2], n, MODE_UU); | |
7779 | break; | |
f678f671 BK |
7780 | default: |
7781 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
068fac77 BK |
7782 | } |
7783 | } | |
7784 | ||
4d108fe3 | 7785 | /* RRRR format */ |
2db92a0c | 7786 | static void decode_rrrr_extract_insert(DisasContext *ctx) |
4d108fe3 BK |
7787 | { |
7788 | uint32_t op2; | |
7789 | int r1, r2, r3, r4; | |
7790 | TCGv tmp_width, tmp_pos; | |
7791 | ||
7792 | r1 = MASK_OP_RRRR_S1(ctx->opcode); | |
7793 | r2 = MASK_OP_RRRR_S2(ctx->opcode); | |
7794 | r3 = MASK_OP_RRRR_S3(ctx->opcode); | |
7795 | r4 = MASK_OP_RRRR_D(ctx->opcode); | |
7796 | op2 = MASK_OP_RRRR_OP2(ctx->opcode); | |
7797 | ||
7798 | tmp_pos = tcg_temp_new(); | |
7799 | tmp_width = tcg_temp_new(); | |
7800 | ||
7801 | switch (op2) { | |
7802 | case OPC2_32_RRRR_DEXTR: | |
7803 | tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f); | |
7804 | if (r1 == r2) { | |
7805 | tcg_gen_rotl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos); | |
7806 | } else { | |
a4d5d153 BK |
7807 | TCGv msw = tcg_temp_new(); |
7808 | TCGv zero = tcg_constant_tl(0); | |
4d108fe3 | 7809 | tcg_gen_shl_tl(tmp_width, cpu_gpr_d[r1], tmp_pos); |
a4d5d153 BK |
7810 | tcg_gen_subfi_tl(msw, 32, tmp_pos); |
7811 | tcg_gen_shr_tl(msw, cpu_gpr_d[r2], msw); | |
7812 | /* | |
7813 | * if pos == 0, then we do cpu_gpr_d[r2] << 32, which is undefined | |
7814 | * behaviour. So check that case here and set the low bits to zero | |
7815 | * which effectivly returns cpu_gpr_d[r1] | |
7816 | */ | |
7817 | tcg_gen_movcond_tl(TCG_COND_EQ, msw, tmp_pos, zero, zero, msw); | |
7818 | tcg_gen_or_tl(cpu_gpr_d[r4], tmp_width, msw); | |
4d108fe3 BK |
7819 | } |
7820 | break; | |
7821 | case OPC2_32_RRRR_EXTR: | |
7822 | case OPC2_32_RRRR_EXTR_U: | |
828066c7 | 7823 | CHECK_REG_PAIR(r3); |
4d108fe3 BK |
7824 | tcg_gen_andi_tl(tmp_width, cpu_gpr_d[r3+1], 0x1f); |
7825 | tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f); | |
7826 | tcg_gen_add_tl(tmp_pos, tmp_pos, tmp_width); | |
7827 | tcg_gen_subfi_tl(tmp_pos, 32, tmp_pos); | |
7828 | tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos); | |
7829 | tcg_gen_subfi_tl(tmp_width, 32, tmp_width); | |
7830 | if (op2 == OPC2_32_RRRR_EXTR) { | |
7831 | tcg_gen_sar_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], tmp_width); | |
7832 | } else { | |
7833 | tcg_gen_shr_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], tmp_width); | |
7834 | } | |
7835 | break; | |
7836 | case OPC2_32_RRRR_INSERT: | |
828066c7 | 7837 | CHECK_REG_PAIR(r3); |
4d108fe3 BK |
7838 | tcg_gen_andi_tl(tmp_width, cpu_gpr_d[r3+1], 0x1f); |
7839 | tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f); | |
7840 | gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], tmp_width, | |
7841 | tmp_pos); | |
7842 | break; | |
f678f671 BK |
7843 | default: |
7844 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
4d108fe3 | 7845 | } |
4d108fe3 BK |
7846 | } |
7847 | ||
eb989d25 | 7848 | /* RRRW format */ |
2db92a0c | 7849 | static void decode_rrrw_extract_insert(DisasContext *ctx) |
eb989d25 BK |
7850 | { |
7851 | uint32_t op2; | |
7852 | int r1, r2, r3, r4; | |
7853 | int32_t width; | |
7854 | ||
7855 | TCGv temp, temp2; | |
7856 | ||
7857 | op2 = MASK_OP_RRRW_OP2(ctx->opcode); | |
7858 | r1 = MASK_OP_RRRW_S1(ctx->opcode); | |
7859 | r2 = MASK_OP_RRRW_S2(ctx->opcode); | |
7860 | r3 = MASK_OP_RRRW_S3(ctx->opcode); | |
7861 | r4 = MASK_OP_RRRW_D(ctx->opcode); | |
7862 | width = MASK_OP_RRRW_WIDTH(ctx->opcode); | |
7863 | ||
7864 | temp = tcg_temp_new(); | |
7865 | ||
7866 | switch (op2) { | |
7867 | case OPC2_32_RRRW_EXTR: | |
7868 | tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f); | |
7869 | tcg_gen_addi_tl(temp, temp, width); | |
7870 | tcg_gen_subfi_tl(temp, 32, temp); | |
7871 | tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp); | |
7872 | tcg_gen_sari_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], 32 - width); | |
7873 | break; | |
7874 | case OPC2_32_RRRW_EXTR_U: | |
7875 | if (width == 0) { | |
7876 | tcg_gen_movi_tl(cpu_gpr_d[r4], 0); | |
7877 | } else { | |
7878 | tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f); | |
7879 | tcg_gen_shr_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp); | |
7880 | tcg_gen_andi_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], ~0u >> (32-width)); | |
7881 | } | |
7882 | break; | |
7883 | case OPC2_32_RRRW_IMASK: | |
7884 | temp2 = tcg_temp_new(); | |
6991777e | 7885 | CHECK_REG_PAIR(r4); |
eb989d25 BK |
7886 | tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f); |
7887 | tcg_gen_movi_tl(temp2, (1 << width) - 1); | |
7888 | tcg_gen_shl_tl(temp2, temp2, temp); | |
7889 | tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r2], temp); | |
7890 | tcg_gen_mov_tl(cpu_gpr_d[r4+1], temp2); | |
eb989d25 BK |
7891 | break; |
7892 | case OPC2_32_RRRW_INSERT: | |
7893 | temp2 = tcg_temp_new(); | |
7894 | ||
7895 | tcg_gen_movi_tl(temp, width); | |
7896 | tcg_gen_andi_tl(temp2, cpu_gpr_d[r3], 0x1f); | |
7897 | gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], temp, temp2); | |
eb989d25 | 7898 | break; |
f678f671 BK |
7899 | default: |
7900 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
eb989d25 | 7901 | } |
eb989d25 BK |
7902 | } |
7903 | ||
b724b012 | 7904 | /* SYS Format*/ |
2db92a0c | 7905 | static void decode_sys_interrupts(DisasContext *ctx) |
b724b012 BK |
7906 | { |
7907 | uint32_t op2; | |
bc3551c4 | 7908 | uint32_t r1; |
b724b012 BK |
7909 | TCGLabel *l1; |
7910 | TCGv tmp; | |
7911 | ||
7912 | op2 = MASK_OP_SYS_OP2(ctx->opcode); | |
bc3551c4 | 7913 | r1 = MASK_OP_SYS_S1D(ctx->opcode); |
b724b012 BK |
7914 | |
7915 | switch (op2) { | |
7916 | case OPC2_32_SYS_DEBUG: | |
7917 | /* raise EXCP_DEBUG */ | |
7918 | break; | |
7919 | case OPC2_32_SYS_DISABLE: | |
57b9c589 BK |
7920 | if (ctx->priv == TRICORE_PRIV_SM || ctx->priv == TRICORE_PRIV_UM1) { |
7921 | tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~ctx->icr_ie_mask); | |
7922 | } else { | |
7923 | generate_trap(ctx, TRAPC_PROT, TIN1_PRIV); | |
7924 | } | |
b724b012 | 7925 | break; |
0b9f9b63 BK |
7926 | case OPC2_32_SYS_DISABLE_D: |
7927 | if (has_feature(ctx, TRICORE_FEATURE_16)) { | |
57b9c589 BK |
7928 | if (ctx->priv == TRICORE_PRIV_SM || ctx->priv == TRICORE_PRIV_UM1) { |
7929 | tcg_gen_extract_tl(cpu_gpr_d[r1], cpu_ICR, | |
7930 | ctx->icr_ie_offset, 1); | |
7931 | tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~ctx->icr_ie_mask); | |
7932 | } else { | |
7933 | generate_trap(ctx, TRAPC_PROT, TIN1_PRIV); | |
7934 | } | |
0b9f9b63 BK |
7935 | } else { |
7936 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
7937 | } | |
b724b012 BK |
7938 | case OPC2_32_SYS_DSYNC: |
7939 | break; | |
7940 | case OPC2_32_SYS_ENABLE: | |
57b9c589 BK |
7941 | if (ctx->priv == TRICORE_PRIV_SM || ctx->priv == TRICORE_PRIV_UM1) { |
7942 | tcg_gen_ori_tl(cpu_ICR, cpu_ICR, ctx->icr_ie_mask); | |
7943 | ctx->base.is_jmp = DISAS_EXIT_UPDATE; | |
7944 | } else { | |
7945 | generate_trap(ctx, TRAPC_PROT, TIN1_PRIV); | |
7946 | } | |
b724b012 BK |
7947 | break; |
7948 | case OPC2_32_SYS_ISYNC: | |
7949 | break; | |
7950 | case OPC2_32_SYS_NOP: | |
7951 | break; | |
7952 | case OPC2_32_SYS_RET: | |
7953 | gen_compute_branch(ctx, op2, 0, 0, 0, 0); | |
7954 | break; | |
0e045f43 BK |
7955 | case OPC2_32_SYS_FRET: |
7956 | gen_fret(ctx); | |
7957 | break; | |
b724b012 | 7958 | case OPC2_32_SYS_RFE: |
ad75a51e | 7959 | gen_helper_rfe(tcg_env); |
1706e04f | 7960 | ctx->base.is_jmp = DISAS_EXIT; |
b724b012 BK |
7961 | break; |
7962 | case OPC2_32_SYS_RFM: | |
878d1b6a | 7963 | if (ctx->priv == TRICORE_PRIV_SM) { |
b724b012 BK |
7964 | tmp = tcg_temp_new(); |
7965 | l1 = gen_new_label(); | |
7966 | ||
ad75a51e | 7967 | tcg_gen_ld32u_tl(tmp, tcg_env, offsetof(CPUTriCoreState, DBGSR)); |
b724b012 BK |
7968 | tcg_gen_andi_tl(tmp, tmp, MASK_DBGSR_DE); |
7969 | tcg_gen_brcondi_tl(TCG_COND_NE, tmp, 1, l1); | |
ad75a51e | 7970 | gen_helper_rfm(tcg_env); |
b724b012 | 7971 | gen_set_label(l1); |
1706e04f | 7972 | ctx->base.is_jmp = DISAS_EXIT; |
b724b012 | 7973 | } else { |
57b9c589 | 7974 | generate_trap(ctx, TRAPC_PROT, TIN1_PRIV); |
b724b012 BK |
7975 | } |
7976 | break; | |
7977 | case OPC2_32_SYS_RSLCX: | |
ad75a51e | 7978 | gen_helper_rslcx(tcg_env); |
b724b012 BK |
7979 | break; |
7980 | case OPC2_32_SYS_SVLCX: | |
ad75a51e | 7981 | gen_helper_svlcx(tcg_env); |
b724b012 | 7982 | break; |
bc3551c4 | 7983 | case OPC2_32_SYS_RESTORE: |
44ee3baf | 7984 | if (has_feature(ctx, TRICORE_FEATURE_16)) { |
878d1b6a | 7985 | if (ctx->priv == TRICORE_PRIV_SM || ctx->priv == TRICORE_PRIV_UM1) { |
a9c37abd BK |
7986 | tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1], |
7987 | ctx->icr_ie_offset, 1); | |
7988 | ctx->base.is_jmp = DISAS_EXIT_UPDATE; | |
57b9c589 BK |
7989 | } else { |
7990 | generate_trap(ctx, TRAPC_PROT, TIN1_PRIV); | |
7991 | } | |
f678f671 BK |
7992 | } else { |
7993 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
7994 | } | |
bc3551c4 | 7995 | break; |
b724b012 | 7996 | case OPC2_32_SYS_TRAPSV: |
518d7fd2 BK |
7997 | l1 = gen_new_label(); |
7998 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_PSW_SV, 0, l1); | |
7999 | generate_trap(ctx, TRAPC_ASSERT, TIN5_SOVF); | |
8000 | gen_set_label(l1); | |
b724b012 BK |
8001 | break; |
8002 | case OPC2_32_SYS_TRAPV: | |
518d7fd2 BK |
8003 | l1 = gen_new_label(); |
8004 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_PSW_V, 0, l1); | |
8005 | generate_trap(ctx, TRAPC_ASSERT, TIN5_OVF); | |
8006 | gen_set_label(l1); | |
b724b012 | 8007 | break; |
f678f671 BK |
8008 | default: |
8009 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
b724b012 BK |
8010 | } |
8011 | } | |
8012 | ||
2db92a0c | 8013 | static void decode_32Bit_opc(DisasContext *ctx) |
0aaeb118 | 8014 | { |
73f874d9 | 8015 | int op1, op2; |
ed516260 BK |
8016 | int32_t r1, r2, r3; |
8017 | int32_t address, const16; | |
fc2ef4a3 | 8018 | int8_t b, const4; |
59543d4e | 8019 | int32_t bpos; |
ed516260 | 8020 | TCGv temp, temp2, temp3; |
59543d4e BK |
8021 | |
8022 | op1 = MASK_OP_MAJOR(ctx->opcode); | |
8023 | ||
7f13420e BK |
8024 | /* handle JNZ.T opcode only being 7 bit long */ |
8025 | if (unlikely((op1 & 0x7f) == OPCM_32_BRN_JTT)) { | |
83c1bb18 BK |
8026 | op1 = OPCM_32_BRN_JTT; |
8027 | } | |
8028 | ||
59543d4e BK |
8029 | switch (op1) { |
8030 | /* ABS-format */ | |
8031 | case OPCM_32_ABS_LDW: | |
2db92a0c | 8032 | decode_abs_ldw(ctx); |
59543d4e BK |
8033 | break; |
8034 | case OPCM_32_ABS_LDB: | |
2db92a0c | 8035 | decode_abs_ldb(ctx); |
59543d4e BK |
8036 | break; |
8037 | case OPCM_32_ABS_LDMST_SWAP: | |
2db92a0c | 8038 | decode_abs_ldst_swap(ctx); |
59543d4e BK |
8039 | break; |
8040 | case OPCM_32_ABS_LDST_CONTEXT: | |
2db92a0c | 8041 | decode_abs_ldst_context(ctx); |
59543d4e BK |
8042 | break; |
8043 | case OPCM_32_ABS_STORE: | |
2db92a0c | 8044 | decode_abs_store(ctx); |
59543d4e BK |
8045 | break; |
8046 | case OPCM_32_ABS_STOREB_H: | |
2db92a0c | 8047 | decode_abs_storeb_h(ctx); |
59543d4e BK |
8048 | break; |
8049 | case OPC1_32_ABS_STOREQ: | |
8050 | address = MASK_OP_ABS_OFF18(ctx->opcode); | |
8051 | r1 = MASK_OP_ABS_S1D(ctx->opcode); | |
151293c2 | 8052 | temp = tcg_constant_i32(EA_ABS_FORMAT(address)); |
59543d4e BK |
8053 | temp2 = tcg_temp_new(); |
8054 | ||
8055 | tcg_gen_shri_tl(temp2, cpu_gpr_d[r1], 16); | |
8056 | tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_LEUW); | |
59543d4e BK |
8057 | break; |
8058 | case OPC1_32_ABS_LD_Q: | |
8059 | address = MASK_OP_ABS_OFF18(ctx->opcode); | |
8060 | r1 = MASK_OP_ABS_S1D(ctx->opcode); | |
151293c2 | 8061 | temp = tcg_constant_i32(EA_ABS_FORMAT(address)); |
59543d4e BK |
8062 | |
8063 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW); | |
8064 | tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); | |
59543d4e | 8065 | break; |
73f874d9 | 8066 | case OPCM_32_ABS_LEA_LHA: |
59543d4e BK |
8067 | address = MASK_OP_ABS_OFF18(ctx->opcode); |
8068 | r1 = MASK_OP_ABS_S1D(ctx->opcode); | |
73f874d9 BK |
8069 | |
8070 | if (has_feature(ctx, TRICORE_FEATURE_162)) { | |
8071 | op2 = MASK_OP_ABS_OP2(ctx->opcode); | |
8072 | if (op2 == OPC2_32_ABS_LHA) { | |
8073 | tcg_gen_movi_tl(cpu_gpr_a[r1], address << 14); | |
8074 | break; | |
8075 | } | |
8076 | /* otherwise translate regular LEA */ | |
8077 | } | |
8078 | ||
59543d4e BK |
8079 | tcg_gen_movi_tl(cpu_gpr_a[r1], EA_ABS_FORMAT(address)); |
8080 | break; | |
8081 | /* ABSB-format */ | |
8082 | case OPC1_32_ABSB_ST_T: | |
8083 | address = MASK_OP_ABS_OFF18(ctx->opcode); | |
8084 | b = MASK_OP_ABSB_B(ctx->opcode); | |
8085 | bpos = MASK_OP_ABSB_BPOS(ctx->opcode); | |
8086 | ||
151293c2 | 8087 | temp = tcg_constant_i32(EA_ABS_FORMAT(address)); |
59543d4e BK |
8088 | temp2 = tcg_temp_new(); |
8089 | ||
8090 | tcg_gen_qemu_ld_tl(temp2, temp, ctx->mem_idx, MO_UB); | |
8091 | tcg_gen_andi_tl(temp2, temp2, ~(0x1u << bpos)); | |
8092 | tcg_gen_ori_tl(temp2, temp2, (b << bpos)); | |
8093 | tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_UB); | |
59543d4e | 8094 | break; |
f718b0bb BK |
8095 | /* B-format */ |
8096 | case OPC1_32_B_CALL: | |
8097 | case OPC1_32_B_CALLA: | |
9e14a7b2 BK |
8098 | case OPC1_32_B_FCALL: |
8099 | case OPC1_32_B_FCALLA: | |
f718b0bb BK |
8100 | case OPC1_32_B_J: |
8101 | case OPC1_32_B_JA: | |
8102 | case OPC1_32_B_JL: | |
8103 | case OPC1_32_B_JLA: | |
436d63ff | 8104 | address = MASK_OP_B_DISP24_SEXT(ctx->opcode); |
f718b0bb BK |
8105 | gen_compute_branch(ctx, op1, 0, 0, 0, address); |
8106 | break; | |
b74f2b5b BK |
8107 | /* Bit-format */ |
8108 | case OPCM_32_BIT_ANDACC: | |
2db92a0c | 8109 | decode_bit_andacc(ctx); |
b74f2b5b BK |
8110 | break; |
8111 | case OPCM_32_BIT_LOGICAL_T1: | |
2db92a0c | 8112 | decode_bit_logical_t(ctx); |
b74f2b5b BK |
8113 | break; |
8114 | case OPCM_32_BIT_INSERT: | |
2db92a0c | 8115 | decode_bit_insert(ctx); |
b74f2b5b BK |
8116 | break; |
8117 | case OPCM_32_BIT_LOGICAL_T2: | |
2db92a0c | 8118 | decode_bit_logical_t2(ctx); |
b74f2b5b BK |
8119 | break; |
8120 | case OPCM_32_BIT_ORAND: | |
2db92a0c | 8121 | decode_bit_orand(ctx); |
b74f2b5b BK |
8122 | break; |
8123 | case OPCM_32_BIT_SH_LOGIC1: | |
2db92a0c | 8124 | decode_bit_sh_logic1(ctx); |
b74f2b5b BK |
8125 | break; |
8126 | case OPCM_32_BIT_SH_LOGIC2: | |
2db92a0c | 8127 | decode_bit_sh_logic2(ctx); |
b74f2b5b | 8128 | break; |
3a16ecb0 BK |
8129 | /* BO Format */ |
8130 | case OPCM_32_BO_ADDRMODE_POST_PRE_BASE: | |
2db92a0c | 8131 | decode_bo_addrmode_post_pre_base(ctx); |
3a16ecb0 BK |
8132 | break; |
8133 | case OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR: | |
2db92a0c | 8134 | decode_bo_addrmode_bitreverse_circular(ctx); |
3a16ecb0 BK |
8135 | break; |
8136 | case OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE: | |
2db92a0c | 8137 | decode_bo_addrmode_ld_post_pre_base(ctx); |
3a16ecb0 BK |
8138 | break; |
8139 | case OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR: | |
2db92a0c | 8140 | decode_bo_addrmode_ld_bitreverse_circular(ctx); |
3a16ecb0 BK |
8141 | break; |
8142 | case OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE: | |
2db92a0c | 8143 | decode_bo_addrmode_stctx_post_pre_base(ctx); |
3a16ecb0 BK |
8144 | break; |
8145 | case OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR: | |
2db92a0c | 8146 | decode_bo_addrmode_ldmst_bitreverse_circular(ctx); |
3a16ecb0 | 8147 | break; |
3fb763cb BK |
8148 | /* BOL-format */ |
8149 | case OPC1_32_BOL_LD_A_LONGOFF: | |
af715d98 | 8150 | case OPC1_32_BOL_LD_W_LONGOFF: |
3fb763cb BK |
8151 | case OPC1_32_BOL_LEA_LONGOFF: |
8152 | case OPC1_32_BOL_ST_W_LONGOFF: | |
8153 | case OPC1_32_BOL_ST_A_LONGOFF: | |
b5fd8fa3 BK |
8154 | case OPC1_32_BOL_LD_B_LONGOFF: |
8155 | case OPC1_32_BOL_LD_BU_LONGOFF: | |
8156 | case OPC1_32_BOL_LD_H_LONGOFF: | |
8157 | case OPC1_32_BOL_LD_HU_LONGOFF: | |
8158 | case OPC1_32_BOL_ST_B_LONGOFF: | |
8159 | case OPC1_32_BOL_ST_H_LONGOFF: | |
2db92a0c | 8160 | decode_bol_opc(ctx, op1); |
3fb763cb | 8161 | break; |
fc2ef4a3 BK |
8162 | /* BRC Format */ |
8163 | case OPCM_32_BRC_EQ_NEQ: | |
8164 | case OPCM_32_BRC_GE: | |
8165 | case OPCM_32_BRC_JLT: | |
8166 | case OPCM_32_BRC_JNE: | |
8167 | const4 = MASK_OP_BRC_CONST4_SEXT(ctx->opcode); | |
8168 | address = MASK_OP_BRC_DISP15_SEXT(ctx->opcode); | |
8169 | r1 = MASK_OP_BRC_S1(ctx->opcode); | |
8170 | gen_compute_branch(ctx, op1, r1, 0, const4, address); | |
8171 | break; | |
83c1bb18 BK |
8172 | /* BRN Format */ |
8173 | case OPCM_32_BRN_JTT: | |
8174 | address = MASK_OP_BRN_DISP15_SEXT(ctx->opcode); | |
8175 | r1 = MASK_OP_BRN_S1(ctx->opcode); | |
8176 | gen_compute_branch(ctx, op1, r1, 0, 0, address); | |
8177 | break; | |
a68e0d54 BK |
8178 | /* BRR Format */ |
8179 | case OPCM_32_BRR_EQ_NEQ: | |
8180 | case OPCM_32_BRR_ADDR_EQ_NEQ: | |
8181 | case OPCM_32_BRR_GE: | |
8182 | case OPCM_32_BRR_JLT: | |
8183 | case OPCM_32_BRR_JNE: | |
8184 | case OPCM_32_BRR_JNZ: | |
8185 | case OPCM_32_BRR_LOOP: | |
8186 | address = MASK_OP_BRR_DISP15_SEXT(ctx->opcode); | |
8187 | r2 = MASK_OP_BRR_S2(ctx->opcode); | |
8188 | r1 = MASK_OP_BRR_S1(ctx->opcode); | |
8189 | gen_compute_branch(ctx, op1, r1, r2, 0, address); | |
8190 | break; | |
0974257e BK |
8191 | /* RC Format */ |
8192 | case OPCM_32_RC_LOGICAL_SHIFT: | |
2db92a0c | 8193 | decode_rc_logical_shift(ctx); |
0974257e BK |
8194 | break; |
8195 | case OPCM_32_RC_ACCUMULATOR: | |
2db92a0c | 8196 | decode_rc_accumulator(ctx); |
0974257e BK |
8197 | break; |
8198 | case OPCM_32_RC_SERVICEROUTINE: | |
2db92a0c | 8199 | decode_rc_serviceroutine(ctx); |
0974257e BK |
8200 | break; |
8201 | case OPCM_32_RC_MUL: | |
2db92a0c | 8202 | decode_rc_mul(ctx); |
0974257e | 8203 | break; |
ed516260 BK |
8204 | /* RCPW Format */ |
8205 | case OPCM_32_RCPW_MASK_INSERT: | |
2db92a0c | 8206 | decode_rcpw_insert(ctx); |
ed516260 BK |
8207 | break; |
8208 | /* RCRR Format */ | |
8209 | case OPC1_32_RCRR_INSERT: | |
8210 | r1 = MASK_OP_RCRR_S1(ctx->opcode); | |
8211 | r2 = MASK_OP_RCRR_S3(ctx->opcode); | |
8212 | r3 = MASK_OP_RCRR_D(ctx->opcode); | |
8213 | const16 = MASK_OP_RCRR_CONST4(ctx->opcode); | |
151293c2 | 8214 | temp = tcg_constant_i32(const16); |
ed516260 BK |
8215 | temp2 = tcg_temp_new(); /* width*/ |
8216 | temp3 = tcg_temp_new(); /* pos */ | |
8217 | ||
222ff2d3 | 8218 | CHECK_REG_PAIR(r2); |
828066c7 | 8219 | |
222ff2d3 BK |
8220 | tcg_gen_andi_tl(temp2, cpu_gpr_d[r2 + 1], 0x1f); |
8221 | tcg_gen_andi_tl(temp3, cpu_gpr_d[r2], 0x1f); | |
ed516260 | 8222 | |
222ff2d3 | 8223 | gen_insert(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, temp2, temp3); |
ed516260 BK |
8224 | break; |
8225 | /* RCRW Format */ | |
8226 | case OPCM_32_RCRW_MASK_INSERT: | |
2db92a0c | 8227 | decode_rcrw_insert(ctx); |
ed516260 | 8228 | break; |
328f1f0f BK |
8229 | /* RCR Format */ |
8230 | case OPCM_32_RCR_COND_SELECT: | |
2db92a0c | 8231 | decode_rcr_cond_select(ctx); |
328f1f0f BK |
8232 | break; |
8233 | case OPCM_32_RCR_MADD: | |
2db92a0c | 8234 | decode_rcr_madd(ctx); |
328f1f0f BK |
8235 | break; |
8236 | case OPCM_32_RCR_MSUB: | |
2db92a0c | 8237 | decode_rcr_msub(ctx); |
328f1f0f | 8238 | break; |
2b2f7d97 BK |
8239 | /* RLC Format */ |
8240 | case OPC1_32_RLC_ADDI: | |
8241 | case OPC1_32_RLC_ADDIH: | |
8242 | case OPC1_32_RLC_ADDIH_A: | |
8243 | case OPC1_32_RLC_MFCR: | |
8244 | case OPC1_32_RLC_MOV: | |
4b5b4435 | 8245 | case OPC1_32_RLC_MOV_64: |
2b2f7d97 BK |
8246 | case OPC1_32_RLC_MOV_U: |
8247 | case OPC1_32_RLC_MOV_H: | |
8248 | case OPC1_32_RLC_MOVH_A: | |
8249 | case OPC1_32_RLC_MTCR: | |
2db92a0c | 8250 | decode_rlc_opc(ctx, op1); |
2b2f7d97 | 8251 | break; |
d5de7839 BK |
8252 | /* RR Format */ |
8253 | case OPCM_32_RR_ACCUMULATOR: | |
2db92a0c | 8254 | decode_rr_accumulator(ctx); |
d5de7839 | 8255 | break; |
0b79a781 | 8256 | case OPCM_32_RR_LOGICAL_SHIFT: |
2db92a0c | 8257 | decode_rr_logical_shift(ctx); |
0b79a781 | 8258 | break; |
37097418 | 8259 | case OPCM_32_RR_ADDRESS: |
2db92a0c | 8260 | decode_rr_address(ctx); |
f2f1585f BK |
8261 | break; |
8262 | case OPCM_32_RR_IDIRECT: | |
2db92a0c | 8263 | decode_rr_idirect(ctx); |
f2f1585f | 8264 | break; |
e2bed107 | 8265 | case OPCM_32_RR_DIVIDE: |
2db92a0c | 8266 | decode_rr_divide(ctx); |
e2bed107 | 8267 | break; |
9655b932 BK |
8268 | /* RR1 Format */ |
8269 | case OPCM_32_RR1_MUL: | |
2db92a0c | 8270 | decode_rr1_mul(ctx); |
9655b932 | 8271 | break; |
f1cc6eaf | 8272 | case OPCM_32_RR1_MULQ: |
2db92a0c | 8273 | decode_rr1_mulq(ctx); |
f1cc6eaf | 8274 | break; |
12f323e6 BK |
8275 | /* RR2 format */ |
8276 | case OPCM_32_RR2_MUL: | |
2db92a0c | 8277 | decode_rr2_mul(ctx); |
12f323e6 | 8278 | break; |
8fb9d0eb BK |
8279 | /* RRPW format */ |
8280 | case OPCM_32_RRPW_EXTRACT_INSERT: | |
2db92a0c | 8281 | decode_rrpw_extract_insert(ctx); |
8fb9d0eb BK |
8282 | break; |
8283 | case OPC1_32_RRPW_DEXTR: | |
8284 | r1 = MASK_OP_RRPW_S1(ctx->opcode); | |
8285 | r2 = MASK_OP_RRPW_S2(ctx->opcode); | |
8286 | r3 = MASK_OP_RRPW_D(ctx->opcode); | |
8287 | const16 = MASK_OP_RRPW_POS(ctx->opcode); | |
48bffe7f BK |
8288 | |
8289 | tcg_gen_extract2_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], cpu_gpr_d[r1], | |
8290 | 32 - const16); | |
8fb9d0eb | 8291 | break; |
09532255 BK |
8292 | /* RRR Format */ |
8293 | case OPCM_32_RRR_COND_SELECT: | |
2db92a0c | 8294 | decode_rrr_cond_select(ctx); |
09532255 BK |
8295 | break; |
8296 | case OPCM_32_RRR_DIVIDE: | |
2db92a0c | 8297 | decode_rrr_divide(ctx); |
1f75cba8 | 8298 | break; |
2984cfbd BK |
8299 | /* RRR2 Format */ |
8300 | case OPCM_32_RRR2_MADD: | |
2db92a0c | 8301 | decode_rrr2_madd(ctx); |
2984cfbd BK |
8302 | break; |
8303 | case OPCM_32_RRR2_MSUB: | |
2db92a0c | 8304 | decode_rrr2_msub(ctx); |
2984cfbd | 8305 | break; |
2e430e1c BK |
8306 | /* RRR1 format */ |
8307 | case OPCM_32_RRR1_MADD: | |
2db92a0c | 8308 | decode_rrr1_madd(ctx); |
2e430e1c | 8309 | break; |
b00aa8ec | 8310 | case OPCM_32_RRR1_MADDQ_H: |
2db92a0c | 8311 | decode_rrr1_maddq_h(ctx); |
b00aa8ec | 8312 | break; |
bebe80fc | 8313 | case OPCM_32_RRR1_MADDSU_H: |
2db92a0c | 8314 | decode_rrr1_maddsu_h(ctx); |
bebe80fc | 8315 | break; |
f4aef476 | 8316 | case OPCM_32_RRR1_MSUB_H: |
2db92a0c | 8317 | decode_rrr1_msub(ctx); |
f4aef476 | 8318 | break; |
62e47b2e | 8319 | case OPCM_32_RRR1_MSUB_Q: |
2db92a0c | 8320 | decode_rrr1_msubq_h(ctx); |
62e47b2e | 8321 | break; |
068fac77 | 8322 | case OPCM_32_RRR1_MSUBAD_H: |
2db92a0c | 8323 | decode_rrr1_msubad_h(ctx); |
068fac77 | 8324 | break; |
4d108fe3 BK |
8325 | /* RRRR format */ |
8326 | case OPCM_32_RRRR_EXTRACT_INSERT: | |
2db92a0c | 8327 | decode_rrrr_extract_insert(ctx); |
1f75cba8 | 8328 | break; |
eb989d25 BK |
8329 | /* RRRW format */ |
8330 | case OPCM_32_RRRW_EXTRACT_INSERT: | |
2db92a0c | 8331 | decode_rrrw_extract_insert(ctx); |
eb989d25 | 8332 | break; |
b724b012 BK |
8333 | /* SYS format */ |
8334 | case OPCM_32_SYS_INTERRUPTS: | |
2db92a0c | 8335 | decode_sys_interrupts(ctx); |
b724b012 BK |
8336 | break; |
8337 | case OPC1_32_SYS_RSTV: | |
8338 | tcg_gen_movi_tl(cpu_PSW_V, 0); | |
8339 | tcg_gen_mov_tl(cpu_PSW_SV, cpu_PSW_V); | |
8340 | tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); | |
8341 | tcg_gen_mov_tl(cpu_PSW_SAV, cpu_PSW_V); | |
8342 | break; | |
f678f671 BK |
8343 | default: |
8344 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
59543d4e | 8345 | } |
0aaeb118 BK |
8346 | } |
8347 | ||
d4881da9 | 8348 | static bool tricore_insn_is_16bit(uint32_t insn) |
0aaeb118 | 8349 | { |
d4881da9 | 8350 | return (insn & 0x1) == 0; |
0aaeb118 BK |
8351 | } |
8352 | ||
1fae1851 BK |
8353 | static void tricore_tr_init_disas_context(DisasContextBase *dcbase, |
8354 | CPUState *cs) | |
48e06fe0 | 8355 | { |
1fae1851 | 8356 | DisasContext *ctx = container_of(dcbase, DisasContext, base); |
b77af26e | 8357 | CPUTriCoreState *env = cpu_env(cs); |
1fae1851 | 8358 | ctx->mem_idx = cpu_mmu_index(env, false); |
878d1b6a BK |
8359 | |
8360 | uint32_t tb_flags = (uint32_t)ctx->base.tb->flags; | |
8361 | ctx->priv = FIELD_EX32(tb_flags, TB_FLAGS, PRIV); | |
8362 | ||
44ee3baf | 8363 | ctx->features = env->features; |
343cdf2c BK |
8364 | if (has_feature(ctx, TRICORE_FEATURE_161)) { |
8365 | ctx->icr_ie_mask = R_ICR_IE_161_MASK; | |
0b9f9b63 | 8366 | ctx->icr_ie_offset = R_ICR_IE_161_SHIFT; |
343cdf2c BK |
8367 | } else { |
8368 | ctx->icr_ie_mask = R_ICR_IE_13_MASK; | |
0b9f9b63 | 8369 | ctx->icr_ie_offset = R_ICR_IE_13_SHIFT; |
343cdf2c | 8370 | } |
1fae1851 BK |
8371 | } |
8372 | ||
8373 | static void tricore_tr_tb_start(DisasContextBase *db, CPUState *cpu) | |
8374 | { | |
8375 | } | |
8376 | ||
8377 | static void tricore_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) | |
8378 | { | |
8379 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
8380 | ||
8381 | tcg_gen_insn_start(ctx->base.pc_next); | |
8382 | } | |
8383 | ||
d4881da9 BK |
8384 | static bool insn_crosses_page(CPUTriCoreState *env, DisasContext *ctx) |
8385 | { | |
8386 | /* | |
8387 | * Return true if the insn at ctx->base.pc_next might cross a page boundary. | |
8388 | * (False positives are OK, false negatives are not.) | |
8389 | * Our caller ensures we are only called if dc->base.pc_next is less than | |
8390 | * 4 bytes from the page boundary, so we cross the page if the first | |
8391 | * 16 bits indicate that this is a 32 bit insn. | |
8392 | */ | |
1f22db19 | 8393 | uint16_t insn = translator_lduw(env, &ctx->base, ctx->base.pc_next); |
d4881da9 BK |
8394 | |
8395 | return !tricore_insn_is_16bit(insn); | |
8396 | } | |
8397 | ||
8398 | ||
1fae1851 BK |
8399 | static void tricore_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) |
8400 | { | |
8401 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
b77af26e | 8402 | CPUTriCoreState *env = cpu_env(cpu); |
d4881da9 BK |
8403 | uint16_t insn_lo; |
8404 | bool is_16bit; | |
1fae1851 | 8405 | |
1f22db19 | 8406 | insn_lo = translator_lduw(env, &ctx->base, ctx->base.pc_next); |
d4881da9 BK |
8407 | is_16bit = tricore_insn_is_16bit(insn_lo); |
8408 | if (is_16bit) { | |
8409 | ctx->opcode = insn_lo; | |
8410 | ctx->pc_succ_insn = ctx->base.pc_next + 2; | |
8411 | decode_16Bit_opc(ctx); | |
8412 | } else { | |
1f22db19 BK |
8413 | uint32_t insn_hi = translator_lduw(env, &ctx->base, |
8414 | ctx->base.pc_next + 2); | |
d4881da9 BK |
8415 | ctx->opcode = insn_hi << 16 | insn_lo; |
8416 | ctx->pc_succ_insn = ctx->base.pc_next + 4; | |
8417 | decode_32Bit_opc(ctx); | |
8418 | } | |
1fae1851 BK |
8419 | ctx->base.pc_next = ctx->pc_succ_insn; |
8420 | ||
8421 | if (ctx->base.is_jmp == DISAS_NEXT) { | |
8422 | target_ulong page_start; | |
8423 | ||
8424 | page_start = ctx->base.pc_first & TARGET_PAGE_MASK; | |
d4881da9 BK |
8425 | if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE |
8426 | || (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE - 3 | |
8427 | && insn_crosses_page(env, ctx))) { | |
1fae1851 | 8428 | ctx->base.is_jmp = DISAS_TOO_MANY; |
0aaeb118 | 8429 | } |
0aaeb118 | 8430 | } |
1fae1851 | 8431 | } |
0aaeb118 | 8432 | |
1fae1851 BK |
8433 | static void tricore_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) |
8434 | { | |
8435 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
4e5e1215 | 8436 | |
1fae1851 BK |
8437 | switch (ctx->base.is_jmp) { |
8438 | case DISAS_TOO_MANY: | |
8439 | gen_goto_tb(ctx, 0, ctx->base.pc_next); | |
8440 | break; | |
2dbd73bf BK |
8441 | case DISAS_EXIT_UPDATE: |
8442 | gen_save_pc(ctx->base.pc_next); | |
8443 | /* fall through */ | |
1706e04f BK |
8444 | case DISAS_EXIT: |
8445 | tcg_gen_exit_tb(NULL, 0); | |
8446 | break; | |
d8f466af BK |
8447 | case DISAS_JUMP: |
8448 | tcg_gen_lookup_and_goto_ptr(); | |
8449 | break; | |
1fae1851 BK |
8450 | case DISAS_NORETURN: |
8451 | break; | |
8452 | default: | |
8453 | g_assert_not_reached(); | |
0aaeb118 | 8454 | } |
1fae1851 | 8455 | } |
0aaeb118 | 8456 | |
8eb806a7 RH |
8457 | static void tricore_tr_disas_log(const DisasContextBase *dcbase, |
8458 | CPUState *cpu, FILE *logfile) | |
1fae1851 | 8459 | { |
8eb806a7 RH |
8460 | fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); |
8461 | target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size); | |
1fae1851 BK |
8462 | } |
8463 | ||
8464 | static const TranslatorOps tricore_tr_ops = { | |
8465 | .init_disas_context = tricore_tr_init_disas_context, | |
8466 | .tb_start = tricore_tr_tb_start, | |
8467 | .insn_start = tricore_tr_insn_start, | |
1fae1851 BK |
8468 | .translate_insn = tricore_tr_translate_insn, |
8469 | .tb_stop = tricore_tr_tb_stop, | |
8470 | .disas_log = tricore_tr_disas_log, | |
8471 | }; | |
8472 | ||
8473 | ||
597f9b2d | 8474 | void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, |
32f0c394 | 8475 | vaddr pc, void *host_pc) |
1fae1851 BK |
8476 | { |
8477 | DisasContext ctx; | |
306c8721 RH |
8478 | translator_loop(cs, tb, max_insns, pc, host_pc, |
8479 | &tricore_tr_ops, &ctx.base); | |
48e06fe0 BK |
8480 | } |
8481 | ||
48e06fe0 BK |
8482 | /* |
8483 | * | |
8484 | * Initialization | |
8485 | * | |
8486 | */ | |
8487 | ||
8488 | void cpu_state_reset(CPUTriCoreState *env) | |
8489 | { | |
0aaeb118 BK |
8490 | /* Reset Regs to Default Value */ |
8491 | env->PSW = 0xb80; | |
996a729f | 8492 | fpu_set_state(env); |
0aaeb118 BK |
8493 | } |
8494 | ||
8495 | static void tricore_tcg_init_csfr(void) | |
8496 | { | |
ad75a51e | 8497 | cpu_PCXI = tcg_global_mem_new(tcg_env, |
0aaeb118 | 8498 | offsetof(CPUTriCoreState, PCXI), "PCXI"); |
ad75a51e | 8499 | cpu_PSW = tcg_global_mem_new(tcg_env, |
0aaeb118 | 8500 | offsetof(CPUTriCoreState, PSW), "PSW"); |
ad75a51e | 8501 | cpu_PC = tcg_global_mem_new(tcg_env, |
0aaeb118 | 8502 | offsetof(CPUTriCoreState, PC), "PC"); |
ad75a51e | 8503 | cpu_ICR = tcg_global_mem_new(tcg_env, |
0aaeb118 | 8504 | offsetof(CPUTriCoreState, ICR), "ICR"); |
48e06fe0 BK |
8505 | } |
8506 | ||
8507 | void tricore_tcg_init(void) | |
8508 | { | |
0aaeb118 | 8509 | int i; |
55c3ceef | 8510 | |
0aaeb118 BK |
8511 | /* reg init */ |
8512 | for (i = 0 ; i < 16 ; i++) { | |
ad75a51e | 8513 | cpu_gpr_a[i] = tcg_global_mem_new(tcg_env, |
0aaeb118 BK |
8514 | offsetof(CPUTriCoreState, gpr_a[i]), |
8515 | regnames_a[i]); | |
8516 | } | |
8517 | for (i = 0 ; i < 16 ; i++) { | |
ad75a51e | 8518 | cpu_gpr_d[i] = tcg_global_mem_new(tcg_env, |
0aaeb118 BK |
8519 | offsetof(CPUTriCoreState, gpr_d[i]), |
8520 | regnames_d[i]); | |
8521 | } | |
8522 | tricore_tcg_init_csfr(); | |
8523 | /* init PSW flag cache */ | |
ad75a51e | 8524 | cpu_PSW_C = tcg_global_mem_new(tcg_env, |
0aaeb118 BK |
8525 | offsetof(CPUTriCoreState, PSW_USB_C), |
8526 | "PSW_C"); | |
ad75a51e | 8527 | cpu_PSW_V = tcg_global_mem_new(tcg_env, |
0aaeb118 BK |
8528 | offsetof(CPUTriCoreState, PSW_USB_V), |
8529 | "PSW_V"); | |
ad75a51e | 8530 | cpu_PSW_SV = tcg_global_mem_new(tcg_env, |
0aaeb118 BK |
8531 | offsetof(CPUTriCoreState, PSW_USB_SV), |
8532 | "PSW_SV"); | |
ad75a51e | 8533 | cpu_PSW_AV = tcg_global_mem_new(tcg_env, |
0aaeb118 BK |
8534 | offsetof(CPUTriCoreState, PSW_USB_AV), |
8535 | "PSW_AV"); | |
ad75a51e | 8536 | cpu_PSW_SAV = tcg_global_mem_new(tcg_env, |
0aaeb118 BK |
8537 | offsetof(CPUTriCoreState, PSW_USB_SAV), |
8538 | "PSW_SAV"); | |
48e06fe0 | 8539 | } |