]>
Commit | Line | Data |
---|---|---|
48e06fe0 BK |
1 | /* |
2 | * TriCore emulation for qemu: main translation routines. | |
3 | * | |
4 | * Copyright (c) 2013-2014 Bastian Koppelmann C-Lab/University Paderborn | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
02754acd | 9 | * version 2.1 of the License, or (at your option) any later version. |
48e06fe0 BK |
10 | * |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | ||
61d9f32b | 21 | #include "qemu/osdep.h" |
48e06fe0 BK |
22 | #include "cpu.h" |
23 | #include "disas/disas.h" | |
63c91552 | 24 | #include "exec/exec-all.h" |
dcb32f1d | 25 | #include "tcg/tcg-op.h" |
48e06fe0 | 26 | #include "exec/cpu_ldst.h" |
90c84c56 | 27 | #include "qemu/qemu-print.h" |
48e06fe0 BK |
28 | |
29 | #include "exec/helper-proto.h" | |
30 | #include "exec/helper-gen.h" | |
31 | ||
7c87d074 | 32 | #include "tricore-opcodes.h" |
6b9f5a42 | 33 | #include "exec/translator.h" |
508127e2 | 34 | #include "exec/log.h" |
0707ec1b | 35 | |
0aaeb118 BK |
36 | /* |
37 | * TCG registers | |
38 | */ | |
39 | static TCGv cpu_PC; | |
40 | static TCGv cpu_PCXI; | |
41 | static TCGv cpu_PSW; | |
42 | static TCGv cpu_ICR; | |
43 | /* GPR registers */ | |
44 | static TCGv cpu_gpr_a[16]; | |
45 | static TCGv cpu_gpr_d[16]; | |
46 | /* PSW Flag cache */ | |
47 | static TCGv cpu_PSW_C; | |
48 | static TCGv cpu_PSW_V; | |
49 | static TCGv cpu_PSW_SV; | |
50 | static TCGv cpu_PSW_AV; | |
51 | static TCGv cpu_PSW_SAV; | |
0aaeb118 BK |
52 | |
53 | #include "exec/gen-icount.h" | |
48e06fe0 BK |
54 | |
55 | static const char *regnames_a[] = { | |
56 | "a0" , "a1" , "a2" , "a3" , "a4" , "a5" , | |
57 | "a6" , "a7" , "a8" , "a9" , "sp" , "a11" , | |
58 | "a12" , "a13" , "a14" , "a15", | |
59 | }; | |
60 | ||
61 | static const char *regnames_d[] = { | |
62 | "d0" , "d1" , "d2" , "d3" , "d4" , "d5" , | |
63 | "d6" , "d7" , "d8" , "d9" , "d10" , "d11" , | |
64 | "d12" , "d13" , "d14" , "d15", | |
65 | }; | |
66 | ||
0aaeb118 | 67 | typedef struct DisasContext { |
6b9f5a42 BK |
68 | DisasContextBase base; |
69 | target_ulong pc_succ_insn; | |
0aaeb118 | 70 | uint32_t opcode; |
0aaeb118 BK |
71 | /* Routine used to access memory */ |
72 | int mem_idx; | |
73 | uint32_t hflags, saved_hflags; | |
44ee3baf | 74 | uint64_t features; |
0aaeb118 BK |
75 | } DisasContext; |
76 | ||
44ee3baf BK |
77 | static int has_feature(DisasContext *ctx, int feature) |
78 | { | |
79 | return (ctx->features & (1ULL << feature)) != 0; | |
80 | } | |
81 | ||
2e430e1c BK |
82 | enum { |
83 | MODE_LL = 0, | |
84 | MODE_LU = 1, | |
85 | MODE_UL = 2, | |
86 | MODE_UU = 3, | |
87 | }; | |
88 | ||
90c84c56 | 89 | void tricore_cpu_dump_state(CPUState *cs, FILE *f, int flags) |
48e06fe0 BK |
90 | { |
91 | TriCoreCPU *cpu = TRICORE_CPU(cs); | |
92 | CPUTriCoreState *env = &cpu->env; | |
45820fcc | 93 | uint32_t psw; |
48e06fe0 BK |
94 | int i; |
95 | ||
45820fcc AZ |
96 | psw = psw_read(env); |
97 | ||
90c84c56 MA |
98 | qemu_fprintf(f, "PC: " TARGET_FMT_lx, env->PC); |
99 | qemu_fprintf(f, " PSW: " TARGET_FMT_lx, psw); | |
100 | qemu_fprintf(f, " ICR: " TARGET_FMT_lx, env->ICR); | |
101 | qemu_fprintf(f, "\nPCXI: " TARGET_FMT_lx, env->PCXI); | |
102 | qemu_fprintf(f, " FCX: " TARGET_FMT_lx, env->FCX); | |
103 | qemu_fprintf(f, " LCX: " TARGET_FMT_lx, env->LCX); | |
45820fcc | 104 | |
48e06fe0 BK |
105 | for (i = 0; i < 16; ++i) { |
106 | if ((i & 3) == 0) { | |
90c84c56 | 107 | qemu_fprintf(f, "\nGPR A%02d:", i); |
48e06fe0 | 108 | } |
90c84c56 | 109 | qemu_fprintf(f, " " TARGET_FMT_lx, env->gpr_a[i]); |
48e06fe0 BK |
110 | } |
111 | for (i = 0; i < 16; ++i) { | |
112 | if ((i & 3) == 0) { | |
90c84c56 | 113 | qemu_fprintf(f, "\nGPR D%02d:", i); |
48e06fe0 | 114 | } |
90c84c56 | 115 | qemu_fprintf(f, " " TARGET_FMT_lx, env->gpr_d[i]); |
48e06fe0 | 116 | } |
90c84c56 | 117 | qemu_fprintf(f, "\n"); |
48e06fe0 BK |
118 | } |
119 | ||
0707ec1b BK |
120 | /* |
121 | * Functions to generate micro-ops | |
122 | */ | |
123 | ||
9a31922b BK |
124 | /* Makros for generating helpers */ |
125 | ||
126 | #define gen_helper_1arg(name, arg) do { \ | |
127 | TCGv_i32 helper_tmp = tcg_const_i32(arg); \ | |
128 | gen_helper_##name(cpu_env, helper_tmp); \ | |
129 | tcg_temp_free_i32(helper_tmp); \ | |
130 | } while (0) | |
131 | ||
9655b932 BK |
132 | #define GEN_HELPER_LL(name, ret, arg0, arg1, n) do { \ |
133 | TCGv arg00 = tcg_temp_new(); \ | |
134 | TCGv arg01 = tcg_temp_new(); \ | |
135 | TCGv arg11 = tcg_temp_new(); \ | |
136 | tcg_gen_sari_tl(arg00, arg0, 16); \ | |
137 | tcg_gen_ext16s_tl(arg01, arg0); \ | |
138 | tcg_gen_ext16s_tl(arg11, arg1); \ | |
139 | gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \ | |
140 | tcg_temp_free(arg00); \ | |
141 | tcg_temp_free(arg01); \ | |
142 | tcg_temp_free(arg11); \ | |
143 | } while (0) | |
144 | ||
145 | #define GEN_HELPER_LU(name, ret, arg0, arg1, n) do { \ | |
146 | TCGv arg00 = tcg_temp_new(); \ | |
147 | TCGv arg01 = tcg_temp_new(); \ | |
148 | TCGv arg10 = tcg_temp_new(); \ | |
149 | TCGv arg11 = tcg_temp_new(); \ | |
150 | tcg_gen_sari_tl(arg00, arg0, 16); \ | |
151 | tcg_gen_ext16s_tl(arg01, arg0); \ | |
152 | tcg_gen_sari_tl(arg11, arg1, 16); \ | |
153 | tcg_gen_ext16s_tl(arg10, arg1); \ | |
154 | gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \ | |
155 | tcg_temp_free(arg00); \ | |
156 | tcg_temp_free(arg01); \ | |
157 | tcg_temp_free(arg10); \ | |
158 | tcg_temp_free(arg11); \ | |
159 | } while (0) | |
160 | ||
161 | #define GEN_HELPER_UL(name, ret, arg0, arg1, n) do { \ | |
162 | TCGv arg00 = tcg_temp_new(); \ | |
163 | TCGv arg01 = tcg_temp_new(); \ | |
164 | TCGv arg10 = tcg_temp_new(); \ | |
165 | TCGv arg11 = tcg_temp_new(); \ | |
166 | tcg_gen_sari_tl(arg00, arg0, 16); \ | |
167 | tcg_gen_ext16s_tl(arg01, arg0); \ | |
168 | tcg_gen_sari_tl(arg10, arg1, 16); \ | |
169 | tcg_gen_ext16s_tl(arg11, arg1); \ | |
170 | gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \ | |
171 | tcg_temp_free(arg00); \ | |
172 | tcg_temp_free(arg01); \ | |
173 | tcg_temp_free(arg10); \ | |
174 | tcg_temp_free(arg11); \ | |
175 | } while (0) | |
176 | ||
177 | #define GEN_HELPER_UU(name, ret, arg0, arg1, n) do { \ | |
178 | TCGv arg00 = tcg_temp_new(); \ | |
179 | TCGv arg01 = tcg_temp_new(); \ | |
180 | TCGv arg11 = tcg_temp_new(); \ | |
181 | tcg_gen_sari_tl(arg01, arg0, 16); \ | |
182 | tcg_gen_ext16s_tl(arg00, arg0); \ | |
183 | tcg_gen_sari_tl(arg11, arg1, 16); \ | |
184 | gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \ | |
185 | tcg_temp_free(arg00); \ | |
186 | tcg_temp_free(arg01); \ | |
187 | tcg_temp_free(arg11); \ | |
188 | } while (0) | |
189 | ||
09532255 BK |
190 | #define GEN_HELPER_RRR(name, rl, rh, al1, ah1, arg2) do { \ |
191 | TCGv_i64 ret = tcg_temp_new_i64(); \ | |
192 | TCGv_i64 arg1 = tcg_temp_new_i64(); \ | |
193 | \ | |
194 | tcg_gen_concat_i32_i64(arg1, al1, ah1); \ | |
195 | gen_helper_##name(ret, arg1, arg2); \ | |
196 | tcg_gen_extr_i64_i32(rl, rh, ret); \ | |
197 | \ | |
198 | tcg_temp_free_i64(ret); \ | |
199 | tcg_temp_free_i64(arg1); \ | |
200 | } while (0) | |
201 | ||
93715571 BK |
202 | #define GEN_HELPER_RR(name, rl, rh, arg1, arg2) do { \ |
203 | TCGv_i64 ret = tcg_temp_new_i64(); \ | |
204 | \ | |
205 | gen_helper_##name(ret, cpu_env, arg1, arg2); \ | |
206 | tcg_gen_extr_i64_i32(rl, rh, ret); \ | |
207 | \ | |
208 | tcg_temp_free_i64(ret); \ | |
209 | } while (0) | |
210 | ||
59543d4e | 211 | #define EA_ABS_FORMAT(con) (((con & 0x3C000) << 14) + (con & 0x3FFF)) |
f718b0bb BK |
212 | #define EA_B_ABSOLUT(con) (((offset & 0xf00000) << 8) | \ |
213 | ((offset & 0x0fffff) << 1)) | |
59543d4e | 214 | |
828066c7 BK |
215 | /* For two 32-bit registers used a 64-bit register, the first |
216 | registernumber needs to be even. Otherwise we trap. */ | |
217 | static inline void generate_trap(DisasContext *ctx, int class, int tin); | |
218 | #define CHECK_REG_PAIR(reg) do { \ | |
219 | if (reg & 0x1) { \ | |
220 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_OPD); \ | |
221 | } \ | |
222 | } while (0) | |
223 | ||
d2798210 BK |
224 | /* Functions for load/save to/from memory */ |
225 | ||
226 | static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2, | |
14776ab5 | 227 | int16_t con, MemOp mop) |
d2798210 BK |
228 | { |
229 | TCGv temp = tcg_temp_new(); | |
230 | tcg_gen_addi_tl(temp, r2, con); | |
231 | tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop); | |
232 | tcg_temp_free(temp); | |
233 | } | |
234 | ||
235 | static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2, | |
14776ab5 | 236 | int16_t con, MemOp mop) |
d2798210 BK |
237 | { |
238 | TCGv temp = tcg_temp_new(); | |
239 | tcg_gen_addi_tl(temp, r2, con); | |
240 | tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop); | |
241 | tcg_temp_free(temp); | |
242 | } | |
243 | ||
59543d4e BK |
244 | static void gen_st_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx) |
245 | { | |
246 | TCGv_i64 temp = tcg_temp_new_i64(); | |
247 | ||
248 | tcg_gen_concat_i32_i64(temp, rl, rh); | |
249 | tcg_gen_qemu_st_i64(temp, address, ctx->mem_idx, MO_LEQ); | |
250 | ||
251 | tcg_temp_free_i64(temp); | |
252 | } | |
253 | ||
3a16ecb0 BK |
254 | static void gen_offset_st_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con, |
255 | DisasContext *ctx) | |
256 | { | |
257 | TCGv temp = tcg_temp_new(); | |
258 | tcg_gen_addi_tl(temp, base, con); | |
259 | gen_st_2regs_64(rh, rl, temp, ctx); | |
260 | tcg_temp_free(temp); | |
261 | } | |
262 | ||
59543d4e BK |
263 | static void gen_ld_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx) |
264 | { | |
265 | TCGv_i64 temp = tcg_temp_new_i64(); | |
266 | ||
267 | tcg_gen_qemu_ld_i64(temp, address, ctx->mem_idx, MO_LEQ); | |
268 | /* write back to two 32 bit regs */ | |
269 | tcg_gen_extr_i64_i32(rl, rh, temp); | |
270 | ||
271 | tcg_temp_free_i64(temp); | |
272 | } | |
273 | ||
3a16ecb0 BK |
274 | static void gen_offset_ld_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con, |
275 | DisasContext *ctx) | |
276 | { | |
277 | TCGv temp = tcg_temp_new(); | |
278 | tcg_gen_addi_tl(temp, base, con); | |
279 | gen_ld_2regs_64(rh, rl, temp, ctx); | |
280 | tcg_temp_free(temp); | |
281 | } | |
282 | ||
283 | static void gen_st_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off, | |
14776ab5 | 284 | MemOp mop) |
3a16ecb0 BK |
285 | { |
286 | TCGv temp = tcg_temp_new(); | |
287 | tcg_gen_addi_tl(temp, r2, off); | |
288 | tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop); | |
289 | tcg_gen_mov_tl(r2, temp); | |
290 | tcg_temp_free(temp); | |
291 | } | |
292 | ||
293 | static void gen_ld_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off, | |
14776ab5 | 294 | MemOp mop) |
3a16ecb0 BK |
295 | { |
296 | TCGv temp = tcg_temp_new(); | |
297 | tcg_gen_addi_tl(temp, r2, off); | |
298 | tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop); | |
299 | tcg_gen_mov_tl(r2, temp); | |
300 | tcg_temp_free(temp); | |
301 | } | |
302 | ||
59543d4e BK |
303 | /* M(EA, word) = (M(EA, word) & ~E[a][63:32]) | (E[a][31:0] & E[a][63:32]); */ |
304 | static void gen_ldmst(DisasContext *ctx, int ereg, TCGv ea) | |
305 | { | |
306 | TCGv temp = tcg_temp_new(); | |
307 | TCGv temp2 = tcg_temp_new(); | |
308 | ||
828066c7 | 309 | CHECK_REG_PAIR(ereg); |
59543d4e BK |
310 | /* temp = (M(EA, word) */ |
311 | tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); | |
312 | /* temp = temp & ~E[a][63:32]) */ | |
313 | tcg_gen_andc_tl(temp, temp, cpu_gpr_d[ereg+1]); | |
314 | /* temp2 = (E[a][31:0] & E[a][63:32]); */ | |
315 | tcg_gen_and_tl(temp2, cpu_gpr_d[ereg], cpu_gpr_d[ereg+1]); | |
316 | /* temp = temp | temp2; */ | |
317 | tcg_gen_or_tl(temp, temp, temp2); | |
318 | /* M(EA, word) = temp; */ | |
319 | tcg_gen_qemu_st_tl(temp, ea, ctx->mem_idx, MO_LEUL); | |
320 | ||
321 | tcg_temp_free(temp); | |
322 | tcg_temp_free(temp2); | |
323 | } | |
324 | ||
325 | /* tmp = M(EA, word); | |
326 | M(EA, word) = D[a]; | |
327 | D[a] = tmp[31:0];*/ | |
328 | static void gen_swap(DisasContext *ctx, int reg, TCGv ea) | |
329 | { | |
330 | TCGv temp = tcg_temp_new(); | |
331 | ||
332 | tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); | |
333 | tcg_gen_qemu_st_tl(cpu_gpr_d[reg], ea, ctx->mem_idx, MO_LEUL); | |
334 | tcg_gen_mov_tl(cpu_gpr_d[reg], temp); | |
335 | ||
336 | tcg_temp_free(temp); | |
337 | } | |
338 | ||
62872ebc BK |
339 | static void gen_cmpswap(DisasContext *ctx, int reg, TCGv ea) |
340 | { | |
341 | TCGv temp = tcg_temp_new(); | |
342 | TCGv temp2 = tcg_temp_new(); | |
343 | tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); | |
344 | tcg_gen_movcond_tl(TCG_COND_EQ, temp2, cpu_gpr_d[reg+1], temp, | |
345 | cpu_gpr_d[reg], temp); | |
346 | tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL); | |
347 | tcg_gen_mov_tl(cpu_gpr_d[reg], temp); | |
348 | ||
349 | tcg_temp_free(temp); | |
350 | tcg_temp_free(temp2); | |
351 | } | |
352 | ||
ddd8cebe BK |
353 | static void gen_swapmsk(DisasContext *ctx, int reg, TCGv ea) |
354 | { | |
355 | TCGv temp = tcg_temp_new(); | |
356 | TCGv temp2 = tcg_temp_new(); | |
357 | TCGv temp3 = tcg_temp_new(); | |
358 | ||
359 | tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); | |
360 | tcg_gen_and_tl(temp2, cpu_gpr_d[reg], cpu_gpr_d[reg+1]); | |
361 | tcg_gen_andc_tl(temp3, temp, cpu_gpr_d[reg+1]); | |
362 | tcg_gen_or_tl(temp2, temp2, temp3); | |
363 | tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL); | |
364 | tcg_gen_mov_tl(cpu_gpr_d[reg], temp); | |
365 | ||
366 | tcg_temp_free(temp); | |
367 | tcg_temp_free(temp2); | |
368 | tcg_temp_free(temp3); | |
369 | } | |
370 | ||
371 | ||
2b2f7d97 BK |
372 | /* We generate loads and store to core special function register (csfr) through |
373 | the function gen_mfcr and gen_mtcr. To handle access permissions, we use 3 | |
374 | makros R, A and E, which allow read-only, all and endinit protected access. | |
375 | These makros also specify in which ISA version the csfr was introduced. */ | |
376 | #define R(ADDRESS, REG, FEATURE) \ | |
377 | case ADDRESS: \ | |
44ee3baf | 378 | if (has_feature(ctx, FEATURE)) { \ |
2b2f7d97 BK |
379 | tcg_gen_ld_tl(ret, cpu_env, offsetof(CPUTriCoreState, REG)); \ |
380 | } \ | |
381 | break; | |
382 | #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) | |
383 | #define E(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) | |
2db92a0c | 384 | static inline void gen_mfcr(DisasContext *ctx, TCGv ret, int32_t offset) |
2b2f7d97 BK |
385 | { |
386 | /* since we're caching PSW make this a special case */ | |
387 | if (offset == 0xfe04) { | |
388 | gen_helper_psw_read(ret, cpu_env); | |
389 | } else { | |
390 | switch (offset) { | |
391 | #include "csfr.def" | |
392 | } | |
393 | } | |
394 | } | |
395 | #undef R | |
396 | #undef A | |
397 | #undef E | |
398 | ||
399 | #define R(ADDRESS, REG, FEATURE) /* don't gen writes to read-only reg, | |
400 | since no execption occurs */ | |
401 | #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) \ | |
402 | case ADDRESS: \ | |
44ee3baf | 403 | if (has_feature(ctx, FEATURE)) { \ |
2b2f7d97 BK |
404 | tcg_gen_st_tl(r1, cpu_env, offsetof(CPUTriCoreState, REG)); \ |
405 | } \ | |
406 | break; | |
407 | /* Endinit protected registers | |
408 | TODO: Since the endinit bit is in a register of a not yet implemented | |
409 | watchdog device, we handle endinit protected registers like | |
410 | all-access registers for now. */ | |
411 | #define E(ADDRESS, REG, FEATURE) A(ADDRESS, REG, FEATURE) | |
2db92a0c | 412 | static inline void gen_mtcr(DisasContext *ctx, TCGv r1, |
2b2f7d97 BK |
413 | int32_t offset) |
414 | { | |
40a1f64b | 415 | if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM) { |
2b2f7d97 BK |
416 | /* since we're caching PSW make this a special case */ |
417 | if (offset == 0xfe04) { | |
418 | gen_helper_psw_write(cpu_env, r1); | |
419 | } else { | |
420 | switch (offset) { | |
421 | #include "csfr.def" | |
422 | } | |
423 | } | |
424 | } else { | |
425 | /* generate privilege trap */ | |
426 | } | |
427 | } | |
428 | ||
0707ec1b BK |
429 | /* Functions for arithmetic instructions */ |
430 | ||
431 | static inline void gen_add_d(TCGv ret, TCGv r1, TCGv r2) | |
432 | { | |
433 | TCGv t0 = tcg_temp_new_i32(); | |
434 | TCGv result = tcg_temp_new_i32(); | |
435 | /* Addition and set V/SV bits */ | |
436 | tcg_gen_add_tl(result, r1, r2); | |
437 | /* calc V bit */ | |
438 | tcg_gen_xor_tl(cpu_PSW_V, result, r1); | |
439 | tcg_gen_xor_tl(t0, r1, r2); | |
440 | tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0); | |
441 | /* Calc SV bit */ | |
442 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
443 | /* Calc AV/SAV bits */ | |
444 | tcg_gen_add_tl(cpu_PSW_AV, result, result); | |
445 | tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); | |
446 | /* calc SAV */ | |
447 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
448 | /* write back result */ | |
449 | tcg_gen_mov_tl(ret, result); | |
450 | ||
451 | tcg_temp_free(result); | |
452 | tcg_temp_free(t0); | |
453 | } | |
454 | ||
2e430e1c BK |
455 | static inline void |
456 | gen_add64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2) | |
457 | { | |
458 | TCGv temp = tcg_temp_new(); | |
459 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
460 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
461 | TCGv_i64 result = tcg_temp_new_i64(); | |
462 | ||
463 | tcg_gen_add_i64(result, r1, r2); | |
464 | /* calc v bit */ | |
465 | tcg_gen_xor_i64(t1, result, r1); | |
466 | tcg_gen_xor_i64(t0, r1, r2); | |
467 | tcg_gen_andc_i64(t1, t1, t0); | |
609ad705 | 468 | tcg_gen_extrh_i64_i32(cpu_PSW_V, t1); |
2e430e1c BK |
469 | /* calc SV bit */ |
470 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
471 | /* calc AV/SAV bits */ | |
609ad705 | 472 | tcg_gen_extrh_i64_i32(temp, result); |
2e430e1c BK |
473 | tcg_gen_add_tl(cpu_PSW_AV, temp, temp); |
474 | tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV); | |
475 | /* calc SAV */ | |
476 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
477 | /* write back result */ | |
478 | tcg_gen_mov_i64(ret, result); | |
479 | ||
480 | tcg_temp_free(temp); | |
481 | tcg_temp_free_i64(result); | |
482 | tcg_temp_free_i64(t0); | |
483 | tcg_temp_free_i64(t1); | |
484 | } | |
485 | ||
486 | static inline void | |
487 | gen_addsub64_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, | |
488 | TCGv r3, void(*op1)(TCGv, TCGv, TCGv), | |
489 | void(*op2)(TCGv, TCGv, TCGv)) | |
490 | { | |
491 | TCGv temp = tcg_temp_new(); | |
492 | TCGv temp2 = tcg_temp_new(); | |
493 | TCGv temp3 = tcg_temp_new(); | |
494 | TCGv temp4 = tcg_temp_new(); | |
495 | ||
496 | (*op1)(temp, r1_low, r2); | |
497 | /* calc V0 bit */ | |
498 | tcg_gen_xor_tl(temp2, temp, r1_low); | |
499 | tcg_gen_xor_tl(temp3, r1_low, r2); | |
500 | if (op1 == tcg_gen_add_tl) { | |
501 | tcg_gen_andc_tl(temp2, temp2, temp3); | |
502 | } else { | |
503 | tcg_gen_and_tl(temp2, temp2, temp3); | |
504 | } | |
505 | ||
506 | (*op2)(temp3, r1_high, r3); | |
507 | /* calc V1 bit */ | |
508 | tcg_gen_xor_tl(cpu_PSW_V, temp3, r1_high); | |
509 | tcg_gen_xor_tl(temp4, r1_high, r3); | |
510 | if (op2 == tcg_gen_add_tl) { | |
511 | tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, temp4); | |
512 | } else { | |
513 | tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp4); | |
514 | } | |
515 | /* combine V0/V1 bits */ | |
516 | tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp2); | |
517 | /* calc sv bit */ | |
518 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
519 | /* write result */ | |
520 | tcg_gen_mov_tl(ret_low, temp); | |
521 | tcg_gen_mov_tl(ret_high, temp3); | |
522 | /* calc AV bit */ | |
523 | tcg_gen_add_tl(temp, ret_low, ret_low); | |
524 | tcg_gen_xor_tl(temp, temp, ret_low); | |
525 | tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); | |
526 | tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, ret_high); | |
527 | tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp); | |
528 | /* calc SAV bit */ | |
529 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
530 | ||
531 | tcg_temp_free(temp); | |
532 | tcg_temp_free(temp2); | |
533 | tcg_temp_free(temp3); | |
534 | tcg_temp_free(temp4); | |
535 | } | |
536 | ||
328f1f0f BK |
537 | /* ret = r2 + (r1 * r3); */ |
538 | static inline void gen_madd32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3) | |
539 | { | |
540 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
541 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
542 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
543 | ||
544 | tcg_gen_ext_i32_i64(t1, r1); | |
545 | tcg_gen_ext_i32_i64(t2, r2); | |
546 | tcg_gen_ext_i32_i64(t3, r3); | |
547 | ||
548 | tcg_gen_mul_i64(t1, t1, t3); | |
549 | tcg_gen_add_i64(t1, t2, t1); | |
550 | ||
ecc7b3aa | 551 | tcg_gen_extrl_i64_i32(ret, t1); |
328f1f0f BK |
552 | /* calc V |
553 | t1 > 0x7fffffff */ | |
554 | tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL); | |
555 | /* t1 < -0x80000000 */ | |
556 | tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL); | |
557 | tcg_gen_or_i64(t2, t2, t3); | |
ecc7b3aa | 558 | tcg_gen_extrl_i64_i32(cpu_PSW_V, t2); |
328f1f0f BK |
559 | tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); |
560 | /* Calc SV bit */ | |
561 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
562 | /* Calc AV/SAV bits */ | |
563 | tcg_gen_add_tl(cpu_PSW_AV, ret, ret); | |
564 | tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); | |
565 | /* calc SAV */ | |
566 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
567 | ||
568 | tcg_temp_free_i64(t1); | |
569 | tcg_temp_free_i64(t2); | |
570 | tcg_temp_free_i64(t3); | |
571 | } | |
572 | ||
573 | static inline void gen_maddi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con) | |
574 | { | |
575 | TCGv temp = tcg_const_i32(con); | |
576 | gen_madd32_d(ret, r1, r2, temp); | |
577 | tcg_temp_free(temp); | |
578 | } | |
579 | ||
580 | static inline void | |
581 | gen_madd64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
582 | TCGv r3) | |
583 | { | |
584 | TCGv t1 = tcg_temp_new(); | |
585 | TCGv t2 = tcg_temp_new(); | |
586 | TCGv t3 = tcg_temp_new(); | |
587 | TCGv t4 = tcg_temp_new(); | |
588 | ||
589 | tcg_gen_muls2_tl(t1, t2, r1, r3); | |
590 | /* only the add can overflow */ | |
591 | tcg_gen_add2_tl(t3, t4, r2_low, r2_high, t1, t2); | |
592 | /* calc V bit */ | |
593 | tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high); | |
594 | tcg_gen_xor_tl(t1, r2_high, t2); | |
595 | tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t1); | |
596 | /* Calc SV bit */ | |
597 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
598 | /* Calc AV/SAV bits */ | |
599 | tcg_gen_add_tl(cpu_PSW_AV, t4, t4); | |
600 | tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV); | |
601 | /* calc SAV */ | |
602 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
603 | /* write back the result */ | |
604 | tcg_gen_mov_tl(ret_low, t3); | |
605 | tcg_gen_mov_tl(ret_high, t4); | |
606 | ||
607 | tcg_temp_free(t1); | |
608 | tcg_temp_free(t2); | |
609 | tcg_temp_free(t3); | |
610 | tcg_temp_free(t4); | |
611 | } | |
612 | ||
613 | static inline void | |
614 | gen_maddu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
615 | TCGv r3) | |
616 | { | |
617 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
618 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
619 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
620 | ||
621 | tcg_gen_extu_i32_i64(t1, r1); | |
622 | tcg_gen_concat_i32_i64(t2, r2_low, r2_high); | |
623 | tcg_gen_extu_i32_i64(t3, r3); | |
624 | ||
625 | tcg_gen_mul_i64(t1, t1, t3); | |
626 | tcg_gen_add_i64(t2, t2, t1); | |
627 | /* write back result */ | |
628 | tcg_gen_extr_i64_i32(ret_low, ret_high, t2); | |
629 | /* only the add overflows, if t2 < t1 | |
630 | calc V bit */ | |
631 | tcg_gen_setcond_i64(TCG_COND_LTU, t2, t2, t1); | |
ecc7b3aa | 632 | tcg_gen_extrl_i64_i32(cpu_PSW_V, t2); |
328f1f0f BK |
633 | tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); |
634 | /* Calc SV bit */ | |
635 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
636 | /* Calc AV/SAV bits */ | |
637 | tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); | |
638 | tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); | |
639 | /* calc SAV */ | |
640 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
641 | ||
642 | tcg_temp_free_i64(t1); | |
643 | tcg_temp_free_i64(t2); | |
644 | tcg_temp_free_i64(t3); | |
645 | } | |
646 | ||
647 | static inline void | |
648 | gen_maddi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
649 | int32_t con) | |
650 | { | |
651 | TCGv temp = tcg_const_i32(con); | |
652 | gen_madd64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); | |
653 | tcg_temp_free(temp); | |
654 | } | |
655 | ||
656 | static inline void | |
657 | gen_maddui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
658 | int32_t con) | |
659 | { | |
660 | TCGv temp = tcg_const_i32(con); | |
661 | gen_maddu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); | |
662 | tcg_temp_free(temp); | |
663 | } | |
664 | ||
2e430e1c BK |
665 | static inline void |
666 | gen_madd_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, | |
667 | TCGv r3, uint32_t n, uint32_t mode) | |
668 | { | |
669 | TCGv temp = tcg_const_i32(n); | |
670 | TCGv temp2 = tcg_temp_new(); | |
671 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
672 | switch (mode) { | |
673 | case MODE_LL: | |
674 | GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); | |
675 | break; | |
676 | case MODE_LU: | |
677 | GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); | |
678 | break; | |
679 | case MODE_UL: | |
680 | GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); | |
681 | break; | |
682 | case MODE_UU: | |
683 | GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); | |
684 | break; | |
685 | } | |
686 | tcg_gen_extr_i64_i32(temp, temp2, temp64); | |
687 | gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, | |
688 | tcg_gen_add_tl, tcg_gen_add_tl); | |
689 | tcg_temp_free(temp); | |
690 | tcg_temp_free(temp2); | |
691 | tcg_temp_free_i64(temp64); | |
692 | } | |
693 | ||
bebe80fc BK |
694 | static inline void |
695 | gen_maddsu_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, | |
696 | TCGv r3, uint32_t n, uint32_t mode) | |
697 | { | |
698 | TCGv temp = tcg_const_i32(n); | |
699 | TCGv temp2 = tcg_temp_new(); | |
700 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
701 | switch (mode) { | |
702 | case MODE_LL: | |
703 | GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); | |
704 | break; | |
705 | case MODE_LU: | |
706 | GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); | |
707 | break; | |
708 | case MODE_UL: | |
709 | GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); | |
710 | break; | |
711 | case MODE_UU: | |
712 | GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); | |
713 | break; | |
714 | } | |
715 | tcg_gen_extr_i64_i32(temp, temp2, temp64); | |
716 | gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, | |
717 | tcg_gen_sub_tl, tcg_gen_add_tl); | |
718 | tcg_temp_free(temp); | |
719 | tcg_temp_free(temp2); | |
720 | tcg_temp_free_i64(temp64); | |
721 | } | |
722 | ||
723 | static inline void | |
724 | gen_maddsum_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, | |
725 | TCGv r3, uint32_t n, uint32_t mode) | |
726 | { | |
727 | TCGv temp = tcg_const_i32(n); | |
728 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
729 | TCGv_i64 temp64_2 = tcg_temp_new_i64(); | |
730 | TCGv_i64 temp64_3 = tcg_temp_new_i64(); | |
731 | switch (mode) { | |
732 | case MODE_LL: | |
733 | GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); | |
734 | break; | |
735 | case MODE_LU: | |
736 | GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); | |
737 | break; | |
738 | case MODE_UL: | |
739 | GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); | |
740 | break; | |
741 | case MODE_UU: | |
742 | GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); | |
743 | break; | |
744 | } | |
745 | tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high); | |
746 | tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ | |
747 | tcg_gen_ext32s_i64(temp64, temp64); /* low */ | |
748 | tcg_gen_sub_i64(temp64, temp64_2, temp64); | |
749 | tcg_gen_shli_i64(temp64, temp64, 16); | |
750 | ||
751 | gen_add64_d(temp64_2, temp64_3, temp64); | |
752 | /* write back result */ | |
753 | tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2); | |
754 | ||
755 | tcg_temp_free(temp); | |
756 | tcg_temp_free_i64(temp64); | |
757 | tcg_temp_free_i64(temp64_2); | |
758 | tcg_temp_free_i64(temp64_3); | |
759 | } | |
760 | ||
2e430e1c BK |
761 | static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2); |
762 | ||
763 | static inline void | |
764 | gen_madds_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, | |
765 | TCGv r3, uint32_t n, uint32_t mode) | |
766 | { | |
767 | TCGv temp = tcg_const_i32(n); | |
768 | TCGv temp2 = tcg_temp_new(); | |
769 | TCGv temp3 = tcg_temp_new(); | |
770 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
771 | ||
772 | switch (mode) { | |
773 | case MODE_LL: | |
774 | GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); | |
775 | break; | |
776 | case MODE_LU: | |
777 | GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); | |
778 | break; | |
779 | case MODE_UL: | |
780 | GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); | |
781 | break; | |
782 | case MODE_UU: | |
783 | GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); | |
784 | break; | |
785 | } | |
786 | tcg_gen_extr_i64_i32(temp, temp2, temp64); | |
787 | gen_adds(ret_low, r1_low, temp); | |
788 | tcg_gen_mov_tl(temp, cpu_PSW_V); | |
789 | tcg_gen_mov_tl(temp3, cpu_PSW_AV); | |
790 | gen_adds(ret_high, r1_high, temp2); | |
791 | /* combine v bits */ | |
792 | tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); | |
793 | /* combine av bits */ | |
794 | tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); | |
795 | ||
796 | tcg_temp_free(temp); | |
797 | tcg_temp_free(temp2); | |
798 | tcg_temp_free(temp3); | |
799 | tcg_temp_free_i64(temp64); | |
800 | ||
801 | } | |
802 | ||
bebe80fc BK |
803 | static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2); |
804 | ||
805 | static inline void | |
806 | gen_maddsus_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, | |
807 | TCGv r3, uint32_t n, uint32_t mode) | |
808 | { | |
809 | TCGv temp = tcg_const_i32(n); | |
810 | TCGv temp2 = tcg_temp_new(); | |
811 | TCGv temp3 = tcg_temp_new(); | |
812 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
813 | ||
814 | switch (mode) { | |
815 | case MODE_LL: | |
816 | GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); | |
817 | break; | |
818 | case MODE_LU: | |
819 | GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); | |
820 | break; | |
821 | case MODE_UL: | |
822 | GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); | |
823 | break; | |
824 | case MODE_UU: | |
825 | GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); | |
826 | break; | |
827 | } | |
828 | tcg_gen_extr_i64_i32(temp, temp2, temp64); | |
829 | gen_subs(ret_low, r1_low, temp); | |
830 | tcg_gen_mov_tl(temp, cpu_PSW_V); | |
831 | tcg_gen_mov_tl(temp3, cpu_PSW_AV); | |
832 | gen_adds(ret_high, r1_high, temp2); | |
833 | /* combine v bits */ | |
834 | tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); | |
835 | /* combine av bits */ | |
836 | tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); | |
837 | ||
838 | tcg_temp_free(temp); | |
839 | tcg_temp_free(temp2); | |
840 | tcg_temp_free(temp3); | |
841 | tcg_temp_free_i64(temp64); | |
842 | ||
843 | } | |
844 | ||
845 | static inline void | |
846 | gen_maddsums_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, | |
847 | TCGv r3, uint32_t n, uint32_t mode) | |
848 | { | |
849 | TCGv temp = tcg_const_i32(n); | |
850 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
851 | TCGv_i64 temp64_2 = tcg_temp_new_i64(); | |
852 | ||
853 | switch (mode) { | |
854 | case MODE_LL: | |
855 | GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); | |
856 | break; | |
857 | case MODE_LU: | |
858 | GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); | |
859 | break; | |
860 | case MODE_UL: | |
861 | GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); | |
862 | break; | |
863 | case MODE_UU: | |
864 | GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); | |
865 | break; | |
866 | } | |
867 | tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ | |
868 | tcg_gen_ext32s_i64(temp64, temp64); /* low */ | |
869 | tcg_gen_sub_i64(temp64, temp64_2, temp64); | |
870 | tcg_gen_shli_i64(temp64, temp64, 16); | |
871 | tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); | |
872 | ||
873 | gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64); | |
874 | tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); | |
875 | ||
876 | tcg_temp_free(temp); | |
877 | tcg_temp_free_i64(temp64); | |
878 | tcg_temp_free_i64(temp64_2); | |
879 | } | |
880 | ||
881 | ||
2e430e1c BK |
882 | static inline void |
883 | gen_maddm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, | |
884 | TCGv r3, uint32_t n, uint32_t mode) | |
885 | { | |
886 | TCGv temp = tcg_const_i32(n); | |
887 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
888 | TCGv_i64 temp64_2 = tcg_temp_new_i64(); | |
889 | TCGv_i64 temp64_3 = tcg_temp_new_i64(); | |
890 | switch (mode) { | |
891 | case MODE_LL: | |
892 | GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp); | |
893 | break; | |
894 | case MODE_LU: | |
895 | GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp); | |
896 | break; | |
897 | case MODE_UL: | |
898 | GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp); | |
899 | break; | |
900 | case MODE_UU: | |
901 | GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp); | |
902 | break; | |
903 | } | |
904 | tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); | |
905 | gen_add64_d(temp64_3, temp64_2, temp64); | |
906 | /* write back result */ | |
907 | tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3); | |
908 | ||
909 | tcg_temp_free(temp); | |
910 | tcg_temp_free_i64(temp64); | |
911 | tcg_temp_free_i64(temp64_2); | |
912 | tcg_temp_free_i64(temp64_3); | |
913 | } | |
914 | ||
915 | static inline void | |
916 | gen_maddms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, | |
917 | TCGv r3, uint32_t n, uint32_t mode) | |
918 | { | |
919 | TCGv temp = tcg_const_i32(n); | |
920 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
921 | TCGv_i64 temp64_2 = tcg_temp_new_i64(); | |
922 | switch (mode) { | |
923 | case MODE_LL: | |
924 | GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp); | |
925 | break; | |
926 | case MODE_LU: | |
927 | GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp); | |
928 | break; | |
929 | case MODE_UL: | |
930 | GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp); | |
931 | break; | |
932 | case MODE_UU: | |
933 | GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp); | |
934 | break; | |
935 | } | |
936 | tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); | |
937 | gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64); | |
938 | tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); | |
939 | ||
940 | tcg_temp_free(temp); | |
941 | tcg_temp_free_i64(temp64); | |
942 | tcg_temp_free_i64(temp64_2); | |
943 | } | |
944 | ||
945 | static inline void | |
946 | gen_maddr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n, | |
947 | uint32_t mode) | |
948 | { | |
949 | TCGv temp = tcg_const_i32(n); | |
950 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
951 | switch (mode) { | |
952 | case MODE_LL: | |
953 | GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); | |
954 | break; | |
955 | case MODE_LU: | |
956 | GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); | |
957 | break; | |
958 | case MODE_UL: | |
959 | GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); | |
960 | break; | |
961 | case MODE_UU: | |
962 | GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); | |
963 | break; | |
964 | } | |
965 | gen_helper_addr_h(ret, cpu_env, temp64, r1_low, r1_high); | |
966 | ||
967 | tcg_temp_free(temp); | |
968 | tcg_temp_free_i64(temp64); | |
969 | } | |
970 | ||
971 | static inline void | |
972 | gen_maddr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) | |
973 | { | |
974 | TCGv temp = tcg_temp_new(); | |
975 | TCGv temp2 = tcg_temp_new(); | |
976 | ||
977 | tcg_gen_andi_tl(temp2, r1, 0xffff0000); | |
978 | tcg_gen_shli_tl(temp, r1, 16); | |
979 | gen_maddr64_h(ret, temp, temp2, r2, r3, n, mode); | |
980 | ||
981 | tcg_temp_free(temp); | |
982 | tcg_temp_free(temp2); | |
983 | } | |
984 | ||
bebe80fc BK |
985 | static inline void |
986 | gen_maddsur32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) | |
987 | { | |
988 | TCGv temp = tcg_const_i32(n); | |
989 | TCGv temp2 = tcg_temp_new(); | |
990 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
991 | switch (mode) { | |
992 | case MODE_LL: | |
993 | GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); | |
994 | break; | |
995 | case MODE_LU: | |
996 | GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); | |
997 | break; | |
998 | case MODE_UL: | |
999 | GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); | |
1000 | break; | |
1001 | case MODE_UU: | |
1002 | GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); | |
1003 | break; | |
1004 | } | |
1005 | tcg_gen_andi_tl(temp2, r1, 0xffff0000); | |
1006 | tcg_gen_shli_tl(temp, r1, 16); | |
1007 | gen_helper_addsur_h(ret, cpu_env, temp64, temp, temp2); | |
1008 | ||
1009 | tcg_temp_free(temp); | |
1010 | tcg_temp_free(temp2); | |
1011 | tcg_temp_free_i64(temp64); | |
1012 | } | |
1013 | ||
1014 | ||
2e430e1c BK |
1015 | static inline void |
1016 | gen_maddr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, | |
1017 | uint32_t n, uint32_t mode) | |
1018 | { | |
1019 | TCGv temp = tcg_const_i32(n); | |
1020 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
1021 | switch (mode) { | |
1022 | case MODE_LL: | |
1023 | GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); | |
1024 | break; | |
1025 | case MODE_LU: | |
1026 | GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); | |
1027 | break; | |
1028 | case MODE_UL: | |
1029 | GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); | |
1030 | break; | |
1031 | case MODE_UU: | |
1032 | GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); | |
1033 | break; | |
1034 | } | |
1035 | gen_helper_addr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high); | |
1036 | ||
1037 | tcg_temp_free(temp); | |
1038 | tcg_temp_free_i64(temp64); | |
1039 | } | |
1040 | ||
1041 | static inline void | |
1042 | gen_maddr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) | |
1043 | { | |
1044 | TCGv temp = tcg_temp_new(); | |
1045 | TCGv temp2 = tcg_temp_new(); | |
1046 | ||
1047 | tcg_gen_andi_tl(temp2, r1, 0xffff0000); | |
1048 | tcg_gen_shli_tl(temp, r1, 16); | |
1049 | gen_maddr64s_h(ret, temp, temp2, r2, r3, n, mode); | |
1050 | ||
1051 | tcg_temp_free(temp); | |
1052 | tcg_temp_free(temp2); | |
1053 | } | |
1054 | ||
bebe80fc BK |
1055 | static inline void |
1056 | gen_maddsur32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) | |
1057 | { | |
1058 | TCGv temp = tcg_const_i32(n); | |
1059 | TCGv temp2 = tcg_temp_new(); | |
1060 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
1061 | switch (mode) { | |
1062 | case MODE_LL: | |
1063 | GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); | |
1064 | break; | |
1065 | case MODE_LU: | |
1066 | GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); | |
1067 | break; | |
1068 | case MODE_UL: | |
1069 | GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); | |
1070 | break; | |
1071 | case MODE_UU: | |
1072 | GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); | |
1073 | break; | |
1074 | } | |
1075 | tcg_gen_andi_tl(temp2, r1, 0xffff0000); | |
1076 | tcg_gen_shli_tl(temp, r1, 16); | |
1077 | gen_helper_addsur_h_ssov(ret, cpu_env, temp64, temp, temp2); | |
1078 | ||
1079 | tcg_temp_free(temp); | |
1080 | tcg_temp_free(temp2); | |
1081 | tcg_temp_free_i64(temp64); | |
1082 | } | |
1083 | ||
b00aa8ec BK |
1084 | static inline void |
1085 | gen_maddr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) | |
1086 | { | |
1087 | TCGv temp = tcg_const_i32(n); | |
1088 | gen_helper_maddr_q(ret, cpu_env, r1, r2, r3, temp); | |
1089 | tcg_temp_free(temp); | |
1090 | } | |
1091 | ||
1092 | static inline void | |
1093 | gen_maddrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) | |
1094 | { | |
1095 | TCGv temp = tcg_const_i32(n); | |
1096 | gen_helper_maddr_q_ssov(ret, cpu_env, r1, r2, r3, temp); | |
1097 | tcg_temp_free(temp); | |
1098 | } | |
1099 | ||
1100 | static inline void | |
1101 | gen_madd32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, | |
2db92a0c | 1102 | uint32_t up_shift) |
b00aa8ec BK |
1103 | { |
1104 | TCGv temp = tcg_temp_new(); | |
1105 | TCGv temp2 = tcg_temp_new(); | |
1106 | TCGv temp3 = tcg_temp_new(); | |
1107 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1108 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
1109 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
1110 | ||
1111 | tcg_gen_ext_i32_i64(t2, arg2); | |
1112 | tcg_gen_ext_i32_i64(t3, arg3); | |
1113 | ||
1114 | tcg_gen_mul_i64(t2, t2, t3); | |
1115 | tcg_gen_shli_i64(t2, t2, n); | |
1116 | ||
1117 | tcg_gen_ext_i32_i64(t1, arg1); | |
1118 | tcg_gen_sari_i64(t2, t2, up_shift); | |
1119 | ||
1120 | tcg_gen_add_i64(t3, t1, t2); | |
ecc7b3aa | 1121 | tcg_gen_extrl_i64_i32(temp3, t3); |
b00aa8ec BK |
1122 | /* calc v bit */ |
1123 | tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL); | |
1124 | tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL); | |
1125 | tcg_gen_or_i64(t1, t1, t2); | |
ecc7b3aa | 1126 | tcg_gen_extrl_i64_i32(cpu_PSW_V, t1); |
b00aa8ec BK |
1127 | tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); |
1128 | /* We produce an overflow on the host if the mul before was | |
1129 | (0x80000000 * 0x80000000) << 1). If this is the | |
1130 | case, we negate the ovf. */ | |
1131 | if (n == 1) { | |
1132 | tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000); | |
1133 | tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3); | |
1134 | tcg_gen_and_tl(temp, temp, temp2); | |
1135 | tcg_gen_shli_tl(temp, temp, 31); | |
1136 | /* negate v bit, if special condition */ | |
1137 | tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp); | |
1138 | } | |
1139 | /* Calc SV bit */ | |
1140 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
1141 | /* Calc AV/SAV bits */ | |
1142 | tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3); | |
1143 | tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV); | |
1144 | /* calc SAV */ | |
1145 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
1146 | /* write back result */ | |
1147 | tcg_gen_mov_tl(ret, temp3); | |
1148 | ||
1149 | tcg_temp_free(temp); | |
1150 | tcg_temp_free(temp2); | |
1151 | tcg_temp_free(temp3); | |
1152 | tcg_temp_free_i64(t1); | |
1153 | tcg_temp_free_i64(t2); | |
1154 | tcg_temp_free_i64(t3); | |
1155 | } | |
1156 | ||
1157 | static inline void | |
1158 | gen_m16add32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n) | |
1159 | { | |
1160 | TCGv temp = tcg_temp_new(); | |
1161 | TCGv temp2 = tcg_temp_new(); | |
1162 | if (n == 0) { | |
1163 | tcg_gen_mul_tl(temp, arg2, arg3); | |
de7ad4ce | 1164 | } else { /* n is expected to be 1 */ |
b00aa8ec BK |
1165 | tcg_gen_mul_tl(temp, arg2, arg3); |
1166 | tcg_gen_shli_tl(temp, temp, 1); | |
1167 | /* catch special case r1 = r2 = 0x8000 */ | |
1168 | tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); | |
1169 | tcg_gen_sub_tl(temp, temp, temp2); | |
1170 | } | |
1171 | gen_add_d(ret, arg1, temp); | |
1172 | ||
1173 | tcg_temp_free(temp); | |
1174 | tcg_temp_free(temp2); | |
1175 | } | |
1176 | ||
1177 | static inline void | |
1178 | gen_m16adds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n) | |
1179 | { | |
1180 | TCGv temp = tcg_temp_new(); | |
1181 | TCGv temp2 = tcg_temp_new(); | |
1182 | if (n == 0) { | |
1183 | tcg_gen_mul_tl(temp, arg2, arg3); | |
de7ad4ce | 1184 | } else { /* n is expected to be 1 */ |
b00aa8ec BK |
1185 | tcg_gen_mul_tl(temp, arg2, arg3); |
1186 | tcg_gen_shli_tl(temp, temp, 1); | |
1187 | /* catch special case r1 = r2 = 0x8000 */ | |
1188 | tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); | |
1189 | tcg_gen_sub_tl(temp, temp, temp2); | |
1190 | } | |
1191 | gen_adds(ret, arg1, temp); | |
1192 | ||
1193 | tcg_temp_free(temp); | |
1194 | tcg_temp_free(temp2); | |
1195 | } | |
1196 | ||
1197 | static inline void | |
1198 | gen_m16add64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, | |
1199 | TCGv arg3, uint32_t n) | |
1200 | { | |
1201 | TCGv temp = tcg_temp_new(); | |
1202 | TCGv temp2 = tcg_temp_new(); | |
1203 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1204 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
1205 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
1206 | ||
1207 | if (n == 0) { | |
1208 | tcg_gen_mul_tl(temp, arg2, arg3); | |
de7ad4ce | 1209 | } else { /* n is expected to be 1 */ |
b00aa8ec BK |
1210 | tcg_gen_mul_tl(temp, arg2, arg3); |
1211 | tcg_gen_shli_tl(temp, temp, 1); | |
1212 | /* catch special case r1 = r2 = 0x8000 */ | |
1213 | tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); | |
1214 | tcg_gen_sub_tl(temp, temp, temp2); | |
1215 | } | |
1216 | tcg_gen_ext_i32_i64(t2, temp); | |
1217 | tcg_gen_shli_i64(t2, t2, 16); | |
1218 | tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); | |
1219 | gen_add64_d(t3, t1, t2); | |
1220 | /* write back result */ | |
1221 | tcg_gen_extr_i64_i32(rl, rh, t3); | |
1222 | ||
1223 | tcg_temp_free_i64(t1); | |
1224 | tcg_temp_free_i64(t2); | |
1225 | tcg_temp_free_i64(t3); | |
1226 | tcg_temp_free(temp); | |
1227 | tcg_temp_free(temp2); | |
1228 | } | |
1229 | ||
1230 | static inline void | |
1231 | gen_m16adds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, | |
1232 | TCGv arg3, uint32_t n) | |
1233 | { | |
1234 | TCGv temp = tcg_temp_new(); | |
1235 | TCGv temp2 = tcg_temp_new(); | |
1236 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1237 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
1238 | ||
1239 | if (n == 0) { | |
1240 | tcg_gen_mul_tl(temp, arg2, arg3); | |
de7ad4ce | 1241 | } else { /* n is expected to be 1 */ |
b00aa8ec BK |
1242 | tcg_gen_mul_tl(temp, arg2, arg3); |
1243 | tcg_gen_shli_tl(temp, temp, 1); | |
1244 | /* catch special case r1 = r2 = 0x8000 */ | |
1245 | tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); | |
1246 | tcg_gen_sub_tl(temp, temp, temp2); | |
1247 | } | |
1248 | tcg_gen_ext_i32_i64(t2, temp); | |
1249 | tcg_gen_shli_i64(t2, t2, 16); | |
1250 | tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); | |
1251 | ||
1252 | gen_helper_add64_ssov(t1, cpu_env, t1, t2); | |
1253 | tcg_gen_extr_i64_i32(rl, rh, t1); | |
1254 | ||
1255 | tcg_temp_free(temp); | |
1256 | tcg_temp_free(temp2); | |
1257 | tcg_temp_free_i64(t1); | |
1258 | tcg_temp_free_i64(t2); | |
1259 | } | |
1260 | ||
1261 | static inline void | |
1262 | gen_madd64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, | |
2db92a0c | 1263 | TCGv arg3, uint32_t n) |
b00aa8ec BK |
1264 | { |
1265 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1266 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
1267 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
1268 | TCGv_i64 t4 = tcg_temp_new_i64(); | |
1269 | TCGv temp, temp2; | |
1270 | ||
1271 | tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); | |
1272 | tcg_gen_ext_i32_i64(t2, arg2); | |
1273 | tcg_gen_ext_i32_i64(t3, arg3); | |
1274 | ||
1275 | tcg_gen_mul_i64(t2, t2, t3); | |
1276 | if (n != 0) { | |
1277 | tcg_gen_shli_i64(t2, t2, 1); | |
1278 | } | |
1279 | tcg_gen_add_i64(t4, t1, t2); | |
1280 | /* calc v bit */ | |
1281 | tcg_gen_xor_i64(t3, t4, t1); | |
1282 | tcg_gen_xor_i64(t2, t1, t2); | |
1283 | tcg_gen_andc_i64(t3, t3, t2); | |
609ad705 | 1284 | tcg_gen_extrh_i64_i32(cpu_PSW_V, t3); |
b00aa8ec BK |
1285 | /* We produce an overflow on the host if the mul before was |
1286 | (0x80000000 * 0x80000000) << 1). If this is the | |
1287 | case, we negate the ovf. */ | |
1288 | if (n == 1) { | |
1289 | temp = tcg_temp_new(); | |
1290 | temp2 = tcg_temp_new(); | |
1291 | tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000); | |
1292 | tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3); | |
1293 | tcg_gen_and_tl(temp, temp, temp2); | |
1294 | tcg_gen_shli_tl(temp, temp, 31); | |
1295 | /* negate v bit, if special condition */ | |
1296 | tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp); | |
1297 | ||
1298 | tcg_temp_free(temp); | |
1299 | tcg_temp_free(temp2); | |
1300 | } | |
1301 | /* write back result */ | |
1302 | tcg_gen_extr_i64_i32(rl, rh, t4); | |
1303 | /* Calc SV bit */ | |
1304 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
1305 | /* Calc AV/SAV bits */ | |
1306 | tcg_gen_add_tl(cpu_PSW_AV, rh, rh); | |
1307 | tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV); | |
1308 | /* calc SAV */ | |
1309 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
1310 | ||
1311 | tcg_temp_free_i64(t1); | |
1312 | tcg_temp_free_i64(t2); | |
1313 | tcg_temp_free_i64(t3); | |
1314 | tcg_temp_free_i64(t4); | |
1315 | } | |
1316 | ||
1317 | static inline void | |
1318 | gen_madds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, | |
1319 | uint32_t up_shift) | |
1320 | { | |
1321 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1322 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
1323 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
1324 | ||
1325 | tcg_gen_ext_i32_i64(t1, arg1); | |
1326 | tcg_gen_ext_i32_i64(t2, arg2); | |
1327 | tcg_gen_ext_i32_i64(t3, arg3); | |
1328 | ||
1329 | tcg_gen_mul_i64(t2, t2, t3); | |
1330 | tcg_gen_sari_i64(t2, t2, up_shift - n); | |
1331 | ||
1332 | gen_helper_madd32_q_add_ssov(ret, cpu_env, t1, t2); | |
1333 | ||
1334 | tcg_temp_free_i64(t1); | |
1335 | tcg_temp_free_i64(t2); | |
1336 | tcg_temp_free_i64(t3); | |
1337 | } | |
1338 | ||
1339 | static inline void | |
1340 | gen_madds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, | |
1341 | TCGv arg3, uint32_t n) | |
1342 | { | |
1343 | TCGv_i64 r1 = tcg_temp_new_i64(); | |
1344 | TCGv temp = tcg_const_i32(n); | |
1345 | ||
1346 | tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high); | |
1347 | gen_helper_madd64_q_ssov(r1, cpu_env, r1, arg2, arg3, temp); | |
1348 | tcg_gen_extr_i64_i32(rl, rh, r1); | |
2e430e1c | 1349 | |
b00aa8ec BK |
1350 | tcg_temp_free_i64(r1); |
1351 | tcg_temp_free(temp); | |
1352 | } | |
328f1f0f BK |
1353 | /* ret = r2 - (r1 * r3); */ |
1354 | static inline void gen_msub32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3) | |
1355 | { | |
1356 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1357 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
1358 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
1359 | ||
1360 | tcg_gen_ext_i32_i64(t1, r1); | |
1361 | tcg_gen_ext_i32_i64(t2, r2); | |
1362 | tcg_gen_ext_i32_i64(t3, r3); | |
1363 | ||
1364 | tcg_gen_mul_i64(t1, t1, t3); | |
1365 | tcg_gen_sub_i64(t1, t2, t1); | |
1366 | ||
ecc7b3aa | 1367 | tcg_gen_extrl_i64_i32(ret, t1); |
328f1f0f BK |
1368 | /* calc V |
1369 | t2 > 0x7fffffff */ | |
1370 | tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL); | |
1371 | /* result < -0x80000000 */ | |
1372 | tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL); | |
1373 | tcg_gen_or_i64(t2, t2, t3); | |
ecc7b3aa | 1374 | tcg_gen_extrl_i64_i32(cpu_PSW_V, t2); |
328f1f0f BK |
1375 | tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); |
1376 | ||
1377 | /* Calc SV bit */ | |
1378 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
1379 | /* Calc AV/SAV bits */ | |
1380 | tcg_gen_add_tl(cpu_PSW_AV, ret, ret); | |
1381 | tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); | |
1382 | /* calc SAV */ | |
1383 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
1384 | ||
1385 | tcg_temp_free_i64(t1); | |
1386 | tcg_temp_free_i64(t2); | |
1387 | tcg_temp_free_i64(t3); | |
1388 | } | |
1389 | ||
1390 | static inline void gen_msubi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con) | |
1391 | { | |
1392 | TCGv temp = tcg_const_i32(con); | |
1393 | gen_msub32_d(ret, r1, r2, temp); | |
1394 | tcg_temp_free(temp); | |
1395 | } | |
1396 | ||
1397 | static inline void | |
1398 | gen_msub64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
1399 | TCGv r3) | |
1400 | { | |
1401 | TCGv t1 = tcg_temp_new(); | |
1402 | TCGv t2 = tcg_temp_new(); | |
1403 | TCGv t3 = tcg_temp_new(); | |
1404 | TCGv t4 = tcg_temp_new(); | |
1405 | ||
1406 | tcg_gen_muls2_tl(t1, t2, r1, r3); | |
1407 | /* only the sub can overflow */ | |
1408 | tcg_gen_sub2_tl(t3, t4, r2_low, r2_high, t1, t2); | |
1409 | /* calc V bit */ | |
1410 | tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high); | |
1411 | tcg_gen_xor_tl(t1, r2_high, t2); | |
1412 | tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, t1); | |
1413 | /* Calc SV bit */ | |
1414 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
1415 | /* Calc AV/SAV bits */ | |
1416 | tcg_gen_add_tl(cpu_PSW_AV, t4, t4); | |
1417 | tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV); | |
1418 | /* calc SAV */ | |
1419 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
1420 | /* write back the result */ | |
1421 | tcg_gen_mov_tl(ret_low, t3); | |
1422 | tcg_gen_mov_tl(ret_high, t4); | |
1423 | ||
1424 | tcg_temp_free(t1); | |
1425 | tcg_temp_free(t2); | |
1426 | tcg_temp_free(t3); | |
1427 | tcg_temp_free(t4); | |
1428 | } | |
1429 | ||
1430 | static inline void | |
1431 | gen_msubi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
1432 | int32_t con) | |
1433 | { | |
1434 | TCGv temp = tcg_const_i32(con); | |
1435 | gen_msub64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); | |
1436 | tcg_temp_free(temp); | |
1437 | } | |
1438 | ||
1439 | static inline void | |
1440 | gen_msubu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
1441 | TCGv r3) | |
1442 | { | |
1443 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1444 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
1445 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
1446 | ||
1447 | tcg_gen_extu_i32_i64(t1, r1); | |
1448 | tcg_gen_concat_i32_i64(t2, r2_low, r2_high); | |
1449 | tcg_gen_extu_i32_i64(t3, r3); | |
1450 | ||
1451 | tcg_gen_mul_i64(t1, t1, t3); | |
1452 | tcg_gen_sub_i64(t3, t2, t1); | |
1453 | tcg_gen_extr_i64_i32(ret_low, ret_high, t3); | |
1454 | /* calc V bit, only the sub can overflow, if t1 > t2 */ | |
1455 | tcg_gen_setcond_i64(TCG_COND_GTU, t1, t1, t2); | |
ecc7b3aa | 1456 | tcg_gen_extrl_i64_i32(cpu_PSW_V, t1); |
328f1f0f BK |
1457 | tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); |
1458 | /* Calc SV bit */ | |
1459 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
1460 | /* Calc AV/SAV bits */ | |
1461 | tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); | |
1462 | tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); | |
1463 | /* calc SAV */ | |
1464 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
1465 | ||
1466 | tcg_temp_free_i64(t1); | |
1467 | tcg_temp_free_i64(t2); | |
1468 | tcg_temp_free_i64(t3); | |
1469 | } | |
1470 | ||
1471 | static inline void | |
1472 | gen_msubui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
1473 | int32_t con) | |
1474 | { | |
1475 | TCGv temp = tcg_const_i32(con); | |
1476 | gen_msubu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); | |
1477 | tcg_temp_free(temp); | |
1478 | } | |
1479 | ||
0707ec1b BK |
1480 | static inline void gen_addi_d(TCGv ret, TCGv r1, target_ulong r2) |
1481 | { | |
1482 | TCGv temp = tcg_const_i32(r2); | |
1483 | gen_add_d(ret, r1, temp); | |
1484 | tcg_temp_free(temp); | |
1485 | } | |
0974257e BK |
1486 | /* calculate the carry bit too */ |
1487 | static inline void gen_add_CC(TCGv ret, TCGv r1, TCGv r2) | |
1488 | { | |
1489 | TCGv t0 = tcg_temp_new_i32(); | |
1490 | TCGv result = tcg_temp_new_i32(); | |
1491 | ||
1492 | tcg_gen_movi_tl(t0, 0); | |
1493 | /* Addition and set C/V/SV bits */ | |
1494 | tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, r2, t0); | |
1495 | /* calc V bit */ | |
1496 | tcg_gen_xor_tl(cpu_PSW_V, result, r1); | |
1497 | tcg_gen_xor_tl(t0, r1, r2); | |
1498 | tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0); | |
1499 | /* Calc SV bit */ | |
1500 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
1501 | /* Calc AV/SAV bits */ | |
1502 | tcg_gen_add_tl(cpu_PSW_AV, result, result); | |
1503 | tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); | |
1504 | /* calc SAV */ | |
1505 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
1506 | /* write back result */ | |
1507 | tcg_gen_mov_tl(ret, result); | |
1508 | ||
1509 | tcg_temp_free(result); | |
1510 | tcg_temp_free(t0); | |
1511 | } | |
1512 | ||
1513 | static inline void gen_addi_CC(TCGv ret, TCGv r1, int32_t con) | |
1514 | { | |
1515 | TCGv temp = tcg_const_i32(con); | |
1516 | gen_add_CC(ret, r1, temp); | |
1517 | tcg_temp_free(temp); | |
1518 | } | |
1519 | ||
1520 | static inline void gen_addc_CC(TCGv ret, TCGv r1, TCGv r2) | |
1521 | { | |
1522 | TCGv carry = tcg_temp_new_i32(); | |
1523 | TCGv t0 = tcg_temp_new_i32(); | |
1524 | TCGv result = tcg_temp_new_i32(); | |
1525 | ||
1526 | tcg_gen_movi_tl(t0, 0); | |
1527 | tcg_gen_setcondi_tl(TCG_COND_NE, carry, cpu_PSW_C, 0); | |
1528 | /* Addition, carry and set C/V/SV bits */ | |
1529 | tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, carry, t0); | |
1530 | tcg_gen_add2_i32(result, cpu_PSW_C, result, cpu_PSW_C, r2, t0); | |
1531 | /* calc V bit */ | |
1532 | tcg_gen_xor_tl(cpu_PSW_V, result, r1); | |
1533 | tcg_gen_xor_tl(t0, r1, r2); | |
1534 | tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0); | |
1535 | /* Calc SV bit */ | |
1536 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
1537 | /* Calc AV/SAV bits */ | |
1538 | tcg_gen_add_tl(cpu_PSW_AV, result, result); | |
1539 | tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); | |
1540 | /* calc SAV */ | |
1541 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
1542 | /* write back result */ | |
1543 | tcg_gen_mov_tl(ret, result); | |
1544 | ||
1545 | tcg_temp_free(result); | |
1546 | tcg_temp_free(t0); | |
1547 | tcg_temp_free(carry); | |
1548 | } | |
1549 | ||
1550 | static inline void gen_addci_CC(TCGv ret, TCGv r1, int32_t con) | |
1551 | { | |
1552 | TCGv temp = tcg_const_i32(con); | |
1553 | gen_addc_CC(ret, r1, temp); | |
1554 | tcg_temp_free(temp); | |
1555 | } | |
0707ec1b BK |
1556 | |
1557 | static inline void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3, | |
1558 | TCGv r4) | |
1559 | { | |
1560 | TCGv temp = tcg_temp_new(); | |
1561 | TCGv temp2 = tcg_temp_new(); | |
1562 | TCGv result = tcg_temp_new(); | |
1563 | TCGv mask = tcg_temp_new(); | |
1564 | TCGv t0 = tcg_const_i32(0); | |
1565 | ||
1566 | /* create mask for sticky bits */ | |
1567 | tcg_gen_setcond_tl(cond, mask, r4, t0); | |
1568 | tcg_gen_shli_tl(mask, mask, 31); | |
1569 | ||
1570 | tcg_gen_add_tl(result, r1, r2); | |
1571 | /* Calc PSW_V */ | |
1572 | tcg_gen_xor_tl(temp, result, r1); | |
1573 | tcg_gen_xor_tl(temp2, r1, r2); | |
1574 | tcg_gen_andc_tl(temp, temp, temp2); | |
1575 | tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V); | |
1576 | /* Set PSW_SV */ | |
1577 | tcg_gen_and_tl(temp, temp, mask); | |
1578 | tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV); | |
1579 | /* calc AV bit */ | |
1580 | tcg_gen_add_tl(temp, result, result); | |
1581 | tcg_gen_xor_tl(temp, temp, result); | |
1582 | tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV); | |
1583 | /* calc SAV bit */ | |
1584 | tcg_gen_and_tl(temp, temp, mask); | |
1585 | tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV); | |
1586 | /* write back result */ | |
5f30046f | 1587 | tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1); |
0707ec1b BK |
1588 | |
1589 | tcg_temp_free(t0); | |
1590 | tcg_temp_free(temp); | |
1591 | tcg_temp_free(temp2); | |
1592 | tcg_temp_free(result); | |
1593 | tcg_temp_free(mask); | |
1594 | } | |
1595 | ||
1596 | static inline void gen_condi_add(TCGCond cond, TCGv r1, int32_t r2, | |
1597 | TCGv r3, TCGv r4) | |
1598 | { | |
1599 | TCGv temp = tcg_const_i32(r2); | |
1600 | gen_cond_add(cond, r1, temp, r3, r4); | |
1601 | tcg_temp_free(temp); | |
1602 | } | |
1603 | ||
2692802a BK |
1604 | static inline void gen_sub_d(TCGv ret, TCGv r1, TCGv r2) |
1605 | { | |
1606 | TCGv temp = tcg_temp_new_i32(); | |
1607 | TCGv result = tcg_temp_new_i32(); | |
1608 | ||
1609 | tcg_gen_sub_tl(result, r1, r2); | |
1610 | /* calc V bit */ | |
1611 | tcg_gen_xor_tl(cpu_PSW_V, result, r1); | |
1612 | tcg_gen_xor_tl(temp, r1, r2); | |
1613 | tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp); | |
1614 | /* calc SV bit */ | |
1615 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
1616 | /* Calc AV bit */ | |
1617 | tcg_gen_add_tl(cpu_PSW_AV, result, result); | |
1618 | tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); | |
1619 | /* calc SAV bit */ | |
1620 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
1621 | /* write back result */ | |
1622 | tcg_gen_mov_tl(ret, result); | |
1623 | ||
1624 | tcg_temp_free(temp); | |
1625 | tcg_temp_free(result); | |
1626 | } | |
1627 | ||
f4aef476 BK |
1628 | static inline void |
1629 | gen_sub64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2) | |
1630 | { | |
1631 | TCGv temp = tcg_temp_new(); | |
1632 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
1633 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1634 | TCGv_i64 result = tcg_temp_new_i64(); | |
1635 | ||
1636 | tcg_gen_sub_i64(result, r1, r2); | |
1637 | /* calc v bit */ | |
1638 | tcg_gen_xor_i64(t1, result, r1); | |
1639 | tcg_gen_xor_i64(t0, r1, r2); | |
1640 | tcg_gen_and_i64(t1, t1, t0); | |
609ad705 | 1641 | tcg_gen_extrh_i64_i32(cpu_PSW_V, t1); |
f4aef476 BK |
1642 | /* calc SV bit */ |
1643 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
1644 | /* calc AV/SAV bits */ | |
609ad705 | 1645 | tcg_gen_extrh_i64_i32(temp, result); |
f4aef476 BK |
1646 | tcg_gen_add_tl(cpu_PSW_AV, temp, temp); |
1647 | tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV); | |
1648 | /* calc SAV */ | |
1649 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
1650 | /* write back result */ | |
1651 | tcg_gen_mov_i64(ret, result); | |
1652 | ||
1653 | tcg_temp_free(temp); | |
1654 | tcg_temp_free_i64(result); | |
1655 | tcg_temp_free_i64(t0); | |
1656 | tcg_temp_free_i64(t1); | |
1657 | } | |
1658 | ||
d5de7839 BK |
1659 | static inline void gen_sub_CC(TCGv ret, TCGv r1, TCGv r2) |
1660 | { | |
1661 | TCGv result = tcg_temp_new(); | |
1662 | TCGv temp = tcg_temp_new(); | |
1663 | ||
1664 | tcg_gen_sub_tl(result, r1, r2); | |
1665 | /* calc C bit */ | |
1666 | tcg_gen_setcond_tl(TCG_COND_GEU, cpu_PSW_C, r1, r2); | |
1667 | /* calc V bit */ | |
1668 | tcg_gen_xor_tl(cpu_PSW_V, result, r1); | |
1669 | tcg_gen_xor_tl(temp, r1, r2); | |
1670 | tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp); | |
1671 | /* calc SV bit */ | |
1672 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
1673 | /* Calc AV bit */ | |
1674 | tcg_gen_add_tl(cpu_PSW_AV, result, result); | |
1675 | tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); | |
1676 | /* calc SAV bit */ | |
1677 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
1678 | /* write back result */ | |
1679 | tcg_gen_mov_tl(ret, result); | |
1680 | ||
1681 | tcg_temp_free(result); | |
1682 | tcg_temp_free(temp); | |
1683 | } | |
1684 | ||
1685 | static inline void gen_subc_CC(TCGv ret, TCGv r1, TCGv r2) | |
1686 | { | |
1687 | TCGv temp = tcg_temp_new(); | |
1688 | tcg_gen_not_tl(temp, r2); | |
1689 | gen_addc_CC(ret, r1, temp); | |
1690 | tcg_temp_free(temp); | |
1691 | } | |
1692 | ||
09532255 BK |
1693 | static inline void gen_cond_sub(TCGCond cond, TCGv r1, TCGv r2, TCGv r3, |
1694 | TCGv r4) | |
1695 | { | |
1696 | TCGv temp = tcg_temp_new(); | |
1697 | TCGv temp2 = tcg_temp_new(); | |
1698 | TCGv result = tcg_temp_new(); | |
1699 | TCGv mask = tcg_temp_new(); | |
1700 | TCGv t0 = tcg_const_i32(0); | |
1701 | ||
1702 | /* create mask for sticky bits */ | |
1703 | tcg_gen_setcond_tl(cond, mask, r4, t0); | |
1704 | tcg_gen_shli_tl(mask, mask, 31); | |
1705 | ||
1706 | tcg_gen_sub_tl(result, r1, r2); | |
1707 | /* Calc PSW_V */ | |
1708 | tcg_gen_xor_tl(temp, result, r1); | |
1709 | tcg_gen_xor_tl(temp2, r1, r2); | |
1710 | tcg_gen_and_tl(temp, temp, temp2); | |
1711 | tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V); | |
1712 | /* Set PSW_SV */ | |
1713 | tcg_gen_and_tl(temp, temp, mask); | |
1714 | tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV); | |
1715 | /* calc AV bit */ | |
1716 | tcg_gen_add_tl(temp, result, result); | |
1717 | tcg_gen_xor_tl(temp, temp, result); | |
1718 | tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV); | |
1719 | /* calc SAV bit */ | |
1720 | tcg_gen_and_tl(temp, temp, mask); | |
1721 | tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV); | |
1722 | /* write back result */ | |
1723 | tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1); | |
1724 | ||
1725 | tcg_temp_free(t0); | |
1726 | tcg_temp_free(temp); | |
1727 | tcg_temp_free(temp2); | |
1728 | tcg_temp_free(result); | |
1729 | tcg_temp_free(mask); | |
1730 | } | |
1731 | ||
f4aef476 BK |
1732 | static inline void |
1733 | gen_msub_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, | |
1734 | TCGv r3, uint32_t n, uint32_t mode) | |
1735 | { | |
1736 | TCGv temp = tcg_const_i32(n); | |
1737 | TCGv temp2 = tcg_temp_new(); | |
1738 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
1739 | switch (mode) { | |
1740 | case MODE_LL: | |
1741 | GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); | |
1742 | break; | |
1743 | case MODE_LU: | |
1744 | GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); | |
1745 | break; | |
1746 | case MODE_UL: | |
1747 | GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); | |
1748 | break; | |
1749 | case MODE_UU: | |
1750 | GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); | |
1751 | break; | |
1752 | } | |
1753 | tcg_gen_extr_i64_i32(temp, temp2, temp64); | |
1754 | gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, | |
1755 | tcg_gen_sub_tl, tcg_gen_sub_tl); | |
1756 | tcg_temp_free(temp); | |
1757 | tcg_temp_free(temp2); | |
1758 | tcg_temp_free_i64(temp64); | |
1759 | } | |
1760 | ||
1761 | static inline void | |
1762 | gen_msubs_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, | |
1763 | TCGv r3, uint32_t n, uint32_t mode) | |
1764 | { | |
1765 | TCGv temp = tcg_const_i32(n); | |
1766 | TCGv temp2 = tcg_temp_new(); | |
1767 | TCGv temp3 = tcg_temp_new(); | |
1768 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
1769 | ||
1770 | switch (mode) { | |
1771 | case MODE_LL: | |
1772 | GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); | |
1773 | break; | |
1774 | case MODE_LU: | |
1775 | GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); | |
1776 | break; | |
1777 | case MODE_UL: | |
1778 | GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); | |
1779 | break; | |
1780 | case MODE_UU: | |
1781 | GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); | |
1782 | break; | |
1783 | } | |
1784 | tcg_gen_extr_i64_i32(temp, temp2, temp64); | |
1785 | gen_subs(ret_low, r1_low, temp); | |
1786 | tcg_gen_mov_tl(temp, cpu_PSW_V); | |
1787 | tcg_gen_mov_tl(temp3, cpu_PSW_AV); | |
1788 | gen_subs(ret_high, r1_high, temp2); | |
1789 | /* combine v bits */ | |
1790 | tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); | |
1791 | /* combine av bits */ | |
1792 | tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); | |
1793 | ||
1794 | tcg_temp_free(temp); | |
1795 | tcg_temp_free(temp2); | |
1796 | tcg_temp_free(temp3); | |
1797 | tcg_temp_free_i64(temp64); | |
1798 | } | |
1799 | ||
1800 | static inline void | |
1801 | gen_msubm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, | |
1802 | TCGv r3, uint32_t n, uint32_t mode) | |
1803 | { | |
1804 | TCGv temp = tcg_const_i32(n); | |
1805 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
1806 | TCGv_i64 temp64_2 = tcg_temp_new_i64(); | |
1807 | TCGv_i64 temp64_3 = tcg_temp_new_i64(); | |
1808 | switch (mode) { | |
1809 | case MODE_LL: | |
1810 | GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp); | |
1811 | break; | |
1812 | case MODE_LU: | |
1813 | GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp); | |
1814 | break; | |
1815 | case MODE_UL: | |
1816 | GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp); | |
1817 | break; | |
1818 | case MODE_UU: | |
1819 | GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp); | |
1820 | break; | |
1821 | } | |
1822 | tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); | |
1823 | gen_sub64_d(temp64_3, temp64_2, temp64); | |
1824 | /* write back result */ | |
1825 | tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3); | |
1826 | ||
1827 | tcg_temp_free(temp); | |
1828 | tcg_temp_free_i64(temp64); | |
1829 | tcg_temp_free_i64(temp64_2); | |
1830 | tcg_temp_free_i64(temp64_3); | |
1831 | } | |
1832 | ||
1833 | static inline void | |
1834 | gen_msubms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, | |
1835 | TCGv r3, uint32_t n, uint32_t mode) | |
1836 | { | |
1837 | TCGv temp = tcg_const_i32(n); | |
1838 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
1839 | TCGv_i64 temp64_2 = tcg_temp_new_i64(); | |
1840 | switch (mode) { | |
1841 | case MODE_LL: | |
1842 | GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp); | |
1843 | break; | |
1844 | case MODE_LU: | |
1845 | GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp); | |
1846 | break; | |
1847 | case MODE_UL: | |
1848 | GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp); | |
1849 | break; | |
1850 | case MODE_UU: | |
1851 | GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp); | |
1852 | break; | |
1853 | } | |
1854 | tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); | |
1855 | gen_helper_sub64_ssov(temp64, cpu_env, temp64_2, temp64); | |
1856 | tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); | |
1857 | ||
1858 | tcg_temp_free(temp); | |
1859 | tcg_temp_free_i64(temp64); | |
1860 | tcg_temp_free_i64(temp64_2); | |
1861 | } | |
1862 | ||
1863 | static inline void | |
1864 | gen_msubr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n, | |
1865 | uint32_t mode) | |
1866 | { | |
1867 | TCGv temp = tcg_const_i32(n); | |
1868 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
1869 | switch (mode) { | |
1870 | case MODE_LL: | |
1871 | GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); | |
1872 | break; | |
1873 | case MODE_LU: | |
1874 | GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); | |
1875 | break; | |
1876 | case MODE_UL: | |
1877 | GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); | |
1878 | break; | |
1879 | case MODE_UU: | |
1880 | GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); | |
1881 | break; | |
1882 | } | |
1883 | gen_helper_subr_h(ret, cpu_env, temp64, r1_low, r1_high); | |
1884 | ||
1885 | tcg_temp_free(temp); | |
1886 | tcg_temp_free_i64(temp64); | |
1887 | } | |
1888 | ||
1889 | static inline void | |
1890 | gen_msubr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) | |
1891 | { | |
1892 | TCGv temp = tcg_temp_new(); | |
1893 | TCGv temp2 = tcg_temp_new(); | |
1894 | ||
1895 | tcg_gen_andi_tl(temp2, r1, 0xffff0000); | |
1896 | tcg_gen_shli_tl(temp, r1, 16); | |
1897 | gen_msubr64_h(ret, temp, temp2, r2, r3, n, mode); | |
1898 | ||
1899 | tcg_temp_free(temp); | |
1900 | tcg_temp_free(temp2); | |
1901 | } | |
1902 | ||
1903 | static inline void | |
1904 | gen_msubr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, | |
1905 | uint32_t n, uint32_t mode) | |
1906 | { | |
1907 | TCGv temp = tcg_const_i32(n); | |
1908 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
1909 | switch (mode) { | |
1910 | case MODE_LL: | |
1911 | GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); | |
1912 | break; | |
1913 | case MODE_LU: | |
1914 | GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); | |
1915 | break; | |
1916 | case MODE_UL: | |
1917 | GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); | |
1918 | break; | |
1919 | case MODE_UU: | |
1920 | GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); | |
1921 | break; | |
1922 | } | |
1923 | gen_helper_subr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high); | |
1924 | ||
1925 | tcg_temp_free(temp); | |
1926 | tcg_temp_free_i64(temp64); | |
1927 | } | |
1928 | ||
1929 | static inline void | |
1930 | gen_msubr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) | |
1931 | { | |
1932 | TCGv temp = tcg_temp_new(); | |
1933 | TCGv temp2 = tcg_temp_new(); | |
1934 | ||
1935 | tcg_gen_andi_tl(temp2, r1, 0xffff0000); | |
1936 | tcg_gen_shli_tl(temp, r1, 16); | |
1937 | gen_msubr64s_h(ret, temp, temp2, r2, r3, n, mode); | |
1938 | ||
1939 | tcg_temp_free(temp); | |
1940 | tcg_temp_free(temp2); | |
1941 | } | |
1942 | ||
62e47b2e BK |
1943 | static inline void |
1944 | gen_msubr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) | |
1945 | { | |
1946 | TCGv temp = tcg_const_i32(n); | |
1947 | gen_helper_msubr_q(ret, cpu_env, r1, r2, r3, temp); | |
1948 | tcg_temp_free(temp); | |
1949 | } | |
1950 | ||
1951 | static inline void | |
1952 | gen_msubrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) | |
1953 | { | |
1954 | TCGv temp = tcg_const_i32(n); | |
1955 | gen_helper_msubr_q_ssov(ret, cpu_env, r1, r2, r3, temp); | |
1956 | tcg_temp_free(temp); | |
1957 | } | |
1958 | ||
1959 | static inline void | |
1960 | gen_msub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, | |
2db92a0c | 1961 | uint32_t up_shift) |
62e47b2e BK |
1962 | { |
1963 | TCGv temp = tcg_temp_new(); | |
1964 | TCGv temp2 = tcg_temp_new(); | |
1965 | TCGv temp3 = tcg_temp_new(); | |
1966 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1967 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
1968 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
1969 | TCGv_i64 t4 = tcg_temp_new_i64(); | |
1970 | ||
1971 | tcg_gen_ext_i32_i64(t2, arg2); | |
1972 | tcg_gen_ext_i32_i64(t3, arg3); | |
1973 | ||
1974 | tcg_gen_mul_i64(t2, t2, t3); | |
1975 | ||
1976 | tcg_gen_ext_i32_i64(t1, arg1); | |
1977 | /* if we shift part of the fraction out, we need to round up */ | |
1978 | tcg_gen_andi_i64(t4, t2, (1ll << (up_shift - n)) - 1); | |
1979 | tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0); | |
1980 | tcg_gen_sari_i64(t2, t2, up_shift - n); | |
1981 | tcg_gen_add_i64(t2, t2, t4); | |
1982 | ||
1983 | tcg_gen_sub_i64(t3, t1, t2); | |
ecc7b3aa | 1984 | tcg_gen_extrl_i64_i32(temp3, t3); |
62e47b2e BK |
1985 | /* calc v bit */ |
1986 | tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL); | |
1987 | tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL); | |
1988 | tcg_gen_or_i64(t1, t1, t2); | |
ecc7b3aa | 1989 | tcg_gen_extrl_i64_i32(cpu_PSW_V, t1); |
62e47b2e | 1990 | tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); |
62e47b2e BK |
1991 | /* Calc SV bit */ |
1992 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
1993 | /* Calc AV/SAV bits */ | |
1994 | tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3); | |
1995 | tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV); | |
1996 | /* calc SAV */ | |
1997 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
1998 | /* write back result */ | |
1999 | tcg_gen_mov_tl(ret, temp3); | |
2000 | ||
2001 | tcg_temp_free(temp); | |
2002 | tcg_temp_free(temp2); | |
2003 | tcg_temp_free(temp3); | |
2004 | tcg_temp_free_i64(t1); | |
2005 | tcg_temp_free_i64(t2); | |
2006 | tcg_temp_free_i64(t3); | |
2007 | tcg_temp_free_i64(t4); | |
2008 | } | |
2009 | ||
2010 | static inline void | |
2011 | gen_m16sub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n) | |
2012 | { | |
2013 | TCGv temp = tcg_temp_new(); | |
2014 | TCGv temp2 = tcg_temp_new(); | |
2015 | if (n == 0) { | |
2016 | tcg_gen_mul_tl(temp, arg2, arg3); | |
de7ad4ce | 2017 | } else { /* n is expected to be 1 */ |
62e47b2e BK |
2018 | tcg_gen_mul_tl(temp, arg2, arg3); |
2019 | tcg_gen_shli_tl(temp, temp, 1); | |
2020 | /* catch special case r1 = r2 = 0x8000 */ | |
2021 | tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); | |
2022 | tcg_gen_sub_tl(temp, temp, temp2); | |
2023 | } | |
2024 | gen_sub_d(ret, arg1, temp); | |
2025 | ||
2026 | tcg_temp_free(temp); | |
2027 | tcg_temp_free(temp2); | |
2028 | } | |
2029 | ||
2030 | static inline void | |
2031 | gen_m16subs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n) | |
2032 | { | |
2033 | TCGv temp = tcg_temp_new(); | |
2034 | TCGv temp2 = tcg_temp_new(); | |
2035 | if (n == 0) { | |
2036 | tcg_gen_mul_tl(temp, arg2, arg3); | |
de7ad4ce | 2037 | } else { /* n is expected to be 1 */ |
62e47b2e BK |
2038 | tcg_gen_mul_tl(temp, arg2, arg3); |
2039 | tcg_gen_shli_tl(temp, temp, 1); | |
2040 | /* catch special case r1 = r2 = 0x8000 */ | |
2041 | tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); | |
2042 | tcg_gen_sub_tl(temp, temp, temp2); | |
2043 | } | |
2044 | gen_subs(ret, arg1, temp); | |
2045 | ||
2046 | tcg_temp_free(temp); | |
2047 | tcg_temp_free(temp2); | |
2048 | } | |
2049 | ||
2050 | static inline void | |
2051 | gen_m16sub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, | |
2052 | TCGv arg3, uint32_t n) | |
2053 | { | |
2054 | TCGv temp = tcg_temp_new(); | |
2055 | TCGv temp2 = tcg_temp_new(); | |
2056 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
2057 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
2058 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
2059 | ||
2060 | if (n == 0) { | |
2061 | tcg_gen_mul_tl(temp, arg2, arg3); | |
de7ad4ce | 2062 | } else { /* n is expected to be 1 */ |
62e47b2e BK |
2063 | tcg_gen_mul_tl(temp, arg2, arg3); |
2064 | tcg_gen_shli_tl(temp, temp, 1); | |
2065 | /* catch special case r1 = r2 = 0x8000 */ | |
2066 | tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); | |
2067 | tcg_gen_sub_tl(temp, temp, temp2); | |
2068 | } | |
2069 | tcg_gen_ext_i32_i64(t2, temp); | |
2070 | tcg_gen_shli_i64(t2, t2, 16); | |
2071 | tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); | |
2072 | gen_sub64_d(t3, t1, t2); | |
2073 | /* write back result */ | |
2074 | tcg_gen_extr_i64_i32(rl, rh, t3); | |
2075 | ||
2076 | tcg_temp_free_i64(t1); | |
2077 | tcg_temp_free_i64(t2); | |
2078 | tcg_temp_free_i64(t3); | |
2079 | tcg_temp_free(temp); | |
2080 | tcg_temp_free(temp2); | |
2081 | } | |
2082 | ||
2083 | static inline void | |
2084 | gen_m16subs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, | |
2085 | TCGv arg3, uint32_t n) | |
2086 | { | |
2087 | TCGv temp = tcg_temp_new(); | |
2088 | TCGv temp2 = tcg_temp_new(); | |
2089 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
2090 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
2091 | ||
2092 | if (n == 0) { | |
2093 | tcg_gen_mul_tl(temp, arg2, arg3); | |
de7ad4ce | 2094 | } else { /* n is expected to be 1 */ |
62e47b2e BK |
2095 | tcg_gen_mul_tl(temp, arg2, arg3); |
2096 | tcg_gen_shli_tl(temp, temp, 1); | |
2097 | /* catch special case r1 = r2 = 0x8000 */ | |
2098 | tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); | |
2099 | tcg_gen_sub_tl(temp, temp, temp2); | |
2100 | } | |
2101 | tcg_gen_ext_i32_i64(t2, temp); | |
2102 | tcg_gen_shli_i64(t2, t2, 16); | |
2103 | tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); | |
2104 | ||
2105 | gen_helper_sub64_ssov(t1, cpu_env, t1, t2); | |
2106 | tcg_gen_extr_i64_i32(rl, rh, t1); | |
2107 | ||
2108 | tcg_temp_free(temp); | |
2109 | tcg_temp_free(temp2); | |
2110 | tcg_temp_free_i64(t1); | |
2111 | tcg_temp_free_i64(t2); | |
2112 | } | |
2113 | ||
2114 | static inline void | |
2115 | gen_msub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, | |
2db92a0c | 2116 | TCGv arg3, uint32_t n) |
62e47b2e BK |
2117 | { |
2118 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
2119 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
2120 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
2121 | TCGv_i64 t4 = tcg_temp_new_i64(); | |
2122 | TCGv temp, temp2; | |
2123 | ||
2124 | tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); | |
2125 | tcg_gen_ext_i32_i64(t2, arg2); | |
2126 | tcg_gen_ext_i32_i64(t3, arg3); | |
2127 | ||
2128 | tcg_gen_mul_i64(t2, t2, t3); | |
2129 | if (n != 0) { | |
2130 | tcg_gen_shli_i64(t2, t2, 1); | |
2131 | } | |
2132 | tcg_gen_sub_i64(t4, t1, t2); | |
2133 | /* calc v bit */ | |
2134 | tcg_gen_xor_i64(t3, t4, t1); | |
2135 | tcg_gen_xor_i64(t2, t1, t2); | |
2136 | tcg_gen_and_i64(t3, t3, t2); | |
609ad705 | 2137 | tcg_gen_extrh_i64_i32(cpu_PSW_V, t3); |
62e47b2e BK |
2138 | /* We produce an overflow on the host if the mul before was |
2139 | (0x80000000 * 0x80000000) << 1). If this is the | |
2140 | case, we negate the ovf. */ | |
2141 | if (n == 1) { | |
2142 | temp = tcg_temp_new(); | |
2143 | temp2 = tcg_temp_new(); | |
2144 | tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000); | |
2145 | tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3); | |
2146 | tcg_gen_and_tl(temp, temp, temp2); | |
2147 | tcg_gen_shli_tl(temp, temp, 31); | |
2148 | /* negate v bit, if special condition */ | |
2149 | tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp); | |
2150 | ||
2151 | tcg_temp_free(temp); | |
2152 | tcg_temp_free(temp2); | |
2153 | } | |
2154 | /* write back result */ | |
2155 | tcg_gen_extr_i64_i32(rl, rh, t4); | |
2156 | /* Calc SV bit */ | |
2157 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
2158 | /* Calc AV/SAV bits */ | |
2159 | tcg_gen_add_tl(cpu_PSW_AV, rh, rh); | |
2160 | tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV); | |
2161 | /* calc SAV */ | |
2162 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
2163 | ||
2164 | tcg_temp_free_i64(t1); | |
2165 | tcg_temp_free_i64(t2); | |
2166 | tcg_temp_free_i64(t3); | |
2167 | tcg_temp_free_i64(t4); | |
2168 | } | |
2169 | ||
2170 | static inline void | |
2171 | gen_msubs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, | |
2172 | uint32_t up_shift) | |
2173 | { | |
2174 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
2175 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
2176 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
2177 | TCGv_i64 t4 = tcg_temp_new_i64(); | |
2178 | ||
2179 | tcg_gen_ext_i32_i64(t1, arg1); | |
2180 | tcg_gen_ext_i32_i64(t2, arg2); | |
2181 | tcg_gen_ext_i32_i64(t3, arg3); | |
2182 | ||
2183 | tcg_gen_mul_i64(t2, t2, t3); | |
2184 | /* if we shift part of the fraction out, we need to round up */ | |
2185 | tcg_gen_andi_i64(t4, t2, (1ll << (up_shift - n)) - 1); | |
2186 | tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0); | |
2187 | tcg_gen_sari_i64(t3, t2, up_shift - n); | |
2188 | tcg_gen_add_i64(t3, t3, t4); | |
2189 | ||
2190 | gen_helper_msub32_q_sub_ssov(ret, cpu_env, t1, t3); | |
2191 | ||
2192 | tcg_temp_free_i64(t1); | |
2193 | tcg_temp_free_i64(t2); | |
2194 | tcg_temp_free_i64(t3); | |
2195 | tcg_temp_free_i64(t4); | |
2196 | } | |
2197 | ||
2198 | static inline void | |
2199 | gen_msubs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, | |
2200 | TCGv arg3, uint32_t n) | |
2201 | { | |
2202 | TCGv_i64 r1 = tcg_temp_new_i64(); | |
2203 | TCGv temp = tcg_const_i32(n); | |
2204 | ||
2205 | tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high); | |
2206 | gen_helper_msub64_q_ssov(r1, cpu_env, r1, arg2, arg3, temp); | |
2207 | tcg_gen_extr_i64_i32(rl, rh, r1); | |
2208 | ||
2209 | tcg_temp_free_i64(r1); | |
2210 | tcg_temp_free(temp); | |
2211 | } | |
2212 | ||
068fac77 BK |
2213 | static inline void |
2214 | gen_msubad_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, | |
2215 | TCGv r3, uint32_t n, uint32_t mode) | |
2216 | { | |
2217 | TCGv temp = tcg_const_i32(n); | |
2218 | TCGv temp2 = tcg_temp_new(); | |
2219 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
2220 | switch (mode) { | |
2221 | case MODE_LL: | |
2222 | GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); | |
2223 | break; | |
2224 | case MODE_LU: | |
2225 | GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); | |
2226 | break; | |
2227 | case MODE_UL: | |
2228 | GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); | |
2229 | break; | |
2230 | case MODE_UU: | |
2231 | GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); | |
2232 | break; | |
2233 | } | |
2234 | tcg_gen_extr_i64_i32(temp, temp2, temp64); | |
2235 | gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, | |
2236 | tcg_gen_add_tl, tcg_gen_sub_tl); | |
2237 | tcg_temp_free(temp); | |
2238 | tcg_temp_free(temp2); | |
2239 | tcg_temp_free_i64(temp64); | |
2240 | } | |
2241 | ||
2242 | static inline void | |
2243 | gen_msubadm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, | |
2244 | TCGv r3, uint32_t n, uint32_t mode) | |
2245 | { | |
2246 | TCGv temp = tcg_const_i32(n); | |
2247 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
2248 | TCGv_i64 temp64_2 = tcg_temp_new_i64(); | |
2249 | TCGv_i64 temp64_3 = tcg_temp_new_i64(); | |
2250 | switch (mode) { | |
2251 | case MODE_LL: | |
2252 | GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); | |
2253 | break; | |
2254 | case MODE_LU: | |
2255 | GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); | |
2256 | break; | |
2257 | case MODE_UL: | |
2258 | GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); | |
2259 | break; | |
2260 | case MODE_UU: | |
2261 | GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); | |
2262 | break; | |
2263 | } | |
2264 | tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high); | |
2265 | tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ | |
2266 | tcg_gen_ext32s_i64(temp64, temp64); /* low */ | |
2267 | tcg_gen_sub_i64(temp64, temp64_2, temp64); | |
2268 | tcg_gen_shli_i64(temp64, temp64, 16); | |
2269 | ||
2270 | gen_sub64_d(temp64_2, temp64_3, temp64); | |
2271 | /* write back result */ | |
2272 | tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2); | |
2273 | ||
2274 | tcg_temp_free(temp); | |
2275 | tcg_temp_free_i64(temp64); | |
2276 | tcg_temp_free_i64(temp64_2); | |
2277 | tcg_temp_free_i64(temp64_3); | |
2278 | } | |
2279 | ||
2280 | static inline void | |
2281 | gen_msubadr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) | |
2282 | { | |
2283 | TCGv temp = tcg_const_i32(n); | |
2284 | TCGv temp2 = tcg_temp_new(); | |
2285 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
2286 | switch (mode) { | |
2287 | case MODE_LL: | |
2288 | GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); | |
2289 | break; | |
2290 | case MODE_LU: | |
2291 | GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); | |
2292 | break; | |
2293 | case MODE_UL: | |
2294 | GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); | |
2295 | break; | |
2296 | case MODE_UU: | |
2297 | GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); | |
2298 | break; | |
2299 | } | |
2300 | tcg_gen_andi_tl(temp2, r1, 0xffff0000); | |
2301 | tcg_gen_shli_tl(temp, r1, 16); | |
2302 | gen_helper_subadr_h(ret, cpu_env, temp64, temp, temp2); | |
2303 | ||
2304 | tcg_temp_free(temp); | |
2305 | tcg_temp_free(temp2); | |
2306 | tcg_temp_free_i64(temp64); | |
2307 | } | |
2308 | ||
2309 | static inline void | |
2310 | gen_msubads_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, | |
2311 | TCGv r3, uint32_t n, uint32_t mode) | |
2312 | { | |
2313 | TCGv temp = tcg_const_i32(n); | |
2314 | TCGv temp2 = tcg_temp_new(); | |
2315 | TCGv temp3 = tcg_temp_new(); | |
2316 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
2317 | ||
2318 | switch (mode) { | |
2319 | case MODE_LL: | |
2320 | GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); | |
2321 | break; | |
2322 | case MODE_LU: | |
2323 | GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); | |
2324 | break; | |
2325 | case MODE_UL: | |
2326 | GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); | |
2327 | break; | |
2328 | case MODE_UU: | |
2329 | GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); | |
2330 | break; | |
2331 | } | |
2332 | tcg_gen_extr_i64_i32(temp, temp2, temp64); | |
2333 | gen_adds(ret_low, r1_low, temp); | |
2334 | tcg_gen_mov_tl(temp, cpu_PSW_V); | |
2335 | tcg_gen_mov_tl(temp3, cpu_PSW_AV); | |
2336 | gen_subs(ret_high, r1_high, temp2); | |
2337 | /* combine v bits */ | |
2338 | tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); | |
2339 | /* combine av bits */ | |
2340 | tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); | |
2341 | ||
2342 | tcg_temp_free(temp); | |
2343 | tcg_temp_free(temp2); | |
2344 | tcg_temp_free(temp3); | |
2345 | tcg_temp_free_i64(temp64); | |
2346 | } | |
2347 | ||
2348 | static inline void | |
2349 | gen_msubadms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, | |
2350 | TCGv r3, uint32_t n, uint32_t mode) | |
2351 | { | |
2352 | TCGv temp = tcg_const_i32(n); | |
2353 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
2354 | TCGv_i64 temp64_2 = tcg_temp_new_i64(); | |
2355 | ||
2356 | switch (mode) { | |
2357 | case MODE_LL: | |
2358 | GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); | |
2359 | break; | |
2360 | case MODE_LU: | |
2361 | GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); | |
2362 | break; | |
2363 | case MODE_UL: | |
2364 | GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); | |
2365 | break; | |
2366 | case MODE_UU: | |
2367 | GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); | |
2368 | break; | |
2369 | } | |
2370 | tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ | |
2371 | tcg_gen_ext32s_i64(temp64, temp64); /* low */ | |
2372 | tcg_gen_sub_i64(temp64, temp64_2, temp64); | |
2373 | tcg_gen_shli_i64(temp64, temp64, 16); | |
2374 | tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); | |
2375 | ||
2376 | gen_helper_sub64_ssov(temp64, cpu_env, temp64_2, temp64); | |
2377 | tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); | |
2378 | ||
2379 | tcg_temp_free(temp); | |
2380 | tcg_temp_free_i64(temp64); | |
2381 | tcg_temp_free_i64(temp64_2); | |
2382 | } | |
2383 | ||
2384 | static inline void | |
2385 | gen_msubadr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) | |
2386 | { | |
2387 | TCGv temp = tcg_const_i32(n); | |
2388 | TCGv temp2 = tcg_temp_new(); | |
2389 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
2390 | switch (mode) { | |
2391 | case MODE_LL: | |
2392 | GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); | |
2393 | break; | |
2394 | case MODE_LU: | |
2395 | GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); | |
2396 | break; | |
2397 | case MODE_UL: | |
2398 | GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); | |
2399 | break; | |
2400 | case MODE_UU: | |
2401 | GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); | |
2402 | break; | |
2403 | } | |
2404 | tcg_gen_andi_tl(temp2, r1, 0xffff0000); | |
2405 | tcg_gen_shli_tl(temp, r1, 16); | |
2406 | gen_helper_subadr_h_ssov(ret, cpu_env, temp64, temp, temp2); | |
2407 | ||
2408 | tcg_temp_free(temp); | |
2409 | tcg_temp_free(temp2); | |
2410 | tcg_temp_free_i64(temp64); | |
2411 | } | |
2412 | ||
d5de7839 BK |
2413 | static inline void gen_abs(TCGv ret, TCGv r1) |
2414 | { | |
2f8036d2 | 2415 | tcg_gen_abs_tl(ret, r1); |
d5de7839 BK |
2416 | /* overflow can only happen, if r1 = 0x80000000 */ |
2417 | tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, r1, 0x80000000); | |
2418 | tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); | |
2419 | /* calc SV bit */ | |
2420 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
2421 | /* Calc AV bit */ | |
2422 | tcg_gen_add_tl(cpu_PSW_AV, ret, ret); | |
2423 | tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); | |
2424 | /* calc SAV bit */ | |
2425 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
d5de7839 BK |
2426 | } |
2427 | ||
0974257e BK |
2428 | static inline void gen_absdif(TCGv ret, TCGv r1, TCGv r2) |
2429 | { | |
2430 | TCGv temp = tcg_temp_new_i32(); | |
2431 | TCGv result = tcg_temp_new_i32(); | |
2432 | ||
2433 | tcg_gen_sub_tl(result, r1, r2); | |
2434 | tcg_gen_sub_tl(temp, r2, r1); | |
2435 | tcg_gen_movcond_tl(TCG_COND_GT, result, r1, r2, result, temp); | |
2436 | ||
2437 | /* calc V bit */ | |
2438 | tcg_gen_xor_tl(cpu_PSW_V, result, r1); | |
2439 | tcg_gen_xor_tl(temp, result, r2); | |
2440 | tcg_gen_movcond_tl(TCG_COND_GT, cpu_PSW_V, r1, r2, cpu_PSW_V, temp); | |
2441 | tcg_gen_xor_tl(temp, r1, r2); | |
2442 | tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp); | |
2443 | /* calc SV bit */ | |
2444 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
2445 | /* Calc AV bit */ | |
2446 | tcg_gen_add_tl(cpu_PSW_AV, result, result); | |
2447 | tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); | |
2448 | /* calc SAV bit */ | |
2449 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
2450 | /* write back result */ | |
2451 | tcg_gen_mov_tl(ret, result); | |
2452 | ||
2453 | tcg_temp_free(temp); | |
2454 | tcg_temp_free(result); | |
2455 | } | |
2456 | ||
2457 | static inline void gen_absdifi(TCGv ret, TCGv r1, int32_t con) | |
2458 | { | |
2459 | TCGv temp = tcg_const_i32(con); | |
2460 | gen_absdif(ret, r1, temp); | |
2461 | tcg_temp_free(temp); | |
2462 | } | |
2463 | ||
2464 | static inline void gen_absdifsi(TCGv ret, TCGv r1, int32_t con) | |
2465 | { | |
2466 | TCGv temp = tcg_const_i32(con); | |
2467 | gen_helper_absdif_ssov(ret, cpu_env, r1, temp); | |
2468 | tcg_temp_free(temp); | |
2469 | } | |
2470 | ||
2692802a BK |
2471 | static inline void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2) |
2472 | { | |
2473 | TCGv high = tcg_temp_new(); | |
2474 | TCGv low = tcg_temp_new(); | |
2475 | ||
2476 | tcg_gen_muls2_tl(low, high, r1, r2); | |
2477 | tcg_gen_mov_tl(ret, low); | |
2478 | /* calc V bit */ | |
2479 | tcg_gen_sari_tl(low, low, 31); | |
2480 | tcg_gen_setcond_tl(TCG_COND_NE, cpu_PSW_V, high, low); | |
2481 | tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); | |
2482 | /* calc SV bit */ | |
2483 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
2484 | /* Calc AV bit */ | |
2485 | tcg_gen_add_tl(cpu_PSW_AV, ret, ret); | |
2486 | tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); | |
2487 | /* calc SAV bit */ | |
2488 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
2489 | ||
2490 | tcg_temp_free(high); | |
2491 | tcg_temp_free(low); | |
2492 | } | |
2493 | ||
0974257e BK |
2494 | static inline void gen_muli_i32s(TCGv ret, TCGv r1, int32_t con) |
2495 | { | |
2496 | TCGv temp = tcg_const_i32(con); | |
2497 | gen_mul_i32s(ret, r1, temp); | |
2498 | tcg_temp_free(temp); | |
2499 | } | |
2500 | ||
2501 | static inline void gen_mul_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2) | |
2502 | { | |
2503 | tcg_gen_muls2_tl(ret_low, ret_high, r1, r2); | |
2504 | /* clear V bit */ | |
2505 | tcg_gen_movi_tl(cpu_PSW_V, 0); | |
2506 | /* calc SV bit */ | |
2507 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
2508 | /* Calc AV bit */ | |
2509 | tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); | |
2510 | tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); | |
2511 | /* calc SAV bit */ | |
2512 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
2513 | } | |
2514 | ||
2515 | static inline void gen_muli_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, | |
2516 | int32_t con) | |
2517 | { | |
2518 | TCGv temp = tcg_const_i32(con); | |
2519 | gen_mul_i64s(ret_low, ret_high, r1, temp); | |
2520 | tcg_temp_free(temp); | |
2521 | } | |
2522 | ||
2523 | static inline void gen_mul_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2) | |
2524 | { | |
2525 | tcg_gen_mulu2_tl(ret_low, ret_high, r1, r2); | |
2526 | /* clear V bit */ | |
2527 | tcg_gen_movi_tl(cpu_PSW_V, 0); | |
2528 | /* calc SV bit */ | |
2529 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
2530 | /* Calc AV bit */ | |
2531 | tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); | |
2532 | tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); | |
2533 | /* calc SAV bit */ | |
2534 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
2535 | } | |
2536 | ||
2537 | static inline void gen_muli_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, | |
2538 | int32_t con) | |
2539 | { | |
2540 | TCGv temp = tcg_const_i32(con); | |
2541 | gen_mul_i64u(ret_low, ret_high, r1, temp); | |
2542 | tcg_temp_free(temp); | |
2543 | } | |
2544 | ||
2545 | static inline void gen_mulsi_i32(TCGv ret, TCGv r1, int32_t con) | |
2546 | { | |
2547 | TCGv temp = tcg_const_i32(con); | |
2548 | gen_helper_mul_ssov(ret, cpu_env, r1, temp); | |
2549 | tcg_temp_free(temp); | |
2550 | } | |
2551 | ||
2552 | static inline void gen_mulsui_i32(TCGv ret, TCGv r1, int32_t con) | |
2553 | { | |
2554 | TCGv temp = tcg_const_i32(con); | |
2555 | gen_helper_mul_suov(ret, cpu_env, r1, temp); | |
2556 | tcg_temp_free(temp); | |
2557 | } | |
328f1f0f BK |
2558 | /* gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); */ |
2559 | static inline void gen_maddsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) | |
2560 | { | |
2561 | TCGv temp = tcg_const_i32(con); | |
2562 | gen_helper_madd32_ssov(ret, cpu_env, r1, r2, temp); | |
2563 | tcg_temp_free(temp); | |
2564 | } | |
2565 | ||
2566 | static inline void gen_maddsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) | |
2567 | { | |
2568 | TCGv temp = tcg_const_i32(con); | |
2569 | gen_helper_madd32_suov(ret, cpu_env, r1, r2, temp); | |
2570 | tcg_temp_free(temp); | |
2571 | } | |
2572 | ||
f1cc6eaf BK |
2573 | static void |
2574 | gen_mul_q(TCGv rl, TCGv rh, TCGv arg1, TCGv arg2, uint32_t n, uint32_t up_shift) | |
2575 | { | |
2576 | TCGv temp = tcg_temp_new(); | |
2577 | TCGv_i64 temp_64 = tcg_temp_new_i64(); | |
2578 | TCGv_i64 temp2_64 = tcg_temp_new_i64(); | |
2579 | ||
2580 | if (n == 0) { | |
2581 | if (up_shift == 32) { | |
2582 | tcg_gen_muls2_tl(rh, rl, arg1, arg2); | |
2583 | } else if (up_shift == 16) { | |
2584 | tcg_gen_ext_i32_i64(temp_64, arg1); | |
2585 | tcg_gen_ext_i32_i64(temp2_64, arg2); | |
2586 | ||
2587 | tcg_gen_mul_i64(temp_64, temp_64, temp2_64); | |
2588 | tcg_gen_shri_i64(temp_64, temp_64, up_shift); | |
2589 | tcg_gen_extr_i64_i32(rl, rh, temp_64); | |
2590 | } else { | |
2591 | tcg_gen_muls2_tl(rl, rh, arg1, arg2); | |
2592 | } | |
2593 | /* reset v bit */ | |
2594 | tcg_gen_movi_tl(cpu_PSW_V, 0); | |
de7ad4ce | 2595 | } else { /* n is expected to be 1 */ |
f1cc6eaf BK |
2596 | tcg_gen_ext_i32_i64(temp_64, arg1); |
2597 | tcg_gen_ext_i32_i64(temp2_64, arg2); | |
2598 | ||
2599 | tcg_gen_mul_i64(temp_64, temp_64, temp2_64); | |
2600 | ||
2601 | if (up_shift == 0) { | |
2602 | tcg_gen_shli_i64(temp_64, temp_64, 1); | |
2603 | } else { | |
2604 | tcg_gen_shri_i64(temp_64, temp_64, up_shift - 1); | |
2605 | } | |
2606 | tcg_gen_extr_i64_i32(rl, rh, temp_64); | |
de7ad4ce | 2607 | /* overflow only occurs if r1 = r2 = 0x8000 */ |
f1cc6eaf BK |
2608 | if (up_shift == 0) {/* result is 64 bit */ |
2609 | tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rh, | |
2610 | 0x80000000); | |
2611 | } else { /* result is 32 bit */ | |
2612 | tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rl, | |
2613 | 0x80000000); | |
2614 | } | |
2615 | tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); | |
2616 | /* calc sv overflow bit */ | |
2617 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
2618 | } | |
2619 | /* calc av overflow bit */ | |
2620 | if (up_shift == 0) { | |
2621 | tcg_gen_add_tl(cpu_PSW_AV, rh, rh); | |
2622 | tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV); | |
2623 | } else { | |
2624 | tcg_gen_add_tl(cpu_PSW_AV, rl, rl); | |
2625 | tcg_gen_xor_tl(cpu_PSW_AV, rl, cpu_PSW_AV); | |
2626 | } | |
2627 | /* calc sav overflow bit */ | |
2628 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
2629 | tcg_temp_free(temp); | |
2630 | tcg_temp_free_i64(temp_64); | |
2631 | tcg_temp_free_i64(temp2_64); | |
2632 | } | |
2633 | ||
2634 | static void | |
2635 | gen_mul_q_16(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n) | |
2636 | { | |
2637 | TCGv temp = tcg_temp_new(); | |
2638 | if (n == 0) { | |
2639 | tcg_gen_mul_tl(ret, arg1, arg2); | |
de7ad4ce | 2640 | } else { /* n is expected to be 1 */ |
f1cc6eaf BK |
2641 | tcg_gen_mul_tl(ret, arg1, arg2); |
2642 | tcg_gen_shli_tl(ret, ret, 1); | |
2643 | /* catch special case r1 = r2 = 0x8000 */ | |
2644 | tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80000000); | |
2645 | tcg_gen_sub_tl(ret, ret, temp); | |
2646 | } | |
2647 | /* reset v bit */ | |
2648 | tcg_gen_movi_tl(cpu_PSW_V, 0); | |
2649 | /* calc av overflow bit */ | |
2650 | tcg_gen_add_tl(cpu_PSW_AV, ret, ret); | |
2651 | tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); | |
2652 | /* calc sav overflow bit */ | |
2653 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
2654 | ||
2655 | tcg_temp_free(temp); | |
2656 | } | |
2657 | ||
2658 | static void gen_mulr_q(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n) | |
2659 | { | |
2660 | TCGv temp = tcg_temp_new(); | |
2661 | if (n == 0) { | |
2662 | tcg_gen_mul_tl(ret, arg1, arg2); | |
2663 | tcg_gen_addi_tl(ret, ret, 0x8000); | |
2664 | } else { | |
2665 | tcg_gen_mul_tl(ret, arg1, arg2); | |
2666 | tcg_gen_shli_tl(ret, ret, 1); | |
2667 | tcg_gen_addi_tl(ret, ret, 0x8000); | |
2668 | /* catch special case r1 = r2 = 0x8000 */ | |
2669 | tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80008000); | |
2670 | tcg_gen_muli_tl(temp, temp, 0x8001); | |
2671 | tcg_gen_sub_tl(ret, ret, temp); | |
2672 | } | |
2673 | /* reset v bit */ | |
2674 | tcg_gen_movi_tl(cpu_PSW_V, 0); | |
2675 | /* calc av overflow bit */ | |
2676 | tcg_gen_add_tl(cpu_PSW_AV, ret, ret); | |
2677 | tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); | |
2678 | /* calc sav overflow bit */ | |
2679 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
2680 | /* cut halfword off */ | |
2681 | tcg_gen_andi_tl(ret, ret, 0xffff0000); | |
2682 | ||
2683 | tcg_temp_free(temp); | |
2684 | } | |
2685 | ||
2984cfbd BK |
2686 | static inline void |
2687 | gen_madds_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
2688 | TCGv r3) | |
2689 | { | |
2690 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
2691 | tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); | |
2692 | gen_helper_madd64_ssov(temp64, cpu_env, r1, temp64, r3); | |
2693 | tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); | |
2694 | tcg_temp_free_i64(temp64); | |
2695 | } | |
2696 | ||
328f1f0f BK |
2697 | static inline void |
2698 | gen_maddsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
2699 | int32_t con) | |
2700 | { | |
2701 | TCGv temp = tcg_const_i32(con); | |
2984cfbd BK |
2702 | gen_madds_64(ret_low, ret_high, r1, r2_low, r2_high, temp); |
2703 | tcg_temp_free(temp); | |
2704 | } | |
2705 | ||
2706 | static inline void | |
2707 | gen_maddsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
2708 | TCGv r3) | |
2709 | { | |
328f1f0f BK |
2710 | TCGv_i64 temp64 = tcg_temp_new_i64(); |
2711 | tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); | |
2984cfbd | 2712 | gen_helper_madd64_suov(temp64, cpu_env, r1, temp64, r3); |
328f1f0f | 2713 | tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); |
328f1f0f BK |
2714 | tcg_temp_free_i64(temp64); |
2715 | } | |
2716 | ||
2717 | static inline void | |
2718 | gen_maddsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
2719 | int32_t con) | |
2720 | { | |
2721 | TCGv temp = tcg_const_i32(con); | |
2984cfbd | 2722 | gen_maddsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp); |
328f1f0f | 2723 | tcg_temp_free(temp); |
328f1f0f BK |
2724 | } |
2725 | ||
2726 | static inline void gen_msubsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) | |
2727 | { | |
2728 | TCGv temp = tcg_const_i32(con); | |
2729 | gen_helper_msub32_ssov(ret, cpu_env, r1, r2, temp); | |
2730 | tcg_temp_free(temp); | |
2731 | } | |
2732 | ||
2733 | static inline void gen_msubsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) | |
2734 | { | |
2735 | TCGv temp = tcg_const_i32(con); | |
2736 | gen_helper_msub32_suov(ret, cpu_env, r1, r2, temp); | |
2737 | tcg_temp_free(temp); | |
2738 | } | |
2739 | ||
2984cfbd BK |
2740 | static inline void |
2741 | gen_msubs_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
2742 | TCGv r3) | |
2743 | { | |
2744 | TCGv_i64 temp64 = tcg_temp_new_i64(); | |
2745 | tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); | |
2746 | gen_helper_msub64_ssov(temp64, cpu_env, r1, temp64, r3); | |
2747 | tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); | |
2748 | tcg_temp_free_i64(temp64); | |
2749 | } | |
2750 | ||
328f1f0f BK |
2751 | static inline void |
2752 | gen_msubsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
2753 | int32_t con) | |
2754 | { | |
2755 | TCGv temp = tcg_const_i32(con); | |
2984cfbd BK |
2756 | gen_msubs_64(ret_low, ret_high, r1, r2_low, r2_high, temp); |
2757 | tcg_temp_free(temp); | |
2758 | } | |
2759 | ||
2760 | static inline void | |
2761 | gen_msubsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
2762 | TCGv r3) | |
2763 | { | |
328f1f0f BK |
2764 | TCGv_i64 temp64 = tcg_temp_new_i64(); |
2765 | tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); | |
2984cfbd | 2766 | gen_helper_msub64_suov(temp64, cpu_env, r1, temp64, r3); |
328f1f0f | 2767 | tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); |
328f1f0f BK |
2768 | tcg_temp_free_i64(temp64); |
2769 | } | |
2770 | ||
2771 | static inline void | |
2772 | gen_msubsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, | |
2773 | int32_t con) | |
2774 | { | |
2775 | TCGv temp = tcg_const_i32(con); | |
2984cfbd | 2776 | gen_msubsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp); |
328f1f0f | 2777 | tcg_temp_free(temp); |
328f1f0f | 2778 | } |
0974257e | 2779 | |
44ea3430 BK |
2780 | static void gen_saturate(TCGv ret, TCGv arg, int32_t up, int32_t low) |
2781 | { | |
2782 | TCGv sat_neg = tcg_const_i32(low); | |
2783 | TCGv temp = tcg_const_i32(up); | |
2784 | ||
2785 | /* sat_neg = (arg < low ) ? low : arg; */ | |
2786 | tcg_gen_movcond_tl(TCG_COND_LT, sat_neg, arg, sat_neg, sat_neg, arg); | |
2787 | ||
2788 | /* ret = (sat_neg > up ) ? up : sat_neg; */ | |
2789 | tcg_gen_movcond_tl(TCG_COND_GT, ret, sat_neg, temp, temp, sat_neg); | |
2790 | ||
2791 | tcg_temp_free(sat_neg); | |
2792 | tcg_temp_free(temp); | |
2793 | } | |
2794 | ||
2795 | static void gen_saturate_u(TCGv ret, TCGv arg, int32_t up) | |
2796 | { | |
2797 | TCGv temp = tcg_const_i32(up); | |
2798 | /* sat_neg = (arg > up ) ? up : arg; */ | |
2799 | tcg_gen_movcond_tl(TCG_COND_GTU, ret, arg, temp, temp, arg); | |
2800 | tcg_temp_free(temp); | |
2801 | } | |
2802 | ||
0707ec1b BK |
2803 | static void gen_shi(TCGv ret, TCGv r1, int32_t shift_count) |
2804 | { | |
2805 | if (shift_count == -32) { | |
2806 | tcg_gen_movi_tl(ret, 0); | |
2807 | } else if (shift_count >= 0) { | |
2808 | tcg_gen_shli_tl(ret, r1, shift_count); | |
2809 | } else { | |
2810 | tcg_gen_shri_tl(ret, r1, -shift_count); | |
2811 | } | |
2812 | } | |
2813 | ||
0974257e BK |
2814 | static void gen_sh_hi(TCGv ret, TCGv r1, int32_t shiftcount) |
2815 | { | |
2816 | TCGv temp_low, temp_high; | |
2817 | ||
2818 | if (shiftcount == -16) { | |
2819 | tcg_gen_movi_tl(ret, 0); | |
2820 | } else { | |
2821 | temp_high = tcg_temp_new(); | |
2822 | temp_low = tcg_temp_new(); | |
2823 | ||
2824 | tcg_gen_andi_tl(temp_low, r1, 0xffff); | |
2825 | tcg_gen_andi_tl(temp_high, r1, 0xffff0000); | |
2826 | gen_shi(temp_low, temp_low, shiftcount); | |
2827 | gen_shi(ret, temp_high, shiftcount); | |
2828 | tcg_gen_deposit_tl(ret, ret, temp_low, 0, 16); | |
2829 | ||
2830 | tcg_temp_free(temp_low); | |
2831 | tcg_temp_free(temp_high); | |
2832 | } | |
2833 | } | |
2834 | ||
0707ec1b BK |
2835 | static void gen_shaci(TCGv ret, TCGv r1, int32_t shift_count) |
2836 | { | |
2837 | uint32_t msk, msk_start; | |
2838 | TCGv temp = tcg_temp_new(); | |
2839 | TCGv temp2 = tcg_temp_new(); | |
2840 | TCGv t_0 = tcg_const_i32(0); | |
2841 | ||
2842 | if (shift_count == 0) { | |
2843 | /* Clear PSW.C and PSW.V */ | |
2844 | tcg_gen_movi_tl(cpu_PSW_C, 0); | |
2845 | tcg_gen_mov_tl(cpu_PSW_V, cpu_PSW_C); | |
2846 | tcg_gen_mov_tl(ret, r1); | |
2847 | } else if (shift_count == -32) { | |
2848 | /* set PSW.C */ | |
2849 | tcg_gen_mov_tl(cpu_PSW_C, r1); | |
cb8d4c8f | 2850 | /* fill ret completely with sign bit */ |
0707ec1b BK |
2851 | tcg_gen_sari_tl(ret, r1, 31); |
2852 | /* clear PSW.V */ | |
2853 | tcg_gen_movi_tl(cpu_PSW_V, 0); | |
2854 | } else if (shift_count > 0) { | |
2855 | TCGv t_max = tcg_const_i32(0x7FFFFFFF >> shift_count); | |
2856 | TCGv t_min = tcg_const_i32(((int32_t) -0x80000000) >> shift_count); | |
2857 | ||
2858 | /* calc carry */ | |
2859 | msk_start = 32 - shift_count; | |
2860 | msk = ((1 << shift_count) - 1) << msk_start; | |
2861 | tcg_gen_andi_tl(cpu_PSW_C, r1, msk); | |
2862 | /* calc v/sv bits */ | |
2863 | tcg_gen_setcond_tl(TCG_COND_GT, temp, r1, t_max); | |
2864 | tcg_gen_setcond_tl(TCG_COND_LT, temp2, r1, t_min); | |
2865 | tcg_gen_or_tl(cpu_PSW_V, temp, temp2); | |
2866 | tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); | |
2867 | /* calc sv */ | |
2868 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_V, cpu_PSW_SV); | |
2869 | /* do shift */ | |
2870 | tcg_gen_shli_tl(ret, r1, shift_count); | |
2871 | ||
2872 | tcg_temp_free(t_max); | |
2873 | tcg_temp_free(t_min); | |
2874 | } else { | |
2875 | /* clear PSW.V */ | |
2876 | tcg_gen_movi_tl(cpu_PSW_V, 0); | |
2877 | /* calc carry */ | |
2878 | msk = (1 << -shift_count) - 1; | |
2879 | tcg_gen_andi_tl(cpu_PSW_C, r1, msk); | |
2880 | /* do shift */ | |
2881 | tcg_gen_sari_tl(ret, r1, -shift_count); | |
2882 | } | |
2883 | /* calc av overflow bit */ | |
2884 | tcg_gen_add_tl(cpu_PSW_AV, ret, ret); | |
2885 | tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); | |
2886 | /* calc sav overflow bit */ | |
2887 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
2888 | ||
2889 | tcg_temp_free(temp); | |
2890 | tcg_temp_free(temp2); | |
2891 | tcg_temp_free(t_0); | |
2892 | } | |
2893 | ||
0974257e BK |
2894 | static void gen_shas(TCGv ret, TCGv r1, TCGv r2) |
2895 | { | |
2896 | gen_helper_sha_ssov(ret, cpu_env, r1, r2); | |
2897 | } | |
2898 | ||
2899 | static void gen_shasi(TCGv ret, TCGv r1, int32_t con) | |
2900 | { | |
2901 | TCGv temp = tcg_const_i32(con); | |
2902 | gen_shas(ret, r1, temp); | |
2903 | tcg_temp_free(temp); | |
2904 | } | |
2905 | ||
2906 | static void gen_sha_hi(TCGv ret, TCGv r1, int32_t shift_count) | |
2907 | { | |
2908 | TCGv low, high; | |
2909 | ||
2910 | if (shift_count == 0) { | |
2911 | tcg_gen_mov_tl(ret, r1); | |
2912 | } else if (shift_count > 0) { | |
2913 | low = tcg_temp_new(); | |
2914 | high = tcg_temp_new(); | |
2915 | ||
2916 | tcg_gen_andi_tl(high, r1, 0xffff0000); | |
2917 | tcg_gen_shli_tl(low, r1, shift_count); | |
2918 | tcg_gen_shli_tl(ret, high, shift_count); | |
2919 | tcg_gen_deposit_tl(ret, ret, low, 0, 16); | |
2920 | ||
2921 | tcg_temp_free(low); | |
2922 | tcg_temp_free(high); | |
2923 | } else { | |
2924 | low = tcg_temp_new(); | |
2925 | high = tcg_temp_new(); | |
2926 | ||
2927 | tcg_gen_ext16s_tl(low, r1); | |
2928 | tcg_gen_sari_tl(low, low, -shift_count); | |
2929 | tcg_gen_sari_tl(ret, r1, -shift_count); | |
2930 | tcg_gen_deposit_tl(ret, ret, low, 0, 16); | |
2931 | ||
2932 | tcg_temp_free(low); | |
2933 | tcg_temp_free(high); | |
2934 | } | |
2935 | ||
2936 | } | |
2937 | ||
2938 | /* ret = {ret[30:0], (r1 cond r2)}; */ | |
2939 | static void gen_sh_cond(int cond, TCGv ret, TCGv r1, TCGv r2) | |
2940 | { | |
2941 | TCGv temp = tcg_temp_new(); | |
2942 | TCGv temp2 = tcg_temp_new(); | |
2943 | ||
2944 | tcg_gen_shli_tl(temp, ret, 1); | |
2945 | tcg_gen_setcond_tl(cond, temp2, r1, r2); | |
2946 | tcg_gen_or_tl(ret, temp, temp2); | |
2947 | ||
2948 | tcg_temp_free(temp); | |
2949 | tcg_temp_free(temp2); | |
2950 | } | |
2951 | ||
2952 | static void gen_sh_condi(int cond, TCGv ret, TCGv r1, int32_t con) | |
2953 | { | |
2954 | TCGv temp = tcg_const_i32(con); | |
2955 | gen_sh_cond(cond, ret, r1, temp); | |
2956 | tcg_temp_free(temp); | |
2957 | } | |
2958 | ||
2692802a BK |
2959 | static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2) |
2960 | { | |
2961 | gen_helper_add_ssov(ret, cpu_env, r1, r2); | |
2962 | } | |
2963 | ||
0974257e BK |
2964 | static inline void gen_addsi(TCGv ret, TCGv r1, int32_t con) |
2965 | { | |
2966 | TCGv temp = tcg_const_i32(con); | |
2967 | gen_helper_add_ssov(ret, cpu_env, r1, temp); | |
2968 | tcg_temp_free(temp); | |
2969 | } | |
2970 | ||
2971 | static inline void gen_addsui(TCGv ret, TCGv r1, int32_t con) | |
2972 | { | |
2973 | TCGv temp = tcg_const_i32(con); | |
2974 | gen_helper_add_suov(ret, cpu_env, r1, temp); | |
2975 | tcg_temp_free(temp); | |
2976 | } | |
2977 | ||
2692802a BK |
2978 | static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2) |
2979 | { | |
2980 | gen_helper_sub_ssov(ret, cpu_env, r1, r2); | |
2981 | } | |
2982 | ||
0974257e BK |
2983 | static inline void gen_subsu(TCGv ret, TCGv r1, TCGv r2) |
2984 | { | |
2985 | gen_helper_sub_suov(ret, cpu_env, r1, r2); | |
2986 | } | |
2987 | ||
b74f2b5b BK |
2988 | static inline void gen_bit_2op(TCGv ret, TCGv r1, TCGv r2, |
2989 | int pos1, int pos2, | |
2990 | void(*op1)(TCGv, TCGv, TCGv), | |
2991 | void(*op2)(TCGv, TCGv, TCGv)) | |
2992 | { | |
2993 | TCGv temp1, temp2; | |
2994 | ||
2995 | temp1 = tcg_temp_new(); | |
2996 | temp2 = tcg_temp_new(); | |
2997 | ||
2998 | tcg_gen_shri_tl(temp2, r2, pos2); | |
2999 | tcg_gen_shri_tl(temp1, r1, pos1); | |
3000 | ||
3001 | (*op1)(temp1, temp1, temp2); | |
3002 | (*op2)(temp1 , ret, temp1); | |
3003 | ||
3004 | tcg_gen_deposit_tl(ret, ret, temp1, 0, 1); | |
3005 | ||
3006 | tcg_temp_free(temp1); | |
3007 | tcg_temp_free(temp2); | |
3008 | } | |
3009 | ||
3010 | /* ret = r1[pos1] op1 r2[pos2]; */ | |
3011 | static inline void gen_bit_1op(TCGv ret, TCGv r1, TCGv r2, | |
3012 | int pos1, int pos2, | |
3013 | void(*op1)(TCGv, TCGv, TCGv)) | |
3014 | { | |
3015 | TCGv temp1, temp2; | |
3016 | ||
3017 | temp1 = tcg_temp_new(); | |
3018 | temp2 = tcg_temp_new(); | |
3019 | ||
3020 | tcg_gen_shri_tl(temp2, r2, pos2); | |
3021 | tcg_gen_shri_tl(temp1, r1, pos1); | |
3022 | ||
3023 | (*op1)(ret, temp1, temp2); | |
3024 | ||
3025 | tcg_gen_andi_tl(ret, ret, 0x1); | |
3026 | ||
3027 | tcg_temp_free(temp1); | |
3028 | tcg_temp_free(temp2); | |
3029 | } | |
3030 | ||
0974257e BK |
3031 | static inline void gen_accumulating_cond(int cond, TCGv ret, TCGv r1, TCGv r2, |
3032 | void(*op)(TCGv, TCGv, TCGv)) | |
3033 | { | |
3034 | TCGv temp = tcg_temp_new(); | |
3035 | TCGv temp2 = tcg_temp_new(); | |
3036 | /* temp = (arg1 cond arg2 )*/ | |
3037 | tcg_gen_setcond_tl(cond, temp, r1, r2); | |
3038 | /* temp2 = ret[0]*/ | |
3039 | tcg_gen_andi_tl(temp2, ret, 0x1); | |
3040 | /* temp = temp insn temp2 */ | |
3041 | (*op)(temp, temp, temp2); | |
3042 | /* ret = {ret[31:1], temp} */ | |
3043 | tcg_gen_deposit_tl(ret, ret, temp, 0, 1); | |
3044 | ||
3045 | tcg_temp_free(temp); | |
3046 | tcg_temp_free(temp2); | |
3047 | } | |
3048 | ||
3049 | static inline void | |
3050 | gen_accumulating_condi(int cond, TCGv ret, TCGv r1, int32_t con, | |
3051 | void(*op)(TCGv, TCGv, TCGv)) | |
3052 | { | |
3053 | TCGv temp = tcg_const_i32(con); | |
3054 | gen_accumulating_cond(cond, ret, r1, temp, op); | |
3055 | tcg_temp_free(temp); | |
3056 | } | |
3057 | ||
d5de7839 BK |
3058 | /* ret = (r1 cond r2) ? 0xFFFFFFFF ? 0x00000000;*/ |
3059 | static inline void gen_cond_w(TCGCond cond, TCGv ret, TCGv r1, TCGv r2) | |
3060 | { | |
3061 | tcg_gen_setcond_tl(cond, ret, r1, r2); | |
3062 | tcg_gen_neg_tl(ret, ret); | |
3063 | } | |
3064 | ||
0974257e BK |
3065 | static inline void gen_eqany_bi(TCGv ret, TCGv r1, int32_t con) |
3066 | { | |
3067 | TCGv b0 = tcg_temp_new(); | |
3068 | TCGv b1 = tcg_temp_new(); | |
3069 | TCGv b2 = tcg_temp_new(); | |
3070 | TCGv b3 = tcg_temp_new(); | |
3071 | ||
3072 | /* byte 0 */ | |
3073 | tcg_gen_andi_tl(b0, r1, 0xff); | |
3074 | tcg_gen_setcondi_tl(TCG_COND_EQ, b0, b0, con & 0xff); | |
3075 | ||
3076 | /* byte 1 */ | |
3077 | tcg_gen_andi_tl(b1, r1, 0xff00); | |
3078 | tcg_gen_setcondi_tl(TCG_COND_EQ, b1, b1, con & 0xff00); | |
3079 | ||
3080 | /* byte 2 */ | |
3081 | tcg_gen_andi_tl(b2, r1, 0xff0000); | |
3082 | tcg_gen_setcondi_tl(TCG_COND_EQ, b2, b2, con & 0xff0000); | |
3083 | ||
3084 | /* byte 3 */ | |
3085 | tcg_gen_andi_tl(b3, r1, 0xff000000); | |
3086 | tcg_gen_setcondi_tl(TCG_COND_EQ, b3, b3, con & 0xff000000); | |
3087 | ||
3088 | /* combine them */ | |
3089 | tcg_gen_or_tl(ret, b0, b1); | |
3090 | tcg_gen_or_tl(ret, ret, b2); | |
3091 | tcg_gen_or_tl(ret, ret, b3); | |
3092 | ||
3093 | tcg_temp_free(b0); | |
3094 | tcg_temp_free(b1); | |
3095 | tcg_temp_free(b2); | |
3096 | tcg_temp_free(b3); | |
3097 | } | |
3098 | ||
3099 | static inline void gen_eqany_hi(TCGv ret, TCGv r1, int32_t con) | |
3100 | { | |
3101 | TCGv h0 = tcg_temp_new(); | |
3102 | TCGv h1 = tcg_temp_new(); | |
3103 | ||
3104 | /* halfword 0 */ | |
3105 | tcg_gen_andi_tl(h0, r1, 0xffff); | |
3106 | tcg_gen_setcondi_tl(TCG_COND_EQ, h0, h0, con & 0xffff); | |
3107 | ||
3108 | /* halfword 1 */ | |
3109 | tcg_gen_andi_tl(h1, r1, 0xffff0000); | |
3110 | tcg_gen_setcondi_tl(TCG_COND_EQ, h1, h1, con & 0xffff0000); | |
3111 | ||
3112 | /* combine them */ | |
3113 | tcg_gen_or_tl(ret, h0, h1); | |
3114 | ||
3115 | tcg_temp_free(h0); | |
3116 | tcg_temp_free(h1); | |
3117 | } | |
ed516260 BK |
3118 | /* mask = ((1 << width) -1) << pos; |
3119 | ret = (r1 & ~mask) | (r2 << pos) & mask); */ | |
3120 | static inline void gen_insert(TCGv ret, TCGv r1, TCGv r2, TCGv width, TCGv pos) | |
3121 | { | |
3122 | TCGv mask = tcg_temp_new(); | |
3123 | TCGv temp = tcg_temp_new(); | |
3124 | TCGv temp2 = tcg_temp_new(); | |
0974257e | 3125 | |
ed516260 BK |
3126 | tcg_gen_movi_tl(mask, 1); |
3127 | tcg_gen_shl_tl(mask, mask, width); | |
3128 | tcg_gen_subi_tl(mask, mask, 1); | |
3129 | tcg_gen_shl_tl(mask, mask, pos); | |
3130 | ||
3131 | tcg_gen_shl_tl(temp, r2, pos); | |
3132 | tcg_gen_and_tl(temp, temp, mask); | |
3133 | tcg_gen_andc_tl(temp2, r1, mask); | |
3134 | tcg_gen_or_tl(ret, temp, temp2); | |
3135 | ||
3136 | tcg_temp_free(mask); | |
3137 | tcg_temp_free(temp); | |
3138 | tcg_temp_free(temp2); | |
3139 | } | |
0974257e | 3140 | |
e2bed107 BK |
3141 | static inline void gen_bsplit(TCGv rl, TCGv rh, TCGv r1) |
3142 | { | |
3143 | TCGv_i64 temp = tcg_temp_new_i64(); | |
3144 | ||
3145 | gen_helper_bsplit(temp, r1); | |
3146 | tcg_gen_extr_i64_i32(rl, rh, temp); | |
3147 | ||
3148 | tcg_temp_free_i64(temp); | |
3149 | } | |
3150 | ||
3151 | static inline void gen_unpack(TCGv rl, TCGv rh, TCGv r1) | |
3152 | { | |
3153 | TCGv_i64 temp = tcg_temp_new_i64(); | |
3154 | ||
3155 | gen_helper_unpack(temp, r1); | |
3156 | tcg_gen_extr_i64_i32(rl, rh, temp); | |
3157 | ||
3158 | tcg_temp_free_i64(temp); | |
3159 | } | |
3160 | ||
3161 | static inline void | |
2db92a0c | 3162 | gen_dvinit_b(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2) |
e2bed107 BK |
3163 | { |
3164 | TCGv_i64 ret = tcg_temp_new_i64(); | |
3165 | ||
44ee3baf | 3166 | if (!has_feature(ctx, TRICORE_FEATURE_131)) { |
e2bed107 BK |
3167 | gen_helper_dvinit_b_13(ret, cpu_env, r1, r2); |
3168 | } else { | |
3169 | gen_helper_dvinit_b_131(ret, cpu_env, r1, r2); | |
3170 | } | |
3171 | tcg_gen_extr_i64_i32(rl, rh, ret); | |
3172 | ||
3173 | tcg_temp_free_i64(ret); | |
3174 | } | |
3175 | ||
3176 | static inline void | |
2db92a0c | 3177 | gen_dvinit_h(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2) |
e2bed107 BK |
3178 | { |
3179 | TCGv_i64 ret = tcg_temp_new_i64(); | |
3180 | ||
44ee3baf | 3181 | if (!has_feature(ctx, TRICORE_FEATURE_131)) { |
e2bed107 BK |
3182 | gen_helper_dvinit_h_13(ret, cpu_env, r1, r2); |
3183 | } else { | |
3184 | gen_helper_dvinit_h_131(ret, cpu_env, r1, r2); | |
3185 | } | |
3186 | tcg_gen_extr_i64_i32(rl, rh, ret); | |
3187 | ||
3188 | tcg_temp_free_i64(ret); | |
3189 | } | |
3190 | ||
9655b932 BK |
3191 | static void gen_calc_usb_mul_h(TCGv arg_low, TCGv arg_high) |
3192 | { | |
3193 | TCGv temp = tcg_temp_new(); | |
3194 | /* calc AV bit */ | |
3195 | tcg_gen_add_tl(temp, arg_low, arg_low); | |
3196 | tcg_gen_xor_tl(temp, temp, arg_low); | |
3197 | tcg_gen_add_tl(cpu_PSW_AV, arg_high, arg_high); | |
3198 | tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, arg_high); | |
3199 | tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp); | |
3200 | /* calc SAV bit */ | |
3201 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
3202 | tcg_gen_movi_tl(cpu_PSW_V, 0); | |
3203 | tcg_temp_free(temp); | |
3204 | } | |
3205 | ||
3206 | static void gen_calc_usb_mulr_h(TCGv arg) | |
3207 | { | |
3208 | TCGv temp = tcg_temp_new(); | |
3209 | /* calc AV bit */ | |
3210 | tcg_gen_add_tl(temp, arg, arg); | |
3211 | tcg_gen_xor_tl(temp, temp, arg); | |
3212 | tcg_gen_shli_tl(cpu_PSW_AV, temp, 16); | |
3213 | tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp); | |
3214 | /* calc SAV bit */ | |
3215 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
3216 | /* clear V bit */ | |
3217 | tcg_gen_movi_tl(cpu_PSW_V, 0); | |
3218 | tcg_temp_free(temp); | |
3219 | } | |
3220 | ||
9a31922b BK |
3221 | /* helpers for generating program flow micro-ops */ |
3222 | ||
3223 | static inline void gen_save_pc(target_ulong pc) | |
3224 | { | |
3225 | tcg_gen_movi_tl(cpu_PC, pc); | |
3226 | } | |
3227 | ||
1ed8739a BK |
3228 | static void generate_qemu_excp(DisasContext *ctx, int excp) |
3229 | { | |
3230 | TCGv_i32 tmp = tcg_const_i32(excp); | |
3231 | gen_helper_qemu_excp(cpu_env, tmp); | |
3232 | ctx->base.is_jmp = DISAS_NORETURN; | |
3233 | tcg_temp_free(tmp); | |
3234 | } | |
3235 | ||
d6b6f261 | 3236 | static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) |
9a31922b | 3237 | { |
d6b6f261 | 3238 | if (translator_use_goto_tb(&ctx->base, dest)) { |
9a31922b BK |
3239 | tcg_gen_goto_tb(n); |
3240 | gen_save_pc(dest); | |
6b9f5a42 | 3241 | tcg_gen_exit_tb(ctx->base.tb, n); |
9a31922b BK |
3242 | } else { |
3243 | gen_save_pc(dest); | |
6b9f5a42 | 3244 | if (ctx->base.singlestep_enabled) { |
1ed8739a | 3245 | generate_qemu_excp(ctx, EXCP_DEBUG); |
38064715 RH |
3246 | } else { |
3247 | tcg_gen_lookup_and_goto_ptr(); | |
9a31922b | 3248 | } |
9a31922b BK |
3249 | } |
3250 | } | |
3251 | ||
518d7fd2 BK |
3252 | static void generate_trap(DisasContext *ctx, int class, int tin) |
3253 | { | |
3254 | TCGv_i32 classtemp = tcg_const_i32(class); | |
3255 | TCGv_i32 tintemp = tcg_const_i32(tin); | |
3256 | ||
6b9f5a42 | 3257 | gen_save_pc(ctx->base.pc_next); |
518d7fd2 | 3258 | gen_helper_raise_exception_sync(cpu_env, classtemp, tintemp); |
6b9f5a42 | 3259 | ctx->base.is_jmp = DISAS_NORETURN; |
518d7fd2 BK |
3260 | |
3261 | tcg_temp_free(classtemp); | |
3262 | tcg_temp_free(tintemp); | |
3263 | } | |
3264 | ||
9a31922b BK |
3265 | static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1, |
3266 | TCGv r2, int16_t address) | |
3267 | { | |
42a268c2 | 3268 | TCGLabel *jumpLabel = gen_new_label(); |
9a31922b BK |
3269 | tcg_gen_brcond_tl(cond, r1, r2, jumpLabel); |
3270 | ||
6b9f5a42 | 3271 | gen_goto_tb(ctx, 1, ctx->pc_succ_insn); |
9a31922b BK |
3272 | |
3273 | gen_set_label(jumpLabel); | |
6b9f5a42 | 3274 | gen_goto_tb(ctx, 0, ctx->base.pc_next + address * 2); |
9a31922b BK |
3275 | } |
3276 | ||
3277 | static inline void gen_branch_condi(DisasContext *ctx, TCGCond cond, TCGv r1, | |
3278 | int r2, int16_t address) | |
3279 | { | |
3280 | TCGv temp = tcg_const_i32(r2); | |
3281 | gen_branch_cond(ctx, cond, r1, temp, address); | |
3282 | tcg_temp_free(temp); | |
3283 | } | |
3284 | ||
a47b50db BK |
3285 | static void gen_loop(DisasContext *ctx, int r1, int32_t offset) |
3286 | { | |
42a268c2 | 3287 | TCGLabel *l1 = gen_new_label(); |
a47b50db BK |
3288 | |
3289 | tcg_gen_subi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], 1); | |
3290 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr_a[r1], -1, l1); | |
6b9f5a42 | 3291 | gen_goto_tb(ctx, 1, ctx->base.pc_next + offset); |
a47b50db | 3292 | gen_set_label(l1); |
6b9f5a42 | 3293 | gen_goto_tb(ctx, 0, ctx->pc_succ_insn); |
a47b50db BK |
3294 | } |
3295 | ||
9e14a7b2 BK |
3296 | static void gen_fcall_save_ctx(DisasContext *ctx) |
3297 | { | |
3298 | TCGv temp = tcg_temp_new(); | |
3299 | ||
3300 | tcg_gen_addi_tl(temp, cpu_gpr_a[10], -4); | |
3301 | tcg_gen_qemu_st_tl(cpu_gpr_a[11], temp, ctx->mem_idx, MO_LESL); | |
6b9f5a42 | 3302 | tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); |
9e14a7b2 BK |
3303 | tcg_gen_mov_tl(cpu_gpr_a[10], temp); |
3304 | ||
3305 | tcg_temp_free(temp); | |
3306 | } | |
3307 | ||
0e045f43 BK |
3308 | static void gen_fret(DisasContext *ctx) |
3309 | { | |
3310 | TCGv temp = tcg_temp_new(); | |
3311 | ||
3312 | tcg_gen_andi_tl(temp, cpu_gpr_a[11], ~0x1); | |
3313 | tcg_gen_qemu_ld_tl(cpu_gpr_a[11], cpu_gpr_a[10], ctx->mem_idx, MO_LESL); | |
3314 | tcg_gen_addi_tl(cpu_gpr_a[10], cpu_gpr_a[10], 4); | |
3315 | tcg_gen_mov_tl(cpu_PC, temp); | |
07ea28b4 | 3316 | tcg_gen_exit_tb(NULL, 0); |
6b9f5a42 | 3317 | ctx->base.is_jmp = DISAS_NORETURN; |
0e045f43 BK |
3318 | |
3319 | tcg_temp_free(temp); | |
3320 | } | |
3321 | ||
9a31922b BK |
3322 | static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, |
3323 | int r2 , int32_t constant , int32_t offset) | |
3324 | { | |
a68e0d54 | 3325 | TCGv temp, temp2; |
83c1bb18 | 3326 | int n; |
70b02262 | 3327 | |
9a31922b BK |
3328 | switch (opc) { |
3329 | /* SB-format jumps */ | |
3330 | case OPC1_16_SB_J: | |
3331 | case OPC1_32_B_J: | |
6b9f5a42 | 3332 | gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); |
9a31922b | 3333 | break; |
f718b0bb | 3334 | case OPC1_32_B_CALL: |
9a31922b | 3335 | case OPC1_16_SB_CALL: |
6b9f5a42 BK |
3336 | gen_helper_1arg(call, ctx->pc_succ_insn); |
3337 | gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); | |
9a31922b BK |
3338 | break; |
3339 | case OPC1_16_SB_JZ: | |
3340 | gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], 0, offset); | |
3341 | break; | |
3342 | case OPC1_16_SB_JNZ: | |
3343 | gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 0, offset); | |
3344 | break; | |
70b02262 BK |
3345 | /* SBC-format jumps */ |
3346 | case OPC1_16_SBC_JEQ: | |
3347 | gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, offset); | |
3348 | break; | |
dedd8c9c PA |
3349 | case OPC1_16_SBC_JEQ2: |
3350 | gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, | |
3351 | offset + 16); | |
3352 | break; | |
70b02262 BK |
3353 | case OPC1_16_SBC_JNE: |
3354 | gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset); | |
3355 | break; | |
dedd8c9c PA |
3356 | case OPC1_16_SBC_JNE2: |
3357 | gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], | |
3358 | constant, offset + 16); | |
3359 | break; | |
70b02262 BK |
3360 | /* SBRN-format jumps */ |
3361 | case OPC1_16_SBRN_JZ_T: | |
3362 | temp = tcg_temp_new(); | |
3363 | tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant); | |
3364 | gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset); | |
3365 | tcg_temp_free(temp); | |
3366 | break; | |
3367 | case OPC1_16_SBRN_JNZ_T: | |
3368 | temp = tcg_temp_new(); | |
3369 | tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant); | |
3370 | gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset); | |
3371 | tcg_temp_free(temp); | |
3372 | break; | |
a47b50db BK |
3373 | /* SBR-format jumps */ |
3374 | case OPC1_16_SBR_JEQ: | |
3375 | gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], | |
3376 | offset); | |
3377 | break; | |
defda2d4 DB |
3378 | case OPC1_16_SBR_JEQ2: |
3379 | gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], | |
3380 | offset + 16); | |
3381 | break; | |
a47b50db BK |
3382 | case OPC1_16_SBR_JNE: |
3383 | gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], | |
3384 | offset); | |
3385 | break; | |
defda2d4 DB |
3386 | case OPC1_16_SBR_JNE2: |
3387 | gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], | |
3388 | offset + 16); | |
3389 | break; | |
a47b50db BK |
3390 | case OPC1_16_SBR_JNZ: |
3391 | gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], 0, offset); | |
3392 | break; | |
3393 | case OPC1_16_SBR_JNZ_A: | |
3394 | gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset); | |
3395 | break; | |
3396 | case OPC1_16_SBR_JGEZ: | |
3397 | gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], 0, offset); | |
3398 | break; | |
3399 | case OPC1_16_SBR_JGTZ: | |
3400 | gen_branch_condi(ctx, TCG_COND_GT, cpu_gpr_d[r1], 0, offset); | |
3401 | break; | |
3402 | case OPC1_16_SBR_JLEZ: | |
3403 | gen_branch_condi(ctx, TCG_COND_LE, cpu_gpr_d[r1], 0, offset); | |
3404 | break; | |
3405 | case OPC1_16_SBR_JLTZ: | |
3406 | gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], 0, offset); | |
3407 | break; | |
3408 | case OPC1_16_SBR_JZ: | |
3409 | gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], 0, offset); | |
3410 | break; | |
3411 | case OPC1_16_SBR_JZ_A: | |
3412 | gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset); | |
3413 | break; | |
3414 | case OPC1_16_SBR_LOOP: | |
3415 | gen_loop(ctx, r1, offset * 2 - 32); | |
3416 | break; | |
44ea3430 BK |
3417 | /* SR-format jumps */ |
3418 | case OPC1_16_SR_JI: | |
3419 | tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], 0xfffffffe); | |
07ea28b4 | 3420 | tcg_gen_exit_tb(NULL, 0); |
44ea3430 | 3421 | break; |
b724b012 | 3422 | case OPC2_32_SYS_RET: |
44ea3430 BK |
3423 | case OPC2_16_SR_RET: |
3424 | gen_helper_ret(cpu_env); | |
07ea28b4 | 3425 | tcg_gen_exit_tb(NULL, 0); |
44ea3430 | 3426 | break; |
f718b0bb BK |
3427 | /* B-format */ |
3428 | case OPC1_32_B_CALLA: | |
6b9f5a42 | 3429 | gen_helper_1arg(call, ctx->pc_succ_insn); |
f718b0bb BK |
3430 | gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); |
3431 | break; | |
9e14a7b2 BK |
3432 | case OPC1_32_B_FCALL: |
3433 | gen_fcall_save_ctx(ctx); | |
6b9f5a42 | 3434 | gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); |
9e14a7b2 BK |
3435 | break; |
3436 | case OPC1_32_B_FCALLA: | |
3437 | gen_fcall_save_ctx(ctx); | |
3438 | gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); | |
3439 | break; | |
f718b0bb | 3440 | case OPC1_32_B_JLA: |
6b9f5a42 | 3441 | tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); |
40a1f64b | 3442 | /* fall through */ |
f718b0bb BK |
3443 | case OPC1_32_B_JA: |
3444 | gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); | |
3445 | break; | |
3446 | case OPC1_32_B_JL: | |
6b9f5a42 BK |
3447 | tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); |
3448 | gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); | |
f718b0bb | 3449 | break; |
fc2ef4a3 BK |
3450 | /* BOL format */ |
3451 | case OPCM_32_BRC_EQ_NEQ: | |
3452 | if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JEQ) { | |
3453 | gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], constant, offset); | |
3454 | } else { | |
3455 | gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], constant, offset); | |
3456 | } | |
3457 | break; | |
3458 | case OPCM_32_BRC_GE: | |
3459 | if (MASK_OP_BRC_OP2(ctx->opcode) == OP2_32_BRC_JGE) { | |
3460 | gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], constant, offset); | |
3461 | } else { | |
3462 | constant = MASK_OP_BRC_CONST4(ctx->opcode); | |
3463 | gen_branch_condi(ctx, TCG_COND_GEU, cpu_gpr_d[r1], constant, | |
3464 | offset); | |
3465 | } | |
3466 | break; | |
3467 | case OPCM_32_BRC_JLT: | |
3468 | if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JLT) { | |
3469 | gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], constant, offset); | |
3470 | } else { | |
3471 | constant = MASK_OP_BRC_CONST4(ctx->opcode); | |
3472 | gen_branch_condi(ctx, TCG_COND_LTU, cpu_gpr_d[r1], constant, | |
3473 | offset); | |
3474 | } | |
3475 | break; | |
3476 | case OPCM_32_BRC_JNE: | |
3477 | temp = tcg_temp_new(); | |
3478 | if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JNED) { | |
3479 | tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); | |
3480 | /* subi is unconditional */ | |
3481 | tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); | |
3482 | gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset); | |
3483 | } else { | |
3484 | tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); | |
3485 | /* addi is unconditional */ | |
3486 | tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); | |
3487 | gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset); | |
3488 | } | |
3489 | tcg_temp_free(temp); | |
3490 | break; | |
83c1bb18 BK |
3491 | /* BRN format */ |
3492 | case OPCM_32_BRN_JTT: | |
3493 | n = MASK_OP_BRN_N(ctx->opcode); | |
3494 | ||
3495 | temp = tcg_temp_new(); | |
3496 | tcg_gen_andi_tl(temp, cpu_gpr_d[r1], (1 << n)); | |
3497 | ||
3498 | if (MASK_OP_BRN_OP2(ctx->opcode) == OPC2_32_BRN_JNZ_T) { | |
3499 | gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset); | |
3500 | } else { | |
3501 | gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset); | |
3502 | } | |
3503 | tcg_temp_free(temp); | |
3504 | break; | |
a68e0d54 BK |
3505 | /* BRR Format */ |
3506 | case OPCM_32_BRR_EQ_NEQ: | |
3507 | if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ) { | |
3508 | gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], | |
3509 | offset); | |
3510 | } else { | |
3511 | gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], | |
3512 | offset); | |
3513 | } | |
3514 | break; | |
3515 | case OPCM_32_BRR_ADDR_EQ_NEQ: | |
3516 | if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ_A) { | |
3517 | gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_a[r1], cpu_gpr_a[r2], | |
3518 | offset); | |
3519 | } else { | |
3520 | gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_a[r1], cpu_gpr_a[r2], | |
3521 | offset); | |
3522 | } | |
3523 | break; | |
3524 | case OPCM_32_BRR_GE: | |
3525 | if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JGE) { | |
3526 | gen_branch_cond(ctx, TCG_COND_GE, cpu_gpr_d[r1], cpu_gpr_d[r2], | |
3527 | offset); | |
3528 | } else { | |
3529 | gen_branch_cond(ctx, TCG_COND_GEU, cpu_gpr_d[r1], cpu_gpr_d[r2], | |
3530 | offset); | |
3531 | } | |
3532 | break; | |
3533 | case OPCM_32_BRR_JLT: | |
3534 | if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JLT) { | |
3535 | gen_branch_cond(ctx, TCG_COND_LT, cpu_gpr_d[r1], cpu_gpr_d[r2], | |
3536 | offset); | |
3537 | } else { | |
3538 | gen_branch_cond(ctx, TCG_COND_LTU, cpu_gpr_d[r1], cpu_gpr_d[r2], | |
3539 | offset); | |
3540 | } | |
3541 | break; | |
3542 | case OPCM_32_BRR_LOOP: | |
3543 | if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_LOOP) { | |
250ef8c7 | 3544 | gen_loop(ctx, r2, offset * 2); |
a68e0d54 BK |
3545 | } else { |
3546 | /* OPC2_32_BRR_LOOPU */ | |
6b9f5a42 | 3547 | gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); |
a68e0d54 BK |
3548 | } |
3549 | break; | |
3550 | case OPCM_32_BRR_JNE: | |
3551 | temp = tcg_temp_new(); | |
3552 | temp2 = tcg_temp_new(); | |
3553 | if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRR_JNED) { | |
3554 | tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); | |
3555 | /* also save r2, in case of r1 == r2, so r2 is not decremented */ | |
3556 | tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]); | |
3557 | /* subi is unconditional */ | |
3558 | tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); | |
3559 | gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset); | |
3560 | } else { | |
3561 | tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); | |
3562 | /* also save r2, in case of r1 == r2, so r2 is not decremented */ | |
3563 | tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]); | |
3564 | /* addi is unconditional */ | |
3565 | tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); | |
3566 | gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset); | |
3567 | } | |
3568 | tcg_temp_free(temp); | |
3569 | tcg_temp_free(temp2); | |
3570 | break; | |
3571 | case OPCM_32_BRR_JNZ: | |
3572 | if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JNZ_A) { | |
3573 | gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset); | |
3574 | } else { | |
3575 | gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset); | |
3576 | } | |
3577 | break; | |
9a31922b | 3578 | default: |
f678f671 | 3579 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); |
9a31922b | 3580 | } |
6b9f5a42 | 3581 | ctx->base.is_jmp = DISAS_NORETURN; |
9a31922b BK |
3582 | } |
3583 | ||
3584 | ||
0707ec1b BK |
3585 | /* |
3586 | * Functions for decoding instructions | |
3587 | */ | |
3588 | ||
2db92a0c | 3589 | static void decode_src_opc(DisasContext *ctx, int op1) |
0707ec1b BK |
3590 | { |
3591 | int r1; | |
3592 | int32_t const4; | |
3593 | TCGv temp, temp2; | |
3594 | ||
3595 | r1 = MASK_OP_SRC_S1D(ctx->opcode); | |
3596 | const4 = MASK_OP_SRC_CONST4_SEXT(ctx->opcode); | |
3597 | ||
3598 | switch (op1) { | |
3599 | case OPC1_16_SRC_ADD: | |
3600 | gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[r1], const4); | |
3601 | break; | |
3602 | case OPC1_16_SRC_ADD_A15: | |
3603 | gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[15], const4); | |
3604 | break; | |
3605 | case OPC1_16_SRC_ADD_15A: | |
3606 | gen_addi_d(cpu_gpr_d[15], cpu_gpr_d[r1], const4); | |
3607 | break; | |
3608 | case OPC1_16_SRC_ADD_A: | |
3609 | tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], const4); | |
3610 | break; | |
3611 | case OPC1_16_SRC_CADD: | |
3612 | gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const4, cpu_gpr_d[r1], | |
3613 | cpu_gpr_d[15]); | |
3614 | break; | |
3615 | case OPC1_16_SRC_CADDN: | |
3616 | gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const4, cpu_gpr_d[r1], | |
3617 | cpu_gpr_d[15]); | |
3618 | break; | |
3619 | case OPC1_16_SRC_CMOV: | |
3620 | temp = tcg_const_tl(0); | |
3621 | temp2 = tcg_const_tl(const4); | |
3622 | tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp, | |
3623 | temp2, cpu_gpr_d[r1]); | |
3624 | tcg_temp_free(temp); | |
3625 | tcg_temp_free(temp2); | |
3626 | break; | |
3627 | case OPC1_16_SRC_CMOVN: | |
3628 | temp = tcg_const_tl(0); | |
3629 | temp2 = tcg_const_tl(const4); | |
3630 | tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp, | |
3631 | temp2, cpu_gpr_d[r1]); | |
3632 | tcg_temp_free(temp); | |
3633 | tcg_temp_free(temp2); | |
3634 | break; | |
3635 | case OPC1_16_SRC_EQ: | |
3636 | tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1], | |
3637 | const4); | |
3638 | break; | |
3639 | case OPC1_16_SRC_LT: | |
3640 | tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1], | |
3641 | const4); | |
3642 | break; | |
3643 | case OPC1_16_SRC_MOV: | |
3644 | tcg_gen_movi_tl(cpu_gpr_d[r1], const4); | |
3645 | break; | |
3646 | case OPC1_16_SRC_MOV_A: | |
3647 | const4 = MASK_OP_SRC_CONST4(ctx->opcode); | |
3648 | tcg_gen_movi_tl(cpu_gpr_a[r1], const4); | |
3649 | break; | |
fcecf126 | 3650 | case OPC1_16_SRC_MOV_E: |
44ee3baf | 3651 | if (has_feature(ctx, TRICORE_FEATURE_16)) { |
fcecf126 BK |
3652 | tcg_gen_movi_tl(cpu_gpr_d[r1], const4); |
3653 | tcg_gen_sari_tl(cpu_gpr_d[r1+1], cpu_gpr_d[r1], 31); | |
f678f671 BK |
3654 | } else { |
3655 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
3656 | } | |
fcecf126 | 3657 | break; |
0707ec1b BK |
3658 | case OPC1_16_SRC_SH: |
3659 | gen_shi(cpu_gpr_d[r1], cpu_gpr_d[r1], const4); | |
3660 | break; | |
3661 | case OPC1_16_SRC_SHA: | |
3662 | gen_shaci(cpu_gpr_d[r1], cpu_gpr_d[r1], const4); | |
3663 | break; | |
f678f671 BK |
3664 | default: |
3665 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
0707ec1b BK |
3666 | } |
3667 | } | |
3668 | ||
2692802a BK |
3669 | static void decode_srr_opc(DisasContext *ctx, int op1) |
3670 | { | |
3671 | int r1, r2; | |
3672 | TCGv temp; | |
3673 | ||
3674 | r1 = MASK_OP_SRR_S1D(ctx->opcode); | |
3675 | r2 = MASK_OP_SRR_S2(ctx->opcode); | |
3676 | ||
3677 | switch (op1) { | |
3678 | case OPC1_16_SRR_ADD: | |
3679 | gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
3680 | break; | |
3681 | case OPC1_16_SRR_ADD_A15: | |
3682 | gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]); | |
3683 | break; | |
3684 | case OPC1_16_SRR_ADD_15A: | |
3685 | gen_add_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
3686 | break; | |
3687 | case OPC1_16_SRR_ADD_A: | |
3688 | tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], cpu_gpr_a[r2]); | |
3689 | break; | |
3690 | case OPC1_16_SRR_ADDS: | |
3691 | gen_adds(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
3692 | break; | |
3693 | case OPC1_16_SRR_AND: | |
3694 | tcg_gen_and_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
3695 | break; | |
3696 | case OPC1_16_SRR_CMOV: | |
3697 | temp = tcg_const_tl(0); | |
3698 | tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp, | |
3699 | cpu_gpr_d[r2], cpu_gpr_d[r1]); | |
3700 | tcg_temp_free(temp); | |
3701 | break; | |
3702 | case OPC1_16_SRR_CMOVN: | |
3703 | temp = tcg_const_tl(0); | |
3704 | tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp, | |
3705 | cpu_gpr_d[r2], cpu_gpr_d[r1]); | |
3706 | tcg_temp_free(temp); | |
3707 | break; | |
3708 | case OPC1_16_SRR_EQ: | |
3709 | tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1], | |
3710 | cpu_gpr_d[r2]); | |
3711 | break; | |
3712 | case OPC1_16_SRR_LT: | |
3713 | tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1], | |
3714 | cpu_gpr_d[r2]); | |
3715 | break; | |
3716 | case OPC1_16_SRR_MOV: | |
3717 | tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
3718 | break; | |
3719 | case OPC1_16_SRR_MOV_A: | |
3720 | tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_d[r2]); | |
3721 | break; | |
3722 | case OPC1_16_SRR_MOV_AA: | |
3723 | tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_a[r2]); | |
3724 | break; | |
3725 | case OPC1_16_SRR_MOV_D: | |
3726 | tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_a[r2]); | |
3727 | break; | |
3728 | case OPC1_16_SRR_MUL: | |
3729 | gen_mul_i32s(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
3730 | break; | |
3731 | case OPC1_16_SRR_OR: | |
3732 | tcg_gen_or_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
3733 | break; | |
3734 | case OPC1_16_SRR_SUB: | |
3735 | gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
3736 | break; | |
3737 | case OPC1_16_SRR_SUB_A15B: | |
3738 | gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]); | |
3739 | break; | |
3740 | case OPC1_16_SRR_SUB_15AB: | |
3741 | gen_sub_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
3742 | break; | |
3743 | case OPC1_16_SRR_SUBS: | |
3744 | gen_subs(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
3745 | break; | |
3746 | case OPC1_16_SRR_XOR: | |
3747 | tcg_gen_xor_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
3748 | break; | |
f678f671 BK |
3749 | default: |
3750 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
2692802a BK |
3751 | } |
3752 | } | |
3753 | ||
46aa848f BK |
3754 | static void decode_ssr_opc(DisasContext *ctx, int op1) |
3755 | { | |
3756 | int r1, r2; | |
3757 | ||
3758 | r1 = MASK_OP_SSR_S1(ctx->opcode); | |
3759 | r2 = MASK_OP_SSR_S2(ctx->opcode); | |
3760 | ||
3761 | switch (op1) { | |
3762 | case OPC1_16_SSR_ST_A: | |
3763 | tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); | |
3764 | break; | |
3765 | case OPC1_16_SSR_ST_A_POSTINC: | |
3766 | tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); | |
3767 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); | |
3768 | break; | |
3769 | case OPC1_16_SSR_ST_B: | |
3770 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); | |
3771 | break; | |
3772 | case OPC1_16_SSR_ST_B_POSTINC: | |
3773 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); | |
3774 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1); | |
3775 | break; | |
3776 | case OPC1_16_SSR_ST_H: | |
3777 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW); | |
3778 | break; | |
3779 | case OPC1_16_SSR_ST_H_POSTINC: | |
3780 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW); | |
3781 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2); | |
3782 | break; | |
3783 | case OPC1_16_SSR_ST_W: | |
3784 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); | |
3785 | break; | |
3786 | case OPC1_16_SSR_ST_W_POSTINC: | |
3787 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); | |
3788 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); | |
3789 | break; | |
f678f671 BK |
3790 | default: |
3791 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
46aa848f BK |
3792 | } |
3793 | } | |
3794 | ||
5de93515 BK |
3795 | static void decode_sc_opc(DisasContext *ctx, int op1) |
3796 | { | |
3797 | int32_t const16; | |
3798 | ||
3799 | const16 = MASK_OP_SC_CONST8(ctx->opcode); | |
3800 | ||
3801 | switch (op1) { | |
3802 | case OPC1_16_SC_AND: | |
3803 | tcg_gen_andi_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16); | |
3804 | break; | |
3805 | case OPC1_16_SC_BISR: | |
3806 | gen_helper_1arg(bisr, const16 & 0xff); | |
3807 | break; | |
3808 | case OPC1_16_SC_LD_A: | |
3809 | gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL); | |
3810 | break; | |
3811 | case OPC1_16_SC_LD_W: | |
3812 | gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL); | |
3813 | break; | |
3814 | case OPC1_16_SC_MOV: | |
3815 | tcg_gen_movi_tl(cpu_gpr_d[15], const16); | |
3816 | break; | |
3817 | case OPC1_16_SC_OR: | |
3818 | tcg_gen_ori_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16); | |
3819 | break; | |
3820 | case OPC1_16_SC_ST_A: | |
3821 | gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL); | |
3822 | break; | |
3823 | case OPC1_16_SC_ST_W: | |
3824 | gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL); | |
3825 | break; | |
3826 | case OPC1_16_SC_SUB_A: | |
3827 | tcg_gen_subi_tl(cpu_gpr_a[10], cpu_gpr_a[10], const16); | |
3828 | break; | |
f678f671 BK |
3829 | default: |
3830 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
5de93515 BK |
3831 | } |
3832 | } | |
5a7634a2 BK |
3833 | |
3834 | static void decode_slr_opc(DisasContext *ctx, int op1) | |
3835 | { | |
3836 | int r1, r2; | |
3837 | ||
3838 | r1 = MASK_OP_SLR_D(ctx->opcode); | |
3839 | r2 = MASK_OP_SLR_S2(ctx->opcode); | |
3840 | ||
3841 | switch (op1) { | |
3842 | /* SLR-format */ | |
3843 | case OPC1_16_SLR_LD_A: | |
3844 | tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); | |
3845 | break; | |
3846 | case OPC1_16_SLR_LD_A_POSTINC: | |
3847 | tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); | |
3848 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); | |
3849 | break; | |
3850 | case OPC1_16_SLR_LD_BU: | |
3851 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); | |
3852 | break; | |
3853 | case OPC1_16_SLR_LD_BU_POSTINC: | |
3854 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); | |
3855 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1); | |
3856 | break; | |
3857 | case OPC1_16_SLR_LD_H: | |
3858 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW); | |
3859 | break; | |
3860 | case OPC1_16_SLR_LD_H_POSTINC: | |
3861 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW); | |
3862 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2); | |
3863 | break; | |
3864 | case OPC1_16_SLR_LD_W: | |
7bd0eaec | 3865 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); |
5a7634a2 BK |
3866 | break; |
3867 | case OPC1_16_SLR_LD_W_POSTINC: | |
7bd0eaec | 3868 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); |
5a7634a2 BK |
3869 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); |
3870 | break; | |
f678f671 BK |
3871 | default: |
3872 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
5a7634a2 BK |
3873 | } |
3874 | } | |
3875 | ||
3876 | static void decode_sro_opc(DisasContext *ctx, int op1) | |
3877 | { | |
3878 | int r2; | |
3879 | int32_t address; | |
3880 | ||
3881 | r2 = MASK_OP_SRO_S2(ctx->opcode); | |
3882 | address = MASK_OP_SRO_OFF4(ctx->opcode); | |
3883 | ||
3884 | /* SRO-format */ | |
3885 | switch (op1) { | |
3886 | case OPC1_16_SRO_LD_A: | |
3887 | gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL); | |
3888 | break; | |
3889 | case OPC1_16_SRO_LD_BU: | |
3890 | gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB); | |
3891 | break; | |
3892 | case OPC1_16_SRO_LD_H: | |
3893 | gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_LESW); | |
3894 | break; | |
3895 | case OPC1_16_SRO_LD_W: | |
3896 | gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL); | |
3897 | break; | |
3898 | case OPC1_16_SRO_ST_A: | |
3899 | gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL); | |
3900 | break; | |
3901 | case OPC1_16_SRO_ST_B: | |
3902 | gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB); | |
3903 | break; | |
3904 | case OPC1_16_SRO_ST_H: | |
3905 | gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW); | |
3906 | break; | |
3907 | case OPC1_16_SRO_ST_W: | |
3908 | gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL); | |
3909 | break; | |
f678f671 BK |
3910 | default: |
3911 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
5a7634a2 BK |
3912 | } |
3913 | } | |
3914 | ||
2db92a0c | 3915 | static void decode_sr_system(DisasContext *ctx) |
44ea3430 BK |
3916 | { |
3917 | uint32_t op2; | |
3918 | op2 = MASK_OP_SR_OP2(ctx->opcode); | |
3919 | ||
3920 | switch (op2) { | |
3921 | case OPC2_16_SR_NOP: | |
3922 | break; | |
3923 | case OPC2_16_SR_RET: | |
3924 | gen_compute_branch(ctx, op2, 0, 0, 0, 0); | |
3925 | break; | |
3926 | case OPC2_16_SR_RFE: | |
3927 | gen_helper_rfe(cpu_env); | |
07ea28b4 | 3928 | tcg_gen_exit_tb(NULL, 0); |
6b9f5a42 | 3929 | ctx->base.is_jmp = DISAS_NORETURN; |
44ea3430 BK |
3930 | break; |
3931 | case OPC2_16_SR_DEBUG: | |
3932 | /* raise EXCP_DEBUG */ | |
3933 | break; | |
0e045f43 BK |
3934 | case OPC2_16_SR_FRET: |
3935 | gen_fret(ctx); | |
f678f671 BK |
3936 | break; |
3937 | default: | |
3938 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
44ea3430 BK |
3939 | } |
3940 | } | |
3941 | ||
2db92a0c | 3942 | static void decode_sr_accu(DisasContext *ctx) |
44ea3430 BK |
3943 | { |
3944 | uint32_t op2; | |
3945 | uint32_t r1; | |
3946 | TCGv temp; | |
3947 | ||
3948 | r1 = MASK_OP_SR_S1D(ctx->opcode); | |
3949 | op2 = MASK_OP_SR_OP2(ctx->opcode); | |
3950 | ||
3951 | switch (op2) { | |
3952 | case OPC2_16_SR_RSUB: | |
3953 | /* overflow only if r1 = -0x80000000 */ | |
3954 | temp = tcg_const_i32(-0x80000000); | |
3955 | /* calc V bit */ | |
3956 | tcg_gen_setcond_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r1], temp); | |
3957 | tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); | |
3958 | /* calc SV bit */ | |
3959 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
3960 | /* sub */ | |
3961 | tcg_gen_neg_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]); | |
3962 | /* calc av */ | |
3963 | tcg_gen_add_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_gpr_d[r1]); | |
3964 | tcg_gen_xor_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_PSW_AV); | |
3965 | /* calc sav */ | |
3966 | tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); | |
3967 | tcg_temp_free(temp); | |
3968 | break; | |
3969 | case OPC2_16_SR_SAT_B: | |
3970 | gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7f, -0x80); | |
3971 | break; | |
3972 | case OPC2_16_SR_SAT_BU: | |
3973 | gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xff); | |
3974 | break; | |
3975 | case OPC2_16_SR_SAT_H: | |
3976 | gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7fff, -0x8000); | |
3977 | break; | |
3978 | case OPC2_16_SR_SAT_HU: | |
3979 | gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xffff); | |
3980 | break; | |
f678f671 BK |
3981 | default: |
3982 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
44ea3430 BK |
3983 | } |
3984 | } | |
3985 | ||
2db92a0c | 3986 | static void decode_16Bit_opc(DisasContext *ctx) |
0aaeb118 | 3987 | { |
0707ec1b | 3988 | int op1; |
d2798210 BK |
3989 | int r1, r2; |
3990 | int32_t const16; | |
9a31922b | 3991 | int32_t address; |
d2798210 | 3992 | TCGv temp; |
0707ec1b BK |
3993 | |
3994 | op1 = MASK_OP_MAJOR(ctx->opcode); | |
3995 | ||
d2798210 BK |
3996 | /* handle ADDSC.A opcode only being 6 bit long */ |
3997 | if (unlikely((op1 & 0x3f) == OPC1_16_SRRS_ADDSC_A)) { | |
3998 | op1 = OPC1_16_SRRS_ADDSC_A; | |
3999 | } | |
4000 | ||
0707ec1b BK |
4001 | switch (op1) { |
4002 | case OPC1_16_SRC_ADD: | |
4003 | case OPC1_16_SRC_ADD_A15: | |
4004 | case OPC1_16_SRC_ADD_15A: | |
4005 | case OPC1_16_SRC_ADD_A: | |
4006 | case OPC1_16_SRC_CADD: | |
4007 | case OPC1_16_SRC_CADDN: | |
4008 | case OPC1_16_SRC_CMOV: | |
4009 | case OPC1_16_SRC_CMOVN: | |
4010 | case OPC1_16_SRC_EQ: | |
4011 | case OPC1_16_SRC_LT: | |
4012 | case OPC1_16_SRC_MOV: | |
4013 | case OPC1_16_SRC_MOV_A: | |
fcecf126 | 4014 | case OPC1_16_SRC_MOV_E: |
0707ec1b BK |
4015 | case OPC1_16_SRC_SH: |
4016 | case OPC1_16_SRC_SHA: | |
2db92a0c | 4017 | decode_src_opc(ctx, op1); |
0707ec1b | 4018 | break; |
2692802a BK |
4019 | /* SRR-format */ |
4020 | case OPC1_16_SRR_ADD: | |
4021 | case OPC1_16_SRR_ADD_A15: | |
4022 | case OPC1_16_SRR_ADD_15A: | |
4023 | case OPC1_16_SRR_ADD_A: | |
4024 | case OPC1_16_SRR_ADDS: | |
4025 | case OPC1_16_SRR_AND: | |
4026 | case OPC1_16_SRR_CMOV: | |
4027 | case OPC1_16_SRR_CMOVN: | |
4028 | case OPC1_16_SRR_EQ: | |
4029 | case OPC1_16_SRR_LT: | |
4030 | case OPC1_16_SRR_MOV: | |
4031 | case OPC1_16_SRR_MOV_A: | |
4032 | case OPC1_16_SRR_MOV_AA: | |
4033 | case OPC1_16_SRR_MOV_D: | |
4034 | case OPC1_16_SRR_MUL: | |
4035 | case OPC1_16_SRR_OR: | |
4036 | case OPC1_16_SRR_SUB: | |
4037 | case OPC1_16_SRR_SUB_A15B: | |
4038 | case OPC1_16_SRR_SUB_15AB: | |
4039 | case OPC1_16_SRR_SUBS: | |
4040 | case OPC1_16_SRR_XOR: | |
4041 | decode_srr_opc(ctx, op1); | |
4042 | break; | |
46aa848f BK |
4043 | /* SSR-format */ |
4044 | case OPC1_16_SSR_ST_A: | |
4045 | case OPC1_16_SSR_ST_A_POSTINC: | |
4046 | case OPC1_16_SSR_ST_B: | |
4047 | case OPC1_16_SSR_ST_B_POSTINC: | |
4048 | case OPC1_16_SSR_ST_H: | |
4049 | case OPC1_16_SSR_ST_H_POSTINC: | |
4050 | case OPC1_16_SSR_ST_W: | |
4051 | case OPC1_16_SSR_ST_W_POSTINC: | |
4052 | decode_ssr_opc(ctx, op1); | |
4053 | break; | |
d2798210 BK |
4054 | /* SRRS-format */ |
4055 | case OPC1_16_SRRS_ADDSC_A: | |
4056 | r2 = MASK_OP_SRRS_S2(ctx->opcode); | |
4057 | r1 = MASK_OP_SRRS_S1D(ctx->opcode); | |
4058 | const16 = MASK_OP_SRRS_N(ctx->opcode); | |
4059 | temp = tcg_temp_new(); | |
4060 | tcg_gen_shli_tl(temp, cpu_gpr_d[15], const16); | |
4061 | tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], temp); | |
4062 | tcg_temp_free(temp); | |
4063 | break; | |
4064 | /* SLRO-format */ | |
4065 | case OPC1_16_SLRO_LD_A: | |
4066 | r1 = MASK_OP_SLRO_D(ctx->opcode); | |
4067 | const16 = MASK_OP_SLRO_OFF4(ctx->opcode); | |
4068 | gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); | |
4069 | break; | |
4070 | case OPC1_16_SLRO_LD_BU: | |
4071 | r1 = MASK_OP_SLRO_D(ctx->opcode); | |
4072 | const16 = MASK_OP_SLRO_OFF4(ctx->opcode); | |
4073 | gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB); | |
4074 | break; | |
4075 | case OPC1_16_SLRO_LD_H: | |
4076 | r1 = MASK_OP_SLRO_D(ctx->opcode); | |
4077 | const16 = MASK_OP_SLRO_OFF4(ctx->opcode); | |
4078 | gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW); | |
4079 | break; | |
4080 | case OPC1_16_SLRO_LD_W: | |
4081 | r1 = MASK_OP_SLRO_D(ctx->opcode); | |
4082 | const16 = MASK_OP_SLRO_OFF4(ctx->opcode); | |
4083 | gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); | |
4084 | break; | |
9a31922b BK |
4085 | /* SB-format */ |
4086 | case OPC1_16_SB_CALL: | |
4087 | case OPC1_16_SB_J: | |
4088 | case OPC1_16_SB_JNZ: | |
4089 | case OPC1_16_SB_JZ: | |
4090 | address = MASK_OP_SB_DISP8_SEXT(ctx->opcode); | |
4091 | gen_compute_branch(ctx, op1, 0, 0, 0, address); | |
4092 | break; | |
70b02262 BK |
4093 | /* SBC-format */ |
4094 | case OPC1_16_SBC_JEQ: | |
4095 | case OPC1_16_SBC_JNE: | |
4096 | address = MASK_OP_SBC_DISP4(ctx->opcode); | |
4097 | const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode); | |
4098 | gen_compute_branch(ctx, op1, 0, 0, const16, address); | |
4099 | break; | |
dedd8c9c PA |
4100 | case OPC1_16_SBC_JEQ2: |
4101 | case OPC1_16_SBC_JNE2: | |
44ee3baf | 4102 | if (has_feature(ctx, TRICORE_FEATURE_16)) { |
dedd8c9c PA |
4103 | address = MASK_OP_SBC_DISP4(ctx->opcode); |
4104 | const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode); | |
4105 | gen_compute_branch(ctx, op1, 0, 0, const16, address); | |
4106 | } else { | |
4107 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
4108 | } | |
4109 | break; | |
70b02262 BK |
4110 | /* SBRN-format */ |
4111 | case OPC1_16_SBRN_JNZ_T: | |
4112 | case OPC1_16_SBRN_JZ_T: | |
4113 | address = MASK_OP_SBRN_DISP4(ctx->opcode); | |
4114 | const16 = MASK_OP_SBRN_N(ctx->opcode); | |
4115 | gen_compute_branch(ctx, op1, 0, 0, const16, address); | |
4116 | break; | |
a47b50db | 4117 | /* SBR-format */ |
defda2d4 DB |
4118 | case OPC1_16_SBR_JEQ2: |
4119 | case OPC1_16_SBR_JNE2: | |
44ee3baf | 4120 | if (has_feature(ctx, TRICORE_FEATURE_16)) { |
defda2d4 DB |
4121 | r1 = MASK_OP_SBR_S2(ctx->opcode); |
4122 | address = MASK_OP_SBR_DISP4(ctx->opcode); | |
4123 | gen_compute_branch(ctx, op1, r1, 0, 0, address); | |
4124 | } else { | |
4125 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
4126 | } | |
4127 | break; | |
a47b50db BK |
4128 | case OPC1_16_SBR_JEQ: |
4129 | case OPC1_16_SBR_JGEZ: | |
4130 | case OPC1_16_SBR_JGTZ: | |
4131 | case OPC1_16_SBR_JLEZ: | |
4132 | case OPC1_16_SBR_JLTZ: | |
4133 | case OPC1_16_SBR_JNE: | |
4134 | case OPC1_16_SBR_JNZ: | |
4135 | case OPC1_16_SBR_JNZ_A: | |
4136 | case OPC1_16_SBR_JZ: | |
4137 | case OPC1_16_SBR_JZ_A: | |
4138 | case OPC1_16_SBR_LOOP: | |
4139 | r1 = MASK_OP_SBR_S2(ctx->opcode); | |
4140 | address = MASK_OP_SBR_DISP4(ctx->opcode); | |
4141 | gen_compute_branch(ctx, op1, r1, 0, 0, address); | |
4142 | break; | |
5de93515 BK |
4143 | /* SC-format */ |
4144 | case OPC1_16_SC_AND: | |
4145 | case OPC1_16_SC_BISR: | |
4146 | case OPC1_16_SC_LD_A: | |
4147 | case OPC1_16_SC_LD_W: | |
4148 | case OPC1_16_SC_MOV: | |
4149 | case OPC1_16_SC_OR: | |
4150 | case OPC1_16_SC_ST_A: | |
4151 | case OPC1_16_SC_ST_W: | |
4152 | case OPC1_16_SC_SUB_A: | |
4153 | decode_sc_opc(ctx, op1); | |
4154 | break; | |
5a7634a2 BK |
4155 | /* SLR-format */ |
4156 | case OPC1_16_SLR_LD_A: | |
4157 | case OPC1_16_SLR_LD_A_POSTINC: | |
4158 | case OPC1_16_SLR_LD_BU: | |
4159 | case OPC1_16_SLR_LD_BU_POSTINC: | |
4160 | case OPC1_16_SLR_LD_H: | |
4161 | case OPC1_16_SLR_LD_H_POSTINC: | |
4162 | case OPC1_16_SLR_LD_W: | |
4163 | case OPC1_16_SLR_LD_W_POSTINC: | |
4164 | decode_slr_opc(ctx, op1); | |
4165 | break; | |
4166 | /* SRO-format */ | |
4167 | case OPC1_16_SRO_LD_A: | |
4168 | case OPC1_16_SRO_LD_BU: | |
4169 | case OPC1_16_SRO_LD_H: | |
4170 | case OPC1_16_SRO_LD_W: | |
4171 | case OPC1_16_SRO_ST_A: | |
4172 | case OPC1_16_SRO_ST_B: | |
4173 | case OPC1_16_SRO_ST_H: | |
4174 | case OPC1_16_SRO_ST_W: | |
4175 | decode_sro_opc(ctx, op1); | |
4176 | break; | |
4177 | /* SSRO-format */ | |
4178 | case OPC1_16_SSRO_ST_A: | |
4179 | r1 = MASK_OP_SSRO_S1(ctx->opcode); | |
4180 | const16 = MASK_OP_SSRO_OFF4(ctx->opcode); | |
4181 | gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); | |
4182 | break; | |
4183 | case OPC1_16_SSRO_ST_B: | |
4184 | r1 = MASK_OP_SSRO_S1(ctx->opcode); | |
4185 | const16 = MASK_OP_SSRO_OFF4(ctx->opcode); | |
4186 | gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB); | |
4187 | break; | |
4188 | case OPC1_16_SSRO_ST_H: | |
4189 | r1 = MASK_OP_SSRO_S1(ctx->opcode); | |
4190 | const16 = MASK_OP_SSRO_OFF4(ctx->opcode); | |
4191 | gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW); | |
4192 | break; | |
4193 | case OPC1_16_SSRO_ST_W: | |
4194 | r1 = MASK_OP_SSRO_S1(ctx->opcode); | |
4195 | const16 = MASK_OP_SSRO_OFF4(ctx->opcode); | |
4196 | gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); | |
4197 | break; | |
44ea3430 BK |
4198 | /* SR-format */ |
4199 | case OPCM_16_SR_SYSTEM: | |
2db92a0c | 4200 | decode_sr_system(ctx); |
44ea3430 BK |
4201 | break; |
4202 | case OPCM_16_SR_ACCU: | |
2db92a0c | 4203 | decode_sr_accu(ctx); |
44ea3430 BK |
4204 | break; |
4205 | case OPC1_16_SR_JI: | |
4206 | r1 = MASK_OP_SR_S1D(ctx->opcode); | |
4207 | gen_compute_branch(ctx, op1, r1, 0, 0, 0); | |
4208 | break; | |
4209 | case OPC1_16_SR_NOT: | |
4210 | r1 = MASK_OP_SR_S1D(ctx->opcode); | |
4211 | tcg_gen_not_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]); | |
4212 | break; | |
f678f671 BK |
4213 | default: |
4214 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
0707ec1b | 4215 | } |
0aaeb118 BK |
4216 | } |
4217 | ||
59543d4e BK |
4218 | /* |
4219 | * 32 bit instructions | |
4220 | */ | |
4221 | ||
4222 | /* ABS-format */ | |
2db92a0c | 4223 | static void decode_abs_ldw(DisasContext *ctx) |
59543d4e BK |
4224 | { |
4225 | int32_t op2; | |
4226 | int32_t r1; | |
4227 | uint32_t address; | |
4228 | TCGv temp; | |
4229 | ||
4230 | r1 = MASK_OP_ABS_S1D(ctx->opcode); | |
4231 | address = MASK_OP_ABS_OFF18(ctx->opcode); | |
4232 | op2 = MASK_OP_ABS_OP2(ctx->opcode); | |
4233 | ||
4234 | temp = tcg_const_i32(EA_ABS_FORMAT(address)); | |
4235 | ||
4236 | switch (op2) { | |
4237 | case OPC2_32_ABS_LD_A: | |
4238 | tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL); | |
4239 | break; | |
4240 | case OPC2_32_ABS_LD_D: | |
828066c7 | 4241 | CHECK_REG_PAIR(r1); |
59543d4e BK |
4242 | gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); |
4243 | break; | |
4244 | case OPC2_32_ABS_LD_DA: | |
828066c7 | 4245 | CHECK_REG_PAIR(r1); |
59543d4e BK |
4246 | gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); |
4247 | break; | |
4248 | case OPC2_32_ABS_LD_W: | |
4249 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL); | |
4250 | break; | |
f678f671 BK |
4251 | default: |
4252 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
59543d4e BK |
4253 | } |
4254 | ||
4255 | tcg_temp_free(temp); | |
4256 | } | |
4257 | ||
2db92a0c | 4258 | static void decode_abs_ldb(DisasContext *ctx) |
59543d4e BK |
4259 | { |
4260 | int32_t op2; | |
4261 | int32_t r1; | |
4262 | uint32_t address; | |
4263 | TCGv temp; | |
4264 | ||
4265 | r1 = MASK_OP_ABS_S1D(ctx->opcode); | |
4266 | address = MASK_OP_ABS_OFF18(ctx->opcode); | |
4267 | op2 = MASK_OP_ABS_OP2(ctx->opcode); | |
4268 | ||
4269 | temp = tcg_const_i32(EA_ABS_FORMAT(address)); | |
4270 | ||
4271 | switch (op2) { | |
4272 | case OPC2_32_ABS_LD_B: | |
4273 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_SB); | |
4274 | break; | |
4275 | case OPC2_32_ABS_LD_BU: | |
4276 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB); | |
4277 | break; | |
4278 | case OPC2_32_ABS_LD_H: | |
4279 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESW); | |
4280 | break; | |
4281 | case OPC2_32_ABS_LD_HU: | |
4282 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW); | |
4283 | break; | |
f678f671 BK |
4284 | default: |
4285 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
59543d4e BK |
4286 | } |
4287 | ||
4288 | tcg_temp_free(temp); | |
4289 | } | |
4290 | ||
2db92a0c | 4291 | static void decode_abs_ldst_swap(DisasContext *ctx) |
59543d4e BK |
4292 | { |
4293 | int32_t op2; | |
4294 | int32_t r1; | |
4295 | uint32_t address; | |
4296 | TCGv temp; | |
4297 | ||
4298 | r1 = MASK_OP_ABS_S1D(ctx->opcode); | |
4299 | address = MASK_OP_ABS_OFF18(ctx->opcode); | |
4300 | op2 = MASK_OP_ABS_OP2(ctx->opcode); | |
4301 | ||
4302 | temp = tcg_const_i32(EA_ABS_FORMAT(address)); | |
4303 | ||
4304 | switch (op2) { | |
4305 | case OPC2_32_ABS_LDMST: | |
4306 | gen_ldmst(ctx, r1, temp); | |
4307 | break; | |
4308 | case OPC2_32_ABS_SWAP_W: | |
4309 | gen_swap(ctx, r1, temp); | |
4310 | break; | |
f678f671 BK |
4311 | default: |
4312 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
59543d4e BK |
4313 | } |
4314 | ||
4315 | tcg_temp_free(temp); | |
4316 | } | |
4317 | ||
2db92a0c | 4318 | static void decode_abs_ldst_context(DisasContext *ctx) |
59543d4e BK |
4319 | { |
4320 | uint32_t op2; | |
4321 | int32_t off18; | |
4322 | ||
4323 | off18 = MASK_OP_ABS_OFF18(ctx->opcode); | |
4324 | op2 = MASK_OP_ABS_OP2(ctx->opcode); | |
4325 | ||
4326 | switch (op2) { | |
4327 | case OPC2_32_ABS_LDLCX: | |
4328 | gen_helper_1arg(ldlcx, EA_ABS_FORMAT(off18)); | |
4329 | break; | |
4330 | case OPC2_32_ABS_LDUCX: | |
4331 | gen_helper_1arg(lducx, EA_ABS_FORMAT(off18)); | |
4332 | break; | |
4333 | case OPC2_32_ABS_STLCX: | |
4334 | gen_helper_1arg(stlcx, EA_ABS_FORMAT(off18)); | |
4335 | break; | |
4336 | case OPC2_32_ABS_STUCX: | |
4337 | gen_helper_1arg(stucx, EA_ABS_FORMAT(off18)); | |
4338 | break; | |
f678f671 BK |
4339 | default: |
4340 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
59543d4e BK |
4341 | } |
4342 | } | |
4343 | ||
2db92a0c | 4344 | static void decode_abs_store(DisasContext *ctx) |
59543d4e BK |
4345 | { |
4346 | int32_t op2; | |
4347 | int32_t r1; | |
4348 | uint32_t address; | |
4349 | TCGv temp; | |
4350 | ||
4351 | r1 = MASK_OP_ABS_S1D(ctx->opcode); | |
4352 | address = MASK_OP_ABS_OFF18(ctx->opcode); | |
4353 | op2 = MASK_OP_ABS_OP2(ctx->opcode); | |
4354 | ||
4355 | temp = tcg_const_i32(EA_ABS_FORMAT(address)); | |
4356 | ||
4357 | switch (op2) { | |
4358 | case OPC2_32_ABS_ST_A: | |
4359 | tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL); | |
4360 | break; | |
4361 | case OPC2_32_ABS_ST_D: | |
828066c7 | 4362 | CHECK_REG_PAIR(r1); |
59543d4e BK |
4363 | gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); |
4364 | break; | |
4365 | case OPC2_32_ABS_ST_DA: | |
828066c7 | 4366 | CHECK_REG_PAIR(r1); |
59543d4e BK |
4367 | gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); |
4368 | break; | |
4369 | case OPC2_32_ABS_ST_W: | |
4370 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL); | |
4371 | break; | |
f678f671 BK |
4372 | default: |
4373 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
59543d4e BK |
4374 | } |
4375 | tcg_temp_free(temp); | |
4376 | } | |
4377 | ||
2db92a0c | 4378 | static void decode_abs_storeb_h(DisasContext *ctx) |
59543d4e BK |
4379 | { |
4380 | int32_t op2; | |
4381 | int32_t r1; | |
4382 | uint32_t address; | |
4383 | TCGv temp; | |
4384 | ||
4385 | r1 = MASK_OP_ABS_S1D(ctx->opcode); | |
4386 | address = MASK_OP_ABS_OFF18(ctx->opcode); | |
4387 | op2 = MASK_OP_ABS_OP2(ctx->opcode); | |
4388 | ||
4389 | temp = tcg_const_i32(EA_ABS_FORMAT(address)); | |
4390 | ||
4391 | switch (op2) { | |
4392 | case OPC2_32_ABS_ST_B: | |
4393 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB); | |
4394 | break; | |
4395 | case OPC2_32_ABS_ST_H: | |
4396 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW); | |
4397 | break; | |
f678f671 BK |
4398 | default: |
4399 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
59543d4e BK |
4400 | } |
4401 | tcg_temp_free(temp); | |
4402 | } | |
4403 | ||
b74f2b5b BK |
4404 | /* Bit-format */ |
4405 | ||
2db92a0c | 4406 | static void decode_bit_andacc(DisasContext *ctx) |
b74f2b5b BK |
4407 | { |
4408 | uint32_t op2; | |
4409 | int r1, r2, r3; | |
4410 | int pos1, pos2; | |
4411 | ||
4412 | r1 = MASK_OP_BIT_S1(ctx->opcode); | |
4413 | r2 = MASK_OP_BIT_S2(ctx->opcode); | |
4414 | r3 = MASK_OP_BIT_D(ctx->opcode); | |
4415 | pos1 = MASK_OP_BIT_POS1(ctx->opcode); | |
4416 | pos2 = MASK_OP_BIT_POS2(ctx->opcode); | |
4417 | op2 = MASK_OP_BIT_OP2(ctx->opcode); | |
4418 | ||
4419 | ||
4420 | switch (op2) { | |
4421 | case OPC2_32_BIT_AND_AND_T: | |
4422 | gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
4423 | pos1, pos2, &tcg_gen_and_tl, &tcg_gen_and_tl); | |
4424 | break; | |
4425 | case OPC2_32_BIT_AND_ANDN_T: | |
4426 | gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
4427 | pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_and_tl); | |
4428 | break; | |
4429 | case OPC2_32_BIT_AND_NOR_T: | |
4430 | if (TCG_TARGET_HAS_andc_i32) { | |
4431 | gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
4432 | pos1, pos2, &tcg_gen_or_tl, &tcg_gen_andc_tl); | |
4433 | } else { | |
4434 | gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
4435 | pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_and_tl); | |
4436 | } | |
4437 | break; | |
4438 | case OPC2_32_BIT_AND_OR_T: | |
4439 | gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
4440 | pos1, pos2, &tcg_gen_or_tl, &tcg_gen_and_tl); | |
4441 | break; | |
f678f671 BK |
4442 | default: |
4443 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
b74f2b5b BK |
4444 | } |
4445 | } | |
4446 | ||
2db92a0c | 4447 | static void decode_bit_logical_t(DisasContext *ctx) |
b74f2b5b BK |
4448 | { |
4449 | uint32_t op2; | |
4450 | int r1, r2, r3; | |
4451 | int pos1, pos2; | |
4452 | r1 = MASK_OP_BIT_S1(ctx->opcode); | |
4453 | r2 = MASK_OP_BIT_S2(ctx->opcode); | |
4454 | r3 = MASK_OP_BIT_D(ctx->opcode); | |
4455 | pos1 = MASK_OP_BIT_POS1(ctx->opcode); | |
4456 | pos2 = MASK_OP_BIT_POS2(ctx->opcode); | |
4457 | op2 = MASK_OP_BIT_OP2(ctx->opcode); | |
4458 | ||
4459 | switch (op2) { | |
4460 | case OPC2_32_BIT_AND_T: | |
4461 | gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
4462 | pos1, pos2, &tcg_gen_and_tl); | |
4463 | break; | |
4464 | case OPC2_32_BIT_ANDN_T: | |
4465 | gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
4466 | pos1, pos2, &tcg_gen_andc_tl); | |
4467 | break; | |
4468 | case OPC2_32_BIT_NOR_T: | |
4469 | gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
4470 | pos1, pos2, &tcg_gen_nor_tl); | |
4471 | break; | |
4472 | case OPC2_32_BIT_OR_T: | |
4473 | gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
4474 | pos1, pos2, &tcg_gen_or_tl); | |
4475 | break; | |
f678f671 BK |
4476 | default: |
4477 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
b74f2b5b BK |
4478 | } |
4479 | } | |
4480 | ||
2db92a0c | 4481 | static void decode_bit_insert(DisasContext *ctx) |
b74f2b5b BK |
4482 | { |
4483 | uint32_t op2; | |
4484 | int r1, r2, r3; | |
4485 | int pos1, pos2; | |
4486 | TCGv temp; | |
4487 | op2 = MASK_OP_BIT_OP2(ctx->opcode); | |
4488 | r1 = MASK_OP_BIT_S1(ctx->opcode); | |
4489 | r2 = MASK_OP_BIT_S2(ctx->opcode); | |
4490 | r3 = MASK_OP_BIT_D(ctx->opcode); | |
4491 | pos1 = MASK_OP_BIT_POS1(ctx->opcode); | |
4492 | pos2 = MASK_OP_BIT_POS2(ctx->opcode); | |
4493 | ||
4494 | temp = tcg_temp_new(); | |
4495 | ||
4496 | tcg_gen_shri_tl(temp, cpu_gpr_d[r2], pos2); | |
4497 | if (op2 == OPC2_32_BIT_INSN_T) { | |
4498 | tcg_gen_not_tl(temp, temp); | |
4499 | } | |
4500 | tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, pos1, 1); | |
4501 | tcg_temp_free(temp); | |
4502 | } | |
4503 | ||
2db92a0c | 4504 | static void decode_bit_logical_t2(DisasContext *ctx) |
b74f2b5b BK |
4505 | { |
4506 | uint32_t op2; | |
4507 | ||
4508 | int r1, r2, r3; | |
4509 | int pos1, pos2; | |
4510 | ||
4511 | op2 = MASK_OP_BIT_OP2(ctx->opcode); | |
4512 | r1 = MASK_OP_BIT_S1(ctx->opcode); | |
4513 | r2 = MASK_OP_BIT_S2(ctx->opcode); | |
4514 | r3 = MASK_OP_BIT_D(ctx->opcode); | |
4515 | pos1 = MASK_OP_BIT_POS1(ctx->opcode); | |
4516 | pos2 = MASK_OP_BIT_POS2(ctx->opcode); | |
4517 | ||
4518 | switch (op2) { | |
4519 | case OPC2_32_BIT_NAND_T: | |
4520 | gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
4521 | pos1, pos2, &tcg_gen_nand_tl); | |
4522 | break; | |
4523 | case OPC2_32_BIT_ORN_T: | |
4524 | gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
4525 | pos1, pos2, &tcg_gen_orc_tl); | |
4526 | break; | |
4527 | case OPC2_32_BIT_XNOR_T: | |
4528 | gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
4529 | pos1, pos2, &tcg_gen_eqv_tl); | |
4530 | break; | |
4531 | case OPC2_32_BIT_XOR_T: | |
4532 | gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
4533 | pos1, pos2, &tcg_gen_xor_tl); | |
4534 | break; | |
f678f671 BK |
4535 | default: |
4536 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
b74f2b5b BK |
4537 | } |
4538 | } | |
4539 | ||
2db92a0c | 4540 | static void decode_bit_orand(DisasContext *ctx) |
b74f2b5b BK |
4541 | { |
4542 | uint32_t op2; | |
4543 | ||
4544 | int r1, r2, r3; | |
4545 | int pos1, pos2; | |
4546 | ||
4547 | op2 = MASK_OP_BIT_OP2(ctx->opcode); | |
4548 | r1 = MASK_OP_BIT_S1(ctx->opcode); | |
4549 | r2 = MASK_OP_BIT_S2(ctx->opcode); | |
4550 | r3 = MASK_OP_BIT_D(ctx->opcode); | |
4551 | pos1 = MASK_OP_BIT_POS1(ctx->opcode); | |
4552 | pos2 = MASK_OP_BIT_POS2(ctx->opcode); | |
4553 | ||
4554 | switch (op2) { | |
4555 | case OPC2_32_BIT_OR_AND_T: | |
4556 | gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
4557 | pos1, pos2, &tcg_gen_and_tl, &tcg_gen_or_tl); | |
4558 | break; | |
4559 | case OPC2_32_BIT_OR_ANDN_T: | |
4560 | gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
4561 | pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_or_tl); | |
4562 | break; | |
4563 | case OPC2_32_BIT_OR_NOR_T: | |
4564 | if (TCG_TARGET_HAS_orc_i32) { | |
4565 | gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
4566 | pos1, pos2, &tcg_gen_or_tl, &tcg_gen_orc_tl); | |
4567 | } else { | |
4568 | gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
4569 | pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_or_tl); | |
4570 | } | |
4571 | break; | |
4572 | case OPC2_32_BIT_OR_OR_T: | |
4573 | gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
4574 | pos1, pos2, &tcg_gen_or_tl, &tcg_gen_or_tl); | |
4575 | break; | |
f678f671 BK |
4576 | default: |
4577 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
b74f2b5b BK |
4578 | } |
4579 | } | |
4580 | ||
2db92a0c | 4581 | static void decode_bit_sh_logic1(DisasContext *ctx) |
b74f2b5b BK |
4582 | { |
4583 | uint32_t op2; | |
4584 | int r1, r2, r3; | |
4585 | int pos1, pos2; | |
4586 | TCGv temp; | |
4587 | ||
4588 | op2 = MASK_OP_BIT_OP2(ctx->opcode); | |
4589 | r1 = MASK_OP_BIT_S1(ctx->opcode); | |
4590 | r2 = MASK_OP_BIT_S2(ctx->opcode); | |
4591 | r3 = MASK_OP_BIT_D(ctx->opcode); | |
4592 | pos1 = MASK_OP_BIT_POS1(ctx->opcode); | |
4593 | pos2 = MASK_OP_BIT_POS2(ctx->opcode); | |
4594 | ||
4595 | temp = tcg_temp_new(); | |
4596 | ||
4597 | switch (op2) { | |
4598 | case OPC2_32_BIT_SH_AND_T: | |
4599 | gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], | |
4600 | pos1, pos2, &tcg_gen_and_tl); | |
4601 | break; | |
4602 | case OPC2_32_BIT_SH_ANDN_T: | |
4603 | gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], | |
4604 | pos1, pos2, &tcg_gen_andc_tl); | |
4605 | break; | |
4606 | case OPC2_32_BIT_SH_NOR_T: | |
4607 | gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], | |
4608 | pos1, pos2, &tcg_gen_nor_tl); | |
4609 | break; | |
4610 | case OPC2_32_BIT_SH_OR_T: | |
4611 | gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], | |
4612 | pos1, pos2, &tcg_gen_or_tl); | |
4613 | break; | |
f678f671 BK |
4614 | default: |
4615 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
b74f2b5b BK |
4616 | } |
4617 | tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1); | |
4618 | tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp); | |
4619 | tcg_temp_free(temp); | |
4620 | } | |
4621 | ||
2db92a0c | 4622 | static void decode_bit_sh_logic2(DisasContext *ctx) |
b74f2b5b BK |
4623 | { |
4624 | uint32_t op2; | |
4625 | int r1, r2, r3; | |
4626 | int pos1, pos2; | |
4627 | TCGv temp; | |
4628 | ||
4629 | op2 = MASK_OP_BIT_OP2(ctx->opcode); | |
4630 | r1 = MASK_OP_BIT_S1(ctx->opcode); | |
4631 | r2 = MASK_OP_BIT_S2(ctx->opcode); | |
4632 | r3 = MASK_OP_BIT_D(ctx->opcode); | |
4633 | pos1 = MASK_OP_BIT_POS1(ctx->opcode); | |
4634 | pos2 = MASK_OP_BIT_POS2(ctx->opcode); | |
4635 | ||
4636 | temp = tcg_temp_new(); | |
4637 | ||
4638 | switch (op2) { | |
4639 | case OPC2_32_BIT_SH_NAND_T: | |
4640 | gen_bit_1op(temp, cpu_gpr_d[r1] , cpu_gpr_d[r2] , | |
4641 | pos1, pos2, &tcg_gen_nand_tl); | |
4642 | break; | |
4643 | case OPC2_32_BIT_SH_ORN_T: | |
4644 | gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], | |
4645 | pos1, pos2, &tcg_gen_orc_tl); | |
4646 | break; | |
4647 | case OPC2_32_BIT_SH_XNOR_T: | |
4648 | gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], | |
4649 | pos1, pos2, &tcg_gen_eqv_tl); | |
4650 | break; | |
4651 | case OPC2_32_BIT_SH_XOR_T: | |
4652 | gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], | |
4653 | pos1, pos2, &tcg_gen_xor_tl); | |
4654 | break; | |
f678f671 BK |
4655 | default: |
4656 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
b74f2b5b BK |
4657 | } |
4658 | tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1); | |
4659 | tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp); | |
4660 | tcg_temp_free(temp); | |
4661 | } | |
4662 | ||
3a16ecb0 BK |
4663 | /* BO-format */ |
4664 | ||
4665 | ||
2db92a0c | 4666 | static void decode_bo_addrmode_post_pre_base(DisasContext *ctx) |
3a16ecb0 BK |
4667 | { |
4668 | uint32_t op2; | |
4669 | uint32_t off10; | |
4670 | int32_t r1, r2; | |
4671 | TCGv temp; | |
4672 | ||
4673 | r1 = MASK_OP_BO_S1D(ctx->opcode); | |
4674 | r2 = MASK_OP_BO_S2(ctx->opcode); | |
4675 | off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); | |
4676 | op2 = MASK_OP_BO_OP2(ctx->opcode); | |
4677 | ||
4678 | switch (op2) { | |
4679 | case OPC2_32_BO_CACHEA_WI_SHORTOFF: | |
4680 | case OPC2_32_BO_CACHEA_W_SHORTOFF: | |
4681 | case OPC2_32_BO_CACHEA_I_SHORTOFF: | |
4682 | /* instruction to access the cache */ | |
4683 | break; | |
4684 | case OPC2_32_BO_CACHEA_WI_POSTINC: | |
4685 | case OPC2_32_BO_CACHEA_W_POSTINC: | |
4686 | case OPC2_32_BO_CACHEA_I_POSTINC: | |
4687 | /* instruction to access the cache, but we still need to handle | |
4688 | the addressing mode */ | |
f1fdaf55 | 4689 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); |
3a16ecb0 BK |
4690 | break; |
4691 | case OPC2_32_BO_CACHEA_WI_PREINC: | |
4692 | case OPC2_32_BO_CACHEA_W_PREINC: | |
4693 | case OPC2_32_BO_CACHEA_I_PREINC: | |
4694 | /* instruction to access the cache, but we still need to handle | |
4695 | the addressing mode */ | |
f1fdaf55 | 4696 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); |
3a16ecb0 BK |
4697 | break; |
4698 | case OPC2_32_BO_CACHEI_WI_SHORTOFF: | |
4699 | case OPC2_32_BO_CACHEI_W_SHORTOFF: | |
44ee3baf | 4700 | if (!has_feature(ctx, TRICORE_FEATURE_131)) { |
f678f671 BK |
4701 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); |
4702 | } | |
3a16ecb0 BK |
4703 | break; |
4704 | case OPC2_32_BO_CACHEI_W_POSTINC: | |
4705 | case OPC2_32_BO_CACHEI_WI_POSTINC: | |
44ee3baf | 4706 | if (has_feature(ctx, TRICORE_FEATURE_131)) { |
f1fdaf55 | 4707 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); |
f678f671 BK |
4708 | } else { |
4709 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
4710 | } | |
3a16ecb0 BK |
4711 | break; |
4712 | case OPC2_32_BO_CACHEI_W_PREINC: | |
4713 | case OPC2_32_BO_CACHEI_WI_PREINC: | |
44ee3baf | 4714 | if (has_feature(ctx, TRICORE_FEATURE_131)) { |
f1fdaf55 | 4715 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); |
f678f671 BK |
4716 | } else { |
4717 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
4718 | } | |
3a16ecb0 BK |
4719 | break; |
4720 | case OPC2_32_BO_ST_A_SHORTOFF: | |
4721 | gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL); | |
4722 | break; | |
4723 | case OPC2_32_BO_ST_A_POSTINC: | |
4724 | tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, | |
4725 | MO_LESL); | |
4726 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4727 | break; | |
4728 | case OPC2_32_BO_ST_A_PREINC: | |
4729 | gen_st_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL); | |
4730 | break; | |
4731 | case OPC2_32_BO_ST_B_SHORTOFF: | |
4732 | gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); | |
4733 | break; | |
4734 | case OPC2_32_BO_ST_B_POSTINC: | |
4735 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, | |
4736 | MO_UB); | |
4737 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4738 | break; | |
4739 | case OPC2_32_BO_ST_B_PREINC: | |
4740 | gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); | |
4741 | break; | |
4742 | case OPC2_32_BO_ST_D_SHORTOFF: | |
828066c7 | 4743 | CHECK_REG_PAIR(r1); |
3a16ecb0 BK |
4744 | gen_offset_st_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], |
4745 | off10, ctx); | |
4746 | break; | |
4747 | case OPC2_32_BO_ST_D_POSTINC: | |
828066c7 | 4748 | CHECK_REG_PAIR(r1); |
3a16ecb0 BK |
4749 | gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx); |
4750 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4751 | break; | |
4752 | case OPC2_32_BO_ST_D_PREINC: | |
828066c7 | 4753 | CHECK_REG_PAIR(r1); |
3a16ecb0 BK |
4754 | temp = tcg_temp_new(); |
4755 | tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); | |
4756 | gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); | |
4757 | tcg_gen_mov_tl(cpu_gpr_a[r2], temp); | |
4758 | tcg_temp_free(temp); | |
4759 | break; | |
4760 | case OPC2_32_BO_ST_DA_SHORTOFF: | |
828066c7 | 4761 | CHECK_REG_PAIR(r1); |
3a16ecb0 BK |
4762 | gen_offset_st_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], |
4763 | off10, ctx); | |
4764 | break; | |
4765 | case OPC2_32_BO_ST_DA_POSTINC: | |
828066c7 | 4766 | CHECK_REG_PAIR(r1); |
3a16ecb0 BK |
4767 | gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx); |
4768 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4769 | break; | |
4770 | case OPC2_32_BO_ST_DA_PREINC: | |
828066c7 | 4771 | CHECK_REG_PAIR(r1); |
3a16ecb0 BK |
4772 | temp = tcg_temp_new(); |
4773 | tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); | |
4774 | gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); | |
4775 | tcg_gen_mov_tl(cpu_gpr_a[r2], temp); | |
4776 | tcg_temp_free(temp); | |
4777 | break; | |
4778 | case OPC2_32_BO_ST_H_SHORTOFF: | |
4779 | gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); | |
4780 | break; | |
4781 | case OPC2_32_BO_ST_H_POSTINC: | |
4782 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, | |
4783 | MO_LEUW); | |
4784 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4785 | break; | |
4786 | case OPC2_32_BO_ST_H_PREINC: | |
4787 | gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); | |
4788 | break; | |
4789 | case OPC2_32_BO_ST_Q_SHORTOFF: | |
4790 | temp = tcg_temp_new(); | |
4791 | tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); | |
4792 | gen_offset_st(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW); | |
4793 | tcg_temp_free(temp); | |
4794 | break; | |
4795 | case OPC2_32_BO_ST_Q_POSTINC: | |
4796 | temp = tcg_temp_new(); | |
4797 | tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); | |
4798 | tcg_gen_qemu_st_tl(temp, cpu_gpr_a[r2], ctx->mem_idx, | |
4799 | MO_LEUW); | |
4800 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4801 | tcg_temp_free(temp); | |
4802 | break; | |
4803 | case OPC2_32_BO_ST_Q_PREINC: | |
4804 | temp = tcg_temp_new(); | |
4805 | tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); | |
4806 | gen_st_preincr(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW); | |
4807 | tcg_temp_free(temp); | |
4808 | break; | |
4809 | case OPC2_32_BO_ST_W_SHORTOFF: | |
4810 | gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); | |
4811 | break; | |
4812 | case OPC2_32_BO_ST_W_POSTINC: | |
4813 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, | |
4814 | MO_LEUL); | |
4815 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4816 | break; | |
4817 | case OPC2_32_BO_ST_W_PREINC: | |
4818 | gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); | |
4819 | break; | |
f678f671 BK |
4820 | default: |
4821 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
3a16ecb0 BK |
4822 | } |
4823 | } | |
4824 | ||
2db92a0c | 4825 | static void decode_bo_addrmode_bitreverse_circular(DisasContext *ctx) |
3a16ecb0 BK |
4826 | { |
4827 | uint32_t op2; | |
4828 | uint32_t off10; | |
4829 | int32_t r1, r2; | |
4830 | TCGv temp, temp2, temp3; | |
4831 | ||
4832 | r1 = MASK_OP_BO_S1D(ctx->opcode); | |
4833 | r2 = MASK_OP_BO_S2(ctx->opcode); | |
4834 | off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); | |
4835 | op2 = MASK_OP_BO_OP2(ctx->opcode); | |
4836 | ||
4837 | temp = tcg_temp_new(); | |
4838 | temp2 = tcg_temp_new(); | |
4839 | temp3 = tcg_const_i32(off10); | |
828066c7 | 4840 | CHECK_REG_PAIR(r2); |
3a16ecb0 BK |
4841 | tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]); |
4842 | tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); | |
4843 | ||
4844 | switch (op2) { | |
4845 | case OPC2_32_BO_CACHEA_WI_BR: | |
4846 | case OPC2_32_BO_CACHEA_W_BR: | |
4847 | case OPC2_32_BO_CACHEA_I_BR: | |
4848 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
4849 | break; | |
4850 | case OPC2_32_BO_CACHEA_WI_CIRC: | |
4851 | case OPC2_32_BO_CACHEA_W_CIRC: | |
4852 | case OPC2_32_BO_CACHEA_I_CIRC: | |
4853 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); | |
4854 | break; | |
4855 | case OPC2_32_BO_ST_A_BR: | |
4856 | tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); | |
4857 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
4858 | break; | |
4859 | case OPC2_32_BO_ST_A_CIRC: | |
4860 | tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); | |
4861 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); | |
4862 | break; | |
4863 | case OPC2_32_BO_ST_B_BR: | |
4864 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); | |
4865 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
4866 | break; | |
4867 | case OPC2_32_BO_ST_B_CIRC: | |
4868 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); | |
4869 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); | |
4870 | break; | |
4871 | case OPC2_32_BO_ST_D_BR: | |
828066c7 | 4872 | CHECK_REG_PAIR(r1); |
3a16ecb0 BK |
4873 | gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx); |
4874 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
4875 | break; | |
4876 | case OPC2_32_BO_ST_D_CIRC: | |
828066c7 | 4877 | CHECK_REG_PAIR(r1); |
3a16ecb0 BK |
4878 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); |
4879 | tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); | |
4880 | tcg_gen_addi_tl(temp, temp, 4); | |
4881 | tcg_gen_rem_tl(temp, temp, temp2); | |
4882 | tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); | |
4883 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL); | |
4884 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); | |
4885 | break; | |
4886 | case OPC2_32_BO_ST_DA_BR: | |
828066c7 | 4887 | CHECK_REG_PAIR(r1); |
3a16ecb0 BK |
4888 | gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx); |
4889 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
4890 | break; | |
4891 | case OPC2_32_BO_ST_DA_CIRC: | |
828066c7 | 4892 | CHECK_REG_PAIR(r1); |
3a16ecb0 BK |
4893 | tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); |
4894 | tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); | |
4895 | tcg_gen_addi_tl(temp, temp, 4); | |
4896 | tcg_gen_rem_tl(temp, temp, temp2); | |
4897 | tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); | |
4898 | tcg_gen_qemu_st_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL); | |
4899 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); | |
4900 | break; | |
4901 | case OPC2_32_BO_ST_H_BR: | |
4902 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); | |
4903 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
4904 | break; | |
4905 | case OPC2_32_BO_ST_H_CIRC: | |
4906 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); | |
4907 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); | |
4908 | break; | |
4909 | case OPC2_32_BO_ST_Q_BR: | |
4910 | tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); | |
4911 | tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW); | |
4912 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
4913 | break; | |
4914 | case OPC2_32_BO_ST_Q_CIRC: | |
4915 | tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); | |
4916 | tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW); | |
4917 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); | |
4918 | break; | |
4919 | case OPC2_32_BO_ST_W_BR: | |
4920 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); | |
4921 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
4922 | break; | |
4923 | case OPC2_32_BO_ST_W_CIRC: | |
4924 | tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); | |
4925 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); | |
4926 | break; | |
f678f671 BK |
4927 | default: |
4928 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
3a16ecb0 BK |
4929 | } |
4930 | tcg_temp_free(temp); | |
4931 | tcg_temp_free(temp2); | |
4932 | tcg_temp_free(temp3); | |
4933 | } | |
4934 | ||
2db92a0c | 4935 | static void decode_bo_addrmode_ld_post_pre_base(DisasContext *ctx) |
3a16ecb0 BK |
4936 | { |
4937 | uint32_t op2; | |
4938 | uint32_t off10; | |
4939 | int32_t r1, r2; | |
4940 | TCGv temp; | |
4941 | ||
4942 | r1 = MASK_OP_BO_S1D(ctx->opcode); | |
4943 | r2 = MASK_OP_BO_S2(ctx->opcode); | |
4944 | off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); | |
4945 | op2 = MASK_OP_BO_OP2(ctx->opcode); | |
4946 | ||
4947 | switch (op2) { | |
4948 | case OPC2_32_BO_LD_A_SHORTOFF: | |
4949 | gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL); | |
4950 | break; | |
4951 | case OPC2_32_BO_LD_A_POSTINC: | |
4952 | tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, | |
4953 | MO_LEUL); | |
4954 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4955 | break; | |
4956 | case OPC2_32_BO_LD_A_PREINC: | |
4957 | gen_ld_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL); | |
4958 | break; | |
4959 | case OPC2_32_BO_LD_B_SHORTOFF: | |
4960 | gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB); | |
4961 | break; | |
4962 | case OPC2_32_BO_LD_B_POSTINC: | |
4963 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, | |
4964 | MO_SB); | |
4965 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4966 | break; | |
4967 | case OPC2_32_BO_LD_B_PREINC: | |
4968 | gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB); | |
4969 | break; | |
4970 | case OPC2_32_BO_LD_BU_SHORTOFF: | |
4971 | gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); | |
4972 | break; | |
4973 | case OPC2_32_BO_LD_BU_POSTINC: | |
4974 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, | |
4975 | MO_UB); | |
4976 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4977 | break; | |
4978 | case OPC2_32_BO_LD_BU_PREINC: | |
4979 | gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB); | |
4980 | break; | |
4981 | case OPC2_32_BO_LD_D_SHORTOFF: | |
828066c7 | 4982 | CHECK_REG_PAIR(r1); |
3a16ecb0 BK |
4983 | gen_offset_ld_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], |
4984 | off10, ctx); | |
4985 | break; | |
4986 | case OPC2_32_BO_LD_D_POSTINC: | |
828066c7 | 4987 | CHECK_REG_PAIR(r1); |
3a16ecb0 BK |
4988 | gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx); |
4989 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
4990 | break; | |
4991 | case OPC2_32_BO_LD_D_PREINC: | |
828066c7 | 4992 | CHECK_REG_PAIR(r1); |
3a16ecb0 BK |
4993 | temp = tcg_temp_new(); |
4994 | tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); | |
4995 | gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); | |
4996 | tcg_gen_mov_tl(cpu_gpr_a[r2], temp); | |
4997 | tcg_temp_free(temp); | |
4998 | break; | |
4999 | case OPC2_32_BO_LD_DA_SHORTOFF: | |
828066c7 | 5000 | CHECK_REG_PAIR(r1); |
3a16ecb0 BK |
5001 | gen_offset_ld_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], |
5002 | off10, ctx); | |
5003 | break; | |
5004 | case OPC2_32_BO_LD_DA_POSTINC: | |
828066c7 | 5005 | CHECK_REG_PAIR(r1); |
3a16ecb0 BK |
5006 | gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx); |
5007 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
5008 | break; | |
5009 | case OPC2_32_BO_LD_DA_PREINC: | |
828066c7 | 5010 | CHECK_REG_PAIR(r1); |
3a16ecb0 BK |
5011 | temp = tcg_temp_new(); |
5012 | tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); | |
5013 | gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); | |
5014 | tcg_gen_mov_tl(cpu_gpr_a[r2], temp); | |
5015 | tcg_temp_free(temp); | |
5016 | break; | |
5017 | case OPC2_32_BO_LD_H_SHORTOFF: | |
5018 | gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW); | |
5019 | break; | |
5020 | case OPC2_32_BO_LD_H_POSTINC: | |
5021 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, | |
5022 | MO_LESW); | |
5023 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
5024 | break; | |
5025 | case OPC2_32_BO_LD_H_PREINC: | |
5026 | gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW); | |
5027 | break; | |
5028 | case OPC2_32_BO_LD_HU_SHORTOFF: | |
5029 | gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); | |
5030 | break; | |
5031 | case OPC2_32_BO_LD_HU_POSTINC: | |
5032 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, | |
5033 | MO_LEUW); | |
5034 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
5035 | break; | |
5036 | case OPC2_32_BO_LD_HU_PREINC: | |
5037 | gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); | |
5038 | break; | |
5039 | case OPC2_32_BO_LD_Q_SHORTOFF: | |
5040 | gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); | |
5041 | tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); | |
5042 | break; | |
5043 | case OPC2_32_BO_LD_Q_POSTINC: | |
5044 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, | |
5045 | MO_LEUW); | |
5046 | tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); | |
5047 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
5048 | break; | |
5049 | case OPC2_32_BO_LD_Q_PREINC: | |
5050 | gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); | |
5051 | tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); | |
5052 | break; | |
5053 | case OPC2_32_BO_LD_W_SHORTOFF: | |
5054 | gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); | |
5055 | break; | |
5056 | case OPC2_32_BO_LD_W_POSTINC: | |
5057 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, | |
5058 | MO_LEUL); | |
5059 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
5060 | break; | |
5061 | case OPC2_32_BO_LD_W_PREINC: | |
5062 | gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); | |
5063 | break; | |
f678f671 BK |
5064 | default: |
5065 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
3a16ecb0 BK |
5066 | } |
5067 | } | |
5068 | ||
2db92a0c | 5069 | static void decode_bo_addrmode_ld_bitreverse_circular(DisasContext *ctx) |
3a16ecb0 BK |
5070 | { |
5071 | uint32_t op2; | |
5072 | uint32_t off10; | |
5073 | int r1, r2; | |
5074 | ||
5075 | TCGv temp, temp2, temp3; | |
5076 | ||
5077 | r1 = MASK_OP_BO_S1D(ctx->opcode); | |
5078 | r2 = MASK_OP_BO_S2(ctx->opcode); | |
5079 | off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); | |
5080 | op2 = MASK_OP_BO_OP2(ctx->opcode); | |
5081 | ||
5082 | temp = tcg_temp_new(); | |
5083 | temp2 = tcg_temp_new(); | |
5084 | temp3 = tcg_const_i32(off10); | |
828066c7 | 5085 | CHECK_REG_PAIR(r2); |
3a16ecb0 BK |
5086 | tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]); |
5087 | tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); | |
5088 | ||
5089 | ||
5090 | switch (op2) { | |
5091 | case OPC2_32_BO_LD_A_BR: | |
5092 | tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); | |
5093 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
5094 | break; | |
5095 | case OPC2_32_BO_LD_A_CIRC: | |
5096 | tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); | |
5097 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); | |
5098 | break; | |
5099 | case OPC2_32_BO_LD_B_BR: | |
5100 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB); | |
5101 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
5102 | break; | |
5103 | case OPC2_32_BO_LD_B_CIRC: | |
5104 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB); | |
5105 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); | |
5106 | break; | |
5107 | case OPC2_32_BO_LD_BU_BR: | |
5108 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); | |
5109 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
5110 | break; | |
5111 | case OPC2_32_BO_LD_BU_CIRC: | |
5112 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); | |
5113 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); | |
5114 | break; | |
5115 | case OPC2_32_BO_LD_D_BR: | |
828066c7 | 5116 | CHECK_REG_PAIR(r1); |
3a16ecb0 BK |
5117 | gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx); |
5118 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
5119 | break; | |
5120 | case OPC2_32_BO_LD_D_CIRC: | |
828066c7 | 5121 | CHECK_REG_PAIR(r1); |
3a16ecb0 BK |
5122 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); |
5123 | tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); | |
5124 | tcg_gen_addi_tl(temp, temp, 4); | |
5125 | tcg_gen_rem_tl(temp, temp, temp2); | |
5126 | tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); | |
5127 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL); | |
5128 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); | |
5129 | break; | |
5130 | case OPC2_32_BO_LD_DA_BR: | |
828066c7 | 5131 | CHECK_REG_PAIR(r1); |
3a16ecb0 BK |
5132 | gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx); |
5133 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
5134 | break; | |
5135 | case OPC2_32_BO_LD_DA_CIRC: | |
828066c7 | 5136 | CHECK_REG_PAIR(r1); |
3a16ecb0 BK |
5137 | tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); |
5138 | tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); | |
5139 | tcg_gen_addi_tl(temp, temp, 4); | |
5140 | tcg_gen_rem_tl(temp, temp, temp2); | |
5141 | tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); | |
5142 | tcg_gen_qemu_ld_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL); | |
5143 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); | |
5144 | break; | |
5145 | case OPC2_32_BO_LD_H_BR: | |
5146 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW); | |
5147 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
5148 | break; | |
5149 | case OPC2_32_BO_LD_H_CIRC: | |
5150 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW); | |
5151 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); | |
5152 | break; | |
5153 | case OPC2_32_BO_LD_HU_BR: | |
5154 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); | |
5155 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
5156 | break; | |
5157 | case OPC2_32_BO_LD_HU_CIRC: | |
5158 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); | |
5159 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); | |
5160 | break; | |
5161 | case OPC2_32_BO_LD_Q_BR: | |
5162 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); | |
5163 | tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); | |
5164 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
5165 | break; | |
5166 | case OPC2_32_BO_LD_Q_CIRC: | |
5167 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); | |
5168 | tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); | |
5169 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); | |
5170 | break; | |
5171 | case OPC2_32_BO_LD_W_BR: | |
5172 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); | |
5173 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
5174 | break; | |
5175 | case OPC2_32_BO_LD_W_CIRC: | |
5176 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); | |
5177 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); | |
5178 | break; | |
f678f671 BK |
5179 | default: |
5180 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
3a16ecb0 BK |
5181 | } |
5182 | tcg_temp_free(temp); | |
5183 | tcg_temp_free(temp2); | |
5184 | tcg_temp_free(temp3); | |
5185 | } | |
5186 | ||
2db92a0c | 5187 | static void decode_bo_addrmode_stctx_post_pre_base(DisasContext *ctx) |
3a16ecb0 BK |
5188 | { |
5189 | uint32_t op2; | |
5190 | uint32_t off10; | |
5191 | int r1, r2; | |
5192 | ||
5193 | TCGv temp, temp2; | |
5194 | ||
5195 | r1 = MASK_OP_BO_S1D(ctx->opcode); | |
5196 | r2 = MASK_OP_BO_S2(ctx->opcode); | |
5197 | off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); | |
5198 | op2 = MASK_OP_BO_OP2(ctx->opcode); | |
5199 | ||
5200 | ||
5201 | temp = tcg_temp_new(); | |
5202 | temp2 = tcg_temp_new(); | |
5203 | ||
5204 | switch (op2) { | |
5205 | case OPC2_32_BO_LDLCX_SHORTOFF: | |
5206 | tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); | |
5207 | gen_helper_ldlcx(cpu_env, temp); | |
5208 | break; | |
5209 | case OPC2_32_BO_LDMST_SHORTOFF: | |
5210 | tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); | |
5211 | gen_ldmst(ctx, r1, temp); | |
5212 | break; | |
5213 | case OPC2_32_BO_LDMST_POSTINC: | |
5214 | gen_ldmst(ctx, r1, cpu_gpr_a[r2]); | |
5215 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
5216 | break; | |
5217 | case OPC2_32_BO_LDMST_PREINC: | |
5218 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
5219 | gen_ldmst(ctx, r1, cpu_gpr_a[r2]); | |
5220 | break; | |
5221 | case OPC2_32_BO_LDUCX_SHORTOFF: | |
5222 | tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); | |
5223 | gen_helper_lducx(cpu_env, temp); | |
5224 | break; | |
5225 | case OPC2_32_BO_LEA_SHORTOFF: | |
5226 | tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], off10); | |
5227 | break; | |
5228 | case OPC2_32_BO_STLCX_SHORTOFF: | |
5229 | tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); | |
5230 | gen_helper_stlcx(cpu_env, temp); | |
5231 | break; | |
5232 | case OPC2_32_BO_STUCX_SHORTOFF: | |
5233 | tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); | |
5234 | gen_helper_stucx(cpu_env, temp); | |
5235 | break; | |
5236 | case OPC2_32_BO_SWAP_W_SHORTOFF: | |
5237 | tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); | |
5238 | gen_swap(ctx, r1, temp); | |
5239 | break; | |
5240 | case OPC2_32_BO_SWAP_W_POSTINC: | |
5241 | gen_swap(ctx, r1, cpu_gpr_a[r2]); | |
5242 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
5243 | break; | |
5244 | case OPC2_32_BO_SWAP_W_PREINC: | |
5245 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
5246 | gen_swap(ctx, r1, cpu_gpr_a[r2]); | |
5247 | break; | |
62872ebc BK |
5248 | case OPC2_32_BO_CMPSWAP_W_SHORTOFF: |
5249 | tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); | |
5250 | gen_cmpswap(ctx, r1, temp); | |
5251 | break; | |
5252 | case OPC2_32_BO_CMPSWAP_W_POSTINC: | |
5253 | gen_cmpswap(ctx, r1, cpu_gpr_a[r2]); | |
5254 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
5255 | break; | |
5256 | case OPC2_32_BO_CMPSWAP_W_PREINC: | |
5257 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
5258 | gen_cmpswap(ctx, r1, cpu_gpr_a[r2]); | |
5259 | break; | |
ddd8cebe BK |
5260 | case OPC2_32_BO_SWAPMSK_W_SHORTOFF: |
5261 | tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); | |
5262 | gen_swapmsk(ctx, r1, temp); | |
5263 | break; | |
5264 | case OPC2_32_BO_SWAPMSK_W_POSTINC: | |
5265 | gen_swapmsk(ctx, r1, cpu_gpr_a[r2]); | |
5266 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
5267 | break; | |
5268 | case OPC2_32_BO_SWAPMSK_W_PREINC: | |
5269 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); | |
5270 | gen_swapmsk(ctx, r1, cpu_gpr_a[r2]); | |
5271 | break; | |
f678f671 BK |
5272 | default: |
5273 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
3a16ecb0 BK |
5274 | } |
5275 | tcg_temp_free(temp); | |
5276 | tcg_temp_free(temp2); | |
5277 | } | |
5278 | ||
2db92a0c | 5279 | static void decode_bo_addrmode_ldmst_bitreverse_circular(DisasContext *ctx) |
3a16ecb0 BK |
5280 | { |
5281 | uint32_t op2; | |
5282 | uint32_t off10; | |
5283 | int r1, r2; | |
5284 | ||
5285 | TCGv temp, temp2, temp3; | |
5286 | ||
5287 | r1 = MASK_OP_BO_S1D(ctx->opcode); | |
5288 | r2 = MASK_OP_BO_S2(ctx->opcode); | |
5289 | off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); | |
5290 | op2 = MASK_OP_BO_OP2(ctx->opcode); | |
5291 | ||
5292 | temp = tcg_temp_new(); | |
5293 | temp2 = tcg_temp_new(); | |
5294 | temp3 = tcg_const_i32(off10); | |
828066c7 | 5295 | CHECK_REG_PAIR(r2); |
3a16ecb0 BK |
5296 | tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]); |
5297 | tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); | |
5298 | ||
5299 | switch (op2) { | |
5300 | case OPC2_32_BO_LDMST_BR: | |
5301 | gen_ldmst(ctx, r1, temp2); | |
5302 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
5303 | break; | |
5304 | case OPC2_32_BO_LDMST_CIRC: | |
5305 | gen_ldmst(ctx, r1, temp2); | |
5306 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); | |
5307 | break; | |
5308 | case OPC2_32_BO_SWAP_W_BR: | |
5309 | gen_swap(ctx, r1, temp2); | |
5310 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
5311 | break; | |
5312 | case OPC2_32_BO_SWAP_W_CIRC: | |
5313 | gen_swap(ctx, r1, temp2); | |
5314 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); | |
5315 | break; | |
62872ebc BK |
5316 | case OPC2_32_BO_CMPSWAP_W_BR: |
5317 | gen_cmpswap(ctx, r1, temp2); | |
5318 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
5319 | break; | |
5320 | case OPC2_32_BO_CMPSWAP_W_CIRC: | |
5321 | gen_cmpswap(ctx, r1, temp2); | |
5322 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); | |
5323 | break; | |
ddd8cebe BK |
5324 | case OPC2_32_BO_SWAPMSK_W_BR: |
5325 | gen_swapmsk(ctx, r1, temp2); | |
5326 | gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); | |
5327 | break; | |
5328 | case OPC2_32_BO_SWAPMSK_W_CIRC: | |
5329 | gen_swapmsk(ctx, r1, temp2); | |
5330 | gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); | |
5331 | break; | |
f678f671 BK |
5332 | default: |
5333 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
3a16ecb0 | 5334 | } |
62872ebc | 5335 | |
3a16ecb0 BK |
5336 | tcg_temp_free(temp); |
5337 | tcg_temp_free(temp2); | |
5338 | tcg_temp_free(temp3); | |
5339 | } | |
5340 | ||
2db92a0c | 5341 | static void decode_bol_opc(DisasContext *ctx, int32_t op1) |
3fb763cb BK |
5342 | { |
5343 | int r1, r2; | |
5344 | int32_t address; | |
5345 | TCGv temp; | |
5346 | ||
5347 | r1 = MASK_OP_BOL_S1D(ctx->opcode); | |
5348 | r2 = MASK_OP_BOL_S2(ctx->opcode); | |
5349 | address = MASK_OP_BOL_OFF16_SEXT(ctx->opcode); | |
5350 | ||
5351 | switch (op1) { | |
5352 | case OPC1_32_BOL_LD_A_LONGOFF: | |
5353 | temp = tcg_temp_new(); | |
5354 | tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address); | |
5355 | tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LEUL); | |
5356 | tcg_temp_free(temp); | |
5357 | break; | |
af715d98 | 5358 | case OPC1_32_BOL_LD_W_LONGOFF: |
3fb763cb BK |
5359 | temp = tcg_temp_new(); |
5360 | tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address); | |
5361 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUL); | |
5362 | tcg_temp_free(temp); | |
5363 | break; | |
5364 | case OPC1_32_BOL_LEA_LONGOFF: | |
5365 | tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], address); | |
5366 | break; | |
5367 | case OPC1_32_BOL_ST_A_LONGOFF: | |
44ee3baf | 5368 | if (has_feature(ctx, TRICORE_FEATURE_16)) { |
3fb763cb BK |
5369 | gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], address, MO_LEUL); |
5370 | } else { | |
f678f671 | 5371 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); |
3fb763cb BK |
5372 | } |
5373 | break; | |
5374 | case OPC1_32_BOL_ST_W_LONGOFF: | |
5375 | gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUL); | |
5376 | break; | |
b5fd8fa3 | 5377 | case OPC1_32_BOL_LD_B_LONGOFF: |
44ee3baf | 5378 | if (has_feature(ctx, TRICORE_FEATURE_16)) { |
b5fd8fa3 BK |
5379 | gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB); |
5380 | } else { | |
f678f671 | 5381 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); |
b5fd8fa3 BK |
5382 | } |
5383 | break; | |
5384 | case OPC1_32_BOL_LD_BU_LONGOFF: | |
44ee3baf | 5385 | if (has_feature(ctx, TRICORE_FEATURE_16)) { |
b5fd8fa3 BK |
5386 | gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_UB); |
5387 | } else { | |
f678f671 | 5388 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); |
b5fd8fa3 BK |
5389 | } |
5390 | break; | |
5391 | case OPC1_32_BOL_LD_H_LONGOFF: | |
44ee3baf | 5392 | if (has_feature(ctx, TRICORE_FEATURE_16)) { |
b5fd8fa3 BK |
5393 | gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW); |
5394 | } else { | |
f678f671 | 5395 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); |
b5fd8fa3 BK |
5396 | } |
5397 | break; | |
5398 | case OPC1_32_BOL_LD_HU_LONGOFF: | |
44ee3baf | 5399 | if (has_feature(ctx, TRICORE_FEATURE_16)) { |
b5fd8fa3 BK |
5400 | gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUW); |
5401 | } else { | |
f678f671 | 5402 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); |
b5fd8fa3 BK |
5403 | } |
5404 | break; | |
5405 | case OPC1_32_BOL_ST_B_LONGOFF: | |
44ee3baf | 5406 | if (has_feature(ctx, TRICORE_FEATURE_16)) { |
b5fd8fa3 BK |
5407 | gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB); |
5408 | } else { | |
f678f671 | 5409 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); |
b5fd8fa3 BK |
5410 | } |
5411 | break; | |
5412 | case OPC1_32_BOL_ST_H_LONGOFF: | |
44ee3baf | 5413 | if (has_feature(ctx, TRICORE_FEATURE_16)) { |
07e15486 | 5414 | gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW); |
b5fd8fa3 | 5415 | } else { |
f678f671 | 5416 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); |
b5fd8fa3 BK |
5417 | } |
5418 | break; | |
f678f671 BK |
5419 | default: |
5420 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
3fb763cb | 5421 | } |
3fb763cb BK |
5422 | } |
5423 | ||
0974257e | 5424 | /* RC format */ |
2db92a0c | 5425 | static void decode_rc_logical_shift(DisasContext *ctx) |
0974257e BK |
5426 | { |
5427 | uint32_t op2; | |
5428 | int r1, r2; | |
5429 | int32_t const9; | |
5430 | TCGv temp; | |
5431 | ||
5432 | r2 = MASK_OP_RC_D(ctx->opcode); | |
5433 | r1 = MASK_OP_RC_S1(ctx->opcode); | |
5434 | const9 = MASK_OP_RC_CONST9(ctx->opcode); | |
5435 | op2 = MASK_OP_RC_OP2(ctx->opcode); | |
5436 | ||
5437 | temp = tcg_temp_new(); | |
5438 | ||
5439 | switch (op2) { | |
5440 | case OPC2_32_RC_AND: | |
5441 | tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5442 | break; | |
5443 | case OPC2_32_RC_ANDN: | |
5444 | tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9); | |
5445 | break; | |
5446 | case OPC2_32_RC_NAND: | |
5447 | tcg_gen_movi_tl(temp, const9); | |
5448 | tcg_gen_nand_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp); | |
5449 | break; | |
5450 | case OPC2_32_RC_NOR: | |
5451 | tcg_gen_movi_tl(temp, const9); | |
5452 | tcg_gen_nor_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp); | |
5453 | break; | |
5454 | case OPC2_32_RC_OR: | |
5455 | tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5456 | break; | |
5457 | case OPC2_32_RC_ORN: | |
5458 | tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9); | |
5459 | break; | |
5460 | case OPC2_32_RC_SH: | |
5461 | const9 = sextract32(const9, 0, 6); | |
5462 | gen_shi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5463 | break; | |
5464 | case OPC2_32_RC_SH_H: | |
5465 | const9 = sextract32(const9, 0, 5); | |
5466 | gen_sh_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5467 | break; | |
5468 | case OPC2_32_RC_SHA: | |
5469 | const9 = sextract32(const9, 0, 6); | |
5470 | gen_shaci(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5471 | break; | |
5472 | case OPC2_32_RC_SHA_H: | |
5473 | const9 = sextract32(const9, 0, 5); | |
5474 | gen_sha_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5475 | break; | |
5476 | case OPC2_32_RC_SHAS: | |
5477 | gen_shasi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5478 | break; | |
5479 | case OPC2_32_RC_XNOR: | |
5480 | tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5481 | tcg_gen_not_tl(cpu_gpr_d[r2], cpu_gpr_d[r2]); | |
5482 | break; | |
5483 | case OPC2_32_RC_XOR: | |
5484 | tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5485 | break; | |
f678f671 BK |
5486 | default: |
5487 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
0974257e BK |
5488 | } |
5489 | tcg_temp_free(temp); | |
5490 | } | |
5491 | ||
2db92a0c | 5492 | static void decode_rc_accumulator(DisasContext *ctx) |
0974257e BK |
5493 | { |
5494 | uint32_t op2; | |
5495 | int r1, r2; | |
5496 | int16_t const9; | |
5497 | ||
5498 | TCGv temp; | |
5499 | ||
5500 | r2 = MASK_OP_RC_D(ctx->opcode); | |
5501 | r1 = MASK_OP_RC_S1(ctx->opcode); | |
5502 | const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode); | |
5503 | ||
5504 | op2 = MASK_OP_RC_OP2(ctx->opcode); | |
5505 | ||
5506 | temp = tcg_temp_new(); | |
5507 | ||
5508 | switch (op2) { | |
5509 | case OPC2_32_RC_ABSDIF: | |
5510 | gen_absdifi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5511 | break; | |
5512 | case OPC2_32_RC_ABSDIFS: | |
5513 | gen_absdifsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5514 | break; | |
5515 | case OPC2_32_RC_ADD: | |
5516 | gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5517 | break; | |
5518 | case OPC2_32_RC_ADDC: | |
5519 | gen_addci_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5520 | break; | |
5521 | case OPC2_32_RC_ADDS: | |
5522 | gen_addsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5523 | break; | |
5524 | case OPC2_32_RC_ADDS_U: | |
5525 | gen_addsui(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5526 | break; | |
5527 | case OPC2_32_RC_ADDX: | |
5528 | gen_addi_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5529 | break; | |
5530 | case OPC2_32_RC_AND_EQ: | |
5531 | gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
5532 | const9, &tcg_gen_and_tl); | |
5533 | break; | |
5534 | case OPC2_32_RC_AND_GE: | |
5535 | gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
5536 | const9, &tcg_gen_and_tl); | |
5537 | break; | |
5538 | case OPC2_32_RC_AND_GE_U: | |
5539 | const9 = MASK_OP_RC_CONST9(ctx->opcode); | |
5540 | gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
5541 | const9, &tcg_gen_and_tl); | |
5542 | break; | |
5543 | case OPC2_32_RC_AND_LT: | |
5544 | gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
5545 | const9, &tcg_gen_and_tl); | |
5546 | break; | |
5547 | case OPC2_32_RC_AND_LT_U: | |
5548 | const9 = MASK_OP_RC_CONST9(ctx->opcode); | |
5549 | gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
5550 | const9, &tcg_gen_and_tl); | |
5551 | break; | |
5552 | case OPC2_32_RC_AND_NE: | |
5553 | gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
5554 | const9, &tcg_gen_and_tl); | |
5555 | break; | |
5556 | case OPC2_32_RC_EQ: | |
5557 | tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5558 | break; | |
5559 | case OPC2_32_RC_EQANY_B: | |
5560 | gen_eqany_bi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5561 | break; | |
5562 | case OPC2_32_RC_EQANY_H: | |
5563 | gen_eqany_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5564 | break; | |
5565 | case OPC2_32_RC_GE: | |
5566 | tcg_gen_setcondi_tl(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5567 | break; | |
5568 | case OPC2_32_RC_GE_U: | |
5569 | const9 = MASK_OP_RC_CONST9(ctx->opcode); | |
5570 | tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5571 | break; | |
5572 | case OPC2_32_RC_LT: | |
5573 | tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5574 | break; | |
5575 | case OPC2_32_RC_LT_U: | |
5576 | const9 = MASK_OP_RC_CONST9(ctx->opcode); | |
5577 | tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5578 | break; | |
5579 | case OPC2_32_RC_MAX: | |
5580 | tcg_gen_movi_tl(temp, const9); | |
5581 | tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, | |
5582 | cpu_gpr_d[r1], temp); | |
5583 | break; | |
5584 | case OPC2_32_RC_MAX_U: | |
5585 | tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode)); | |
5586 | tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, | |
5587 | cpu_gpr_d[r1], temp); | |
5588 | break; | |
5589 | case OPC2_32_RC_MIN: | |
5590 | tcg_gen_movi_tl(temp, const9); | |
5591 | tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, | |
5592 | cpu_gpr_d[r1], temp); | |
5593 | break; | |
5594 | case OPC2_32_RC_MIN_U: | |
5595 | tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode)); | |
5596 | tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, | |
5597 | cpu_gpr_d[r1], temp); | |
5598 | break; | |
5599 | case OPC2_32_RC_NE: | |
5600 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5601 | break; | |
5602 | case OPC2_32_RC_OR_EQ: | |
5603 | gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
5604 | const9, &tcg_gen_or_tl); | |
5605 | break; | |
5606 | case OPC2_32_RC_OR_GE: | |
5607 | gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
5608 | const9, &tcg_gen_or_tl); | |
5609 | break; | |
5610 | case OPC2_32_RC_OR_GE_U: | |
5611 | const9 = MASK_OP_RC_CONST9(ctx->opcode); | |
5612 | gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
5613 | const9, &tcg_gen_or_tl); | |
5614 | break; | |
5615 | case OPC2_32_RC_OR_LT: | |
5616 | gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
5617 | const9, &tcg_gen_or_tl); | |
5618 | break; | |
5619 | case OPC2_32_RC_OR_LT_U: | |
5620 | const9 = MASK_OP_RC_CONST9(ctx->opcode); | |
5621 | gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
5622 | const9, &tcg_gen_or_tl); | |
5623 | break; | |
5624 | case OPC2_32_RC_OR_NE: | |
5625 | gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
5626 | const9, &tcg_gen_or_tl); | |
5627 | break; | |
5628 | case OPC2_32_RC_RSUB: | |
5629 | tcg_gen_movi_tl(temp, const9); | |
5630 | gen_sub_d(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]); | |
5631 | break; | |
5632 | case OPC2_32_RC_RSUBS: | |
5633 | tcg_gen_movi_tl(temp, const9); | |
5634 | gen_subs(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]); | |
5635 | break; | |
5636 | case OPC2_32_RC_RSUBS_U: | |
5637 | tcg_gen_movi_tl(temp, const9); | |
5638 | gen_subsu(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]); | |
5639 | break; | |
5640 | case OPC2_32_RC_SH_EQ: | |
5641 | gen_sh_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5642 | break; | |
5643 | case OPC2_32_RC_SH_GE: | |
5644 | gen_sh_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5645 | break; | |
5646 | case OPC2_32_RC_SH_GE_U: | |
5647 | const9 = MASK_OP_RC_CONST9(ctx->opcode); | |
5648 | gen_sh_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5649 | break; | |
5650 | case OPC2_32_RC_SH_LT: | |
5651 | gen_sh_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5652 | break; | |
5653 | case OPC2_32_RC_SH_LT_U: | |
5654 | const9 = MASK_OP_RC_CONST9(ctx->opcode); | |
5655 | gen_sh_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5656 | break; | |
5657 | case OPC2_32_RC_SH_NE: | |
5658 | gen_sh_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5659 | break; | |
5660 | case OPC2_32_RC_XOR_EQ: | |
5661 | gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
5662 | const9, &tcg_gen_xor_tl); | |
5663 | break; | |
5664 | case OPC2_32_RC_XOR_GE: | |
5665 | gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
5666 | const9, &tcg_gen_xor_tl); | |
5667 | break; | |
5668 | case OPC2_32_RC_XOR_GE_U: | |
5669 | const9 = MASK_OP_RC_CONST9(ctx->opcode); | |
5670 | gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
5671 | const9, &tcg_gen_xor_tl); | |
5672 | break; | |
5673 | case OPC2_32_RC_XOR_LT: | |
5674 | gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
5675 | const9, &tcg_gen_xor_tl); | |
5676 | break; | |
5677 | case OPC2_32_RC_XOR_LT_U: | |
5678 | const9 = MASK_OP_RC_CONST9(ctx->opcode); | |
5679 | gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
5680 | const9, &tcg_gen_xor_tl); | |
5681 | break; | |
5682 | case OPC2_32_RC_XOR_NE: | |
5683 | gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], | |
5684 | const9, &tcg_gen_xor_tl); | |
5685 | break; | |
f678f671 BK |
5686 | default: |
5687 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
0974257e BK |
5688 | } |
5689 | tcg_temp_free(temp); | |
5690 | } | |
5691 | ||
2db92a0c | 5692 | static void decode_rc_serviceroutine(DisasContext *ctx) |
0974257e BK |
5693 | { |
5694 | uint32_t op2; | |
5695 | uint32_t const9; | |
5696 | ||
5697 | op2 = MASK_OP_RC_OP2(ctx->opcode); | |
5698 | const9 = MASK_OP_RC_CONST9(ctx->opcode); | |
5699 | ||
5700 | switch (op2) { | |
5701 | case OPC2_32_RC_BISR: | |
5702 | gen_helper_1arg(bisr, const9); | |
5703 | break; | |
5704 | case OPC2_32_RC_SYSCALL: | |
5705 | /* TODO: Add exception generation */ | |
5706 | break; | |
f678f671 BK |
5707 | default: |
5708 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
0974257e BK |
5709 | } |
5710 | } | |
5711 | ||
2db92a0c | 5712 | static void decode_rc_mul(DisasContext *ctx) |
0974257e BK |
5713 | { |
5714 | uint32_t op2; | |
5715 | int r1, r2; | |
5716 | int16_t const9; | |
5717 | ||
5718 | r2 = MASK_OP_RC_D(ctx->opcode); | |
5719 | r1 = MASK_OP_RC_S1(ctx->opcode); | |
5720 | const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode); | |
5721 | ||
5722 | op2 = MASK_OP_RC_OP2(ctx->opcode); | |
5723 | ||
5724 | switch (op2) { | |
5725 | case OPC2_32_RC_MUL_32: | |
5726 | gen_muli_i32s(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5727 | break; | |
5728 | case OPC2_32_RC_MUL_64: | |
828066c7 | 5729 | CHECK_REG_PAIR(r2); |
0974257e BK |
5730 | gen_muli_i64s(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9); |
5731 | break; | |
5732 | case OPC2_32_RC_MULS_32: | |
5733 | gen_mulsi_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5734 | break; | |
5735 | case OPC2_32_RC_MUL_U_64: | |
5736 | const9 = MASK_OP_RC_CONST9(ctx->opcode); | |
828066c7 | 5737 | CHECK_REG_PAIR(r2); |
0974257e BK |
5738 | gen_muli_i64u(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9); |
5739 | break; | |
5740 | case OPC2_32_RC_MULS_U_32: | |
5741 | const9 = MASK_OP_RC_CONST9(ctx->opcode); | |
5742 | gen_mulsui_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); | |
5743 | break; | |
f678f671 BK |
5744 | default: |
5745 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
0974257e BK |
5746 | } |
5747 | } | |
5748 | ||
ed516260 | 5749 | /* RCPW format */ |
2db92a0c | 5750 | static void decode_rcpw_insert(DisasContext *ctx) |
ed516260 BK |
5751 | { |
5752 | uint32_t op2; | |
5753 | int r1, r2; | |
5754 | int32_t pos, width, const4; | |
5755 | ||
5756 | TCGv temp; | |
5757 | ||
5758 | op2 = MASK_OP_RCPW_OP2(ctx->opcode); | |
5759 | r1 = MASK_OP_RCPW_S1(ctx->opcode); | |
5760 | r2 = MASK_OP_RCPW_D(ctx->opcode); | |
5761 | const4 = MASK_OP_RCPW_CONST4(ctx->opcode); | |
5762 | width = MASK_OP_RCPW_WIDTH(ctx->opcode); | |
5763 | pos = MASK_OP_RCPW_POS(ctx->opcode); | |
5764 | ||
5765 | switch (op2) { | |
5766 | case OPC2_32_RCPW_IMASK: | |
828066c7 | 5767 | CHECK_REG_PAIR(r2); |
9b620609 AK |
5768 | /* if pos + width > 32 undefined result */ |
5769 | if (pos + width <= 32) { | |
ed516260 BK |
5770 | tcg_gen_movi_tl(cpu_gpr_d[r2+1], ((1u << width) - 1) << pos); |
5771 | tcg_gen_movi_tl(cpu_gpr_d[r2], (const4 << pos)); | |
5772 | } | |
5773 | break; | |
5774 | case OPC2_32_RCPW_INSERT: | |
5775 | /* if pos + width > 32 undefined result */ | |
5776 | if (pos + width <= 32) { | |
5777 | temp = tcg_const_i32(const4); | |
5778 | tcg_gen_deposit_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, pos, width); | |
5779 | tcg_temp_free(temp); | |
5780 | } | |
5781 | break; | |
f678f671 BK |
5782 | default: |
5783 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
ed516260 BK |
5784 | } |
5785 | } | |
5786 | ||
5787 | /* RCRW format */ | |
5788 | ||
2db92a0c | 5789 | static void decode_rcrw_insert(DisasContext *ctx) |
ed516260 BK |
5790 | { |
5791 | uint32_t op2; | |
5792 | int r1, r3, r4; | |
5793 | int32_t width, const4; | |
5794 | ||
5795 | TCGv temp, temp2, temp3; | |
5796 | ||
5797 | op2 = MASK_OP_RCRW_OP2(ctx->opcode); | |
5798 | r1 = MASK_OP_RCRW_S1(ctx->opcode); | |
5799 | r3 = MASK_OP_RCRW_S3(ctx->opcode); | |
5800 | r4 = MASK_OP_RCRW_D(ctx->opcode); | |
5801 | width = MASK_OP_RCRW_WIDTH(ctx->opcode); | |
5802 | const4 = MASK_OP_RCRW_CONST4(ctx->opcode); | |
5803 | ||
5804 | temp = tcg_temp_new(); | |
5805 | temp2 = tcg_temp_new(); | |
5806 | ||
5807 | switch (op2) { | |
5808 | case OPC2_32_RCRW_IMASK: | |
5809 | tcg_gen_andi_tl(temp, cpu_gpr_d[r4], 0x1f); | |
5810 | tcg_gen_movi_tl(temp2, (1 << width) - 1); | |
5811 | tcg_gen_shl_tl(cpu_gpr_d[r3 + 1], temp2, temp); | |
5812 | tcg_gen_movi_tl(temp2, const4); | |
5813 | tcg_gen_shl_tl(cpu_gpr_d[r3], temp2, temp); | |
5814 | break; | |
5815 | case OPC2_32_RCRW_INSERT: | |
5816 | temp3 = tcg_temp_new(); | |
5817 | ||
5818 | tcg_gen_movi_tl(temp, width); | |
5819 | tcg_gen_movi_tl(temp2, const4); | |
5820 | tcg_gen_andi_tl(temp3, cpu_gpr_d[r4], 0x1f); | |
5821 | gen_insert(cpu_gpr_d[r3], cpu_gpr_d[r1], temp2, temp, temp3); | |
5822 | ||
5823 | tcg_temp_free(temp3); | |
5824 | break; | |
f678f671 BK |
5825 | default: |
5826 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
ed516260 BK |
5827 | } |
5828 | tcg_temp_free(temp); | |
5829 | tcg_temp_free(temp2); | |
5830 | } | |
5831 | ||
328f1f0f BK |
5832 | /* RCR format */ |
5833 | ||
2db92a0c | 5834 | static void decode_rcr_cond_select(DisasContext *ctx) |
328f1f0f BK |
5835 | { |
5836 | uint32_t op2; | |
5837 | int r1, r3, r4; | |
5838 | int32_t const9; | |
5839 | ||
5840 | TCGv temp, temp2; | |
5841 | ||
5842 | op2 = MASK_OP_RCR_OP2(ctx->opcode); | |
5843 | r1 = MASK_OP_RCR_S1(ctx->opcode); | |
5844 | const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode); | |
5845 | r3 = MASK_OP_RCR_S3(ctx->opcode); | |
5846 | r4 = MASK_OP_RCR_D(ctx->opcode); | |
5847 | ||
5848 | switch (op2) { | |
5849 | case OPC2_32_RCR_CADD: | |
a00585ee DB |
5850 | gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const9, cpu_gpr_d[r4], |
5851 | cpu_gpr_d[r3]); | |
328f1f0f BK |
5852 | break; |
5853 | case OPC2_32_RCR_CADDN: | |
d1c1d88c DB |
5854 | gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const9, cpu_gpr_d[r4], |
5855 | cpu_gpr_d[r3]); | |
328f1f0f BK |
5856 | break; |
5857 | case OPC2_32_RCR_SEL: | |
5858 | temp = tcg_const_i32(0); | |
5859 | temp2 = tcg_const_i32(const9); | |
5f30046f | 5860 | tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, |
328f1f0f BK |
5861 | cpu_gpr_d[r1], temp2); |
5862 | tcg_temp_free(temp); | |
5863 | tcg_temp_free(temp2); | |
5864 | break; | |
5865 | case OPC2_32_RCR_SELN: | |
5866 | temp = tcg_const_i32(0); | |
5867 | temp2 = tcg_const_i32(const9); | |
5f30046f | 5868 | tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, |
328f1f0f BK |
5869 | cpu_gpr_d[r1], temp2); |
5870 | tcg_temp_free(temp); | |
5871 | tcg_temp_free(temp2); | |
5872 | break; | |
f678f671 BK |
5873 | default: |
5874 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
328f1f0f BK |
5875 | } |
5876 | } | |
5877 | ||
2db92a0c | 5878 | static void decode_rcr_madd(DisasContext *ctx) |
328f1f0f BK |
5879 | { |
5880 | uint32_t op2; | |
5881 | int r1, r3, r4; | |
5882 | int32_t const9; | |
5883 | ||
5884 | ||
5885 | op2 = MASK_OP_RCR_OP2(ctx->opcode); | |
5886 | r1 = MASK_OP_RCR_S1(ctx->opcode); | |
5887 | const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode); | |
5888 | r3 = MASK_OP_RCR_S3(ctx->opcode); | |
5889 | r4 = MASK_OP_RCR_D(ctx->opcode); | |
5890 | ||
5891 | switch (op2) { | |
5892 | case OPC2_32_RCR_MADD_32: | |
5893 | gen_maddi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); | |
5894 | break; | |
5895 | case OPC2_32_RCR_MADD_64: | |
828066c7 BK |
5896 | CHECK_REG_PAIR(r4); |
5897 | CHECK_REG_PAIR(r3); | |
328f1f0f BK |
5898 | gen_maddi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], |
5899 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); | |
5900 | break; | |
5901 | case OPC2_32_RCR_MADDS_32: | |
5902 | gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); | |
5903 | break; | |
5904 | case OPC2_32_RCR_MADDS_64: | |
828066c7 BK |
5905 | CHECK_REG_PAIR(r4); |
5906 | CHECK_REG_PAIR(r3); | |
328f1f0f BK |
5907 | gen_maddsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], |
5908 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); | |
5909 | break; | |
5910 | case OPC2_32_RCR_MADD_U_64: | |
828066c7 BK |
5911 | CHECK_REG_PAIR(r4); |
5912 | CHECK_REG_PAIR(r3); | |
328f1f0f BK |
5913 | const9 = MASK_OP_RCR_CONST9(ctx->opcode); |
5914 | gen_maddui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], | |
5915 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); | |
5916 | break; | |
5917 | case OPC2_32_RCR_MADDS_U_32: | |
5918 | const9 = MASK_OP_RCR_CONST9(ctx->opcode); | |
5919 | gen_maddsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); | |
5920 | break; | |
5921 | case OPC2_32_RCR_MADDS_U_64: | |
828066c7 BK |
5922 | CHECK_REG_PAIR(r4); |
5923 | CHECK_REG_PAIR(r3); | |
328f1f0f BK |
5924 | const9 = MASK_OP_RCR_CONST9(ctx->opcode); |
5925 | gen_maddsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], | |
5926 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); | |
5927 | break; | |
f678f671 BK |
5928 | default: |
5929 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
328f1f0f BK |
5930 | } |
5931 | } | |
5932 | ||
2db92a0c | 5933 | static void decode_rcr_msub(DisasContext *ctx) |
328f1f0f BK |
5934 | { |
5935 | uint32_t op2; | |
5936 | int r1, r3, r4; | |
5937 | int32_t const9; | |
5938 | ||
5939 | ||
5940 | op2 = MASK_OP_RCR_OP2(ctx->opcode); | |
5941 | r1 = MASK_OP_RCR_S1(ctx->opcode); | |
5942 | const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode); | |
5943 | r3 = MASK_OP_RCR_S3(ctx->opcode); | |
5944 | r4 = MASK_OP_RCR_D(ctx->opcode); | |
5945 | ||
5946 | switch (op2) { | |
5947 | case OPC2_32_RCR_MSUB_32: | |
5948 | gen_msubi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); | |
5949 | break; | |
5950 | case OPC2_32_RCR_MSUB_64: | |
828066c7 BK |
5951 | CHECK_REG_PAIR(r4); |
5952 | CHECK_REG_PAIR(r3); | |
328f1f0f BK |
5953 | gen_msubi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], |
5954 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); | |
5955 | break; | |
5956 | case OPC2_32_RCR_MSUBS_32: | |
5957 | gen_msubsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); | |
5958 | break; | |
5959 | case OPC2_32_RCR_MSUBS_64: | |
828066c7 BK |
5960 | CHECK_REG_PAIR(r4); |
5961 | CHECK_REG_PAIR(r3); | |
328f1f0f BK |
5962 | gen_msubsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], |
5963 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); | |
5964 | break; | |
5965 | case OPC2_32_RCR_MSUB_U_64: | |
828066c7 BK |
5966 | CHECK_REG_PAIR(r4); |
5967 | CHECK_REG_PAIR(r3); | |
328f1f0f BK |
5968 | const9 = MASK_OP_RCR_CONST9(ctx->opcode); |
5969 | gen_msubui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], | |
5970 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); | |
5971 | break; | |
5972 | case OPC2_32_RCR_MSUBS_U_32: | |
5973 | const9 = MASK_OP_RCR_CONST9(ctx->opcode); | |
5974 | gen_msubsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); | |
5975 | break; | |
5976 | case OPC2_32_RCR_MSUBS_U_64: | |
828066c7 BK |
5977 | CHECK_REG_PAIR(r4); |
5978 | CHECK_REG_PAIR(r3); | |
328f1f0f BK |
5979 | const9 = MASK_OP_RCR_CONST9(ctx->opcode); |
5980 | gen_msubsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], | |
5981 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); | |
5982 | break; | |
f678f671 BK |
5983 | default: |
5984 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
328f1f0f BK |
5985 | } |
5986 | } | |
5987 | ||
2b2f7d97 BK |
5988 | /* RLC format */ |
5989 | ||
2db92a0c | 5990 | static void decode_rlc_opc(DisasContext *ctx, |
2b2f7d97 BK |
5991 | uint32_t op1) |
5992 | { | |
5993 | int32_t const16; | |
5994 | int r1, r2; | |
5995 | ||
5996 | const16 = MASK_OP_RLC_CONST16_SEXT(ctx->opcode); | |
5997 | r1 = MASK_OP_RLC_S1(ctx->opcode); | |
5998 | r2 = MASK_OP_RLC_D(ctx->opcode); | |
5999 | ||
6000 | switch (op1) { | |
6001 | case OPC1_32_RLC_ADDI: | |
f0cab01b | 6002 | gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16); |
2b2f7d97 BK |
6003 | break; |
6004 | case OPC1_32_RLC_ADDIH: | |
f0cab01b | 6005 | gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16 << 16); |
2b2f7d97 BK |
6006 | break; |
6007 | case OPC1_32_RLC_ADDIH_A: | |
6008 | tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r1], const16 << 16); | |
6009 | break; | |
6010 | case OPC1_32_RLC_MFCR: | |
436d63ff | 6011 | const16 = MASK_OP_RLC_CONST16(ctx->opcode); |
2db92a0c | 6012 | gen_mfcr(ctx, cpu_gpr_d[r2], const16); |
2b2f7d97 BK |
6013 | break; |
6014 | case OPC1_32_RLC_MOV: | |
6015 | tcg_gen_movi_tl(cpu_gpr_d[r2], const16); | |
6016 | break; | |
4b5b4435 | 6017 | case OPC1_32_RLC_MOV_64: |
44ee3baf | 6018 | if (has_feature(ctx, TRICORE_FEATURE_16)) { |
828066c7 | 6019 | CHECK_REG_PAIR(r2); |
4b5b4435 AZ |
6020 | tcg_gen_movi_tl(cpu_gpr_d[r2], const16); |
6021 | tcg_gen_movi_tl(cpu_gpr_d[r2+1], const16 >> 15); | |
6022 | } else { | |
f678f671 | 6023 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); |
4b5b4435 AZ |
6024 | } |
6025 | break; | |
2b2f7d97 BK |
6026 | case OPC1_32_RLC_MOV_U: |
6027 | const16 = MASK_OP_RLC_CONST16(ctx->opcode); | |
6028 | tcg_gen_movi_tl(cpu_gpr_d[r2], const16); | |
6029 | break; | |
6030 | case OPC1_32_RLC_MOV_H: | |
6031 | tcg_gen_movi_tl(cpu_gpr_d[r2], const16 << 16); | |
6032 | break; | |
6033 | case OPC1_32_RLC_MOVH_A: | |
6034 | tcg_gen_movi_tl(cpu_gpr_a[r2], const16 << 16); | |
6035 | break; | |
6036 | case OPC1_32_RLC_MTCR: | |
436d63ff | 6037 | const16 = MASK_OP_RLC_CONST16(ctx->opcode); |
2db92a0c | 6038 | gen_mtcr(ctx, cpu_gpr_d[r1], const16); |
2b2f7d97 | 6039 | break; |
f678f671 BK |
6040 | default: |
6041 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
2b2f7d97 BK |
6042 | } |
6043 | } | |
6044 | ||
d5de7839 | 6045 | /* RR format */ |
2db92a0c | 6046 | static void decode_rr_accumulator(DisasContext *ctx) |
d5de7839 BK |
6047 | { |
6048 | uint32_t op2; | |
6049 | int r3, r2, r1; | |
6050 | ||
550929dd PA |
6051 | TCGv temp; |
6052 | ||
d5de7839 BK |
6053 | r3 = MASK_OP_RR_D(ctx->opcode); |
6054 | r2 = MASK_OP_RR_S2(ctx->opcode); | |
6055 | r1 = MASK_OP_RR_S1(ctx->opcode); | |
6056 | op2 = MASK_OP_RR_OP2(ctx->opcode); | |
6057 | ||
6058 | switch (op2) { | |
6059 | case OPC2_32_RR_ABS: | |
6060 | gen_abs(cpu_gpr_d[r3], cpu_gpr_d[r2]); | |
6061 | break; | |
6062 | case OPC2_32_RR_ABS_B: | |
6063 | gen_helper_abs_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]); | |
6064 | break; | |
6065 | case OPC2_32_RR_ABS_H: | |
6066 | gen_helper_abs_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]); | |
6067 | break; | |
6068 | case OPC2_32_RR_ABSDIF: | |
6069 | gen_absdif(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6070 | break; | |
6071 | case OPC2_32_RR_ABSDIF_B: | |
6072 | gen_helper_absdif_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], | |
6073 | cpu_gpr_d[r2]); | |
6074 | break; | |
6075 | case OPC2_32_RR_ABSDIF_H: | |
6076 | gen_helper_absdif_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], | |
6077 | cpu_gpr_d[r2]); | |
6078 | break; | |
6079 | case OPC2_32_RR_ABSDIFS: | |
6080 | gen_helper_absdif_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], | |
6081 | cpu_gpr_d[r2]); | |
6082 | break; | |
6083 | case OPC2_32_RR_ABSDIFS_H: | |
6084 | gen_helper_absdif_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], | |
6085 | cpu_gpr_d[r2]); | |
6086 | break; | |
6087 | case OPC2_32_RR_ABSS: | |
6088 | gen_helper_abs_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]); | |
6089 | break; | |
6090 | case OPC2_32_RR_ABSS_H: | |
6091 | gen_helper_abs_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]); | |
6092 | break; | |
6093 | case OPC2_32_RR_ADD: | |
6094 | gen_add_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6095 | break; | |
6096 | case OPC2_32_RR_ADD_B: | |
6097 | gen_helper_add_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6098 | break; | |
6099 | case OPC2_32_RR_ADD_H: | |
6100 | gen_helper_add_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6101 | break; | |
6102 | case OPC2_32_RR_ADDC: | |
6103 | gen_addc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6104 | break; | |
6105 | case OPC2_32_RR_ADDS: | |
6106 | gen_adds(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6107 | break; | |
6108 | case OPC2_32_RR_ADDS_H: | |
6109 | gen_helper_add_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], | |
6110 | cpu_gpr_d[r2]); | |
6111 | break; | |
6112 | case OPC2_32_RR_ADDS_HU: | |
6113 | gen_helper_add_h_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], | |
6114 | cpu_gpr_d[r2]); | |
6115 | break; | |
6116 | case OPC2_32_RR_ADDS_U: | |
6117 | gen_helper_add_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], | |
6118 | cpu_gpr_d[r2]); | |
6119 | break; | |
6120 | case OPC2_32_RR_ADDX: | |
6121 | gen_add_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6122 | break; | |
6123 | case OPC2_32_RR_AND_EQ: | |
6124 | gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6125 | cpu_gpr_d[r2], &tcg_gen_and_tl); | |
6126 | break; | |
6127 | case OPC2_32_RR_AND_GE: | |
6128 | gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6129 | cpu_gpr_d[r2], &tcg_gen_and_tl); | |
6130 | break; | |
6131 | case OPC2_32_RR_AND_GE_U: | |
6132 | gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6133 | cpu_gpr_d[r2], &tcg_gen_and_tl); | |
6134 | break; | |
6135 | case OPC2_32_RR_AND_LT: | |
6136 | gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6137 | cpu_gpr_d[r2], &tcg_gen_and_tl); | |
6138 | break; | |
6139 | case OPC2_32_RR_AND_LT_U: | |
6140 | gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6141 | cpu_gpr_d[r2], &tcg_gen_and_tl); | |
6142 | break; | |
6143 | case OPC2_32_RR_AND_NE: | |
6144 | gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6145 | cpu_gpr_d[r2], &tcg_gen_and_tl); | |
6146 | break; | |
6147 | case OPC2_32_RR_EQ: | |
6148 | tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6149 | cpu_gpr_d[r2]); | |
6150 | break; | |
6151 | case OPC2_32_RR_EQ_B: | |
6152 | gen_helper_eq_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6153 | break; | |
6154 | case OPC2_32_RR_EQ_H: | |
6155 | gen_helper_eq_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6156 | break; | |
6157 | case OPC2_32_RR_EQ_W: | |
6158 | gen_cond_w(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6159 | break; | |
6160 | case OPC2_32_RR_EQANY_B: | |
6161 | gen_helper_eqany_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6162 | break; | |
6163 | case OPC2_32_RR_EQANY_H: | |
6164 | gen_helper_eqany_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6165 | break; | |
6166 | case OPC2_32_RR_GE: | |
6167 | tcg_gen_setcond_tl(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6168 | cpu_gpr_d[r2]); | |
6169 | break; | |
6170 | case OPC2_32_RR_GE_U: | |
6171 | tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6172 | cpu_gpr_d[r2]); | |
6173 | break; | |
6174 | case OPC2_32_RR_LT: | |
6175 | tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6176 | cpu_gpr_d[r2]); | |
6177 | break; | |
6178 | case OPC2_32_RR_LT_U: | |
6179 | tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6180 | cpu_gpr_d[r2]); | |
6181 | break; | |
6182 | case OPC2_32_RR_LT_B: | |
6183 | gen_helper_lt_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6184 | break; | |
6185 | case OPC2_32_RR_LT_BU: | |
6186 | gen_helper_lt_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6187 | break; | |
6188 | case OPC2_32_RR_LT_H: | |
6189 | gen_helper_lt_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6190 | break; | |
6191 | case OPC2_32_RR_LT_HU: | |
6192 | gen_helper_lt_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6193 | break; | |
6194 | case OPC2_32_RR_LT_W: | |
6195 | gen_cond_w(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6196 | break; | |
6197 | case OPC2_32_RR_LT_WU: | |
6198 | gen_cond_w(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6199 | break; | |
6200 | case OPC2_32_RR_MAX: | |
6201 | tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6202 | cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6203 | break; | |
6204 | case OPC2_32_RR_MAX_U: | |
6205 | tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6206 | cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6207 | break; | |
6208 | case OPC2_32_RR_MAX_B: | |
6209 | gen_helper_max_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6210 | break; | |
6211 | case OPC2_32_RR_MAX_BU: | |
6212 | gen_helper_max_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6213 | break; | |
6214 | case OPC2_32_RR_MAX_H: | |
6215 | gen_helper_max_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6216 | break; | |
6217 | case OPC2_32_RR_MAX_HU: | |
6218 | gen_helper_max_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6219 | break; | |
6220 | case OPC2_32_RR_MIN: | |
6221 | tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6222 | cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6223 | break; | |
6224 | case OPC2_32_RR_MIN_U: | |
6225 | tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6226 | cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6227 | break; | |
6228 | case OPC2_32_RR_MIN_B: | |
6229 | gen_helper_min_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6230 | break; | |
6231 | case OPC2_32_RR_MIN_BU: | |
6232 | gen_helper_min_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6233 | break; | |
6234 | case OPC2_32_RR_MIN_H: | |
6235 | gen_helper_min_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6236 | break; | |
6237 | case OPC2_32_RR_MIN_HU: | |
6238 | gen_helper_min_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6239 | break; | |
6240 | case OPC2_32_RR_MOV: | |
6241 | tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); | |
6242 | break; | |
550929dd | 6243 | case OPC2_32_RR_MOV_64: |
44ee3baf | 6244 | if (has_feature(ctx, TRICORE_FEATURE_16)) { |
550929dd PA |
6245 | temp = tcg_temp_new(); |
6246 | ||
6247 | CHECK_REG_PAIR(r3); | |
6248 | tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); | |
6249 | tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); | |
6250 | tcg_gen_mov_tl(cpu_gpr_d[r3 + 1], temp); | |
6251 | ||
6252 | tcg_temp_free(temp); | |
6253 | } else { | |
6254 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
6255 | } | |
6256 | break; | |
defda2d4 | 6257 | case OPC2_32_RR_MOVS_64: |
44ee3baf | 6258 | if (has_feature(ctx, TRICORE_FEATURE_16)) { |
defda2d4 DB |
6259 | CHECK_REG_PAIR(r3); |
6260 | tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); | |
6261 | tcg_gen_sari_tl(cpu_gpr_d[r3 + 1], cpu_gpr_d[r2], 31); | |
6262 | } else { | |
6263 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
6264 | } | |
6265 | break; | |
d5de7839 BK |
6266 | case OPC2_32_RR_NE: |
6267 | tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6268 | cpu_gpr_d[r2]); | |
6269 | break; | |
6270 | case OPC2_32_RR_OR_EQ: | |
6271 | gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6272 | cpu_gpr_d[r2], &tcg_gen_or_tl); | |
6273 | break; | |
6274 | case OPC2_32_RR_OR_GE: | |
6275 | gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6276 | cpu_gpr_d[r2], &tcg_gen_or_tl); | |
6277 | break; | |
6278 | case OPC2_32_RR_OR_GE_U: | |
6279 | gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6280 | cpu_gpr_d[r2], &tcg_gen_or_tl); | |
6281 | break; | |
6282 | case OPC2_32_RR_OR_LT: | |
6283 | gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6284 | cpu_gpr_d[r2], &tcg_gen_or_tl); | |
6285 | break; | |
6286 | case OPC2_32_RR_OR_LT_U: | |
6287 | gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6288 | cpu_gpr_d[r2], &tcg_gen_or_tl); | |
6289 | break; | |
6290 | case OPC2_32_RR_OR_NE: | |
6291 | gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6292 | cpu_gpr_d[r2], &tcg_gen_or_tl); | |
6293 | break; | |
6294 | case OPC2_32_RR_SAT_B: | |
6295 | gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7f, -0x80); | |
6296 | break; | |
6297 | case OPC2_32_RR_SAT_BU: | |
6298 | gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xff); | |
6299 | break; | |
6300 | case OPC2_32_RR_SAT_H: | |
6301 | gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7fff, -0x8000); | |
6302 | break; | |
6303 | case OPC2_32_RR_SAT_HU: | |
6304 | gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xffff); | |
6305 | break; | |
6306 | case OPC2_32_RR_SH_EQ: | |
6307 | gen_sh_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6308 | cpu_gpr_d[r2]); | |
6309 | break; | |
6310 | case OPC2_32_RR_SH_GE: | |
6311 | gen_sh_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6312 | cpu_gpr_d[r2]); | |
6313 | break; | |
6314 | case OPC2_32_RR_SH_GE_U: | |
6315 | gen_sh_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6316 | cpu_gpr_d[r2]); | |
6317 | break; | |
6318 | case OPC2_32_RR_SH_LT: | |
6319 | gen_sh_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6320 | cpu_gpr_d[r2]); | |
6321 | break; | |
6322 | case OPC2_32_RR_SH_LT_U: | |
6323 | gen_sh_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6324 | cpu_gpr_d[r2]); | |
6325 | break; | |
6326 | case OPC2_32_RR_SH_NE: | |
6327 | gen_sh_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6328 | cpu_gpr_d[r2]); | |
6329 | break; | |
6330 | case OPC2_32_RR_SUB: | |
6331 | gen_sub_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6332 | break; | |
6333 | case OPC2_32_RR_SUB_B: | |
6334 | gen_helper_sub_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6335 | break; | |
6336 | case OPC2_32_RR_SUB_H: | |
6337 | gen_helper_sub_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6338 | break; | |
6339 | case OPC2_32_RR_SUBC: | |
6340 | gen_subc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6341 | break; | |
6342 | case OPC2_32_RR_SUBS: | |
6343 | gen_subs(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6344 | break; | |
6345 | case OPC2_32_RR_SUBS_U: | |
6346 | gen_subsu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6347 | break; | |
6348 | case OPC2_32_RR_SUBS_H: | |
6349 | gen_helper_sub_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], | |
6350 | cpu_gpr_d[r2]); | |
6351 | break; | |
6352 | case OPC2_32_RR_SUBS_HU: | |
6353 | gen_helper_sub_h_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], | |
6354 | cpu_gpr_d[r2]); | |
6355 | break; | |
6356 | case OPC2_32_RR_SUBX: | |
6357 | gen_sub_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6358 | break; | |
6359 | case OPC2_32_RR_XOR_EQ: | |
6360 | gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6361 | cpu_gpr_d[r2], &tcg_gen_xor_tl); | |
6362 | break; | |
6363 | case OPC2_32_RR_XOR_GE: | |
6364 | gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6365 | cpu_gpr_d[r2], &tcg_gen_xor_tl); | |
6366 | break; | |
6367 | case OPC2_32_RR_XOR_GE_U: | |
6368 | gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6369 | cpu_gpr_d[r2], &tcg_gen_xor_tl); | |
6370 | break; | |
6371 | case OPC2_32_RR_XOR_LT: | |
6372 | gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6373 | cpu_gpr_d[r2], &tcg_gen_xor_tl); | |
6374 | break; | |
6375 | case OPC2_32_RR_XOR_LT_U: | |
6376 | gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6377 | cpu_gpr_d[r2], &tcg_gen_xor_tl); | |
6378 | break; | |
6379 | case OPC2_32_RR_XOR_NE: | |
6380 | gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], | |
6381 | cpu_gpr_d[r2], &tcg_gen_xor_tl); | |
6382 | break; | |
f678f671 BK |
6383 | default: |
6384 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
d5de7839 BK |
6385 | } |
6386 | } | |
6387 | ||
2db92a0c | 6388 | static void decode_rr_logical_shift(DisasContext *ctx) |
0b79a781 BK |
6389 | { |
6390 | uint32_t op2; | |
6391 | int r3, r2, r1; | |
6392 | TCGv temp; | |
6393 | ||
6394 | r3 = MASK_OP_RR_D(ctx->opcode); | |
6395 | r2 = MASK_OP_RR_S2(ctx->opcode); | |
6396 | r1 = MASK_OP_RR_S1(ctx->opcode); | |
6397 | ||
6398 | temp = tcg_temp_new(); | |
6399 | op2 = MASK_OP_RR_OP2(ctx->opcode); | |
6400 | ||
6401 | switch (op2) { | |
6402 | case OPC2_32_RR_AND: | |
6403 | tcg_gen_and_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6404 | break; | |
6405 | case OPC2_32_RR_ANDN: | |
6406 | tcg_gen_andc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6407 | break; | |
6408 | case OPC2_32_RR_CLO: | |
0efa8208 RH |
6409 | tcg_gen_not_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); |
6410 | tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], TARGET_LONG_BITS); | |
0b79a781 BK |
6411 | break; |
6412 | case OPC2_32_RR_CLO_H: | |
6413 | gen_helper_clo_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); | |
6414 | break; | |
6415 | case OPC2_32_RR_CLS: | |
16256947 | 6416 | tcg_gen_clrsb_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); |
0b79a781 BK |
6417 | break; |
6418 | case OPC2_32_RR_CLS_H: | |
6419 | gen_helper_cls_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); | |
6420 | break; | |
6421 | case OPC2_32_RR_CLZ: | |
0efa8208 | 6422 | tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], TARGET_LONG_BITS); |
0b79a781 BK |
6423 | break; |
6424 | case OPC2_32_RR_CLZ_H: | |
6425 | gen_helper_clz_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); | |
6426 | break; | |
6427 | case OPC2_32_RR_NAND: | |
6428 | tcg_gen_nand_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6429 | break; | |
6430 | case OPC2_32_RR_NOR: | |
6431 | tcg_gen_nor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6432 | break; | |
6433 | case OPC2_32_RR_OR: | |
6434 | tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6435 | break; | |
6436 | case OPC2_32_RR_ORN: | |
6437 | tcg_gen_orc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6438 | break; | |
6439 | case OPC2_32_RR_SH: | |
6440 | gen_helper_sh(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6441 | break; | |
6442 | case OPC2_32_RR_SH_H: | |
6443 | gen_helper_sh_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6444 | break; | |
6445 | case OPC2_32_RR_SHA: | |
6446 | gen_helper_sha(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6447 | break; | |
6448 | case OPC2_32_RR_SHA_H: | |
6449 | gen_helper_sha_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6450 | break; | |
6451 | case OPC2_32_RR_SHAS: | |
6452 | gen_shas(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6453 | break; | |
6454 | case OPC2_32_RR_XNOR: | |
6455 | tcg_gen_eqv_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6456 | break; | |
6457 | case OPC2_32_RR_XOR: | |
6458 | tcg_gen_xor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6459 | break; | |
f678f671 BK |
6460 | default: |
6461 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
0b79a781 BK |
6462 | } |
6463 | tcg_temp_free(temp); | |
6464 | } | |
6465 | ||
2db92a0c | 6466 | static void decode_rr_address(DisasContext *ctx) |
f2f1585f BK |
6467 | { |
6468 | uint32_t op2, n; | |
6469 | int r1, r2, r3; | |
6470 | TCGv temp; | |
6471 | ||
6472 | op2 = MASK_OP_RR_OP2(ctx->opcode); | |
6473 | r3 = MASK_OP_RR_D(ctx->opcode); | |
6474 | r2 = MASK_OP_RR_S2(ctx->opcode); | |
6475 | r1 = MASK_OP_RR_S1(ctx->opcode); | |
6476 | n = MASK_OP_RR_N(ctx->opcode); | |
6477 | ||
6478 | switch (op2) { | |
6479 | case OPC2_32_RR_ADD_A: | |
6480 | tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]); | |
6481 | break; | |
6482 | case OPC2_32_RR_ADDSC_A: | |
6483 | temp = tcg_temp_new(); | |
6484 | tcg_gen_shli_tl(temp, cpu_gpr_d[r1], n); | |
6485 | tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r2], temp); | |
6486 | tcg_temp_free(temp); | |
6487 | break; | |
6488 | case OPC2_32_RR_ADDSC_AT: | |
6489 | temp = tcg_temp_new(); | |
6490 | tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 3); | |
6491 | tcg_gen_add_tl(temp, cpu_gpr_a[r2], temp); | |
6492 | tcg_gen_andi_tl(cpu_gpr_a[r3], temp, 0xFFFFFFFC); | |
6493 | tcg_temp_free(temp); | |
6494 | break; | |
6495 | case OPC2_32_RR_EQ_A: | |
6496 | tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1], | |
6497 | cpu_gpr_a[r2]); | |
6498 | break; | |
6499 | case OPC2_32_RR_EQZ: | |
6500 | tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1], 0); | |
6501 | break; | |
6502 | case OPC2_32_RR_GE_A: | |
6503 | tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_a[r1], | |
6504 | cpu_gpr_a[r2]); | |
6505 | break; | |
6506 | case OPC2_32_RR_LT_A: | |
6507 | tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_a[r1], | |
6508 | cpu_gpr_a[r2]); | |
6509 | break; | |
6510 | case OPC2_32_RR_MOV_A: | |
6511 | tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_d[r2]); | |
6512 | break; | |
6513 | case OPC2_32_RR_MOV_AA: | |
6514 | tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_a[r2]); | |
6515 | break; | |
6516 | case OPC2_32_RR_MOV_D: | |
6517 | tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_a[r2]); | |
6518 | break; | |
6519 | case OPC2_32_RR_NE_A: | |
6520 | tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1], | |
6521 | cpu_gpr_a[r2]); | |
6522 | break; | |
6523 | case OPC2_32_RR_NEZ_A: | |
6524 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1], 0); | |
6525 | break; | |
6526 | case OPC2_32_RR_SUB_A: | |
6527 | tcg_gen_sub_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]); | |
6528 | break; | |
f678f671 BK |
6529 | default: |
6530 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
f2f1585f BK |
6531 | } |
6532 | } | |
6533 | ||
2db92a0c | 6534 | static void decode_rr_idirect(DisasContext *ctx) |
f2f1585f BK |
6535 | { |
6536 | uint32_t op2; | |
6537 | int r1; | |
6538 | ||
6539 | op2 = MASK_OP_RR_OP2(ctx->opcode); | |
6540 | r1 = MASK_OP_RR_S1(ctx->opcode); | |
6541 | ||
6542 | switch (op2) { | |
6543 | case OPC2_32_RR_JI: | |
6544 | tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); | |
6545 | break; | |
6546 | case OPC2_32_RR_JLI: | |
6b9f5a42 | 6547 | tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); |
f2f1585f BK |
6548 | tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); |
6549 | break; | |
6550 | case OPC2_32_RR_CALLI: | |
6b9f5a42 | 6551 | gen_helper_1arg(call, ctx->pc_succ_insn); |
f2f1585f BK |
6552 | tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); |
6553 | break; | |
9e14a7b2 BK |
6554 | case OPC2_32_RR_FCALLI: |
6555 | gen_fcall_save_ctx(ctx); | |
6556 | tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); | |
6557 | break; | |
f678f671 BK |
6558 | default: |
6559 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
f2f1585f | 6560 | } |
07ea28b4 | 6561 | tcg_gen_exit_tb(NULL, 0); |
6b9f5a42 | 6562 | ctx->base.is_jmp = DISAS_NORETURN; |
f2f1585f BK |
6563 | } |
6564 | ||
2db92a0c | 6565 | static void decode_rr_divide(DisasContext *ctx) |
e2bed107 BK |
6566 | { |
6567 | uint32_t op2; | |
6568 | int r1, r2, r3; | |
6569 | ||
2b9d09bb | 6570 | TCGv temp, temp2, temp3; |
e2bed107 BK |
6571 | |
6572 | op2 = MASK_OP_RR_OP2(ctx->opcode); | |
6573 | r3 = MASK_OP_RR_D(ctx->opcode); | |
6574 | r2 = MASK_OP_RR_S2(ctx->opcode); | |
6575 | r1 = MASK_OP_RR_S1(ctx->opcode); | |
6576 | ||
6577 | switch (op2) { | |
6578 | case OPC2_32_RR_BMERGE: | |
6579 | gen_helper_bmerge(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6580 | break; | |
6581 | case OPC2_32_RR_BSPLIT: | |
828066c7 | 6582 | CHECK_REG_PAIR(r3); |
e2bed107 BK |
6583 | gen_bsplit(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]); |
6584 | break; | |
6585 | case OPC2_32_RR_DVINIT_B: | |
828066c7 | 6586 | CHECK_REG_PAIR(r3); |
2db92a0c | 6587 | gen_dvinit_b(ctx, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], |
e2bed107 BK |
6588 | cpu_gpr_d[r2]); |
6589 | break; | |
6590 | case OPC2_32_RR_DVINIT_BU: | |
6591 | temp = tcg_temp_new(); | |
6592 | temp2 = tcg_temp_new(); | |
2b9d09bb | 6593 | temp3 = tcg_temp_new(); |
828066c7 | 6594 | CHECK_REG_PAIR(r3); |
2b9d09bb | 6595 | tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 8); |
e2bed107 BK |
6596 | /* reset av */ |
6597 | tcg_gen_movi_tl(cpu_PSW_AV, 0); | |
44ee3baf | 6598 | if (!has_feature(ctx, TRICORE_FEATURE_131)) { |
e2bed107 | 6599 | /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */ |
2f8036d2 PMD |
6600 | tcg_gen_abs_tl(temp, temp3); |
6601 | tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]); | |
e2bed107 BK |
6602 | tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2); |
6603 | } else { | |
6604 | /* overflow = (D[b] == 0) */ | |
6605 | tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0); | |
6606 | } | |
6607 | tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); | |
6608 | /* sv */ | |
6609 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
6610 | /* write result */ | |
e2bed107 | 6611 | tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 24); |
2b9d09bb | 6612 | tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3); |
e2bed107 BK |
6613 | |
6614 | tcg_temp_free(temp); | |
6615 | tcg_temp_free(temp2); | |
2b9d09bb | 6616 | tcg_temp_free(temp3); |
e2bed107 BK |
6617 | break; |
6618 | case OPC2_32_RR_DVINIT_H: | |
828066c7 | 6619 | CHECK_REG_PAIR(r3); |
2db92a0c | 6620 | gen_dvinit_h(ctx, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], |
e2bed107 BK |
6621 | cpu_gpr_d[r2]); |
6622 | break; | |
6623 | case OPC2_32_RR_DVINIT_HU: | |
6624 | temp = tcg_temp_new(); | |
6625 | temp2 = tcg_temp_new(); | |
2b9d09bb | 6626 | temp3 = tcg_temp_new(); |
828066c7 | 6627 | CHECK_REG_PAIR(r3); |
2b9d09bb | 6628 | tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 16); |
e2bed107 BK |
6629 | /* reset av */ |
6630 | tcg_gen_movi_tl(cpu_PSW_AV, 0); | |
44ee3baf | 6631 | if (!has_feature(ctx, TRICORE_FEATURE_131)) { |
e2bed107 | 6632 | /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */ |
2f8036d2 PMD |
6633 | tcg_gen_abs_tl(temp, temp3); |
6634 | tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]); | |
e2bed107 BK |
6635 | tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2); |
6636 | } else { | |
6637 | /* overflow = (D[b] == 0) */ | |
6638 | tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0); | |
6639 | } | |
6640 | tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); | |
6641 | /* sv */ | |
6642 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
6643 | /* write result */ | |
2b9d09bb | 6644 | tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 16); |
05b6ca9b | 6645 | tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3); |
e2bed107 BK |
6646 | tcg_temp_free(temp); |
6647 | tcg_temp_free(temp2); | |
2b9d09bb | 6648 | tcg_temp_free(temp3); |
e2bed107 BK |
6649 | break; |
6650 | case OPC2_32_RR_DVINIT: | |
6651 | temp = tcg_temp_new(); | |
6652 | temp2 = tcg_temp_new(); | |
828066c7 | 6653 | CHECK_REG_PAIR(r3); |
e2bed107 BK |
6654 | /* overflow = ((D[b] == 0) || |
6655 | ((D[b] == 0xFFFFFFFF) && (D[a] == 0x80000000))) */ | |
6656 | tcg_gen_setcondi_tl(TCG_COND_EQ, temp, cpu_gpr_d[r2], 0xffffffff); | |
6657 | tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r1], 0x80000000); | |
6658 | tcg_gen_and_tl(temp, temp, temp2); | |
6659 | tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r2], 0); | |
6660 | tcg_gen_or_tl(cpu_PSW_V, temp, temp2); | |
6661 | tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); | |
6662 | /* sv */ | |
6663 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
6664 | /* reset av */ | |
6665 | tcg_gen_movi_tl(cpu_PSW_AV, 0); | |
6666 | /* write result */ | |
6667 | tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); | |
6668 | /* sign extend to high reg */ | |
6669 | tcg_gen_sari_tl(cpu_gpr_d[r3+1], cpu_gpr_d[r1], 31); | |
6670 | tcg_temp_free(temp); | |
6671 | tcg_temp_free(temp2); | |
6672 | break; | |
6673 | case OPC2_32_RR_DVINIT_U: | |
6674 | /* overflow = (D[b] == 0) */ | |
6675 | tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0); | |
6676 | tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); | |
6677 | /* sv */ | |
6678 | tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); | |
6679 | /* reset av */ | |
6680 | tcg_gen_movi_tl(cpu_PSW_AV, 0); | |
6681 | /* write result */ | |
6682 | tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); | |
6683 | /* zero extend to high reg*/ | |
6684 | tcg_gen_movi_tl(cpu_gpr_d[r3+1], 0); | |
6685 | break; | |
6686 | case OPC2_32_RR_PARITY: | |
6687 | gen_helper_parity(cpu_gpr_d[r3], cpu_gpr_d[r1]); | |
6688 | break; | |
6689 | case OPC2_32_RR_UNPACK: | |
828066c7 | 6690 | CHECK_REG_PAIR(r3); |
e2bed107 BK |
6691 | gen_unpack(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]); |
6692 | break; | |
e5c96c82 | 6693 | case OPC2_32_RR_CRC32: |
44ee3baf | 6694 | if (has_feature(ctx, TRICORE_FEATURE_161)) { |
e5c96c82 | 6695 | gen_helper_crc32(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); |
f678f671 BK |
6696 | } else { |
6697 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
6698 | } | |
e5c96c82 | 6699 | break; |
93715571 | 6700 | case OPC2_32_RR_DIV: |
44ee3baf | 6701 | if (has_feature(ctx, TRICORE_FEATURE_16)) { |
93715571 BK |
6702 | GEN_HELPER_RR(divide, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], |
6703 | cpu_gpr_d[r2]); | |
f678f671 BK |
6704 | } else { |
6705 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
6706 | } | |
93715571 BK |
6707 | break; |
6708 | case OPC2_32_RR_DIV_U: | |
44ee3baf | 6709 | if (has_feature(ctx, TRICORE_FEATURE_16)) { |
93715571 BK |
6710 | GEN_HELPER_RR(divide_u, cpu_gpr_d[r3], cpu_gpr_d[r3+1], |
6711 | cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
f678f671 BK |
6712 | } else { |
6713 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
6714 | } | |
93715571 | 6715 | break; |
daab3f7f BK |
6716 | case OPC2_32_RR_MUL_F: |
6717 | gen_helper_fmul(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6718 | break; | |
446ee5b2 BK |
6719 | case OPC2_32_RR_DIV_F: |
6720 | gen_helper_fdiv(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6721 | break; | |
743cd09d BK |
6722 | case OPC2_32_RR_CMP_F: |
6723 | gen_helper_fcmp(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6724 | break; | |
0d4c3b80 BK |
6725 | case OPC2_32_RR_FTOI: |
6726 | gen_helper_ftoi(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); | |
6727 | break; | |
6728 | case OPC2_32_RR_ITOF: | |
6729 | gen_helper_itof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); | |
6730 | break; | |
8f75983d BK |
6731 | case OPC2_32_RR_FTOUZ: |
6732 | gen_helper_ftouz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); | |
6733 | break; | |
50788a3f BK |
6734 | case OPC2_32_RR_UPDFL: |
6735 | gen_helper_updfl(cpu_env, cpu_gpr_d[r1]); | |
6736 | break; | |
4e6fd2e3 DB |
6737 | case OPC2_32_RR_UTOF: |
6738 | gen_helper_utof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); | |
6739 | break; | |
1fa79fb0 DB |
6740 | case OPC2_32_RR_FTOIZ: |
6741 | gen_helper_ftoiz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); | |
6742 | break; | |
8317ea06 AK |
6743 | case OPC2_32_RR_QSEED_F: |
6744 | gen_helper_qseed(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); | |
6745 | break; | |
f678f671 BK |
6746 | default: |
6747 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
e2bed107 BK |
6748 | } |
6749 | } | |
6750 | ||
9655b932 | 6751 | /* RR1 Format */ |
2db92a0c | 6752 | static void decode_rr1_mul(DisasContext *ctx) |
9655b932 BK |
6753 | { |
6754 | uint32_t op2; | |
6755 | ||
6756 | int r1, r2, r3; | |
6757 | TCGv n; | |
6758 | TCGv_i64 temp64; | |
6759 | ||
6760 | r1 = MASK_OP_RR1_S1(ctx->opcode); | |
6761 | r2 = MASK_OP_RR1_S2(ctx->opcode); | |
6762 | r3 = MASK_OP_RR1_D(ctx->opcode); | |
6763 | n = tcg_const_i32(MASK_OP_RR1_N(ctx->opcode)); | |
6764 | op2 = MASK_OP_RR1_OP2(ctx->opcode); | |
6765 | ||
6766 | switch (op2) { | |
6767 | case OPC2_32_RR1_MUL_H_32_LL: | |
6768 | temp64 = tcg_temp_new_i64(); | |
828066c7 | 6769 | CHECK_REG_PAIR(r3); |
9655b932 BK |
6770 | GEN_HELPER_LL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); |
6771 | tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); | |
6772 | gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); | |
6773 | tcg_temp_free_i64(temp64); | |
6774 | break; | |
6775 | case OPC2_32_RR1_MUL_H_32_LU: | |
6776 | temp64 = tcg_temp_new_i64(); | |
828066c7 | 6777 | CHECK_REG_PAIR(r3); |
9655b932 BK |
6778 | GEN_HELPER_LU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); |
6779 | tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); | |
6780 | gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); | |
6781 | tcg_temp_free_i64(temp64); | |
6782 | break; | |
6783 | case OPC2_32_RR1_MUL_H_32_UL: | |
6784 | temp64 = tcg_temp_new_i64(); | |
828066c7 | 6785 | CHECK_REG_PAIR(r3); |
9655b932 BK |
6786 | GEN_HELPER_UL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); |
6787 | tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); | |
6788 | gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); | |
6789 | tcg_temp_free_i64(temp64); | |
6790 | break; | |
6791 | case OPC2_32_RR1_MUL_H_32_UU: | |
6792 | temp64 = tcg_temp_new_i64(); | |
828066c7 | 6793 | CHECK_REG_PAIR(r3); |
9655b932 BK |
6794 | GEN_HELPER_UU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); |
6795 | tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); | |
6796 | gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); | |
6797 | tcg_temp_free_i64(temp64); | |
6798 | break; | |
6799 | case OPC2_32_RR1_MULM_H_64_LL: | |
6800 | temp64 = tcg_temp_new_i64(); | |
828066c7 | 6801 | CHECK_REG_PAIR(r3); |
9655b932 BK |
6802 | GEN_HELPER_LL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); |
6803 | tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); | |
6804 | /* reset V bit */ | |
6805 | tcg_gen_movi_tl(cpu_PSW_V, 0); | |
6806 | /* reset AV bit */ | |
6807 | tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); | |
6808 | tcg_temp_free_i64(temp64); | |
6809 | break; | |
6810 | case OPC2_32_RR1_MULM_H_64_LU: | |
6811 | temp64 = tcg_temp_new_i64(); | |
828066c7 | 6812 | CHECK_REG_PAIR(r3); |
9655b932 BK |
6813 | GEN_HELPER_LU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); |
6814 | tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); | |
6815 | /* reset V bit */ | |
6816 | tcg_gen_movi_tl(cpu_PSW_V, 0); | |
6817 | /* reset AV bit */ | |
6818 | tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); | |
6819 | tcg_temp_free_i64(temp64); | |
6820 | break; | |
6821 | case OPC2_32_RR1_MULM_H_64_UL: | |
6822 | temp64 = tcg_temp_new_i64(); | |
828066c7 | 6823 | CHECK_REG_PAIR(r3); |
9655b932 BK |
6824 | GEN_HELPER_UL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); |
6825 | tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); | |
6826 | /* reset V bit */ | |
6827 | tcg_gen_movi_tl(cpu_PSW_V, 0); | |
6828 | /* reset AV bit */ | |
6829 | tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); | |
6830 | tcg_temp_free_i64(temp64); | |
6831 | break; | |
6832 | case OPC2_32_RR1_MULM_H_64_UU: | |
6833 | temp64 = tcg_temp_new_i64(); | |
828066c7 | 6834 | CHECK_REG_PAIR(r3); |
9655b932 BK |
6835 | GEN_HELPER_UU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); |
6836 | tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); | |
6837 | /* reset V bit */ | |
6838 | tcg_gen_movi_tl(cpu_PSW_V, 0); | |
6839 | /* reset AV bit */ | |
6840 | tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); | |
6841 | tcg_temp_free_i64(temp64); | |
6842 | ||
6843 | break; | |
6844 | case OPC2_32_RR1_MULR_H_16_LL: | |
6845 | GEN_HELPER_LL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); | |
6846 | gen_calc_usb_mulr_h(cpu_gpr_d[r3]); | |
6847 | break; | |
6848 | case OPC2_32_RR1_MULR_H_16_LU: | |
6849 | GEN_HELPER_LU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); | |
6850 | gen_calc_usb_mulr_h(cpu_gpr_d[r3]); | |
6851 | break; | |
6852 | case OPC2_32_RR1_MULR_H_16_UL: | |
6853 | GEN_HELPER_UL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); | |
6854 | gen_calc_usb_mulr_h(cpu_gpr_d[r3]); | |
6855 | break; | |
6856 | case OPC2_32_RR1_MULR_H_16_UU: | |
6857 | GEN_HELPER_UU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); | |
6858 | gen_calc_usb_mulr_h(cpu_gpr_d[r3]); | |
6859 | break; | |
f678f671 BK |
6860 | default: |
6861 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
9655b932 BK |
6862 | } |
6863 | tcg_temp_free(n); | |
6864 | } | |
6865 | ||
2db92a0c | 6866 | static void decode_rr1_mulq(DisasContext *ctx) |
f1cc6eaf BK |
6867 | { |
6868 | uint32_t op2; | |
6869 | int r1, r2, r3; | |
6870 | uint32_t n; | |
6871 | ||
6872 | TCGv temp, temp2; | |
6873 | ||
6874 | r1 = MASK_OP_RR1_S1(ctx->opcode); | |
6875 | r2 = MASK_OP_RR1_S2(ctx->opcode); | |
6876 | r3 = MASK_OP_RR1_D(ctx->opcode); | |
6877 | n = MASK_OP_RR1_N(ctx->opcode); | |
6878 | op2 = MASK_OP_RR1_OP2(ctx->opcode); | |
6879 | ||
6880 | temp = tcg_temp_new(); | |
6881 | temp2 = tcg_temp_new(); | |
6882 | ||
6883 | switch (op2) { | |
6884 | case OPC2_32_RR1_MUL_Q_32: | |
6885 | gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], cpu_gpr_d[r2], n, 32); | |
6886 | break; | |
6887 | case OPC2_32_RR1_MUL_Q_64: | |
828066c7 | 6888 | CHECK_REG_PAIR(r3); |
f1cc6eaf BK |
6889 | gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], |
6890 | n, 0); | |
6891 | break; | |
6892 | case OPC2_32_RR1_MUL_Q_32_L: | |
6893 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); | |
6894 | gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16); | |
6895 | break; | |
6896 | case OPC2_32_RR1_MUL_Q_64_L: | |
828066c7 | 6897 | CHECK_REG_PAIR(r3); |
f1cc6eaf BK |
6898 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); |
6899 | gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0); | |
6900 | break; | |
6901 | case OPC2_32_RR1_MUL_Q_32_U: | |
6902 | tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); | |
6903 | gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16); | |
6904 | break; | |
6905 | case OPC2_32_RR1_MUL_Q_64_U: | |
828066c7 | 6906 | CHECK_REG_PAIR(r3); |
f1cc6eaf BK |
6907 | tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); |
6908 | gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0); | |
6909 | break; | |
6910 | case OPC2_32_RR1_MUL_Q_32_LL: | |
6911 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); | |
6912 | tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); | |
6913 | gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n); | |
6914 | break; | |
6915 | case OPC2_32_RR1_MUL_Q_32_UU: | |
6916 | tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); | |
6917 | tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); | |
6918 | gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n); | |
6919 | break; | |
6920 | case OPC2_32_RR1_MULR_Q_32_L: | |
6921 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); | |
6922 | tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); | |
6923 | gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n); | |
6924 | break; | |
6925 | case OPC2_32_RR1_MULR_Q_32_U: | |
6926 | tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); | |
6927 | tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); | |
6928 | gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n); | |
6929 | break; | |
f678f671 BK |
6930 | default: |
6931 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
f1cc6eaf BK |
6932 | } |
6933 | tcg_temp_free(temp); | |
6934 | tcg_temp_free(temp2); | |
6935 | } | |
6936 | ||
12f323e6 | 6937 | /* RR2 format */ |
2db92a0c | 6938 | static void decode_rr2_mul(DisasContext *ctx) |
12f323e6 BK |
6939 | { |
6940 | uint32_t op2; | |
6941 | int r1, r2, r3; | |
6942 | ||
6943 | op2 = MASK_OP_RR2_OP2(ctx->opcode); | |
6944 | r1 = MASK_OP_RR2_S1(ctx->opcode); | |
6945 | r2 = MASK_OP_RR2_S2(ctx->opcode); | |
6946 | r3 = MASK_OP_RR2_D(ctx->opcode); | |
6947 | switch (op2) { | |
6948 | case OPC2_32_RR2_MUL_32: | |
6949 | gen_mul_i32s(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
6950 | break; | |
6951 | case OPC2_32_RR2_MUL_64: | |
828066c7 | 6952 | CHECK_REG_PAIR(r3); |
12f323e6 BK |
6953 | gen_mul_i64s(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], |
6954 | cpu_gpr_d[r2]); | |
6955 | break; | |
6956 | case OPC2_32_RR2_MULS_32: | |
6957 | gen_helper_mul_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], | |
6958 | cpu_gpr_d[r2]); | |
6959 | break; | |
6960 | case OPC2_32_RR2_MUL_U_64: | |
828066c7 | 6961 | CHECK_REG_PAIR(r3); |
12f323e6 BK |
6962 | gen_mul_i64u(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], |
6963 | cpu_gpr_d[r2]); | |
6964 | break; | |
6965 | case OPC2_32_RR2_MULS_U_32: | |
6966 | gen_helper_mul_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], | |
6967 | cpu_gpr_d[r2]); | |
6968 | break; | |
f678f671 BK |
6969 | default: |
6970 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
12f323e6 BK |
6971 | } |
6972 | } | |
6973 | ||
8fb9d0eb | 6974 | /* RRPW format */ |
2db92a0c | 6975 | static void decode_rrpw_extract_insert(DisasContext *ctx) |
8fb9d0eb BK |
6976 | { |
6977 | uint32_t op2; | |
6978 | int r1, r2, r3; | |
6979 | int32_t pos, width; | |
00747984 | 6980 | TCGv temp; |
8fb9d0eb BK |
6981 | |
6982 | op2 = MASK_OP_RRPW_OP2(ctx->opcode); | |
6983 | r1 = MASK_OP_RRPW_S1(ctx->opcode); | |
6984 | r2 = MASK_OP_RRPW_S2(ctx->opcode); | |
6985 | r3 = MASK_OP_RRPW_D(ctx->opcode); | |
6986 | pos = MASK_OP_RRPW_POS(ctx->opcode); | |
6987 | width = MASK_OP_RRPW_WIDTH(ctx->opcode); | |
6988 | ||
6989 | switch (op2) { | |
6990 | case OPC2_32_RRPW_EXTR: | |
a21993c7 BK |
6991 | if (width == 0) { |
6992 | tcg_gen_movi_tl(cpu_gpr_d[r3], 0); | |
6993 | break; | |
6994 | } | |
6995 | ||
9b620609 | 6996 | if (pos + width <= 32) { |
8fb9d0eb BK |
6997 | /* optimize special cases */ |
6998 | if ((pos == 0) && (width == 8)) { | |
6999 | tcg_gen_ext8s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); | |
7000 | } else if ((pos == 0) && (width == 16)) { | |
7001 | tcg_gen_ext16s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); | |
7002 | } else { | |
7003 | tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 32 - pos - width); | |
7004 | tcg_gen_sari_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 32 - width); | |
7005 | } | |
7006 | } | |
7007 | break; | |
7008 | case OPC2_32_RRPW_EXTR_U: | |
7009 | if (width == 0) { | |
7010 | tcg_gen_movi_tl(cpu_gpr_d[r3], 0); | |
7011 | } else { | |
7012 | tcg_gen_shri_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], pos); | |
7013 | tcg_gen_andi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], ~0u >> (32-width)); | |
7014 | } | |
7015 | break; | |
7016 | case OPC2_32_RRPW_IMASK: | |
828066c7 | 7017 | CHECK_REG_PAIR(r3); |
00747984 | 7018 | |
9b620609 | 7019 | if (pos + width <= 32) { |
00747984 BK |
7020 | temp = tcg_temp_new(); |
7021 | tcg_gen_movi_tl(temp, ((1u << width) - 1) << pos); | |
8fb9d0eb | 7022 | tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], pos); |
00747984 BK |
7023 | tcg_gen_mov_tl(cpu_gpr_d[r3 + 1], temp); |
7024 | tcg_temp_free(temp); | |
8fb9d0eb | 7025 | } |
00747984 | 7026 | |
8fb9d0eb BK |
7027 | break; |
7028 | case OPC2_32_RRPW_INSERT: | |
61b26250 | 7029 | if (pos + width <= 32) { |
8fb9d0eb | 7030 | tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], |
61b26250 | 7031 | pos, width); |
8fb9d0eb BK |
7032 | } |
7033 | break; | |
f678f671 BK |
7034 | default: |
7035 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
8fb9d0eb BK |
7036 | } |
7037 | } | |
7038 | ||
09532255 | 7039 | /* RRR format */ |
2db92a0c | 7040 | static void decode_rrr_cond_select(DisasContext *ctx) |
09532255 BK |
7041 | { |
7042 | uint32_t op2; | |
7043 | int r1, r2, r3, r4; | |
7044 | TCGv temp; | |
7045 | ||
7046 | op2 = MASK_OP_RRR_OP2(ctx->opcode); | |
7047 | r1 = MASK_OP_RRR_S1(ctx->opcode); | |
7048 | r2 = MASK_OP_RRR_S2(ctx->opcode); | |
7049 | r3 = MASK_OP_RRR_S3(ctx->opcode); | |
7050 | r4 = MASK_OP_RRR_D(ctx->opcode); | |
7051 | ||
7052 | switch (op2) { | |
7053 | case OPC2_32_RRR_CADD: | |
7054 | gen_cond_add(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], | |
7055 | cpu_gpr_d[r4], cpu_gpr_d[r3]); | |
7056 | break; | |
7057 | case OPC2_32_RRR_CADDN: | |
7058 | gen_cond_add(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4], | |
7059 | cpu_gpr_d[r3]); | |
7060 | break; | |
7061 | case OPC2_32_RRR_CSUB: | |
7062 | gen_cond_sub(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4], | |
7063 | cpu_gpr_d[r3]); | |
7064 | break; | |
7065 | case OPC2_32_RRR_CSUBN: | |
7066 | gen_cond_sub(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4], | |
7067 | cpu_gpr_d[r3]); | |
7068 | break; | |
7069 | case OPC2_32_RRR_SEL: | |
7070 | temp = tcg_const_i32(0); | |
7071 | tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, | |
7072 | cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
7073 | tcg_temp_free(temp); | |
7074 | break; | |
7075 | case OPC2_32_RRR_SELN: | |
7076 | temp = tcg_const_i32(0); | |
7077 | tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, | |
7078 | cpu_gpr_d[r1], cpu_gpr_d[r2]); | |
7079 | tcg_temp_free(temp); | |
7080 | break; | |
f678f671 BK |
7081 | default: |
7082 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
09532255 BK |
7083 | } |
7084 | } | |
7085 | ||
2db92a0c | 7086 | static void decode_rrr_divide(DisasContext *ctx) |
09532255 BK |
7087 | { |
7088 | uint32_t op2; | |
7089 | ||
7090 | int r1, r2, r3, r4; | |
7091 | ||
7092 | op2 = MASK_OP_RRR_OP2(ctx->opcode); | |
7093 | r1 = MASK_OP_RRR_S1(ctx->opcode); | |
7094 | r2 = MASK_OP_RRR_S2(ctx->opcode); | |
7095 | r3 = MASK_OP_RRR_S3(ctx->opcode); | |
7096 | r4 = MASK_OP_RRR_D(ctx->opcode); | |
7097 | ||
7098 | switch (op2) { | |
7099 | case OPC2_32_RRR_DVADJ: | |
c433a171 | 7100 | CHECK_REG_PAIR(r3); |
828066c7 | 7101 | CHECK_REG_PAIR(r4); |
09532255 BK |
7102 | GEN_HELPER_RRR(dvadj, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7103 | cpu_gpr_d[r3+1], cpu_gpr_d[r2]); | |
7104 | break; | |
7105 | case OPC2_32_RRR_DVSTEP: | |
c433a171 | 7106 | CHECK_REG_PAIR(r3); |
828066c7 | 7107 | CHECK_REG_PAIR(r4); |
09532255 BK |
7108 | GEN_HELPER_RRR(dvstep, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7109 | cpu_gpr_d[r3+1], cpu_gpr_d[r2]); | |
7110 | break; | |
7111 | case OPC2_32_RRR_DVSTEP_U: | |
c433a171 | 7112 | CHECK_REG_PAIR(r3); |
828066c7 | 7113 | CHECK_REG_PAIR(r4); |
09532255 BK |
7114 | GEN_HELPER_RRR(dvstep_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7115 | cpu_gpr_d[r3+1], cpu_gpr_d[r2]); | |
7116 | break; | |
7117 | case OPC2_32_RRR_IXMAX: | |
c433a171 | 7118 | CHECK_REG_PAIR(r3); |
828066c7 | 7119 | CHECK_REG_PAIR(r4); |
09532255 BK |
7120 | GEN_HELPER_RRR(ixmax, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7121 | cpu_gpr_d[r3+1], cpu_gpr_d[r2]); | |
7122 | break; | |
7123 | case OPC2_32_RRR_IXMAX_U: | |
c433a171 | 7124 | CHECK_REG_PAIR(r3); |
828066c7 | 7125 | CHECK_REG_PAIR(r4); |
09532255 BK |
7126 | GEN_HELPER_RRR(ixmax_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7127 | cpu_gpr_d[r3+1], cpu_gpr_d[r2]); | |
7128 | break; | |
7129 | case OPC2_32_RRR_IXMIN: | |
c433a171 | 7130 | CHECK_REG_PAIR(r3); |
828066c7 | 7131 | CHECK_REG_PAIR(r4); |
09532255 BK |
7132 | GEN_HELPER_RRR(ixmin, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7133 | cpu_gpr_d[r3+1], cpu_gpr_d[r2]); | |
7134 | break; | |
7135 | case OPC2_32_RRR_IXMIN_U: | |
c433a171 | 7136 | CHECK_REG_PAIR(r3); |
828066c7 | 7137 | CHECK_REG_PAIR(r4); |
09532255 BK |
7138 | GEN_HELPER_RRR(ixmin_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7139 | cpu_gpr_d[r3+1], cpu_gpr_d[r2]); | |
7140 | break; | |
7141 | case OPC2_32_RRR_PACK: | |
c433a171 | 7142 | CHECK_REG_PAIR(r3); |
09532255 BK |
7143 | gen_helper_pack(cpu_gpr_d[r4], cpu_PSW_C, cpu_gpr_d[r3], |
7144 | cpu_gpr_d[r3+1], cpu_gpr_d[r1]); | |
7145 | break; | |
baf410dc BK |
7146 | case OPC2_32_RRR_ADD_F: |
7147 | gen_helper_fadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]); | |
7148 | break; | |
7149 | case OPC2_32_RRR_SUB_F: | |
7150 | gen_helper_fsub(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]); | |
7151 | break; | |
ddd7fead BK |
7152 | case OPC2_32_RRR_MADD_F: |
7153 | gen_helper_fmadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], | |
7154 | cpu_gpr_d[r2], cpu_gpr_d[r3]); | |
7155 | break; | |
7156 | case OPC2_32_RRR_MSUB_F: | |
7157 | gen_helper_fmsub(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], | |
7158 | cpu_gpr_d[r2], cpu_gpr_d[r3]); | |
7159 | break; | |
f678f671 BK |
7160 | default: |
7161 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
09532255 BK |
7162 | } |
7163 | } | |
7164 | ||
2984cfbd | 7165 | /* RRR2 format */ |
2db92a0c | 7166 | static void decode_rrr2_madd(DisasContext *ctx) |
2984cfbd BK |
7167 | { |
7168 | uint32_t op2; | |
7169 | uint32_t r1, r2, r3, r4; | |
7170 | ||
7171 | op2 = MASK_OP_RRR2_OP2(ctx->opcode); | |
7172 | r1 = MASK_OP_RRR2_S1(ctx->opcode); | |
7173 | r2 = MASK_OP_RRR2_S2(ctx->opcode); | |
7174 | r3 = MASK_OP_RRR2_S3(ctx->opcode); | |
7175 | r4 = MASK_OP_RRR2_D(ctx->opcode); | |
7176 | switch (op2) { | |
7177 | case OPC2_32_RRR2_MADD_32: | |
7178 | gen_madd32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], | |
7179 | cpu_gpr_d[r2]); | |
7180 | break; | |
7181 | case OPC2_32_RRR2_MADD_64: | |
828066c7 BK |
7182 | CHECK_REG_PAIR(r4); |
7183 | CHECK_REG_PAIR(r3); | |
2984cfbd BK |
7184 | gen_madd64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], |
7185 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); | |
7186 | break; | |
7187 | case OPC2_32_RRR2_MADDS_32: | |
7188 | gen_helper_madd32_ssov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], | |
7189 | cpu_gpr_d[r3], cpu_gpr_d[r2]); | |
7190 | break; | |
7191 | case OPC2_32_RRR2_MADDS_64: | |
828066c7 BK |
7192 | CHECK_REG_PAIR(r4); |
7193 | CHECK_REG_PAIR(r3); | |
2984cfbd BK |
7194 | gen_madds_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], |
7195 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); | |
7196 | break; | |
7197 | case OPC2_32_RRR2_MADD_U_64: | |
828066c7 BK |
7198 | CHECK_REG_PAIR(r4); |
7199 | CHECK_REG_PAIR(r3); | |
2984cfbd BK |
7200 | gen_maddu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], |
7201 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); | |
7202 | break; | |
7203 | case OPC2_32_RRR2_MADDS_U_32: | |
7204 | gen_helper_madd32_suov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], | |
7205 | cpu_gpr_d[r3], cpu_gpr_d[r2]); | |
7206 | break; | |
7207 | case OPC2_32_RRR2_MADDS_U_64: | |
828066c7 BK |
7208 | CHECK_REG_PAIR(r4); |
7209 | CHECK_REG_PAIR(r3); | |
2984cfbd BK |
7210 | gen_maddsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], |
7211 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); | |
7212 | break; | |
f678f671 BK |
7213 | default: |
7214 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
2984cfbd BK |
7215 | } |
7216 | } | |
7217 | ||
2db92a0c | 7218 | static void decode_rrr2_msub(DisasContext *ctx) |
2984cfbd BK |
7219 | { |
7220 | uint32_t op2; | |
7221 | uint32_t r1, r2, r3, r4; | |
7222 | ||
7223 | op2 = MASK_OP_RRR2_OP2(ctx->opcode); | |
7224 | r1 = MASK_OP_RRR2_S1(ctx->opcode); | |
7225 | r2 = MASK_OP_RRR2_S2(ctx->opcode); | |
7226 | r3 = MASK_OP_RRR2_S3(ctx->opcode); | |
7227 | r4 = MASK_OP_RRR2_D(ctx->opcode); | |
7228 | ||
7229 | switch (op2) { | |
7230 | case OPC2_32_RRR2_MSUB_32: | |
7231 | gen_msub32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], | |
7232 | cpu_gpr_d[r2]); | |
7233 | break; | |
7234 | case OPC2_32_RRR2_MSUB_64: | |
828066c7 BK |
7235 | CHECK_REG_PAIR(r4); |
7236 | CHECK_REG_PAIR(r3); | |
2984cfbd BK |
7237 | gen_msub64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], |
7238 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); | |
7239 | break; | |
7240 | case OPC2_32_RRR2_MSUBS_32: | |
7241 | gen_helper_msub32_ssov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], | |
7242 | cpu_gpr_d[r3], cpu_gpr_d[r2]); | |
7243 | break; | |
7244 | case OPC2_32_RRR2_MSUBS_64: | |
828066c7 BK |
7245 | CHECK_REG_PAIR(r4); |
7246 | CHECK_REG_PAIR(r3); | |
2984cfbd BK |
7247 | gen_msubs_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], |
7248 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); | |
7249 | break; | |
7250 | case OPC2_32_RRR2_MSUB_U_64: | |
7251 | gen_msubu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], | |
7252 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); | |
7253 | break; | |
7254 | case OPC2_32_RRR2_MSUBS_U_32: | |
7255 | gen_helper_msub32_suov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], | |
7256 | cpu_gpr_d[r3], cpu_gpr_d[r2]); | |
7257 | break; | |
7258 | case OPC2_32_RRR2_MSUBS_U_64: | |
828066c7 BK |
7259 | CHECK_REG_PAIR(r4); |
7260 | CHECK_REG_PAIR(r3); | |
2984cfbd BK |
7261 | gen_msubsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], |
7262 | cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); | |
7263 | break; | |
f678f671 BK |
7264 | default: |
7265 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
2984cfbd BK |
7266 | } |
7267 | } | |
7268 | ||
2e430e1c | 7269 | /* RRR1 format */ |
2db92a0c | 7270 | static void decode_rrr1_madd(DisasContext *ctx) |
2e430e1c BK |
7271 | { |
7272 | uint32_t op2; | |
7273 | uint32_t r1, r2, r3, r4, n; | |
7274 | ||
7275 | op2 = MASK_OP_RRR1_OP2(ctx->opcode); | |
7276 | r1 = MASK_OP_RRR1_S1(ctx->opcode); | |
7277 | r2 = MASK_OP_RRR1_S2(ctx->opcode); | |
7278 | r3 = MASK_OP_RRR1_S3(ctx->opcode); | |
7279 | r4 = MASK_OP_RRR1_D(ctx->opcode); | |
7280 | n = MASK_OP_RRR1_N(ctx->opcode); | |
7281 | ||
7282 | switch (op2) { | |
7283 | case OPC2_32_RRR1_MADD_H_LL: | |
828066c7 BK |
7284 | CHECK_REG_PAIR(r4); |
7285 | CHECK_REG_PAIR(r3); | |
2e430e1c BK |
7286 | gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7287 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); | |
7288 | break; | |
7289 | case OPC2_32_RRR1_MADD_H_LU: | |
828066c7 BK |
7290 | CHECK_REG_PAIR(r4); |
7291 | CHECK_REG_PAIR(r3); | |
2e430e1c BK |
7292 | gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7293 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); | |
7294 | break; | |
7295 | case OPC2_32_RRR1_MADD_H_UL: | |
828066c7 BK |
7296 | CHECK_REG_PAIR(r4); |
7297 | CHECK_REG_PAIR(r3); | |
2e430e1c BK |
7298 | gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7299 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); | |
7300 | break; | |
7301 | case OPC2_32_RRR1_MADD_H_UU: | |
828066c7 BK |
7302 | CHECK_REG_PAIR(r4); |
7303 | CHECK_REG_PAIR(r3); | |
2e430e1c BK |
7304 | gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7305 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); | |
7306 | break; | |
7307 | case OPC2_32_RRR1_MADDS_H_LL: | |
828066c7 BK |
7308 | CHECK_REG_PAIR(r4); |
7309 | CHECK_REG_PAIR(r3); | |
2e430e1c BK |
7310 | gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7311 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); | |
7312 | break; | |
7313 | case OPC2_32_RRR1_MADDS_H_LU: | |
828066c7 BK |
7314 | CHECK_REG_PAIR(r4); |
7315 | CHECK_REG_PAIR(r3); | |
2e430e1c BK |
7316 | gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7317 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); | |
7318 | break; | |
7319 | case OPC2_32_RRR1_MADDS_H_UL: | |
828066c7 BK |
7320 | CHECK_REG_PAIR(r4); |
7321 | CHECK_REG_PAIR(r3); | |
2e430e1c BK |
7322 | gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7323 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); | |
7324 | break; | |
7325 | case OPC2_32_RRR1_MADDS_H_UU: | |
828066c7 BK |
7326 | CHECK_REG_PAIR(r4); |
7327 | CHECK_REG_PAIR(r3); | |
2e430e1c BK |
7328 | gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7329 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); | |
7330 | break; | |
7331 | case OPC2_32_RRR1_MADDM_H_LL: | |
828066c7 BK |
7332 | CHECK_REG_PAIR(r4); |
7333 | CHECK_REG_PAIR(r3); | |
2e430e1c BK |
7334 | gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7335 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); | |
7336 | break; | |
7337 | case OPC2_32_RRR1_MADDM_H_LU: | |
828066c7 BK |
7338 | CHECK_REG_PAIR(r4); |
7339 | CHECK_REG_PAIR(r3); | |
2e430e1c BK |
7340 | gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7341 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); | |
7342 | break; | |
7343 | case OPC2_32_RRR1_MADDM_H_UL: | |
828066c7 BK |
7344 | CHECK_REG_PAIR(r4); |
7345 | CHECK_REG_PAIR(r3); | |
2e430e1c BK |
7346 | gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7347 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); | |
7348 | break; | |
7349 | case OPC2_32_RRR1_MADDM_H_UU: | |
828066c7 BK |
7350 | CHECK_REG_PAIR(r4); |
7351 | CHECK_REG_PAIR(r3); | |
2e430e1c BK |
7352 | gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7353 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); | |
7354 | break; | |
7355 | case OPC2_32_RRR1_MADDMS_H_LL: | |
828066c7 BK |
7356 | CHECK_REG_PAIR(r4); |
7357 | CHECK_REG_PAIR(r3); | |
2e430e1c BK |
7358 | gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7359 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); | |
7360 | break; | |
7361 | case OPC2_32_RRR1_MADDMS_H_LU: | |
828066c7 BK |
7362 | CHECK_REG_PAIR(r4); |
7363 | CHECK_REG_PAIR(r3); | |
2e430e1c BK |
7364 | gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7365 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); | |
7366 | break; | |
7367 | case OPC2_32_RRR1_MADDMS_H_UL: | |
828066c7 BK |
7368 | CHECK_REG_PAIR(r4); |
7369 | CHECK_REG_PAIR(r3); | |
2e430e1c BK |
7370 | gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7371 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); | |
7372 | break; | |
7373 | case OPC2_32_RRR1_MADDMS_H_UU: | |
828066c7 BK |
7374 | CHECK_REG_PAIR(r4); |
7375 | CHECK_REG_PAIR(r3); | |
2e430e1c BK |
7376 | gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7377 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); | |
7378 | break; | |
7379 | case OPC2_32_RRR1_MADDR_H_LL: | |
7380 | gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7381 | cpu_gpr_d[r2], n, MODE_LL); | |
7382 | break; | |
7383 | case OPC2_32_RRR1_MADDR_H_LU: | |
7384 | gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7385 | cpu_gpr_d[r2], n, MODE_LU); | |
7386 | break; | |
7387 | case OPC2_32_RRR1_MADDR_H_UL: | |
7388 | gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7389 | cpu_gpr_d[r2], n, MODE_UL); | |
7390 | break; | |
7391 | case OPC2_32_RRR1_MADDR_H_UU: | |
7392 | gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7393 | cpu_gpr_d[r2], n, MODE_UU); | |
7394 | break; | |
7395 | case OPC2_32_RRR1_MADDRS_H_LL: | |
7396 | gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7397 | cpu_gpr_d[r2], n, MODE_LL); | |
7398 | break; | |
7399 | case OPC2_32_RRR1_MADDRS_H_LU: | |
7400 | gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7401 | cpu_gpr_d[r2], n, MODE_LU); | |
7402 | break; | |
7403 | case OPC2_32_RRR1_MADDRS_H_UL: | |
7404 | gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7405 | cpu_gpr_d[r2], n, MODE_UL); | |
7406 | break; | |
7407 | case OPC2_32_RRR1_MADDRS_H_UU: | |
7408 | gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7409 | cpu_gpr_d[r2], n, MODE_UU); | |
7410 | break; | |
f678f671 BK |
7411 | default: |
7412 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
2e430e1c BK |
7413 | } |
7414 | } | |
7415 | ||
2db92a0c | 7416 | static void decode_rrr1_maddq_h(DisasContext *ctx) |
b00aa8ec BK |
7417 | { |
7418 | uint32_t op2; | |
7419 | uint32_t r1, r2, r3, r4, n; | |
7420 | TCGv temp, temp2; | |
7421 | ||
7422 | op2 = MASK_OP_RRR1_OP2(ctx->opcode); | |
7423 | r1 = MASK_OP_RRR1_S1(ctx->opcode); | |
7424 | r2 = MASK_OP_RRR1_S2(ctx->opcode); | |
7425 | r3 = MASK_OP_RRR1_S3(ctx->opcode); | |
7426 | r4 = MASK_OP_RRR1_D(ctx->opcode); | |
7427 | n = MASK_OP_RRR1_N(ctx->opcode); | |
7428 | ||
7429 | temp = tcg_const_i32(n); | |
7430 | temp2 = tcg_temp_new(); | |
7431 | ||
7432 | switch (op2) { | |
7433 | case OPC2_32_RRR1_MADD_Q_32: | |
7434 | gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
2db92a0c | 7435 | cpu_gpr_d[r2], n, 32); |
b00aa8ec BK |
7436 | break; |
7437 | case OPC2_32_RRR1_MADD_Q_64: | |
828066c7 BK |
7438 | CHECK_REG_PAIR(r4); |
7439 | CHECK_REG_PAIR(r3); | |
b00aa8ec BK |
7440 | gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7441 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
2db92a0c | 7442 | n); |
b00aa8ec BK |
7443 | break; |
7444 | case OPC2_32_RRR1_MADD_Q_32_L: | |
7445 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); | |
7446 | gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
2db92a0c | 7447 | temp, n, 16); |
b00aa8ec BK |
7448 | break; |
7449 | case OPC2_32_RRR1_MADD_Q_64_L: | |
828066c7 BK |
7450 | CHECK_REG_PAIR(r4); |
7451 | CHECK_REG_PAIR(r3); | |
b00aa8ec BK |
7452 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); |
7453 | gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
7454 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, | |
2db92a0c | 7455 | n); |
b00aa8ec BK |
7456 | break; |
7457 | case OPC2_32_RRR1_MADD_Q_32_U: | |
7458 | tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); | |
7459 | gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
2db92a0c | 7460 | temp, n, 16); |
b00aa8ec BK |
7461 | break; |
7462 | case OPC2_32_RRR1_MADD_Q_64_U: | |
828066c7 BK |
7463 | CHECK_REG_PAIR(r4); |
7464 | CHECK_REG_PAIR(r3); | |
b00aa8ec BK |
7465 | tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); |
7466 | gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
7467 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, | |
2db92a0c | 7468 | n); |
b00aa8ec BK |
7469 | break; |
7470 | case OPC2_32_RRR1_MADD_Q_32_LL: | |
7471 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); | |
7472 | tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); | |
7473 | gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); | |
7474 | break; | |
7475 | case OPC2_32_RRR1_MADD_Q_64_LL: | |
828066c7 BK |
7476 | CHECK_REG_PAIR(r4); |
7477 | CHECK_REG_PAIR(r3); | |
b00aa8ec BK |
7478 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); |
7479 | tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); | |
7480 | gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
7481 | cpu_gpr_d[r3+1], temp, temp2, n); | |
7482 | break; | |
7483 | case OPC2_32_RRR1_MADD_Q_32_UU: | |
7484 | tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); | |
7485 | tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); | |
7486 | gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); | |
7487 | break; | |
7488 | case OPC2_32_RRR1_MADD_Q_64_UU: | |
828066c7 BK |
7489 | CHECK_REG_PAIR(r4); |
7490 | CHECK_REG_PAIR(r3); | |
b00aa8ec BK |
7491 | tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); |
7492 | tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); | |
7493 | gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
7494 | cpu_gpr_d[r3+1], temp, temp2, n); | |
7495 | break; | |
7496 | case OPC2_32_RRR1_MADDS_Q_32: | |
7497 | gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7498 | cpu_gpr_d[r2], n, 32); | |
7499 | break; | |
7500 | case OPC2_32_RRR1_MADDS_Q_64: | |
828066c7 BK |
7501 | CHECK_REG_PAIR(r4); |
7502 | CHECK_REG_PAIR(r3); | |
b00aa8ec BK |
7503 | gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7504 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
7505 | n); | |
7506 | break; | |
7507 | case OPC2_32_RRR1_MADDS_Q_32_L: | |
7508 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); | |
7509 | gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7510 | temp, n, 16); | |
7511 | break; | |
7512 | case OPC2_32_RRR1_MADDS_Q_64_L: | |
828066c7 BK |
7513 | CHECK_REG_PAIR(r4); |
7514 | CHECK_REG_PAIR(r3); | |
b00aa8ec BK |
7515 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); |
7516 | gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
7517 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, | |
7518 | n); | |
7519 | break; | |
7520 | case OPC2_32_RRR1_MADDS_Q_32_U: | |
7521 | tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); | |
7522 | gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7523 | temp, n, 16); | |
7524 | break; | |
7525 | case OPC2_32_RRR1_MADDS_Q_64_U: | |
828066c7 BK |
7526 | CHECK_REG_PAIR(r4); |
7527 | CHECK_REG_PAIR(r3); | |
b00aa8ec BK |
7528 | tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); |
7529 | gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
7530 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, | |
7531 | n); | |
7532 | break; | |
7533 | case OPC2_32_RRR1_MADDS_Q_32_LL: | |
7534 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); | |
7535 | tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); | |
7536 | gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); | |
7537 | break; | |
7538 | case OPC2_32_RRR1_MADDS_Q_64_LL: | |
828066c7 BK |
7539 | CHECK_REG_PAIR(r4); |
7540 | CHECK_REG_PAIR(r3); | |
b00aa8ec BK |
7541 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); |
7542 | tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); | |
7543 | gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
7544 | cpu_gpr_d[r3+1], temp, temp2, n); | |
7545 | break; | |
7546 | case OPC2_32_RRR1_MADDS_Q_32_UU: | |
7547 | tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); | |
7548 | tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); | |
7549 | gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); | |
7550 | break; | |
7551 | case OPC2_32_RRR1_MADDS_Q_64_UU: | |
828066c7 BK |
7552 | CHECK_REG_PAIR(r4); |
7553 | CHECK_REG_PAIR(r3); | |
b00aa8ec BK |
7554 | tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); |
7555 | tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); | |
7556 | gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
7557 | cpu_gpr_d[r3+1], temp, temp2, n); | |
7558 | break; | |
7559 | case OPC2_32_RRR1_MADDR_H_64_UL: | |
828066c7 | 7560 | CHECK_REG_PAIR(r3); |
b00aa8ec BK |
7561 | gen_maddr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1], |
7562 | cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); | |
7563 | break; | |
7564 | case OPC2_32_RRR1_MADDRS_H_64_UL: | |
828066c7 | 7565 | CHECK_REG_PAIR(r3); |
b00aa8ec BK |
7566 | gen_maddr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1], |
7567 | cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); | |
7568 | break; | |
7569 | case OPC2_32_RRR1_MADDR_Q_32_LL: | |
7570 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); | |
7571 | tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); | |
7572 | gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); | |
7573 | break; | |
7574 | case OPC2_32_RRR1_MADDR_Q_32_UU: | |
7575 | tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); | |
7576 | tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); | |
7577 | gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); | |
7578 | break; | |
7579 | case OPC2_32_RRR1_MADDRS_Q_32_LL: | |
7580 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); | |
7581 | tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); | |
7582 | gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); | |
7583 | break; | |
7584 | case OPC2_32_RRR1_MADDRS_Q_32_UU: | |
7585 | tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); | |
7586 | tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); | |
7587 | gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); | |
7588 | break; | |
f678f671 BK |
7589 | default: |
7590 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
b00aa8ec BK |
7591 | } |
7592 | tcg_temp_free(temp); | |
7593 | tcg_temp_free(temp2); | |
7594 | } | |
7595 | ||
2db92a0c | 7596 | static void decode_rrr1_maddsu_h(DisasContext *ctx) |
bebe80fc BK |
7597 | { |
7598 | uint32_t op2; | |
7599 | uint32_t r1, r2, r3, r4, n; | |
7600 | ||
7601 | op2 = MASK_OP_RRR1_OP2(ctx->opcode); | |
7602 | r1 = MASK_OP_RRR1_S1(ctx->opcode); | |
7603 | r2 = MASK_OP_RRR1_S2(ctx->opcode); | |
7604 | r3 = MASK_OP_RRR1_S3(ctx->opcode); | |
7605 | r4 = MASK_OP_RRR1_D(ctx->opcode); | |
7606 | n = MASK_OP_RRR1_N(ctx->opcode); | |
7607 | ||
7608 | switch (op2) { | |
7609 | case OPC2_32_RRR1_MADDSU_H_32_LL: | |
828066c7 BK |
7610 | CHECK_REG_PAIR(r4); |
7611 | CHECK_REG_PAIR(r3); | |
bebe80fc BK |
7612 | gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7613 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); | |
7614 | break; | |
7615 | case OPC2_32_RRR1_MADDSU_H_32_LU: | |
828066c7 BK |
7616 | CHECK_REG_PAIR(r4); |
7617 | CHECK_REG_PAIR(r3); | |
bebe80fc BK |
7618 | gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7619 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); | |
7620 | break; | |
7621 | case OPC2_32_RRR1_MADDSU_H_32_UL: | |
828066c7 BK |
7622 | CHECK_REG_PAIR(r4); |
7623 | CHECK_REG_PAIR(r3); | |
bebe80fc BK |
7624 | gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7625 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); | |
7626 | break; | |
7627 | case OPC2_32_RRR1_MADDSU_H_32_UU: | |
828066c7 BK |
7628 | CHECK_REG_PAIR(r4); |
7629 | CHECK_REG_PAIR(r3); | |
bebe80fc BK |
7630 | gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7631 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); | |
7632 | break; | |
7633 | case OPC2_32_RRR1_MADDSUS_H_32_LL: | |
828066c7 BK |
7634 | CHECK_REG_PAIR(r4); |
7635 | CHECK_REG_PAIR(r3); | |
bebe80fc BK |
7636 | gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7637 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
7638 | n, MODE_LL); | |
7639 | break; | |
7640 | case OPC2_32_RRR1_MADDSUS_H_32_LU: | |
828066c7 BK |
7641 | CHECK_REG_PAIR(r4); |
7642 | CHECK_REG_PAIR(r3); | |
bebe80fc BK |
7643 | gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7644 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
7645 | n, MODE_LU); | |
7646 | break; | |
7647 | case OPC2_32_RRR1_MADDSUS_H_32_UL: | |
828066c7 BK |
7648 | CHECK_REG_PAIR(r4); |
7649 | CHECK_REG_PAIR(r3); | |
bebe80fc BK |
7650 | gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7651 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
7652 | n, MODE_UL); | |
7653 | break; | |
7654 | case OPC2_32_RRR1_MADDSUS_H_32_UU: | |
828066c7 BK |
7655 | CHECK_REG_PAIR(r4); |
7656 | CHECK_REG_PAIR(r3); | |
bebe80fc BK |
7657 | gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7658 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
7659 | n, MODE_UU); | |
7660 | break; | |
7661 | case OPC2_32_RRR1_MADDSUM_H_64_LL: | |
828066c7 BK |
7662 | CHECK_REG_PAIR(r4); |
7663 | CHECK_REG_PAIR(r3); | |
bebe80fc BK |
7664 | gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7665 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
7666 | n, MODE_LL); | |
7667 | break; | |
7668 | case OPC2_32_RRR1_MADDSUM_H_64_LU: | |
828066c7 BK |
7669 | CHECK_REG_PAIR(r4); |
7670 | CHECK_REG_PAIR(r3); | |
bebe80fc BK |
7671 | gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7672 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
7673 | n, MODE_LU); | |
7674 | break; | |
7675 | case OPC2_32_RRR1_MADDSUM_H_64_UL: | |
828066c7 BK |
7676 | CHECK_REG_PAIR(r4); |
7677 | CHECK_REG_PAIR(r3); | |
bebe80fc BK |
7678 | gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7679 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
7680 | n, MODE_UL); | |
7681 | break; | |
7682 | case OPC2_32_RRR1_MADDSUM_H_64_UU: | |
828066c7 BK |
7683 | CHECK_REG_PAIR(r4); |
7684 | CHECK_REG_PAIR(r3); | |
bebe80fc BK |
7685 | gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7686 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
7687 | n, MODE_UU); | |
7688 | break; | |
7689 | case OPC2_32_RRR1_MADDSUMS_H_64_LL: | |
828066c7 BK |
7690 | CHECK_REG_PAIR(r4); |
7691 | CHECK_REG_PAIR(r3); | |
bebe80fc BK |
7692 | gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7693 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
7694 | n, MODE_LL); | |
7695 | break; | |
7696 | case OPC2_32_RRR1_MADDSUMS_H_64_LU: | |
828066c7 BK |
7697 | CHECK_REG_PAIR(r4); |
7698 | CHECK_REG_PAIR(r3); | |
bebe80fc BK |
7699 | gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7700 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
7701 | n, MODE_LU); | |
7702 | break; | |
7703 | case OPC2_32_RRR1_MADDSUMS_H_64_UL: | |
828066c7 BK |
7704 | CHECK_REG_PAIR(r4); |
7705 | CHECK_REG_PAIR(r3); | |
bebe80fc BK |
7706 | gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7707 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
7708 | n, MODE_UL); | |
7709 | break; | |
7710 | case OPC2_32_RRR1_MADDSUMS_H_64_UU: | |
828066c7 BK |
7711 | CHECK_REG_PAIR(r4); |
7712 | CHECK_REG_PAIR(r3); | |
bebe80fc BK |
7713 | gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7714 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
7715 | n, MODE_UU); | |
7716 | break; | |
7717 | case OPC2_32_RRR1_MADDSUR_H_16_LL: | |
7718 | gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7719 | cpu_gpr_d[r2], n, MODE_LL); | |
7720 | break; | |
7721 | case OPC2_32_RRR1_MADDSUR_H_16_LU: | |
7722 | gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7723 | cpu_gpr_d[r2], n, MODE_LU); | |
7724 | break; | |
7725 | case OPC2_32_RRR1_MADDSUR_H_16_UL: | |
7726 | gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7727 | cpu_gpr_d[r2], n, MODE_UL); | |
7728 | break; | |
7729 | case OPC2_32_RRR1_MADDSUR_H_16_UU: | |
7730 | gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7731 | cpu_gpr_d[r2], n, MODE_UU); | |
7732 | break; | |
7733 | case OPC2_32_RRR1_MADDSURS_H_16_LL: | |
7734 | gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7735 | cpu_gpr_d[r2], n, MODE_LL); | |
7736 | break; | |
7737 | case OPC2_32_RRR1_MADDSURS_H_16_LU: | |
7738 | gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7739 | cpu_gpr_d[r2], n, MODE_LU); | |
7740 | break; | |
7741 | case OPC2_32_RRR1_MADDSURS_H_16_UL: | |
7742 | gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7743 | cpu_gpr_d[r2], n, MODE_UL); | |
7744 | break; | |
7745 | case OPC2_32_RRR1_MADDSURS_H_16_UU: | |
7746 | gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7747 | cpu_gpr_d[r2], n, MODE_UU); | |
7748 | break; | |
f678f671 BK |
7749 | default: |
7750 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
bebe80fc BK |
7751 | } |
7752 | } | |
7753 | ||
2db92a0c | 7754 | static void decode_rrr1_msub(DisasContext *ctx) |
f4aef476 BK |
7755 | { |
7756 | uint32_t op2; | |
7757 | uint32_t r1, r2, r3, r4, n; | |
7758 | ||
7759 | op2 = MASK_OP_RRR1_OP2(ctx->opcode); | |
7760 | r1 = MASK_OP_RRR1_S1(ctx->opcode); | |
7761 | r2 = MASK_OP_RRR1_S2(ctx->opcode); | |
7762 | r3 = MASK_OP_RRR1_S3(ctx->opcode); | |
7763 | r4 = MASK_OP_RRR1_D(ctx->opcode); | |
7764 | n = MASK_OP_RRR1_N(ctx->opcode); | |
7765 | ||
7766 | switch (op2) { | |
7767 | case OPC2_32_RRR1_MSUB_H_LL: | |
828066c7 BK |
7768 | CHECK_REG_PAIR(r4); |
7769 | CHECK_REG_PAIR(r3); | |
f4aef476 BK |
7770 | gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7771 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); | |
7772 | break; | |
7773 | case OPC2_32_RRR1_MSUB_H_LU: | |
828066c7 BK |
7774 | CHECK_REG_PAIR(r4); |
7775 | CHECK_REG_PAIR(r3); | |
f4aef476 BK |
7776 | gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7777 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); | |
7778 | break; | |
7779 | case OPC2_32_RRR1_MSUB_H_UL: | |
828066c7 BK |
7780 | CHECK_REG_PAIR(r4); |
7781 | CHECK_REG_PAIR(r3); | |
f4aef476 BK |
7782 | gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7783 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); | |
7784 | break; | |
7785 | case OPC2_32_RRR1_MSUB_H_UU: | |
828066c7 BK |
7786 | CHECK_REG_PAIR(r4); |
7787 | CHECK_REG_PAIR(r3); | |
f4aef476 BK |
7788 | gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7789 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); | |
7790 | break; | |
7791 | case OPC2_32_RRR1_MSUBS_H_LL: | |
828066c7 BK |
7792 | CHECK_REG_PAIR(r4); |
7793 | CHECK_REG_PAIR(r3); | |
f4aef476 BK |
7794 | gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7795 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); | |
7796 | break; | |
7797 | case OPC2_32_RRR1_MSUBS_H_LU: | |
828066c7 BK |
7798 | CHECK_REG_PAIR(r4); |
7799 | CHECK_REG_PAIR(r3); | |
f4aef476 BK |
7800 | gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7801 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); | |
7802 | break; | |
7803 | case OPC2_32_RRR1_MSUBS_H_UL: | |
828066c7 BK |
7804 | CHECK_REG_PAIR(r4); |
7805 | CHECK_REG_PAIR(r3); | |
f4aef476 BK |
7806 | gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7807 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); | |
7808 | break; | |
7809 | case OPC2_32_RRR1_MSUBS_H_UU: | |
828066c7 BK |
7810 | CHECK_REG_PAIR(r4); |
7811 | CHECK_REG_PAIR(r3); | |
f4aef476 BK |
7812 | gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7813 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); | |
7814 | break; | |
7815 | case OPC2_32_RRR1_MSUBM_H_LL: | |
828066c7 BK |
7816 | CHECK_REG_PAIR(r4); |
7817 | CHECK_REG_PAIR(r3); | |
f4aef476 BK |
7818 | gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7819 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); | |
7820 | break; | |
7821 | case OPC2_32_RRR1_MSUBM_H_LU: | |
828066c7 BK |
7822 | CHECK_REG_PAIR(r4); |
7823 | CHECK_REG_PAIR(r3); | |
f4aef476 BK |
7824 | gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7825 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); | |
7826 | break; | |
7827 | case OPC2_32_RRR1_MSUBM_H_UL: | |
828066c7 BK |
7828 | CHECK_REG_PAIR(r4); |
7829 | CHECK_REG_PAIR(r3); | |
f4aef476 BK |
7830 | gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7831 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); | |
7832 | break; | |
7833 | case OPC2_32_RRR1_MSUBM_H_UU: | |
828066c7 BK |
7834 | CHECK_REG_PAIR(r4); |
7835 | CHECK_REG_PAIR(r3); | |
f4aef476 BK |
7836 | gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7837 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); | |
7838 | break; | |
7839 | case OPC2_32_RRR1_MSUBMS_H_LL: | |
828066c7 BK |
7840 | CHECK_REG_PAIR(r4); |
7841 | CHECK_REG_PAIR(r3); | |
f4aef476 BK |
7842 | gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7843 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); | |
7844 | break; | |
7845 | case OPC2_32_RRR1_MSUBMS_H_LU: | |
828066c7 BK |
7846 | CHECK_REG_PAIR(r4); |
7847 | CHECK_REG_PAIR(r3); | |
f4aef476 BK |
7848 | gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7849 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); | |
7850 | break; | |
7851 | case OPC2_32_RRR1_MSUBMS_H_UL: | |
828066c7 BK |
7852 | CHECK_REG_PAIR(r4); |
7853 | CHECK_REG_PAIR(r3); | |
f4aef476 BK |
7854 | gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7855 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); | |
7856 | break; | |
7857 | case OPC2_32_RRR1_MSUBMS_H_UU: | |
828066c7 BK |
7858 | CHECK_REG_PAIR(r4); |
7859 | CHECK_REG_PAIR(r3); | |
f4aef476 BK |
7860 | gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7861 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); | |
7862 | break; | |
7863 | case OPC2_32_RRR1_MSUBR_H_LL: | |
7864 | gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7865 | cpu_gpr_d[r2], n, MODE_LL); | |
7866 | break; | |
7867 | case OPC2_32_RRR1_MSUBR_H_LU: | |
7868 | gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7869 | cpu_gpr_d[r2], n, MODE_LU); | |
7870 | break; | |
7871 | case OPC2_32_RRR1_MSUBR_H_UL: | |
7872 | gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7873 | cpu_gpr_d[r2], n, MODE_UL); | |
7874 | break; | |
7875 | case OPC2_32_RRR1_MSUBR_H_UU: | |
7876 | gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7877 | cpu_gpr_d[r2], n, MODE_UU); | |
7878 | break; | |
7879 | case OPC2_32_RRR1_MSUBRS_H_LL: | |
7880 | gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7881 | cpu_gpr_d[r2], n, MODE_LL); | |
7882 | break; | |
7883 | case OPC2_32_RRR1_MSUBRS_H_LU: | |
7884 | gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7885 | cpu_gpr_d[r2], n, MODE_LU); | |
7886 | break; | |
7887 | case OPC2_32_RRR1_MSUBRS_H_UL: | |
7888 | gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7889 | cpu_gpr_d[r2], n, MODE_UL); | |
7890 | break; | |
7891 | case OPC2_32_RRR1_MSUBRS_H_UU: | |
7892 | gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7893 | cpu_gpr_d[r2], n, MODE_UU); | |
7894 | break; | |
f678f671 BK |
7895 | default: |
7896 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
f4aef476 BK |
7897 | } |
7898 | } | |
7899 | ||
2db92a0c | 7900 | static void decode_rrr1_msubq_h(DisasContext *ctx) |
62e47b2e BK |
7901 | { |
7902 | uint32_t op2; | |
7903 | uint32_t r1, r2, r3, r4, n; | |
7904 | TCGv temp, temp2; | |
7905 | ||
7906 | op2 = MASK_OP_RRR1_OP2(ctx->opcode); | |
7907 | r1 = MASK_OP_RRR1_S1(ctx->opcode); | |
7908 | r2 = MASK_OP_RRR1_S2(ctx->opcode); | |
7909 | r3 = MASK_OP_RRR1_S3(ctx->opcode); | |
7910 | r4 = MASK_OP_RRR1_D(ctx->opcode); | |
7911 | n = MASK_OP_RRR1_N(ctx->opcode); | |
7912 | ||
7913 | temp = tcg_const_i32(n); | |
7914 | temp2 = tcg_temp_new(); | |
7915 | ||
7916 | switch (op2) { | |
7917 | case OPC2_32_RRR1_MSUB_Q_32: | |
7918 | gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
2db92a0c | 7919 | cpu_gpr_d[r2], n, 32); |
62e47b2e BK |
7920 | break; |
7921 | case OPC2_32_RRR1_MSUB_Q_64: | |
828066c7 BK |
7922 | CHECK_REG_PAIR(r4); |
7923 | CHECK_REG_PAIR(r3); | |
62e47b2e BK |
7924 | gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7925 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
2db92a0c | 7926 | n); |
62e47b2e BK |
7927 | break; |
7928 | case OPC2_32_RRR1_MSUB_Q_32_L: | |
7929 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); | |
7930 | gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
2db92a0c | 7931 | temp, n, 16); |
62e47b2e BK |
7932 | break; |
7933 | case OPC2_32_RRR1_MSUB_Q_64_L: | |
828066c7 BK |
7934 | CHECK_REG_PAIR(r4); |
7935 | CHECK_REG_PAIR(r3); | |
62e47b2e BK |
7936 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); |
7937 | gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
7938 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, | |
2db92a0c | 7939 | n); |
62e47b2e BK |
7940 | break; |
7941 | case OPC2_32_RRR1_MSUB_Q_32_U: | |
7942 | tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); | |
7943 | gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
2db92a0c | 7944 | temp, n, 16); |
62e47b2e BK |
7945 | break; |
7946 | case OPC2_32_RRR1_MSUB_Q_64_U: | |
828066c7 BK |
7947 | CHECK_REG_PAIR(r4); |
7948 | CHECK_REG_PAIR(r3); | |
62e47b2e BK |
7949 | tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); |
7950 | gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
7951 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, | |
2db92a0c | 7952 | n); |
62e47b2e BK |
7953 | break; |
7954 | case OPC2_32_RRR1_MSUB_Q_32_LL: | |
7955 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); | |
7956 | tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); | |
7957 | gen_m16sub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); | |
7958 | break; | |
7959 | case OPC2_32_RRR1_MSUB_Q_64_LL: | |
828066c7 BK |
7960 | CHECK_REG_PAIR(r4); |
7961 | CHECK_REG_PAIR(r3); | |
62e47b2e BK |
7962 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); |
7963 | tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); | |
7964 | gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
7965 | cpu_gpr_d[r3+1], temp, temp2, n); | |
7966 | break; | |
7967 | case OPC2_32_RRR1_MSUB_Q_32_UU: | |
7968 | tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); | |
7969 | tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); | |
7970 | gen_m16sub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); | |
7971 | break; | |
7972 | case OPC2_32_RRR1_MSUB_Q_64_UU: | |
828066c7 BK |
7973 | CHECK_REG_PAIR(r4); |
7974 | CHECK_REG_PAIR(r3); | |
62e47b2e BK |
7975 | tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); |
7976 | tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); | |
7977 | gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
7978 | cpu_gpr_d[r3+1], temp, temp2, n); | |
7979 | break; | |
7980 | case OPC2_32_RRR1_MSUBS_Q_32: | |
7981 | gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7982 | cpu_gpr_d[r2], n, 32); | |
7983 | break; | |
7984 | case OPC2_32_RRR1_MSUBS_Q_64: | |
828066c7 BK |
7985 | CHECK_REG_PAIR(r4); |
7986 | CHECK_REG_PAIR(r3); | |
62e47b2e BK |
7987 | gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
7988 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
7989 | n); | |
7990 | break; | |
7991 | case OPC2_32_RRR1_MSUBS_Q_32_L: | |
7992 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); | |
7993 | gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
7994 | temp, n, 16); | |
7995 | break; | |
7996 | case OPC2_32_RRR1_MSUBS_Q_64_L: | |
828066c7 BK |
7997 | CHECK_REG_PAIR(r4); |
7998 | CHECK_REG_PAIR(r3); | |
62e47b2e BK |
7999 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); |
8000 | gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
8001 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, | |
8002 | n); | |
8003 | break; | |
8004 | case OPC2_32_RRR1_MSUBS_Q_32_U: | |
8005 | tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); | |
8006 | gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
8007 | temp, n, 16); | |
8008 | break; | |
8009 | case OPC2_32_RRR1_MSUBS_Q_64_U: | |
828066c7 BK |
8010 | CHECK_REG_PAIR(r4); |
8011 | CHECK_REG_PAIR(r3); | |
62e47b2e BK |
8012 | tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); |
8013 | gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
8014 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, | |
8015 | n); | |
8016 | break; | |
8017 | case OPC2_32_RRR1_MSUBS_Q_32_LL: | |
8018 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); | |
8019 | tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); | |
8020 | gen_m16subs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); | |
8021 | break; | |
8022 | case OPC2_32_RRR1_MSUBS_Q_64_LL: | |
828066c7 BK |
8023 | CHECK_REG_PAIR(r4); |
8024 | CHECK_REG_PAIR(r3); | |
62e47b2e BK |
8025 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); |
8026 | tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); | |
8027 | gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
8028 | cpu_gpr_d[r3+1], temp, temp2, n); | |
8029 | break; | |
8030 | case OPC2_32_RRR1_MSUBS_Q_32_UU: | |
8031 | tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); | |
8032 | tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); | |
8033 | gen_m16subs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); | |
8034 | break; | |
8035 | case OPC2_32_RRR1_MSUBS_Q_64_UU: | |
828066c7 BK |
8036 | CHECK_REG_PAIR(r4); |
8037 | CHECK_REG_PAIR(r3); | |
62e47b2e BK |
8038 | tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); |
8039 | tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); | |
8040 | gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], | |
8041 | cpu_gpr_d[r3+1], temp, temp2, n); | |
8042 | break; | |
8043 | case OPC2_32_RRR1_MSUBR_H_64_UL: | |
828066c7 | 8044 | CHECK_REG_PAIR(r3); |
62e47b2e BK |
8045 | gen_msubr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1], |
8046 | cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); | |
8047 | break; | |
8048 | case OPC2_32_RRR1_MSUBRS_H_64_UL: | |
828066c7 | 8049 | CHECK_REG_PAIR(r3); |
62e47b2e BK |
8050 | gen_msubr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1], |
8051 | cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); | |
8052 | break; | |
8053 | case OPC2_32_RRR1_MSUBR_Q_32_LL: | |
8054 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); | |
8055 | tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); | |
8056 | gen_msubr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); | |
8057 | break; | |
8058 | case OPC2_32_RRR1_MSUBR_Q_32_UU: | |
8059 | tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); | |
8060 | tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); | |
8061 | gen_msubr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); | |
8062 | break; | |
8063 | case OPC2_32_RRR1_MSUBRS_Q_32_LL: | |
8064 | tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); | |
8065 | tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); | |
8066 | gen_msubrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); | |
8067 | break; | |
8068 | case OPC2_32_RRR1_MSUBRS_Q_32_UU: | |
8069 | tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); | |
8070 | tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); | |
8071 | gen_msubrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); | |
8072 | break; | |
f678f671 BK |
8073 | default: |
8074 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
62e47b2e BK |
8075 | } |
8076 | tcg_temp_free(temp); | |
8077 | tcg_temp_free(temp2); | |
8078 | } | |
8079 | ||
2db92a0c | 8080 | static void decode_rrr1_msubad_h(DisasContext *ctx) |
068fac77 BK |
8081 | { |
8082 | uint32_t op2; | |
8083 | uint32_t r1, r2, r3, r4, n; | |
8084 | ||
8085 | op2 = MASK_OP_RRR1_OP2(ctx->opcode); | |
8086 | r1 = MASK_OP_RRR1_S1(ctx->opcode); | |
8087 | r2 = MASK_OP_RRR1_S2(ctx->opcode); | |
8088 | r3 = MASK_OP_RRR1_S3(ctx->opcode); | |
8089 | r4 = MASK_OP_RRR1_D(ctx->opcode); | |
8090 | n = MASK_OP_RRR1_N(ctx->opcode); | |
8091 | ||
8092 | switch (op2) { | |
8093 | case OPC2_32_RRR1_MSUBAD_H_32_LL: | |
828066c7 BK |
8094 | CHECK_REG_PAIR(r4); |
8095 | CHECK_REG_PAIR(r3); | |
068fac77 BK |
8096 | gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
8097 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); | |
8098 | break; | |
8099 | case OPC2_32_RRR1_MSUBAD_H_32_LU: | |
828066c7 BK |
8100 | CHECK_REG_PAIR(r4); |
8101 | CHECK_REG_PAIR(r3); | |
068fac77 BK |
8102 | gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
8103 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); | |
8104 | break; | |
8105 | case OPC2_32_RRR1_MSUBAD_H_32_UL: | |
828066c7 BK |
8106 | CHECK_REG_PAIR(r4); |
8107 | CHECK_REG_PAIR(r3); | |
068fac77 BK |
8108 | gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
8109 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); | |
8110 | break; | |
8111 | case OPC2_32_RRR1_MSUBAD_H_32_UU: | |
828066c7 BK |
8112 | CHECK_REG_PAIR(r4); |
8113 | CHECK_REG_PAIR(r3); | |
068fac77 BK |
8114 | gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
8115 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); | |
8116 | break; | |
8117 | case OPC2_32_RRR1_MSUBADS_H_32_LL: | |
828066c7 BK |
8118 | CHECK_REG_PAIR(r4); |
8119 | CHECK_REG_PAIR(r3); | |
068fac77 BK |
8120 | gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
8121 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
8122 | n, MODE_LL); | |
8123 | break; | |
8124 | case OPC2_32_RRR1_MSUBADS_H_32_LU: | |
828066c7 BK |
8125 | CHECK_REG_PAIR(r4); |
8126 | CHECK_REG_PAIR(r3); | |
068fac77 BK |
8127 | gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
8128 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
8129 | n, MODE_LU); | |
8130 | break; | |
8131 | case OPC2_32_RRR1_MSUBADS_H_32_UL: | |
828066c7 BK |
8132 | CHECK_REG_PAIR(r4); |
8133 | CHECK_REG_PAIR(r3); | |
068fac77 BK |
8134 | gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
8135 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
8136 | n, MODE_UL); | |
8137 | break; | |
8138 | case OPC2_32_RRR1_MSUBADS_H_32_UU: | |
828066c7 BK |
8139 | CHECK_REG_PAIR(r4); |
8140 | CHECK_REG_PAIR(r3); | |
068fac77 BK |
8141 | gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
8142 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
8143 | n, MODE_UU); | |
8144 | break; | |
8145 | case OPC2_32_RRR1_MSUBADM_H_64_LL: | |
828066c7 BK |
8146 | CHECK_REG_PAIR(r4); |
8147 | CHECK_REG_PAIR(r3); | |
068fac77 BK |
8148 | gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
8149 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
8150 | n, MODE_LL); | |
8151 | break; | |
8152 | case OPC2_32_RRR1_MSUBADM_H_64_LU: | |
828066c7 BK |
8153 | CHECK_REG_PAIR(r4); |
8154 | CHECK_REG_PAIR(r3); | |
068fac77 BK |
8155 | gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
8156 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
8157 | n, MODE_LU); | |
8158 | break; | |
8159 | case OPC2_32_RRR1_MSUBADM_H_64_UL: | |
828066c7 BK |
8160 | CHECK_REG_PAIR(r4); |
8161 | CHECK_REG_PAIR(r3); | |
068fac77 BK |
8162 | gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
8163 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
8164 | n, MODE_UL); | |
8165 | break; | |
8166 | case OPC2_32_RRR1_MSUBADM_H_64_UU: | |
828066c7 BK |
8167 | CHECK_REG_PAIR(r4); |
8168 | CHECK_REG_PAIR(r3); | |
068fac77 BK |
8169 | gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
8170 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
8171 | n, MODE_UU); | |
8172 | break; | |
8173 | case OPC2_32_RRR1_MSUBADMS_H_64_LL: | |
828066c7 BK |
8174 | CHECK_REG_PAIR(r4); |
8175 | CHECK_REG_PAIR(r3); | |
068fac77 BK |
8176 | gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
8177 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
8178 | n, MODE_LL); | |
8179 | break; | |
8180 | case OPC2_32_RRR1_MSUBADMS_H_64_LU: | |
828066c7 BK |
8181 | CHECK_REG_PAIR(r4); |
8182 | CHECK_REG_PAIR(r3); | |
068fac77 BK |
8183 | gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
8184 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
8185 | n, MODE_LU); | |
8186 | break; | |
8187 | case OPC2_32_RRR1_MSUBADMS_H_64_UL: | |
828066c7 BK |
8188 | CHECK_REG_PAIR(r4); |
8189 | CHECK_REG_PAIR(r3); | |
068fac77 BK |
8190 | gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
8191 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
8192 | n, MODE_UL); | |
8193 | break; | |
8194 | case OPC2_32_RRR1_MSUBADMS_H_64_UU: | |
828066c7 BK |
8195 | CHECK_REG_PAIR(r4); |
8196 | CHECK_REG_PAIR(r3); | |
068fac77 BK |
8197 | gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], |
8198 | cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], | |
8199 | n, MODE_UU); | |
8200 | break; | |
8201 | case OPC2_32_RRR1_MSUBADR_H_16_LL: | |
8202 | gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
8203 | cpu_gpr_d[r2], n, MODE_LL); | |
8204 | break; | |
8205 | case OPC2_32_RRR1_MSUBADR_H_16_LU: | |
8206 | gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
8207 | cpu_gpr_d[r2], n, MODE_LU); | |
8208 | break; | |
8209 | case OPC2_32_RRR1_MSUBADR_H_16_UL: | |
8210 | gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
8211 | cpu_gpr_d[r2], n, MODE_UL); | |
8212 | break; | |
8213 | case OPC2_32_RRR1_MSUBADR_H_16_UU: | |
8214 | gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
8215 | cpu_gpr_d[r2], n, MODE_UU); | |
8216 | break; | |
8217 | case OPC2_32_RRR1_MSUBADRS_H_16_LL: | |
8218 | gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
8219 | cpu_gpr_d[r2], n, MODE_LL); | |
8220 | break; | |
8221 | case OPC2_32_RRR1_MSUBADRS_H_16_LU: | |
8222 | gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
8223 | cpu_gpr_d[r2], n, MODE_LU); | |
8224 | break; | |
8225 | case OPC2_32_RRR1_MSUBADRS_H_16_UL: | |
8226 | gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
8227 | cpu_gpr_d[r2], n, MODE_UL); | |
8228 | break; | |
8229 | case OPC2_32_RRR1_MSUBADRS_H_16_UU: | |
8230 | gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], | |
8231 | cpu_gpr_d[r2], n, MODE_UU); | |
8232 | break; | |
f678f671 BK |
8233 | default: |
8234 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
068fac77 BK |
8235 | } |
8236 | } | |
8237 | ||
4d108fe3 | 8238 | /* RRRR format */ |
2db92a0c | 8239 | static void decode_rrrr_extract_insert(DisasContext *ctx) |
4d108fe3 BK |
8240 | { |
8241 | uint32_t op2; | |
8242 | int r1, r2, r3, r4; | |
8243 | TCGv tmp_width, tmp_pos; | |
8244 | ||
8245 | r1 = MASK_OP_RRRR_S1(ctx->opcode); | |
8246 | r2 = MASK_OP_RRRR_S2(ctx->opcode); | |
8247 | r3 = MASK_OP_RRRR_S3(ctx->opcode); | |
8248 | r4 = MASK_OP_RRRR_D(ctx->opcode); | |
8249 | op2 = MASK_OP_RRRR_OP2(ctx->opcode); | |
8250 | ||
8251 | tmp_pos = tcg_temp_new(); | |
8252 | tmp_width = tcg_temp_new(); | |
8253 | ||
8254 | switch (op2) { | |
8255 | case OPC2_32_RRRR_DEXTR: | |
8256 | tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f); | |
8257 | if (r1 == r2) { | |
8258 | tcg_gen_rotl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos); | |
8259 | } else { | |
8260 | tcg_gen_shl_tl(tmp_width, cpu_gpr_d[r1], tmp_pos); | |
8261 | tcg_gen_subfi_tl(tmp_pos, 32, tmp_pos); | |
8262 | tcg_gen_shr_tl(tmp_pos, cpu_gpr_d[r2], tmp_pos); | |
8263 | tcg_gen_or_tl(cpu_gpr_d[r4], tmp_width, tmp_pos); | |
8264 | } | |
8265 | break; | |
8266 | case OPC2_32_RRRR_EXTR: | |
8267 | case OPC2_32_RRRR_EXTR_U: | |
828066c7 | 8268 | CHECK_REG_PAIR(r3); |
4d108fe3 BK |
8269 | tcg_gen_andi_tl(tmp_width, cpu_gpr_d[r3+1], 0x1f); |
8270 | tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f); | |
8271 | tcg_gen_add_tl(tmp_pos, tmp_pos, tmp_width); | |
8272 | tcg_gen_subfi_tl(tmp_pos, 32, tmp_pos); | |
8273 | tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos); | |
8274 | tcg_gen_subfi_tl(tmp_width, 32, tmp_width); | |
8275 | if (op2 == OPC2_32_RRRR_EXTR) { | |
8276 | tcg_gen_sar_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], tmp_width); | |
8277 | } else { | |
8278 | tcg_gen_shr_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], tmp_width); | |
8279 | } | |
8280 | break; | |
8281 | case OPC2_32_RRRR_INSERT: | |
828066c7 | 8282 | CHECK_REG_PAIR(r3); |
4d108fe3 BK |
8283 | tcg_gen_andi_tl(tmp_width, cpu_gpr_d[r3+1], 0x1f); |
8284 | tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f); | |
8285 | gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], tmp_width, | |
8286 | tmp_pos); | |
8287 | break; | |
f678f671 BK |
8288 | default: |
8289 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
4d108fe3 BK |
8290 | } |
8291 | tcg_temp_free(tmp_pos); | |
8292 | tcg_temp_free(tmp_width); | |
8293 | } | |
8294 | ||
eb989d25 | 8295 | /* RRRW format */ |
2db92a0c | 8296 | static void decode_rrrw_extract_insert(DisasContext *ctx) |
eb989d25 BK |
8297 | { |
8298 | uint32_t op2; | |
8299 | int r1, r2, r3, r4; | |
8300 | int32_t width; | |
8301 | ||
8302 | TCGv temp, temp2; | |
8303 | ||
8304 | op2 = MASK_OP_RRRW_OP2(ctx->opcode); | |
8305 | r1 = MASK_OP_RRRW_S1(ctx->opcode); | |
8306 | r2 = MASK_OP_RRRW_S2(ctx->opcode); | |
8307 | r3 = MASK_OP_RRRW_S3(ctx->opcode); | |
8308 | r4 = MASK_OP_RRRW_D(ctx->opcode); | |
8309 | width = MASK_OP_RRRW_WIDTH(ctx->opcode); | |
8310 | ||
8311 | temp = tcg_temp_new(); | |
8312 | ||
8313 | switch (op2) { | |
8314 | case OPC2_32_RRRW_EXTR: | |
8315 | tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f); | |
8316 | tcg_gen_addi_tl(temp, temp, width); | |
8317 | tcg_gen_subfi_tl(temp, 32, temp); | |
8318 | tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp); | |
8319 | tcg_gen_sari_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], 32 - width); | |
8320 | break; | |
8321 | case OPC2_32_RRRW_EXTR_U: | |
8322 | if (width == 0) { | |
8323 | tcg_gen_movi_tl(cpu_gpr_d[r4], 0); | |
8324 | } else { | |
8325 | tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f); | |
8326 | tcg_gen_shr_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp); | |
8327 | tcg_gen_andi_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], ~0u >> (32-width)); | |
8328 | } | |
8329 | break; | |
8330 | case OPC2_32_RRRW_IMASK: | |
8331 | temp2 = tcg_temp_new(); | |
8332 | ||
8333 | tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f); | |
8334 | tcg_gen_movi_tl(temp2, (1 << width) - 1); | |
8335 | tcg_gen_shl_tl(temp2, temp2, temp); | |
8336 | tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r2], temp); | |
8337 | tcg_gen_mov_tl(cpu_gpr_d[r4+1], temp2); | |
8338 | ||
8339 | tcg_temp_free(temp2); | |
8340 | break; | |
8341 | case OPC2_32_RRRW_INSERT: | |
8342 | temp2 = tcg_temp_new(); | |
8343 | ||
8344 | tcg_gen_movi_tl(temp, width); | |
8345 | tcg_gen_andi_tl(temp2, cpu_gpr_d[r3], 0x1f); | |
8346 | gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], temp, temp2); | |
8347 | ||
8348 | tcg_temp_free(temp2); | |
8349 | break; | |
f678f671 BK |
8350 | default: |
8351 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
eb989d25 BK |
8352 | } |
8353 | tcg_temp_free(temp); | |
8354 | } | |
8355 | ||
b724b012 | 8356 | /* SYS Format*/ |
2db92a0c | 8357 | static void decode_sys_interrupts(DisasContext *ctx) |
b724b012 BK |
8358 | { |
8359 | uint32_t op2; | |
bc3551c4 | 8360 | uint32_t r1; |
b724b012 BK |
8361 | TCGLabel *l1; |
8362 | TCGv tmp; | |
8363 | ||
8364 | op2 = MASK_OP_SYS_OP2(ctx->opcode); | |
bc3551c4 | 8365 | r1 = MASK_OP_SYS_S1D(ctx->opcode); |
b724b012 BK |
8366 | |
8367 | switch (op2) { | |
8368 | case OPC2_32_SYS_DEBUG: | |
8369 | /* raise EXCP_DEBUG */ | |
8370 | break; | |
8371 | case OPC2_32_SYS_DISABLE: | |
d1cbc28a | 8372 | tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~MASK_ICR_IE_1_3); |
b724b012 BK |
8373 | break; |
8374 | case OPC2_32_SYS_DSYNC: | |
8375 | break; | |
8376 | case OPC2_32_SYS_ENABLE: | |
d1cbc28a | 8377 | tcg_gen_ori_tl(cpu_ICR, cpu_ICR, MASK_ICR_IE_1_3); |
b724b012 BK |
8378 | break; |
8379 | case OPC2_32_SYS_ISYNC: | |
8380 | break; | |
8381 | case OPC2_32_SYS_NOP: | |
8382 | break; | |
8383 | case OPC2_32_SYS_RET: | |
8384 | gen_compute_branch(ctx, op2, 0, 0, 0, 0); | |
8385 | break; | |
0e045f43 BK |
8386 | case OPC2_32_SYS_FRET: |
8387 | gen_fret(ctx); | |
8388 | break; | |
b724b012 BK |
8389 | case OPC2_32_SYS_RFE: |
8390 | gen_helper_rfe(cpu_env); | |
07ea28b4 | 8391 | tcg_gen_exit_tb(NULL, 0); |
6b9f5a42 | 8392 | ctx->base.is_jmp = DISAS_NORETURN; |
b724b012 BK |
8393 | break; |
8394 | case OPC2_32_SYS_RFM: | |
8395 | if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM) { | |
8396 | tmp = tcg_temp_new(); | |
8397 | l1 = gen_new_label(); | |
8398 | ||
8399 | tcg_gen_ld32u_tl(tmp, cpu_env, offsetof(CPUTriCoreState, DBGSR)); | |
8400 | tcg_gen_andi_tl(tmp, tmp, MASK_DBGSR_DE); | |
8401 | tcg_gen_brcondi_tl(TCG_COND_NE, tmp, 1, l1); | |
8402 | gen_helper_rfm(cpu_env); | |
8403 | gen_set_label(l1); | |
07ea28b4 | 8404 | tcg_gen_exit_tb(NULL, 0); |
6b9f5a42 | 8405 | ctx->base.is_jmp = DISAS_NORETURN; |
b724b012 BK |
8406 | tcg_temp_free(tmp); |
8407 | } else { | |
8408 | /* generate privilege trap */ | |
8409 | } | |
8410 | break; | |
8411 | case OPC2_32_SYS_RSLCX: | |
8412 | gen_helper_rslcx(cpu_env); | |
8413 | break; | |
8414 | case OPC2_32_SYS_SVLCX: | |
8415 | gen_helper_svlcx(cpu_env); | |
8416 | break; | |
bc3551c4 | 8417 | case OPC2_32_SYS_RESTORE: |
44ee3baf | 8418 | if (has_feature(ctx, TRICORE_FEATURE_16)) { |
bc3551c4 BK |
8419 | if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM || |
8420 | (ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_UM1) { | |
8421 | tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1], 8, 1); | |
8422 | } /* else raise privilege trap */ | |
f678f671 BK |
8423 | } else { |
8424 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
8425 | } | |
bc3551c4 | 8426 | break; |
b724b012 | 8427 | case OPC2_32_SYS_TRAPSV: |
518d7fd2 BK |
8428 | l1 = gen_new_label(); |
8429 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_PSW_SV, 0, l1); | |
8430 | generate_trap(ctx, TRAPC_ASSERT, TIN5_SOVF); | |
8431 | gen_set_label(l1); | |
b724b012 BK |
8432 | break; |
8433 | case OPC2_32_SYS_TRAPV: | |
518d7fd2 BK |
8434 | l1 = gen_new_label(); |
8435 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_PSW_V, 0, l1); | |
8436 | generate_trap(ctx, TRAPC_ASSERT, TIN5_OVF); | |
8437 | gen_set_label(l1); | |
b724b012 | 8438 | break; |
f678f671 BK |
8439 | default: |
8440 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
b724b012 BK |
8441 | } |
8442 | } | |
8443 | ||
2db92a0c | 8444 | static void decode_32Bit_opc(DisasContext *ctx) |
0aaeb118 | 8445 | { |
59543d4e | 8446 | int op1; |
ed516260 BK |
8447 | int32_t r1, r2, r3; |
8448 | int32_t address, const16; | |
fc2ef4a3 | 8449 | int8_t b, const4; |
59543d4e | 8450 | int32_t bpos; |
ed516260 | 8451 | TCGv temp, temp2, temp3; |
59543d4e BK |
8452 | |
8453 | op1 = MASK_OP_MAJOR(ctx->opcode); | |
8454 | ||
7f13420e BK |
8455 | /* handle JNZ.T opcode only being 7 bit long */ |
8456 | if (unlikely((op1 & 0x7f) == OPCM_32_BRN_JTT)) { | |
83c1bb18 BK |
8457 | op1 = OPCM_32_BRN_JTT; |
8458 | } | |
8459 | ||
59543d4e BK |
8460 | switch (op1) { |
8461 | /* ABS-format */ | |
8462 | case OPCM_32_ABS_LDW: | |
2db92a0c | 8463 | decode_abs_ldw(ctx); |
59543d4e BK |
8464 | break; |
8465 | case OPCM_32_ABS_LDB: | |
2db92a0c | 8466 | decode_abs_ldb(ctx); |
59543d4e BK |
8467 | break; |
8468 | case OPCM_32_ABS_LDMST_SWAP: | |
2db92a0c | 8469 | decode_abs_ldst_swap(ctx); |
59543d4e BK |
8470 | break; |
8471 | case OPCM_32_ABS_LDST_CONTEXT: | |
2db92a0c | 8472 | decode_abs_ldst_context(ctx); |
59543d4e BK |
8473 | break; |
8474 | case OPCM_32_ABS_STORE: | |
2db92a0c | 8475 | decode_abs_store(ctx); |
59543d4e BK |
8476 | break; |
8477 | case OPCM_32_ABS_STOREB_H: | |
2db92a0c | 8478 | decode_abs_storeb_h(ctx); |
59543d4e BK |
8479 | break; |
8480 | case OPC1_32_ABS_STOREQ: | |
8481 | address = MASK_OP_ABS_OFF18(ctx->opcode); | |
8482 | r1 = MASK_OP_ABS_S1D(ctx->opcode); | |
8483 | temp = tcg_const_i32(EA_ABS_FORMAT(address)); | |
8484 | temp2 = tcg_temp_new(); | |
8485 | ||
8486 | tcg_gen_shri_tl(temp2, cpu_gpr_d[r1], 16); | |
8487 | tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_LEUW); | |
8488 | ||
8489 | tcg_temp_free(temp2); | |
8490 | tcg_temp_free(temp); | |
8491 | break; | |
8492 | case OPC1_32_ABS_LD_Q: | |
8493 | address = MASK_OP_ABS_OFF18(ctx->opcode); | |
8494 | r1 = MASK_OP_ABS_S1D(ctx->opcode); | |
8495 | temp = tcg_const_i32(EA_ABS_FORMAT(address)); | |
8496 | ||
8497 | tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW); | |
8498 | tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); | |
8499 | ||
8500 | tcg_temp_free(temp); | |
8501 | break; | |
8502 | case OPC1_32_ABS_LEA: | |
8503 | address = MASK_OP_ABS_OFF18(ctx->opcode); | |
8504 | r1 = MASK_OP_ABS_S1D(ctx->opcode); | |
8505 | tcg_gen_movi_tl(cpu_gpr_a[r1], EA_ABS_FORMAT(address)); | |
8506 | break; | |
8507 | /* ABSB-format */ | |
8508 | case OPC1_32_ABSB_ST_T: | |
8509 | address = MASK_OP_ABS_OFF18(ctx->opcode); | |
8510 | b = MASK_OP_ABSB_B(ctx->opcode); | |
8511 | bpos = MASK_OP_ABSB_BPOS(ctx->opcode); | |
8512 | ||
8513 | temp = tcg_const_i32(EA_ABS_FORMAT(address)); | |
8514 | temp2 = tcg_temp_new(); | |
8515 | ||
8516 | tcg_gen_qemu_ld_tl(temp2, temp, ctx->mem_idx, MO_UB); | |
8517 | tcg_gen_andi_tl(temp2, temp2, ~(0x1u << bpos)); | |
8518 | tcg_gen_ori_tl(temp2, temp2, (b << bpos)); | |
8519 | tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_UB); | |
8520 | ||
8521 | tcg_temp_free(temp); | |
8522 | tcg_temp_free(temp2); | |
8523 | break; | |
f718b0bb BK |
8524 | /* B-format */ |
8525 | case OPC1_32_B_CALL: | |
8526 | case OPC1_32_B_CALLA: | |
9e14a7b2 BK |
8527 | case OPC1_32_B_FCALL: |
8528 | case OPC1_32_B_FCALLA: | |
f718b0bb BK |
8529 | case OPC1_32_B_J: |
8530 | case OPC1_32_B_JA: | |
8531 | case OPC1_32_B_JL: | |
8532 | case OPC1_32_B_JLA: | |
436d63ff | 8533 | address = MASK_OP_B_DISP24_SEXT(ctx->opcode); |
f718b0bb BK |
8534 | gen_compute_branch(ctx, op1, 0, 0, 0, address); |
8535 | break; | |
b74f2b5b BK |
8536 | /* Bit-format */ |
8537 | case OPCM_32_BIT_ANDACC: | |
2db92a0c | 8538 | decode_bit_andacc(ctx); |
b74f2b5b BK |
8539 | break; |
8540 | case OPCM_32_BIT_LOGICAL_T1: | |
2db92a0c | 8541 | decode_bit_logical_t(ctx); |
b74f2b5b BK |
8542 | break; |
8543 | case OPCM_32_BIT_INSERT: | |
2db92a0c | 8544 | decode_bit_insert(ctx); |
b74f2b5b BK |
8545 | break; |
8546 | case OPCM_32_BIT_LOGICAL_T2: | |
2db92a0c | 8547 | decode_bit_logical_t2(ctx); |
b74f2b5b BK |
8548 | break; |
8549 | case OPCM_32_BIT_ORAND: | |
2db92a0c | 8550 | decode_bit_orand(ctx); |
b74f2b5b BK |
8551 | break; |
8552 | case OPCM_32_BIT_SH_LOGIC1: | |
2db92a0c | 8553 | decode_bit_sh_logic1(ctx); |
b74f2b5b BK |
8554 | break; |
8555 | case OPCM_32_BIT_SH_LOGIC2: | |
2db92a0c | 8556 | decode_bit_sh_logic2(ctx); |
b74f2b5b | 8557 | break; |
3a16ecb0 BK |
8558 | /* BO Format */ |
8559 | case OPCM_32_BO_ADDRMODE_POST_PRE_BASE: | |
2db92a0c | 8560 | decode_bo_addrmode_post_pre_base(ctx); |
3a16ecb0 BK |
8561 | break; |
8562 | case OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR: | |
2db92a0c | 8563 | decode_bo_addrmode_bitreverse_circular(ctx); |
3a16ecb0 BK |
8564 | break; |
8565 | case OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE: | |
2db92a0c | 8566 | decode_bo_addrmode_ld_post_pre_base(ctx); |
3a16ecb0 BK |
8567 | break; |
8568 | case OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR: | |
2db92a0c | 8569 | decode_bo_addrmode_ld_bitreverse_circular(ctx); |
3a16ecb0 BK |
8570 | break; |
8571 | case OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE: | |
2db92a0c | 8572 | decode_bo_addrmode_stctx_post_pre_base(ctx); |
3a16ecb0 BK |
8573 | break; |
8574 | case OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR: | |
2db92a0c | 8575 | decode_bo_addrmode_ldmst_bitreverse_circular(ctx); |
3a16ecb0 | 8576 | break; |
3fb763cb BK |
8577 | /* BOL-format */ |
8578 | case OPC1_32_BOL_LD_A_LONGOFF: | |
af715d98 | 8579 | case OPC1_32_BOL_LD_W_LONGOFF: |
3fb763cb BK |
8580 | case OPC1_32_BOL_LEA_LONGOFF: |
8581 | case OPC1_32_BOL_ST_W_LONGOFF: | |
8582 | case OPC1_32_BOL_ST_A_LONGOFF: | |
b5fd8fa3 BK |
8583 | case OPC1_32_BOL_LD_B_LONGOFF: |
8584 | case OPC1_32_BOL_LD_BU_LONGOFF: | |
8585 | case OPC1_32_BOL_LD_H_LONGOFF: | |
8586 | case OPC1_32_BOL_LD_HU_LONGOFF: | |
8587 | case OPC1_32_BOL_ST_B_LONGOFF: | |
8588 | case OPC1_32_BOL_ST_H_LONGOFF: | |
2db92a0c | 8589 | decode_bol_opc(ctx, op1); |
3fb763cb | 8590 | break; |
fc2ef4a3 BK |
8591 | /* BRC Format */ |
8592 | case OPCM_32_BRC_EQ_NEQ: | |
8593 | case OPCM_32_BRC_GE: | |
8594 | case OPCM_32_BRC_JLT: | |
8595 | case OPCM_32_BRC_JNE: | |
8596 | const4 = MASK_OP_BRC_CONST4_SEXT(ctx->opcode); | |
8597 | address = MASK_OP_BRC_DISP15_SEXT(ctx->opcode); | |
8598 | r1 = MASK_OP_BRC_S1(ctx->opcode); | |
8599 | gen_compute_branch(ctx, op1, r1, 0, const4, address); | |
8600 | break; | |
83c1bb18 BK |
8601 | /* BRN Format */ |
8602 | case OPCM_32_BRN_JTT: | |
8603 | address = MASK_OP_BRN_DISP15_SEXT(ctx->opcode); | |
8604 | r1 = MASK_OP_BRN_S1(ctx->opcode); | |
8605 | gen_compute_branch(ctx, op1, r1, 0, 0, address); | |
8606 | break; | |
a68e0d54 BK |
8607 | /* BRR Format */ |
8608 | case OPCM_32_BRR_EQ_NEQ: | |
8609 | case OPCM_32_BRR_ADDR_EQ_NEQ: | |
8610 | case OPCM_32_BRR_GE: | |
8611 | case OPCM_32_BRR_JLT: | |
8612 | case OPCM_32_BRR_JNE: | |
8613 | case OPCM_32_BRR_JNZ: | |
8614 | case OPCM_32_BRR_LOOP: | |
8615 | address = MASK_OP_BRR_DISP15_SEXT(ctx->opcode); | |
8616 | r2 = MASK_OP_BRR_S2(ctx->opcode); | |
8617 | r1 = MASK_OP_BRR_S1(ctx->opcode); | |
8618 | gen_compute_branch(ctx, op1, r1, r2, 0, address); | |
8619 | break; | |
0974257e BK |
8620 | /* RC Format */ |
8621 | case OPCM_32_RC_LOGICAL_SHIFT: | |
2db92a0c | 8622 | decode_rc_logical_shift(ctx); |
0974257e BK |
8623 | break; |
8624 | case OPCM_32_RC_ACCUMULATOR: | |
2db92a0c | 8625 | decode_rc_accumulator(ctx); |
0974257e BK |
8626 | break; |
8627 | case OPCM_32_RC_SERVICEROUTINE: | |
2db92a0c | 8628 | decode_rc_serviceroutine(ctx); |
0974257e BK |
8629 | break; |
8630 | case OPCM_32_RC_MUL: | |
2db92a0c | 8631 | decode_rc_mul(ctx); |
0974257e | 8632 | break; |
ed516260 BK |
8633 | /* RCPW Format */ |
8634 | case OPCM_32_RCPW_MASK_INSERT: | |
2db92a0c | 8635 | decode_rcpw_insert(ctx); |
ed516260 BK |
8636 | break; |
8637 | /* RCRR Format */ | |
8638 | case OPC1_32_RCRR_INSERT: | |
8639 | r1 = MASK_OP_RCRR_S1(ctx->opcode); | |
8640 | r2 = MASK_OP_RCRR_S3(ctx->opcode); | |
8641 | r3 = MASK_OP_RCRR_D(ctx->opcode); | |
8642 | const16 = MASK_OP_RCRR_CONST4(ctx->opcode); | |
8643 | temp = tcg_const_i32(const16); | |
8644 | temp2 = tcg_temp_new(); /* width*/ | |
8645 | temp3 = tcg_temp_new(); /* pos */ | |
8646 | ||
828066c7 BK |
8647 | CHECK_REG_PAIR(r3); |
8648 | ||
ed516260 BK |
8649 | tcg_gen_andi_tl(temp2, cpu_gpr_d[r3+1], 0x1f); |
8650 | tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f); | |
8651 | ||
8652 | gen_insert(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, temp2, temp3); | |
8653 | ||
8654 | tcg_temp_free(temp); | |
8655 | tcg_temp_free(temp2); | |
8656 | tcg_temp_free(temp3); | |
8657 | break; | |
8658 | /* RCRW Format */ | |
8659 | case OPCM_32_RCRW_MASK_INSERT: | |
2db92a0c | 8660 | decode_rcrw_insert(ctx); |
ed516260 | 8661 | break; |
328f1f0f BK |
8662 | /* RCR Format */ |
8663 | case OPCM_32_RCR_COND_SELECT: | |
2db92a0c | 8664 | decode_rcr_cond_select(ctx); |
328f1f0f BK |
8665 | break; |
8666 | case OPCM_32_RCR_MADD: | |
2db92a0c | 8667 | decode_rcr_madd(ctx); |
328f1f0f BK |
8668 | break; |
8669 | case OPCM_32_RCR_MSUB: | |
2db92a0c | 8670 | decode_rcr_msub(ctx); |
328f1f0f | 8671 | break; |
2b2f7d97 BK |
8672 | /* RLC Format */ |
8673 | case OPC1_32_RLC_ADDI: | |
8674 | case OPC1_32_RLC_ADDIH: | |
8675 | case OPC1_32_RLC_ADDIH_A: | |
8676 | case OPC1_32_RLC_MFCR: | |
8677 | case OPC1_32_RLC_MOV: | |
4b5b4435 | 8678 | case OPC1_32_RLC_MOV_64: |
2b2f7d97 BK |
8679 | case OPC1_32_RLC_MOV_U: |
8680 | case OPC1_32_RLC_MOV_H: | |
8681 | case OPC1_32_RLC_MOVH_A: | |
8682 | case OPC1_32_RLC_MTCR: | |
2db92a0c | 8683 | decode_rlc_opc(ctx, op1); |
2b2f7d97 | 8684 | break; |
d5de7839 BK |
8685 | /* RR Format */ |
8686 | case OPCM_32_RR_ACCUMULATOR: | |
2db92a0c | 8687 | decode_rr_accumulator(ctx); |
d5de7839 | 8688 | break; |
0b79a781 | 8689 | case OPCM_32_RR_LOGICAL_SHIFT: |
2db92a0c | 8690 | decode_rr_logical_shift(ctx); |
0b79a781 | 8691 | break; |
37097418 | 8692 | case OPCM_32_RR_ADDRESS: |
2db92a0c | 8693 | decode_rr_address(ctx); |
f2f1585f BK |
8694 | break; |
8695 | case OPCM_32_RR_IDIRECT: | |
2db92a0c | 8696 | decode_rr_idirect(ctx); |
f2f1585f | 8697 | break; |
e2bed107 | 8698 | case OPCM_32_RR_DIVIDE: |
2db92a0c | 8699 | decode_rr_divide(ctx); |
e2bed107 | 8700 | break; |
9655b932 BK |
8701 | /* RR1 Format */ |
8702 | case OPCM_32_RR1_MUL: | |
2db92a0c | 8703 | decode_rr1_mul(ctx); |
9655b932 | 8704 | break; |
f1cc6eaf | 8705 | case OPCM_32_RR1_MULQ: |
2db92a0c | 8706 | decode_rr1_mulq(ctx); |
f1cc6eaf | 8707 | break; |
12f323e6 BK |
8708 | /* RR2 format */ |
8709 | case OPCM_32_RR2_MUL: | |
2db92a0c | 8710 | decode_rr2_mul(ctx); |
12f323e6 | 8711 | break; |
8fb9d0eb BK |
8712 | /* RRPW format */ |
8713 | case OPCM_32_RRPW_EXTRACT_INSERT: | |
2db92a0c | 8714 | decode_rrpw_extract_insert(ctx); |
8fb9d0eb BK |
8715 | break; |
8716 | case OPC1_32_RRPW_DEXTR: | |
8717 | r1 = MASK_OP_RRPW_S1(ctx->opcode); | |
8718 | r2 = MASK_OP_RRPW_S2(ctx->opcode); | |
8719 | r3 = MASK_OP_RRPW_D(ctx->opcode); | |
8720 | const16 = MASK_OP_RRPW_POS(ctx->opcode); | |
8721 | if (r1 == r2) { | |
8722 | tcg_gen_rotli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], const16); | |
8723 | } else { | |
8724 | temp = tcg_temp_new(); | |
00e1754f BK |
8725 | tcg_gen_shli_tl(temp, cpu_gpr_d[r1], const16); |
8726 | tcg_gen_shri_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], 32 - const16); | |
8fb9d0eb BK |
8727 | tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp); |
8728 | tcg_temp_free(temp); | |
8729 | } | |
8730 | break; | |
09532255 BK |
8731 | /* RRR Format */ |
8732 | case OPCM_32_RRR_COND_SELECT: | |
2db92a0c | 8733 | decode_rrr_cond_select(ctx); |
09532255 BK |
8734 | break; |
8735 | case OPCM_32_RRR_DIVIDE: | |
2db92a0c | 8736 | decode_rrr_divide(ctx); |
1f75cba8 | 8737 | break; |
2984cfbd BK |
8738 | /* RRR2 Format */ |
8739 | case OPCM_32_RRR2_MADD: | |
2db92a0c | 8740 | decode_rrr2_madd(ctx); |
2984cfbd BK |
8741 | break; |
8742 | case OPCM_32_RRR2_MSUB: | |
2db92a0c | 8743 | decode_rrr2_msub(ctx); |
2984cfbd | 8744 | break; |
2e430e1c BK |
8745 | /* RRR1 format */ |
8746 | case OPCM_32_RRR1_MADD: | |
2db92a0c | 8747 | decode_rrr1_madd(ctx); |
2e430e1c | 8748 | break; |
b00aa8ec | 8749 | case OPCM_32_RRR1_MADDQ_H: |
2db92a0c | 8750 | decode_rrr1_maddq_h(ctx); |
b00aa8ec | 8751 | break; |
bebe80fc | 8752 | case OPCM_32_RRR1_MADDSU_H: |
2db92a0c | 8753 | decode_rrr1_maddsu_h(ctx); |
bebe80fc | 8754 | break; |
f4aef476 | 8755 | case OPCM_32_RRR1_MSUB_H: |
2db92a0c | 8756 | decode_rrr1_msub(ctx); |
f4aef476 | 8757 | break; |
62e47b2e | 8758 | case OPCM_32_RRR1_MSUB_Q: |
2db92a0c | 8759 | decode_rrr1_msubq_h(ctx); |
62e47b2e | 8760 | break; |
068fac77 | 8761 | case OPCM_32_RRR1_MSUBAD_H: |
2db92a0c | 8762 | decode_rrr1_msubad_h(ctx); |
068fac77 | 8763 | break; |
4d108fe3 BK |
8764 | /* RRRR format */ |
8765 | case OPCM_32_RRRR_EXTRACT_INSERT: | |
2db92a0c | 8766 | decode_rrrr_extract_insert(ctx); |
1f75cba8 | 8767 | break; |
eb989d25 BK |
8768 | /* RRRW format */ |
8769 | case OPCM_32_RRRW_EXTRACT_INSERT: | |
2db92a0c | 8770 | decode_rrrw_extract_insert(ctx); |
eb989d25 | 8771 | break; |
b724b012 BK |
8772 | /* SYS format */ |
8773 | case OPCM_32_SYS_INTERRUPTS: | |
2db92a0c | 8774 | decode_sys_interrupts(ctx); |
b724b012 BK |
8775 | break; |
8776 | case OPC1_32_SYS_RSTV: | |
8777 | tcg_gen_movi_tl(cpu_PSW_V, 0); | |
8778 | tcg_gen_mov_tl(cpu_PSW_SV, cpu_PSW_V); | |
8779 | tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); | |
8780 | tcg_gen_mov_tl(cpu_PSW_SAV, cpu_PSW_V); | |
8781 | break; | |
f678f671 BK |
8782 | default: |
8783 | generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); | |
59543d4e | 8784 | } |
0aaeb118 BK |
8785 | } |
8786 | ||
d4881da9 | 8787 | static bool tricore_insn_is_16bit(uint32_t insn) |
0aaeb118 | 8788 | { |
d4881da9 | 8789 | return (insn & 0x1) == 0; |
0aaeb118 BK |
8790 | } |
8791 | ||
1fae1851 BK |
8792 | static void tricore_tr_init_disas_context(DisasContextBase *dcbase, |
8793 | CPUState *cs) | |
48e06fe0 | 8794 | { |
1fae1851 | 8795 | DisasContext *ctx = container_of(dcbase, DisasContext, base); |
9c489ea6 | 8796 | CPUTriCoreState *env = cs->env_ptr; |
1fae1851 BK |
8797 | ctx->mem_idx = cpu_mmu_index(env, false); |
8798 | ctx->hflags = (uint32_t)ctx->base.tb->flags; | |
44ee3baf | 8799 | ctx->features = env->features; |
1fae1851 BK |
8800 | } |
8801 | ||
8802 | static void tricore_tr_tb_start(DisasContextBase *db, CPUState *cpu) | |
8803 | { | |
8804 | } | |
8805 | ||
8806 | static void tricore_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) | |
8807 | { | |
8808 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
8809 | ||
8810 | tcg_gen_insn_start(ctx->base.pc_next); | |
8811 | } | |
8812 | ||
d4881da9 BK |
8813 | static bool insn_crosses_page(CPUTriCoreState *env, DisasContext *ctx) |
8814 | { | |
8815 | /* | |
8816 | * Return true if the insn at ctx->base.pc_next might cross a page boundary. | |
8817 | * (False positives are OK, false negatives are not.) | |
8818 | * Our caller ensures we are only called if dc->base.pc_next is less than | |
8819 | * 4 bytes from the page boundary, so we cross the page if the first | |
8820 | * 16 bits indicate that this is a 32 bit insn. | |
8821 | */ | |
8822 | uint16_t insn = cpu_lduw_code(env, ctx->base.pc_next); | |
8823 | ||
8824 | return !tricore_insn_is_16bit(insn); | |
8825 | } | |
8826 | ||
8827 | ||
1fae1851 BK |
8828 | static void tricore_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) |
8829 | { | |
8830 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
8831 | CPUTriCoreState *env = cpu->env_ptr; | |
d4881da9 BK |
8832 | uint16_t insn_lo; |
8833 | bool is_16bit; | |
1fae1851 | 8834 | |
d4881da9 BK |
8835 | insn_lo = cpu_lduw_code(env, ctx->base.pc_next); |
8836 | is_16bit = tricore_insn_is_16bit(insn_lo); | |
8837 | if (is_16bit) { | |
8838 | ctx->opcode = insn_lo; | |
8839 | ctx->pc_succ_insn = ctx->base.pc_next + 2; | |
8840 | decode_16Bit_opc(ctx); | |
8841 | } else { | |
8842 | uint32_t insn_hi = cpu_lduw_code(env, ctx->base.pc_next + 2); | |
8843 | ctx->opcode = insn_hi << 16 | insn_lo; | |
8844 | ctx->pc_succ_insn = ctx->base.pc_next + 4; | |
8845 | decode_32Bit_opc(ctx); | |
8846 | } | |
1fae1851 BK |
8847 | ctx->base.pc_next = ctx->pc_succ_insn; |
8848 | ||
8849 | if (ctx->base.is_jmp == DISAS_NEXT) { | |
8850 | target_ulong page_start; | |
8851 | ||
8852 | page_start = ctx->base.pc_first & TARGET_PAGE_MASK; | |
d4881da9 BK |
8853 | if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE |
8854 | || (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE - 3 | |
8855 | && insn_crosses_page(env, ctx))) { | |
1fae1851 | 8856 | ctx->base.is_jmp = DISAS_TOO_MANY; |
0aaeb118 | 8857 | } |
0aaeb118 | 8858 | } |
1fae1851 | 8859 | } |
0aaeb118 | 8860 | |
1fae1851 BK |
8861 | static void tricore_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) |
8862 | { | |
8863 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
4e5e1215 | 8864 | |
1fae1851 BK |
8865 | switch (ctx->base.is_jmp) { |
8866 | case DISAS_TOO_MANY: | |
8867 | gen_goto_tb(ctx, 0, ctx->base.pc_next); | |
8868 | break; | |
8869 | case DISAS_NORETURN: | |
8870 | break; | |
8871 | default: | |
8872 | g_assert_not_reached(); | |
0aaeb118 | 8873 | } |
1fae1851 | 8874 | } |
0aaeb118 | 8875 | |
1fae1851 BK |
8876 | static void tricore_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) |
8877 | { | |
8878 | qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); | |
8879 | log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); | |
8880 | } | |
8881 | ||
8882 | static const TranslatorOps tricore_tr_ops = { | |
8883 | .init_disas_context = tricore_tr_init_disas_context, | |
8884 | .tb_start = tricore_tr_tb_start, | |
8885 | .insn_start = tricore_tr_insn_start, | |
1fae1851 BK |
8886 | .translate_insn = tricore_tr_translate_insn, |
8887 | .tb_stop = tricore_tr_tb_stop, | |
8888 | .disas_log = tricore_tr_disas_log, | |
8889 | }; | |
8890 | ||
8891 | ||
8892 | void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) | |
8893 | { | |
8894 | DisasContext ctx; | |
8895 | translator_loop(&tricore_tr_ops, &ctx.base, cs, tb, max_insns); | |
48e06fe0 BK |
8896 | } |
8897 | ||
48e06fe0 | 8898 | void |
bad729e2 RH |
8899 | restore_state_to_opc(CPUTriCoreState *env, TranslationBlock *tb, |
8900 | target_ulong *data) | |
48e06fe0 | 8901 | { |
bad729e2 | 8902 | env->PC = data[0]; |
48e06fe0 BK |
8903 | } |
8904 | /* | |
8905 | * | |
8906 | * Initialization | |
8907 | * | |
8908 | */ | |
8909 | ||
8910 | void cpu_state_reset(CPUTriCoreState *env) | |
8911 | { | |
0aaeb118 BK |
8912 | /* Reset Regs to Default Value */ |
8913 | env->PSW = 0xb80; | |
996a729f | 8914 | fpu_set_state(env); |
0aaeb118 BK |
8915 | } |
8916 | ||
8917 | static void tricore_tcg_init_csfr(void) | |
8918 | { | |
e1ccc054 | 8919 | cpu_PCXI = tcg_global_mem_new(cpu_env, |
0aaeb118 | 8920 | offsetof(CPUTriCoreState, PCXI), "PCXI"); |
e1ccc054 | 8921 | cpu_PSW = tcg_global_mem_new(cpu_env, |
0aaeb118 | 8922 | offsetof(CPUTriCoreState, PSW), "PSW"); |
e1ccc054 | 8923 | cpu_PC = tcg_global_mem_new(cpu_env, |
0aaeb118 | 8924 | offsetof(CPUTriCoreState, PC), "PC"); |
e1ccc054 | 8925 | cpu_ICR = tcg_global_mem_new(cpu_env, |
0aaeb118 | 8926 | offsetof(CPUTriCoreState, ICR), "ICR"); |
48e06fe0 BK |
8927 | } |
8928 | ||
8929 | void tricore_tcg_init(void) | |
8930 | { | |
0aaeb118 | 8931 | int i; |
55c3ceef | 8932 | |
0aaeb118 BK |
8933 | /* reg init */ |
8934 | for (i = 0 ; i < 16 ; i++) { | |
e1ccc054 | 8935 | cpu_gpr_a[i] = tcg_global_mem_new(cpu_env, |
0aaeb118 BK |
8936 | offsetof(CPUTriCoreState, gpr_a[i]), |
8937 | regnames_a[i]); | |
8938 | } | |
8939 | for (i = 0 ; i < 16 ; i++) { | |
e1ccc054 | 8940 | cpu_gpr_d[i] = tcg_global_mem_new(cpu_env, |
0aaeb118 BK |
8941 | offsetof(CPUTriCoreState, gpr_d[i]), |
8942 | regnames_d[i]); | |
8943 | } | |
8944 | tricore_tcg_init_csfr(); | |
8945 | /* init PSW flag cache */ | |
e1ccc054 | 8946 | cpu_PSW_C = tcg_global_mem_new(cpu_env, |
0aaeb118 BK |
8947 | offsetof(CPUTriCoreState, PSW_USB_C), |
8948 | "PSW_C"); | |
e1ccc054 | 8949 | cpu_PSW_V = tcg_global_mem_new(cpu_env, |
0aaeb118 BK |
8950 | offsetof(CPUTriCoreState, PSW_USB_V), |
8951 | "PSW_V"); | |
e1ccc054 | 8952 | cpu_PSW_SV = tcg_global_mem_new(cpu_env, |
0aaeb118 BK |
8953 | offsetof(CPUTriCoreState, PSW_USB_SV), |
8954 | "PSW_SV"); | |
e1ccc054 | 8955 | cpu_PSW_AV = tcg_global_mem_new(cpu_env, |
0aaeb118 BK |
8956 | offsetof(CPUTriCoreState, PSW_USB_AV), |
8957 | "PSW_AV"); | |
e1ccc054 | 8958 | cpu_PSW_SAV = tcg_global_mem_new(cpu_env, |
0aaeb118 BK |
8959 | offsetof(CPUTriCoreState, PSW_USB_SAV), |
8960 | "PSW_SAV"); | |
48e06fe0 | 8961 | } |