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a4633e16 AF |
1 | /* |
2 | * QEMU Xtensa CPU | |
3 | * | |
4 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
5 | * All rights reserved. | |
6 | * | |
7 | * Redistribution and use in source and binary forms, with or without | |
8 | * modification, are permitted provided that the following conditions are met: | |
9 | * * Redistributions of source code must retain the above copyright | |
10 | * notice, this list of conditions and the following disclaimer. | |
11 | * * Redistributions in binary form must reproduce the above copyright | |
12 | * notice, this list of conditions and the following disclaimer in the | |
13 | * documentation and/or other materials provided with the distribution. | |
14 | * * Neither the name of the Open Source and Linux Lab nor the | |
15 | * names of its contributors may be used to endorse or promote products | |
16 | * derived from this software without specific prior written permission. | |
17 | * | |
18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY | |
22 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
23 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
24 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
25 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
27 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
28 | */ | |
29 | #ifndef QEMU_XTENSA_CPU_QOM_H | |
30 | #define QEMU_XTENSA_CPU_QOM_H | |
31 | ||
2e5b09fd | 32 | #include "hw/core/cpu.h" |
db1015e9 | 33 | #include "qom/object.h" |
a4633e16 AF |
34 | |
35 | #define TYPE_XTENSA_CPU "xtensa-cpu" | |
36 | ||
db1015e9 EH |
37 | typedef struct XtensaCPU XtensaCPU; |
38 | typedef struct XtensaCPUClass XtensaCPUClass; | |
8110fa1d EH |
39 | DECLARE_OBJ_CHECKERS(XtensaCPU, XtensaCPUClass, |
40 | XTENSA_CPU, TYPE_XTENSA_CPU) | |
a4633e16 | 41 | |
da374261 PB |
42 | typedef struct XtensaConfig XtensaConfig; |
43 | ||
a4633e16 AF |
44 | /** |
45 | * XtensaCPUClass: | |
5f6c9643 | 46 | * @parent_realize: The parent class' realize handler. |
a4633e16 | 47 | * @parent_reset: The parent class' reset handler. |
67cce561 | 48 | * @config: The CPU core configuration. |
a4633e16 AF |
49 | * |
50 | * An Xtensa CPU model. | |
51 | */ | |
db1015e9 | 52 | struct XtensaCPUClass { |
a4633e16 AF |
53 | /*< private >*/ |
54 | CPUClass parent_class; | |
55 | /*< public >*/ | |
56 | ||
5f6c9643 | 57 | DeviceRealize parent_realize; |
781c67ca | 58 | DeviceReset parent_reset; |
67cce561 AF |
59 | |
60 | const XtensaConfig *config; | |
db1015e9 | 61 | }; |
a4633e16 | 62 | |
97a8ea5a | 63 | |
a4633e16 | 64 | #endif |