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a4633e16 AF |
1 | /* |
2 | * QEMU Xtensa CPU | |
3 | * | |
5087a72c | 4 | * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. |
a4633e16 AF |
5 | * Copyright (c) 2012 SUSE LINUX Products GmbH |
6 | * All rights reserved. | |
7 | * | |
8 | * Redistribution and use in source and binary forms, with or without | |
9 | * modification, are permitted provided that the following conditions are met: | |
10 | * * Redistributions of source code must retain the above copyright | |
11 | * notice, this list of conditions and the following disclaimer. | |
12 | * * Redistributions in binary form must reproduce the above copyright | |
13 | * notice, this list of conditions and the following disclaimer in the | |
14 | * documentation and/or other materials provided with the distribution. | |
15 | * * Neither the name of the Open Source and Linux Lab nor the | |
16 | * names of its contributors may be used to endorse or promote products | |
17 | * derived from this software without specific prior written permission. | |
18 | * | |
19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
20 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY | |
23 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
24 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
26 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
28 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
29 | */ | |
30 | ||
09aae23d | 31 | #include "qemu/osdep.h" |
da34e65c | 32 | #include "qapi/error.h" |
15be3171 | 33 | #include "cpu.h" |
cfa9f051 | 34 | #include "fpu/softfloat.h" |
0b8fa32f | 35 | #include "qemu/module.h" |
004a5690 | 36 | #include "migration/vmstate.h" |
a4633e16 AF |
37 | |
38 | ||
f45748f1 AF |
39 | static void xtensa_cpu_set_pc(CPUState *cs, vaddr value) |
40 | { | |
41 | XtensaCPU *cpu = XTENSA_CPU(cs); | |
42 | ||
43 | cpu->env.pc = value; | |
44 | } | |
45 | ||
8c2e1b00 AF |
46 | static bool xtensa_cpu_has_work(CPUState *cs) |
47 | { | |
ba7651fb | 48 | #ifndef CONFIG_USER_ONLY |
8c2e1b00 AF |
49 | XtensaCPU *cpu = XTENSA_CPU(cs); |
50 | ||
bd527a83 | 51 | return !cpu->env.runstall && cpu->env.pending_irq_level; |
ba7651fb MF |
52 | #else |
53 | return true; | |
54 | #endif | |
8c2e1b00 AF |
55 | } |
56 | ||
130ea832 MF |
57 | #ifdef CONFIG_USER_ONLY |
58 | static bool abi_call0; | |
59 | ||
60 | void xtensa_set_abi_call0(void) | |
61 | { | |
62 | abi_call0 = true; | |
63 | } | |
64 | ||
65 | bool xtensa_abi_call0(void) | |
66 | { | |
67 | return abi_call0; | |
68 | } | |
69 | #endif | |
70 | ||
781c67ca | 71 | static void xtensa_cpu_reset(DeviceState *dev) |
a4633e16 | 72 | { |
781c67ca | 73 | CPUState *s = CPU(dev); |
a4633e16 AF |
74 | XtensaCPU *cpu = XTENSA_CPU(s); |
75 | XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(cpu); | |
76 | CPUXtensaState *env = &cpu->env; | |
cfa9f051 MF |
77 | bool dfpu = xtensa_option_enabled(env->config, |
78 | XTENSA_OPTION_DFP_COPROCESSOR); | |
a4633e16 | 79 | |
781c67ca | 80 | xcc->parent_reset(dev); |
a4633e16 | 81 | |
17ab14ac | 82 | env->pc = env->config->exception_vector[EXC_RESET0 + env->static_vectors]; |
5087a72c | 83 | env->sregs[LITBASE] &= ~1; |
ba7651fb | 84 | #ifndef CONFIG_USER_ONLY |
5087a72c AF |
85 | env->sregs[PS] = xtensa_option_enabled(env->config, |
86 | XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10; | |
ba7651fb MF |
87 | env->pending_irq_level = 0; |
88 | #else | |
130ea832 MF |
89 | env->sregs[PS] = PS_UM | (3 << PS_RING_SHIFT); |
90 | if (xtensa_option_enabled(env->config, | |
91 | XTENSA_OPTION_WINDOWED_REGISTER) && | |
92 | !xtensa_abi_call0()) { | |
93 | env->sregs[PS] |= PS_WOE; | |
94 | } | |
ab97f050 | 95 | env->sregs[CPENABLE] = 0xff; |
ba7651fb | 96 | #endif |
5087a72c AF |
97 | env->sregs[VECBASE] = env->config->vecbase; |
98 | env->sregs[IBREAKENABLE] = 0; | |
9e03ade4 | 99 | env->sregs[MEMCTL] = MEMCTL_IL0EN & env->config->memctl_mask; |
fcc803d1 MF |
100 | env->sregs[ATOMCTL] = xtensa_option_enabled(env->config, |
101 | XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15; | |
604e1f9c MF |
102 | env->sregs[CONFIGID0] = env->config->configid[0]; |
103 | env->sregs[CONFIGID1] = env->config->configid[1]; | |
b345e140 | 104 | env->exclusive_addr = -1; |
5087a72c | 105 | |
ba7651fb | 106 | #ifndef CONFIG_USER_ONLY |
5087a72c | 107 | reset_mmu(env); |
bd527a83 | 108 | s->halted = env->runstall; |
ba7651fb | 109 | #endif |
cfa9f051 MF |
110 | set_no_signaling_nans(!dfpu, &env->fp_status); |
111 | set_use_first_nan(!dfpu, &env->fp_status); | |
a4633e16 AF |
112 | } |
113 | ||
67cce561 AF |
114 | static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model) |
115 | { | |
116 | ObjectClass *oc; | |
117 | char *typename; | |
118 | ||
a5247d76 | 119 | typename = g_strdup_printf(XTENSA_CPU_TYPE_NAME("%s"), cpu_model); |
67cce561 AF |
120 | oc = object_class_by_name(typename); |
121 | g_free(typename); | |
122 | if (oc == NULL || !object_class_dynamic_cast(oc, TYPE_XTENSA_CPU) || | |
123 | object_class_is_abstract(oc)) { | |
124 | return NULL; | |
125 | } | |
126 | return oc; | |
127 | } | |
128 | ||
5a6539e6 MF |
129 | static void xtensa_cpu_disas_set_info(CPUState *cs, disassemble_info *info) |
130 | { | |
131 | XtensaCPU *cpu = XTENSA_CPU(cs); | |
132 | ||
133 | info->private_data = cpu->env.config->isa; | |
134 | info->print_insn = print_insn_xtensa; | |
135 | } | |
136 | ||
5f6c9643 AF |
137 | static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp) |
138 | { | |
a0e372f0 | 139 | CPUState *cs = CPU(dev); |
5f6c9643 | 140 | XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(dev); |
ce5b1bbf LV |
141 | Error *local_err = NULL; |
142 | ||
ba7651fb MF |
143 | #ifndef CONFIG_USER_ONLY |
144 | xtensa_irq_init(&XTENSA_CPU(dev)->env); | |
145 | #endif | |
8e36271b | 146 | |
ce5b1bbf LV |
147 | cpu_exec_realizefn(cs, &local_err); |
148 | if (local_err != NULL) { | |
149 | error_propagate(errp, local_err); | |
150 | return; | |
151 | } | |
5f6c9643 | 152 | |
a0e372f0 AF |
153 | cs->gdb_num_regs = xcc->config->gdb_regmap.num_regs; |
154 | ||
14a10fc3 AF |
155 | qemu_init_vcpu(cs); |
156 | ||
5f6c9643 AF |
157 | xcc->parent_realize(dev, errp); |
158 | } | |
159 | ||
e554bbc6 AF |
160 | static void xtensa_cpu_initfn(Object *obj) |
161 | { | |
162 | XtensaCPU *cpu = XTENSA_CPU(obj); | |
67cce561 | 163 | XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj); |
e554bbc6 AF |
164 | CPUXtensaState *env = &cpu->env; |
165 | ||
7506ed90 | 166 | cpu_set_cpustate_pointers(cpu); |
67cce561 | 167 | env->config = xcc->config; |
25733ead | 168 | |
ba7651fb | 169 | #ifndef CONFIG_USER_ONLY |
3a3c9dc4 MF |
170 | env->address_space_er = g_malloc(sizeof(*env->address_space_er)); |
171 | env->system_er = g_malloc(sizeof(*env->system_er)); | |
09d98b69 | 172 | memory_region_init_io(env->system_er, obj, NULL, env, "er", |
3a3c9dc4 MF |
173 | UINT64_C(0x100000000)); |
174 | address_space_init(env->address_space_er, env->system_er, "ER"); | |
ba7651fb | 175 | #endif |
e554bbc6 AF |
176 | } |
177 | ||
4336073b | 178 | #ifndef CONFIG_USER_ONLY |
004a5690 AF |
179 | static const VMStateDescription vmstate_xtensa_cpu = { |
180 | .name = "cpu", | |
181 | .unmigratable = 1, | |
182 | }; | |
8b80bd28 PMD |
183 | |
184 | #include "hw/core/sysemu-cpu-ops.h" | |
185 | ||
186 | static const struct SysemuCPUOps xtensa_sysemu_ops = { | |
08928c6d | 187 | .get_phys_page_debug = xtensa_cpu_get_phys_page_debug, |
8b80bd28 | 188 | }; |
4336073b | 189 | #endif |
004a5690 | 190 | |
78271684 CF |
191 | #include "hw/core/tcg-cpu-ops.h" |
192 | ||
11906557 | 193 | static const struct TCGCPUOps xtensa_tcg_ops = { |
78271684 | 194 | .initialize = xtensa_translate_init, |
78271684 CF |
195 | .debug_excp_handler = xtensa_breakpoint_handler, |
196 | ||
197 | #ifndef CONFIG_USER_ONLY | |
6407f64f | 198 | .tlb_fill = xtensa_cpu_tlb_fill, |
f364a7f9 | 199 | .cpu_exec_interrupt = xtensa_cpu_exec_interrupt, |
78271684 CF |
200 | .do_interrupt = xtensa_cpu_do_interrupt, |
201 | .do_transaction_failed = xtensa_cpu_do_transaction_failed, | |
202 | .do_unaligned_access = xtensa_cpu_do_unaligned_access, | |
203 | #endif /* !CONFIG_USER_ONLY */ | |
204 | }; | |
205 | ||
a4633e16 AF |
206 | static void xtensa_cpu_class_init(ObjectClass *oc, void *data) |
207 | { | |
004a5690 | 208 | DeviceClass *dc = DEVICE_CLASS(oc); |
a4633e16 AF |
209 | CPUClass *cc = CPU_CLASS(oc); |
210 | XtensaCPUClass *xcc = XTENSA_CPU_CLASS(cc); | |
211 | ||
bf853881 PMD |
212 | device_class_set_parent_realize(dc, xtensa_cpu_realizefn, |
213 | &xcc->parent_realize); | |
5f6c9643 | 214 | |
781c67ca | 215 | device_class_set_parent_reset(dc, xtensa_cpu_reset, &xcc->parent_reset); |
004a5690 | 216 | |
67cce561 | 217 | cc->class_by_name = xtensa_cpu_class_by_name; |
8c2e1b00 | 218 | cc->has_work = xtensa_cpu_has_work; |
878096ee | 219 | cc->dump_state = xtensa_cpu_dump_state; |
f45748f1 | 220 | cc->set_pc = xtensa_cpu_set_pc; |
5b50e790 AF |
221 | cc->gdb_read_register = xtensa_cpu_gdb_read_register; |
222 | cc->gdb_write_register = xtensa_cpu_gdb_write_register; | |
2472b6c0 | 223 | cc->gdb_stop_before_watchpoint = true; |
b008c456 | 224 | #ifndef CONFIG_USER_ONLY |
8b80bd28 | 225 | cc->sysemu_ops = &xtensa_sysemu_ops; |
4336073b | 226 | dc->vmsd = &vmstate_xtensa_cpu; |
00b941e5 | 227 | #endif |
5a6539e6 | 228 | cc->disas_set_info = xtensa_cpu_disas_set_info; |
78271684 | 229 | cc->tcg_ops = &xtensa_tcg_ops; |
a4633e16 AF |
230 | } |
231 | ||
232 | static const TypeInfo xtensa_cpu_type_info = { | |
233 | .name = TYPE_XTENSA_CPU, | |
234 | .parent = TYPE_CPU, | |
235 | .instance_size = sizeof(XtensaCPU), | |
e554bbc6 | 236 | .instance_init = xtensa_cpu_initfn, |
67cce561 | 237 | .abstract = true, |
a4633e16 AF |
238 | .class_size = sizeof(XtensaCPUClass), |
239 | .class_init = xtensa_cpu_class_init, | |
240 | }; | |
241 | ||
242 | static void xtensa_cpu_register_types(void) | |
243 | { | |
244 | type_register_static(&xtensa_cpu_type_info); | |
245 | } | |
246 | ||
247 | type_init(xtensa_cpu_register_types) |