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qom: Introduce CPUClass.tcg_initialize
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1/*
2 * QEMU Xtensa CPU
3 *
5087a72c 4 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
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5 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
09aae23d 31#include "qemu/osdep.h"
da34e65c 32#include "qapi/error.h"
15be3171 33#include "cpu.h"
a4633e16 34#include "qemu-common.h"
004a5690 35#include "migration/vmstate.h"
63c91552 36#include "exec/exec-all.h"
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37
38
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39static void xtensa_cpu_set_pc(CPUState *cs, vaddr value)
40{
41 XtensaCPU *cpu = XTENSA_CPU(cs);
42
43 cpu->env.pc = value;
44}
45
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46static bool xtensa_cpu_has_work(CPUState *cs)
47{
48 XtensaCPU *cpu = XTENSA_CPU(cs);
49
bd527a83 50 return !cpu->env.runstall && cpu->env.pending_irq_level;
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51}
52
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53/* CPUClass::reset() */
54static void xtensa_cpu_reset(CPUState *s)
55{
56 XtensaCPU *cpu = XTENSA_CPU(s);
57 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(cpu);
58 CPUXtensaState *env = &cpu->env;
59
60 xcc->parent_reset(s);
61
5087a72c 62 env->exception_taken = 0;
17ab14ac 63 env->pc = env->config->exception_vector[EXC_RESET0 + env->static_vectors];
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64 env->sregs[LITBASE] &= ~1;
65 env->sregs[PS] = xtensa_option_enabled(env->config,
66 XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10;
67 env->sregs[VECBASE] = env->config->vecbase;
68 env->sregs[IBREAKENABLE] = 0;
9e03ade4 69 env->sregs[MEMCTL] = MEMCTL_IL0EN & env->config->memctl_mask;
4e41d2f5 70 env->sregs[CACHEATTR] = 0x22222222;
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71 env->sregs[ATOMCTL] = xtensa_option_enabled(env->config,
72 XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15;
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73 env->sregs[CONFIGID0] = env->config->configid[0];
74 env->sregs[CONFIGID1] = env->config->configid[1];
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75
76 env->pending_irq_level = 0;
77 reset_mmu(env);
bd527a83 78 s->halted = env->runstall;
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79}
80
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81static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model)
82{
83 ObjectClass *oc;
84 char *typename;
85
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86 typename = g_strdup_printf("%s-" TYPE_XTENSA_CPU, cpu_model);
87 oc = object_class_by_name(typename);
88 g_free(typename);
89 if (oc == NULL || !object_class_dynamic_cast(oc, TYPE_XTENSA_CPU) ||
90 object_class_is_abstract(oc)) {
91 return NULL;
92 }
93 return oc;
94}
95
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96static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp)
97{
a0e372f0 98 CPUState *cs = CPU(dev);
8e36271b 99 XtensaCPU *cpu = XTENSA_CPU(dev);
5f6c9643 100 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(dev);
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101 Error *local_err = NULL;
102
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103 xtensa_irq_init(&cpu->env);
104
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105 cpu_exec_realizefn(cs, &local_err);
106 if (local_err != NULL) {
107 error_propagate(errp, local_err);
108 return;
109 }
5f6c9643 110
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111 cs->gdb_num_regs = xcc->config->gdb_regmap.num_regs;
112
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113 qemu_init_vcpu(cs);
114
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115 xcc->parent_realize(dev, errp);
116}
117
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118static void xtensa_cpu_initfn(Object *obj)
119{
c05efcb1 120 CPUState *cs = CPU(obj);
e554bbc6 121 XtensaCPU *cpu = XTENSA_CPU(obj);
67cce561 122 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj);
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123 CPUXtensaState *env = &cpu->env;
124
c05efcb1 125 cs->env_ptr = env;
67cce561 126 env->config = xcc->config;
25733ead 127
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128 env->address_space_er = g_malloc(sizeof(*env->address_space_er));
129 env->system_er = g_malloc(sizeof(*env->system_er));
130 memory_region_init_io(env->system_er, NULL, NULL, env, "er",
131 UINT64_C(0x100000000));
132 address_space_init(env->address_space_er, env->system_er, "ER");
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133}
134
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135static const VMStateDescription vmstate_xtensa_cpu = {
136 .name = "cpu",
137 .unmigratable = 1,
138};
139
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140static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
141{
004a5690 142 DeviceClass *dc = DEVICE_CLASS(oc);
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143 CPUClass *cc = CPU_CLASS(oc);
144 XtensaCPUClass *xcc = XTENSA_CPU_CLASS(cc);
145
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146 xcc->parent_realize = dc->realize;
147 dc->realize = xtensa_cpu_realizefn;
148
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149 xcc->parent_reset = cc->reset;
150 cc->reset = xtensa_cpu_reset;
004a5690 151
67cce561 152 cc->class_by_name = xtensa_cpu_class_by_name;
8c2e1b00 153 cc->has_work = xtensa_cpu_has_work;
97a8ea5a 154 cc->do_interrupt = xtensa_cpu_do_interrupt;
37f3616a 155 cc->cpu_exec_interrupt = xtensa_cpu_exec_interrupt;
878096ee 156 cc->dump_state = xtensa_cpu_dump_state;
f45748f1 157 cc->set_pc = xtensa_cpu_set_pc;
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158 cc->gdb_read_register = xtensa_cpu_gdb_read_register;
159 cc->gdb_write_register = xtensa_cpu_gdb_write_register;
2472b6c0 160 cc->gdb_stop_before_watchpoint = true;
00b941e5 161#ifndef CONFIG_USER_ONLY
93e22326 162 cc->do_unaligned_access = xtensa_cpu_do_unaligned_access;
00b941e5 163 cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
4246e225 164 cc->do_unassigned_access = xtensa_cpu_do_unassigned_access;
00b941e5 165#endif
86025ee4 166 cc->debug_excp_handler = xtensa_breakpoint_handler;
55c3ceef 167 cc->tcg_initialize = xtensa_translate_init;
004a5690 168 dc->vmsd = &vmstate_xtensa_cpu;
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169}
170
171static const TypeInfo xtensa_cpu_type_info = {
172 .name = TYPE_XTENSA_CPU,
173 .parent = TYPE_CPU,
174 .instance_size = sizeof(XtensaCPU),
e554bbc6 175 .instance_init = xtensa_cpu_initfn,
67cce561 176 .abstract = true,
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177 .class_size = sizeof(XtensaCPUClass),
178 .class_init = xtensa_cpu_class_init,
179};
180
181static void xtensa_cpu_register_types(void)
182{
183 type_register_static(&xtensa_cpu_type_info);
184}
185
186type_init(xtensa_cpu_register_types)