[mirror_qemu.git] / target / xtensa / cpu.h

/*
 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in the
 *       documentation and/or other materials provided with the distribution.
 *     * Neither the name of the Open Source and Linux Lab nor the
 *       names of its contributors may be used to endorse or promote products
 *       derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef XTENSA_CPU_H
#define XTENSA_CPU_H

#define ALIGNED_ONLY
#define TARGET_LONG_BITS 32

#define CPUArchState struct CPUXtensaState

#include "qemu-common.h"
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#include "fpu/softfloat.h"

#define NB_MMU_MODES 4

#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
#define TARGET_PAGE_BITS 12

enum {
    /* Additional instructions */
    XTENSA_OPTION_CODE_DENSITY,
    XTENSA_OPTION_LOOP,
    XTENSA_OPTION_EXTENDED_L32R,
    XTENSA_OPTION_16_BIT_IMUL,
    XTENSA_OPTION_32_BIT_IMUL,
    XTENSA_OPTION_32_BIT_IMUL_HIGH,
    XTENSA_OPTION_32_BIT_IDIV,
    XTENSA_OPTION_MAC16,
    XTENSA_OPTION_MISC_OP_NSA,
    XTENSA_OPTION_MISC_OP_MINMAX,
    XTENSA_OPTION_MISC_OP_SEXT,
    XTENSA_OPTION_MISC_OP_CLAMPS,
    XTENSA_OPTION_COPROCESSOR,
    XTENSA_OPTION_BOOLEAN,
    XTENSA_OPTION_FP_COPROCESSOR,
    XTENSA_OPTION_MP_SYNCHRO,
    XTENSA_OPTION_CONDITIONAL_STORE,
    XTENSA_OPTION_ATOMCTL,
    XTENSA_OPTION_DEPBITS,

    /* Interrupts and exceptions */
    XTENSA_OPTION_EXCEPTION,
    XTENSA_OPTION_RELOCATABLE_VECTOR,
    XTENSA_OPTION_UNALIGNED_EXCEPTION,
    XTENSA_OPTION_INTERRUPT,
    XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
    XTENSA_OPTION_TIMER_INTERRUPT,

    /* Local memory */
    XTENSA_OPTION_ICACHE,
    XTENSA_OPTION_ICACHE_TEST,
    XTENSA_OPTION_ICACHE_INDEX_LOCK,
    XTENSA_OPTION_DCACHE,
    XTENSA_OPTION_DCACHE_TEST,
    XTENSA_OPTION_DCACHE_INDEX_LOCK,
    XTENSA_OPTION_IRAM,
    XTENSA_OPTION_IROM,
    XTENSA_OPTION_DRAM,
    XTENSA_OPTION_DROM,
    XTENSA_OPTION_XLMI,
    XTENSA_OPTION_HW_ALIGNMENT,
    XTENSA_OPTION_MEMORY_ECC_PARITY,

    /* Memory protection and translation */
    XTENSA_OPTION_REGION_PROTECTION,
    XTENSA_OPTION_REGION_TRANSLATION,
    XTENSA_OPTION_MMU,
    XTENSA_OPTION_CACHEATTR,

    /* Other */
    XTENSA_OPTION_WINDOWED_REGISTER,
    XTENSA_OPTION_PROCESSOR_INTERFACE,
    XTENSA_OPTION_MISC_SR,
    XTENSA_OPTION_THREAD_POINTER,
    XTENSA_OPTION_PROCESSOR_ID,
    XTENSA_OPTION_DEBUG,
    XTENSA_OPTION_TRACE_PORT,
    XTENSA_OPTION_EXTERN_REGS,
};

enum {
    THREADPTR = 231,
    FCR = 232,
    FSR = 233,
};

enum {
    LBEG = 0,
    LEND = 1,
    LCOUNT = 2,
    SAR = 3,
    BR = 4,
    LITBASE = 5,
    SCOMPARE1 = 12,
    ACCLO = 16,
    ACCHI = 17,
    MR = 32,
    WINDOW_BASE = 72,
    WINDOW_START = 73,
    PTEVADDR = 83,
    RASID = 90,
    ITLBCFG = 91,
    DTLBCFG = 92,
    IBREAKENABLE = 96,
    MEMCTL = 97,
    CACHEATTR = 98,
    ATOMCTL = 99,
    IBREAKA = 128,
    DBREAKA = 144,
    DBREAKC = 160,
    CONFIGID0 = 176,
    EPC1 = 177,
    DEPC = 192,
    EPS2 = 194,
    CONFIGID1 = 208,
    EXCSAVE1 = 209,
    CPENABLE = 224,
    INTSET = 226,
    INTCLEAR = 227,
    INTENABLE = 228,
    PS = 230,
    VECBASE = 231,
    EXCCAUSE = 232,
    DEBUGCAUSE = 233,
    CCOUNT = 234,
    PRID = 235,
    ICOUNT = 236,
    ICOUNTLEVEL = 237,
    EXCVADDR = 238,
    CCOMPARE = 240,
    MISC = 244,
};

#define PS_INTLEVEL 0xf
#define PS_INTLEVEL_SHIFT 0

#define PS_EXCM 0x10
#define PS_UM 0x20

#define PS_RING 0xc0
#define PS_RING_SHIFT 6

#define PS_OWB 0xf00
#define PS_OWB_SHIFT 8

#define PS_CALLINC 0x30000
#define PS_CALLINC_SHIFT 16
#define PS_CALLINC_LEN 2

#define PS_WOE 0x40000

#define DEBUGCAUSE_IC 0x1
#define DEBUGCAUSE_IB 0x2
#define DEBUGCAUSE_DB 0x4
#define DEBUGCAUSE_BI 0x8
#define DEBUGCAUSE_BN 0x10
#define DEBUGCAUSE_DI 0x20
#define DEBUGCAUSE_DBNUM 0xf00
#define DEBUGCAUSE_DBNUM_SHIFT 8

#define DBREAKC_SB 0x80000000
#define DBREAKC_LB 0x40000000
#define DBREAKC_SB_LB (DBREAKC_SB | DBREAKC_LB)
#define DBREAKC_MASK 0x3f

#define MEMCTL_INIT 0x00800000
#define MEMCTL_IUSEWAYS_SHIFT 18
#define MEMCTL_IUSEWAYS_LEN 5
#define MEMCTL_IUSEWAYS_MASK 0x007c0000
#define MEMCTL_DALLOCWAYS_SHIFT 13
#define MEMCTL_DALLOCWAYS_LEN 5
#define MEMCTL_DALLOCWAYS_MASK 0x0003e000
#define MEMCTL_DUSEWAYS_SHIFT 8
#define MEMCTL_DUSEWAYS_LEN 5
#define MEMCTL_DUSEWAYS_MASK 0x00001f00
#define MEMCTL_ISNP 0x4
#define MEMCTL_DSNP 0x2
#define MEMCTL_IL0EN 0x1

#define MAX_NAREG 64
#define MAX_NINTERRUPT 32
#define MAX_NLEVEL 6
#define MAX_NNMI 1
#define MAX_NCCOMPARE 3
#define MAX_TLB_WAY_SIZE 8
#define MAX_NDBREAK 2
#define MAX_NMEMORY 4

#define REGION_PAGE_MASK 0xe0000000

#define PAGE_CACHE_MASK    0x700
#define PAGE_CACHE_SHIFT   8
#define PAGE_CACHE_INVALID 0x000
#define PAGE_CACHE_BYPASS  0x100
#define PAGE_CACHE_WT      0x200
#define PAGE_CACHE_WB      0x400
#define PAGE_CACHE_ISOLATE 0x600

enum {
    /* Static vectors */
    EXC_RESET0,
    EXC_RESET1,
    EXC_MEMORY_ERROR,

    /* Dynamic vectors */
    EXC_WINDOW_OVERFLOW4,
    EXC_WINDOW_UNDERFLOW4,
    EXC_WINDOW_OVERFLOW8,
    EXC_WINDOW_UNDERFLOW8,
    EXC_WINDOW_OVERFLOW12,
    EXC_WINDOW_UNDERFLOW12,
    EXC_IRQ,
    EXC_KERNEL,
    EXC_USER,
    EXC_DOUBLE,
    EXC_DEBUG,
    EXC_MAX
};

enum {
    ILLEGAL_INSTRUCTION_CAUSE = 0,
    SYSCALL_CAUSE,
    INSTRUCTION_FETCH_ERROR_CAUSE,
    LOAD_STORE_ERROR_CAUSE,
    LEVEL1_INTERRUPT_CAUSE,
    ALLOCA_CAUSE,
    INTEGER_DIVIDE_BY_ZERO_CAUSE,
    PRIVILEGED_CAUSE = 8,
    LOAD_STORE_ALIGNMENT_CAUSE,

    INSTR_PIF_DATA_ERROR_CAUSE = 12,
    LOAD_STORE_PIF_DATA_ERROR_CAUSE,
    INSTR_PIF_ADDR_ERROR_CAUSE,
    LOAD_STORE_PIF_ADDR_ERROR_CAUSE,

    INST_TLB_MISS_CAUSE,
    INST_TLB_MULTI_HIT_CAUSE,
    INST_FETCH_PRIVILEGE_CAUSE,
    INST_FETCH_PROHIBITED_CAUSE = 20,
    LOAD_STORE_TLB_MISS_CAUSE = 24,
    LOAD_STORE_TLB_MULTI_HIT_CAUSE,
    LOAD_STORE_PRIVILEGE_CAUSE,
    LOAD_PROHIBITED_CAUSE = 28,
    STORE_PROHIBITED_CAUSE,

    COPROCESSOR0_DISABLED = 32,
};

typedef enum {
    INTTYPE_LEVEL,
    INTTYPE_EDGE,
    INTTYPE_NMI,
    INTTYPE_SOFTWARE,
    INTTYPE_TIMER,
    INTTYPE_DEBUG,
    INTTYPE_WRITE_ERR,
    INTTYPE_PROFILING,
    INTTYPE_MAX
} interrupt_type;

struct CPUXtensaState;

typedef struct xtensa_tlb_entry {
    uint32_t vaddr;
    uint32_t paddr;
    uint8_t asid;
    uint8_t attr;
    bool variable;
} xtensa_tlb_entry;

typedef struct xtensa_tlb {
    unsigned nways;
    const unsigned way_size[10];
    bool varway56;
    unsigned nrefillentries;
} xtensa_tlb;

typedef struct XtensaGdbReg {
    int targno;
    int type;
    int group;
    unsigned size;
} XtensaGdbReg;

typedef struct XtensaGdbRegmap {
    int num_regs;
    int num_core_regs;
    /* PC + a + ar + sr + ur */
    XtensaGdbReg reg[1 + 16 + 64 + 256 + 256];
} XtensaGdbRegmap;

typedef struct XtensaCcompareTimer {
    struct CPUXtensaState *env;
    QEMUTimer *timer;
} XtensaCcompareTimer;

typedef struct XtensaMemory {
    unsigned num;
    struct XtensaMemoryRegion {
        uint32_t addr;
        uint32_t size;
    } location[MAX_NMEMORY];
} XtensaMemory;

struct XtensaConfig {
    const char *name;
    uint64_t options;
    XtensaGdbRegmap gdb_regmap;
    unsigned nareg;
    int excm_level;
    int ndepc;
    uint32_t vecbase;
    uint32_t exception_vector[EXC_MAX];
    unsigned ninterrupt;
    unsigned nlevel;
    uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1];
    uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1];
    uint32_t inttype_mask[INTTYPE_MAX];
    struct {
        uint32_t level;
        interrupt_type inttype;
    } interrupt[MAX_NINTERRUPT];
    unsigned nccompare;
    uint32_t timerint[MAX_NCCOMPARE];
    unsigned nextint;
    unsigned extint[MAX_NINTERRUPT];

    unsigned debug_level;
    unsigned nibreak;
    unsigned ndbreak;

    unsigned icache_ways;
    unsigned dcache_ways;
    uint32_t memctl_mask;

    XtensaMemory instrom;
    XtensaMemory instram;
    XtensaMemory datarom;
    XtensaMemory dataram;
    XtensaMemory sysrom;
    XtensaMemory sysram;

    uint32_t configid[2];

    uint32_t clock_freq_khz;

    xtensa_tlb itlb;
    xtensa_tlb dtlb;
};

typedef struct XtensaConfigList {
    const XtensaConfig *config;
    struct XtensaConfigList *next;
} XtensaConfigList;

#ifdef HOST_WORDS_BIGENDIAN
enum {
    FP_F32_HIGH,
    FP_F32_LOW,
};
#else
enum {
    FP_F32_LOW,
    FP_F32_HIGH,
};
#endif

typedef struct CPUXtensaState {
    const XtensaConfig *config;
    uint32_t regs[16];
    uint32_t pc;
    uint32_t sregs[256];
    uint32_t uregs[256];
    uint32_t phys_regs[MAX_NAREG];
    union {
        float32 f32[2];
        float64 f64;
    } fregs[16];
    float_status fp_status;

    xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE];
    xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE];
    unsigned autorefill_idx;
    bool runstall;
    AddressSpace *address_space_er;
    MemoryRegion *system_er;
    int pending_irq_level; /* level of last raised IRQ */
    void **irq_inputs;
    XtensaCcompareTimer ccompare[MAX_NCCOMPARE];
    uint64_t time_base;
    uint64_t ccount_time;
    uint32_t ccount_base;

    int exception_taken;
    int yield_needed;
    unsigned static_vectors;

    /* Watchpoints for DBREAK registers */
    struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK];

    CPU_COMMON
} CPUXtensaState;

/**
 * XtensaCPU:
 * @env: #CPUXtensaState
 *
 * An Xtensa CPU.
 */
struct XtensaCPU {
    /*< private >*/
    CPUState parent_obj;
    /*< public >*/

    CPUXtensaState env;
};

static inline XtensaCPU *xtensa_env_get_cpu(const CPUXtensaState *env)
{
    return container_of(env, XtensaCPU, env);
}

#define ENV_GET_CPU(e) CPU(xtensa_env_get_cpu(e))

#define ENV_OFFSET offsetof(XtensaCPU, env)

void xtensa_cpu_do_interrupt(CPUState *cpu);
bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request);
void xtensa_cpu_do_unassigned_access(CPUState *cpu, hwaddr addr,
                                     bool is_write, bool is_exec, int opaque,
                                     unsigned size);
void xtensa_cpu_dump_state(CPUState *cpu, FILE *f,
                           fprintf_function cpu_fprintf, int flags);
hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
int xtensa_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
int xtensa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
                                    MMUAccessType access_type,
                                    int mmu_idx, uintptr_t retaddr);

#define cpu_signal_handler cpu_xtensa_signal_handler
#define cpu_list xtensa_cpu_list

#ifdef TARGET_WORDS_BIGENDIAN
#define XTENSA_DEFAULT_CPU_MODEL "fsf"
#else
#define XTENSA_DEFAULT_CPU_MODEL "dc232b"
#endif

#define cpu_init(cpu_model) cpu_generic_init(TYPE_XTENSA_CPU, cpu_model)

void xtensa_translate_init(void);
void xtensa_breakpoint_handler(CPUState *cs);
void xtensa_finalize_config(XtensaConfig *config);
void xtensa_register_core(XtensaConfigList *node);
void xtensa_sim_open_console(Chardev *chr);
void check_interrupts(CPUXtensaState *s);
void xtensa_irq_init(CPUXtensaState *env);
void *xtensa_get_extint(CPUXtensaState *env, unsigned extint);
void xtensa_timer_irq(CPUXtensaState *env, uint32_t id, uint32_t active);
int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc);
void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf);
void xtensa_sync_window_from_phys(CPUXtensaState *env);
void xtensa_sync_phys_from_window(CPUXtensaState *env);
uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way);
void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb,
        uint32_t *vpn, uint32_t wi, uint32_t *ei);
int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
        uint32_t *pwi, uint32_t *pei, uint8_t *pring);
void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
        xtensa_tlb_entry *entry, bool dtlb,
        unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
        unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
        uint32_t vaddr, int is_write, int mmu_idx,
        uint32_t *paddr, uint32_t *page_size, unsigned *access);
void reset_mmu(CPUXtensaState *env);
void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env);
void debug_exception_env(CPUXtensaState *new_env, uint32_t cause);
static inline MemoryRegion *xtensa_get_er_region(CPUXtensaState *env)
{
    return env->system_er;
}

static inline void xtensa_select_static_vectors(CPUXtensaState *env,
                                                unsigned n)
{
    assert(n < 2);
    env->static_vectors = n;
}
void xtensa_runstall(CPUXtensaState *env, bool runstall);

#define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
#define XTENSA_OPTION_ALL (~(uint64_t)0)

static inline bool xtensa_option_bits_enabled(const XtensaConfig *config,
        uint64_t opt)
{
    return (config->options & opt) != 0;
}

static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt)
{
    return xtensa_option_bits_enabled(config, XTENSA_OPTION_BIT(opt));
}

static inline int xtensa_get_cintlevel(const CPUXtensaState *env)
{
    int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT;
    if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) {
        level = env->config->excm_level;
    }
    return level;
}

static inline int xtensa_get_ring(const CPUXtensaState *env)
{
    if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
        return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
    } else {
        return 0;
    }
}

static inline int xtensa_get_cring(const CPUXtensaState *env)
{
    if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) &&
            (env->sregs[PS] & PS_EXCM) == 0) {
        return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
    } else {
        return 0;
    }
}

static inline xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env,
        bool dtlb, unsigned wi, unsigned ei)
{
    return dtlb ?
        env->dtlb[wi] + ei :
        env->itlb[wi] + ei;
}

static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env)
{
    return env->sregs[WINDOW_START] |
        (env->sregs[WINDOW_START] << env->config->nareg / 4);
}

/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _ring0
#define MMU_MODE1_SUFFIX _ring1
#define MMU_MODE2_SUFFIX _ring2
#define MMU_MODE3_SUFFIX _ring3

static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch)
{
    return xtensa_get_cring(env);
}

#define XTENSA_TBFLAG_RING_MASK 0x3
#define XTENSA_TBFLAG_EXCM 0x4
#define XTENSA_TBFLAG_LITBASE 0x8
#define XTENSA_TBFLAG_DEBUG 0x10
#define XTENSA_TBFLAG_ICOUNT 0x20
#define XTENSA_TBFLAG_CPENABLE_MASK 0x3fc0
#define XTENSA_TBFLAG_CPENABLE_SHIFT 6
#define XTENSA_TBFLAG_EXCEPTION 0x4000
#define XTENSA_TBFLAG_WINDOW_MASK 0x18000
#define XTENSA_TBFLAG_WINDOW_SHIFT 15
#define XTENSA_TBFLAG_YIELD 0x20000

static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
        target_ulong *cs_base, uint32_t *flags)
{
    CPUState *cs = CPU(xtensa_env_get_cpu(env));

    *pc = env->pc;
    *cs_base = 0;
    *flags = 0;
    *flags |= xtensa_get_ring(env);
    if (env->sregs[PS] & PS_EXCM) {
        *flags |= XTENSA_TBFLAG_EXCM;
    }
    if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&
            (env->sregs[LITBASE] & 1)) {
        *flags |= XTENSA_TBFLAG_LITBASE;
    }
    if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) {
        if (xtensa_get_cintlevel(env) < env->config->debug_level) {
            *flags |= XTENSA_TBFLAG_DEBUG;
        }
        if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) {
            *flags |= XTENSA_TBFLAG_ICOUNT;
        }
    }
    if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) {
        *flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT;
    }
    if (cs->singlestep_enabled && env->exception_taken) {
        *flags |= XTENSA_TBFLAG_EXCEPTION;
    }
    if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER) &&
        (env->sregs[PS] & (PS_WOE | PS_EXCM)) == PS_WOE) {
        uint32_t windowstart = xtensa_replicate_windowstart(env) >>
            (env->sregs[WINDOW_BASE] + 1);
        uint32_t w = ctz32(windowstart | 0x8);

        *flags |= w << XTENSA_TBFLAG_WINDOW_SHIFT;
    } else {
        *flags |= 3 << XTENSA_TBFLAG_WINDOW_SHIFT;
    }
    if (env->yield_needed) {
        *flags |= XTENSA_TBFLAG_YIELD;
    }
}

#include "exec/cpu-all.h"

#endif
Commit	Line	Data
2328826b MF	1	/*
	2	* Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
	3	* All rights reserved.
	4	*
	5	* Redistribution and use in source and binary forms, with or without
	6	* modification, are permitted provided that the following conditions are met:
	7	* * Redistributions of source code must retain the above copyright
	8	* notice, this list of conditions and the following disclaimer.
	9	* * Redistributions in binary form must reproduce the above copyright
	10	* notice, this list of conditions and the following disclaimer in the
	11	* documentation and/or other materials provided with the distribution.
	12	* * Neither the name of the Open Source and Linux Lab nor the
	13	* names of its contributors may be used to endorse or promote products
	14	* derived from this software without specific prior written permission.
	15	*
	16	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	17	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	18	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	19	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
	20	* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	21	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	22	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
	23	* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	24	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	25	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	26	*/
	27
07f5a258 MA	28	#ifndef XTENSA_CPU_H
07f5a258 MA	29	#define XTENSA_CPU_H
2328826b	30
d94f0a8e	31	#define ALIGNED_ONLY
2328826b	32	#define TARGET_LONG_BITS 32
2328826b	33
9349b4f9	34	#define CPUArchState struct CPUXtensaState
2328826b	35
2328826b	36	#include "qemu-common.h"
da374261	37	#include "cpu-qom.h"
022c62cb	38	#include "exec/cpu-defs.h"
dd519cbe	39	#include "fpu/softfloat.h"
2328826b	40
2328826b MF	41	#define NB_MMU_MODES 4
	42
	43	#define TARGET_PHYS_ADDR_SPACE_BITS 32
	44	#define TARGET_VIRT_ADDR_SPACE_BITS 32
	45	#define TARGET_PAGE_BITS 12
	46
dedc5eae MF	47	enum {
	48	/* Additional instructions */
	49	XTENSA_OPTION_CODE_DENSITY,
	50	XTENSA_OPTION_LOOP,
	51	XTENSA_OPTION_EXTENDED_L32R,
	52	XTENSA_OPTION_16_BIT_IMUL,
	53	XTENSA_OPTION_32_BIT_IMUL,
7f65f4b0	54	XTENSA_OPTION_32_BIT_IMUL_HIGH,
dedc5eae MF	55	XTENSA_OPTION_32_BIT_IDIV,
dedc5eae MF	56	XTENSA_OPTION_MAC16,
7f65f4b0 MF	57	XTENSA_OPTION_MISC_OP_NSA,
	58	XTENSA_OPTION_MISC_OP_MINMAX,
	59	XTENSA_OPTION_MISC_OP_SEXT,
	60	XTENSA_OPTION_MISC_OP_CLAMPS,
dedc5eae MF	61	XTENSA_OPTION_COPROCESSOR,
	62	XTENSA_OPTION_BOOLEAN,
	63	XTENSA_OPTION_FP_COPROCESSOR,
	64	XTENSA_OPTION_MP_SYNCHRO,
	65	XTENSA_OPTION_CONDITIONAL_STORE,
fcc803d1	66	XTENSA_OPTION_ATOMCTL,
5eeb40c5	67	XTENSA_OPTION_DEPBITS,
dedc5eae MF	68
	69	/* Interrupts and exceptions */
	70	XTENSA_OPTION_EXCEPTION,
	71	XTENSA_OPTION_RELOCATABLE_VECTOR,
	72	XTENSA_OPTION_UNALIGNED_EXCEPTION,
	73	XTENSA_OPTION_INTERRUPT,
	74	XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
	75	XTENSA_OPTION_TIMER_INTERRUPT,
	76
	77	/* Local memory */
	78	XTENSA_OPTION_ICACHE,
	79	XTENSA_OPTION_ICACHE_TEST,
	80	XTENSA_OPTION_ICACHE_INDEX_LOCK,
	81	XTENSA_OPTION_DCACHE,
	82	XTENSA_OPTION_DCACHE_TEST,
	83	XTENSA_OPTION_DCACHE_INDEX_LOCK,
	84	XTENSA_OPTION_IRAM,
	85	XTENSA_OPTION_IROM,
	86	XTENSA_OPTION_DRAM,
	87	XTENSA_OPTION_DROM,
	88	XTENSA_OPTION_XLMI,
	89	XTENSA_OPTION_HW_ALIGNMENT,
	90	XTENSA_OPTION_MEMORY_ECC_PARITY,
	91
	92	/* Memory protection and translation */
	93	XTENSA_OPTION_REGION_PROTECTION,
	94	XTENSA_OPTION_REGION_TRANSLATION,
	95	XTENSA_OPTION_MMU,
4e41d2f5	96	XTENSA_OPTION_CACHEATTR,
dedc5eae MF	97
	98	/* Other */
	99	XTENSA_OPTION_WINDOWED_REGISTER,
	100	XTENSA_OPTION_PROCESSOR_INTERFACE,
	101	XTENSA_OPTION_MISC_SR,
	102	XTENSA_OPTION_THREAD_POINTER,
	103	XTENSA_OPTION_PROCESSOR_ID,
	104	XTENSA_OPTION_DEBUG,
	105	XTENSA_OPTION_TRACE_PORT,
3a3c9dc4	106	XTENSA_OPTION_EXTERN_REGS,
dedc5eae MF	107	};
dedc5eae MF	108
2af3da91 MF	109	enum {
	110	THREADPTR = 231,
	111	FCR = 232,
	112	FSR = 233,
	113	};
	114
3580ecad	115	enum {
797d780b MF	116	LBEG = 0,
	117	LEND = 1,
	118	LCOUNT = 2,
3580ecad	119	SAR = 3,
4dd85b6b	120	BR = 4,
6ad6dbf7	121	LITBASE = 5,
809377aa	122	SCOMPARE1 = 12,
6825b6c3 MF	123	ACCLO = 16,
	124	ACCHI = 17,
	125	MR = 32,
553e44f9 MF	126	WINDOW_BASE = 72,
553e44f9 MF	127	WINDOW_START = 73,
b67ea0cd MF	128	PTEVADDR = 83,
	129	RASID = 90,
	130	ITLBCFG = 91,
	131	DTLBCFG = 92,
e61dc8f7	132	IBREAKENABLE = 96,
9e03ade4	133	MEMCTL = 97,
4e41d2f5	134	CACHEATTR = 98,
fcc803d1	135	ATOMCTL = 99,
e61dc8f7	136	IBREAKA = 128,
f14c4b5f MF	137	DBREAKA = 144,
f14c4b5f MF	138	DBREAKC = 160,
604e1f9c	139	CONFIGID0 = 176,
40643d7c MF	140	EPC1 = 177,
40643d7c MF	141	DEPC = 192,
b994e91b	142	EPS2 = 194,
604e1f9c	143	CONFIGID1 = 208,
40643d7c	144	EXCSAVE1 = 209,
f3df4c04	145	CPENABLE = 224,
b994e91b MF	146	INTSET = 226,
	147	INTCLEAR = 227,
	148	INTENABLE = 228,
f0a548b9	149	PS = 230,
97836cee	150	VECBASE = 231,
40643d7c	151	EXCCAUSE = 232,
ab58c5b4	152	DEBUGCAUSE = 233,
b994e91b	153	CCOUNT = 234,
f3df4c04	154	PRID = 235,
35b5c044 MF	155	ICOUNT = 236,
35b5c044 MF	156	ICOUNTLEVEL = 237,
40643d7c	157	EXCVADDR = 238,
b994e91b	158	CCOMPARE = 240,
b7909d81	159	MISC = 244,
3580ecad MF	160	};
3580ecad MF	161
f0a548b9 MF	162	#define PS_INTLEVEL 0xf
	163	#define PS_INTLEVEL_SHIFT 0
	164
	165	#define PS_EXCM 0x10
	166	#define PS_UM 0x20
	167
	168	#define PS_RING 0xc0
	169	#define PS_RING_SHIFT 6
	170
	171	#define PS_OWB 0xf00
	172	#define PS_OWB_SHIFT 8
	173
	174	#define PS_CALLINC 0x30000
	175	#define PS_CALLINC_SHIFT 16
	176	#define PS_CALLINC_LEN 2
	177
	178	#define PS_WOE 0x40000
	179
ab58c5b4 MF	180	#define DEBUGCAUSE_IC 0x1
	181	#define DEBUGCAUSE_IB 0x2
	182	#define DEBUGCAUSE_DB 0x4
	183	#define DEBUGCAUSE_BI 0x8
	184	#define DEBUGCAUSE_BN 0x10
	185	#define DEBUGCAUSE_DI 0x20
	186	#define DEBUGCAUSE_DBNUM 0xf00
	187	#define DEBUGCAUSE_DBNUM_SHIFT 8
	188
f14c4b5f MF	189	#define DBREAKC_SB 0x80000000
	190	#define DBREAKC_LB 0x40000000
	191	#define DBREAKC_SB_LB (DBREAKC_SB \| DBREAKC_LB)
	192	#define DBREAKC_MASK 0x3f
	193
9e03ade4 MF	194	#define MEMCTL_INIT 0x00800000
	195	#define MEMCTL_IUSEWAYS_SHIFT 18
	196	#define MEMCTL_IUSEWAYS_LEN 5
	197	#define MEMCTL_IUSEWAYS_MASK 0x007c0000
	198	#define MEMCTL_DALLOCWAYS_SHIFT 13
	199	#define MEMCTL_DALLOCWAYS_LEN 5
	200	#define MEMCTL_DALLOCWAYS_MASK 0x0003e000
	201	#define MEMCTL_DUSEWAYS_SHIFT 8
	202	#define MEMCTL_DUSEWAYS_LEN 5
	203	#define MEMCTL_DUSEWAYS_MASK 0x00001f00
	204	#define MEMCTL_ISNP 0x4
	205	#define MEMCTL_DSNP 0x2
	206	#define MEMCTL_IL0EN 0x1
	207
553e44f9	208	#define MAX_NAREG 64
b994e91b MF	209	#define MAX_NINTERRUPT 32
	210	#define MAX_NLEVEL 6
	211	#define MAX_NNMI 1
	212	#define MAX_NCCOMPARE 3
b67ea0cd	213	#define MAX_TLB_WAY_SIZE 8
f14c4b5f	214	#define MAX_NDBREAK 2
b68755c1	215	#define MAX_NMEMORY 4
b67ea0cd MF	216
b67ea0cd MF	217	#define REGION_PAGE_MASK 0xe0000000
553e44f9	218
fcc803d1 MF	219	#define PAGE_CACHE_MASK 0x700
	220	#define PAGE_CACHE_SHIFT 8
	221	#define PAGE_CACHE_INVALID 0x000
	222	#define PAGE_CACHE_BYPASS 0x100
	223	#define PAGE_CACHE_WT 0x200
	224	#define PAGE_CACHE_WB 0x400
	225	#define PAGE_CACHE_ISOLATE 0x600
	226
40643d7c MF	227	enum {
40643d7c MF	228	/* Static vectors */
17ab14ac MF	229	EXC_RESET0,
17ab14ac MF	230	EXC_RESET1,
40643d7c MF	231	EXC_MEMORY_ERROR,
	232
	233	/* Dynamic vectors */
	234	EXC_WINDOW_OVERFLOW4,
	235	EXC_WINDOW_UNDERFLOW4,
	236	EXC_WINDOW_OVERFLOW8,
	237	EXC_WINDOW_UNDERFLOW8,
	238	EXC_WINDOW_OVERFLOW12,
	239	EXC_WINDOW_UNDERFLOW12,
	240	EXC_IRQ,
	241	EXC_KERNEL,
	242	EXC_USER,
	243	EXC_DOUBLE,
e61dc8f7	244	EXC_DEBUG,
40643d7c MF	245	EXC_MAX
	246	};
	247
	248	enum {
	249	ILLEGAL_INSTRUCTION_CAUSE = 0,
	250	SYSCALL_CAUSE,
	251	INSTRUCTION_FETCH_ERROR_CAUSE,
	252	LOAD_STORE_ERROR_CAUSE,
	253	LEVEL1_INTERRUPT_CAUSE,
	254	ALLOCA_CAUSE,
	255	INTEGER_DIVIDE_BY_ZERO_CAUSE,
	256	PRIVILEGED_CAUSE = 8,
	257	LOAD_STORE_ALIGNMENT_CAUSE,
	258
	259	INSTR_PIF_DATA_ERROR_CAUSE = 12,
	260	LOAD_STORE_PIF_DATA_ERROR_CAUSE,
	261	INSTR_PIF_ADDR_ERROR_CAUSE,
	262	LOAD_STORE_PIF_ADDR_ERROR_CAUSE,
	263
	264	INST_TLB_MISS_CAUSE,
	265	INST_TLB_MULTI_HIT_CAUSE,
	266	INST_FETCH_PRIVILEGE_CAUSE,
	267	INST_FETCH_PROHIBITED_CAUSE = 20,
	268	LOAD_STORE_TLB_MISS_CAUSE = 24,
	269	LOAD_STORE_TLB_MULTI_HIT_CAUSE,
	270	LOAD_STORE_PRIVILEGE_CAUSE,
	271	LOAD_PROHIBITED_CAUSE = 28,
	272	STORE_PROHIBITED_CAUSE,
	273
	274	COPROCESSOR0_DISABLED = 32,
	275	};
	276
b994e91b MF	277	typedef enum {
	278	INTTYPE_LEVEL,
	279	INTTYPE_EDGE,
	280	INTTYPE_NMI,
	281	INTTYPE_SOFTWARE,
	282	INTTYPE_TIMER,
	283	INTTYPE_DEBUG,
	284	INTTYPE_WRITE_ERR,
dec71d2d	285	INTTYPE_PROFILING,
b994e91b MF	286	INTTYPE_MAX
	287	} interrupt_type;
	288
59a71f75 MF	289	struct CPUXtensaState;
59a71f75 MF	290
b67ea0cd MF	291	typedef struct xtensa_tlb_entry {
	292	uint32_t vaddr;
	293	uint32_t paddr;
	294	uint8_t asid;
	295	uint8_t attr;
	296	bool variable;
	297	} xtensa_tlb_entry;
	298
	299	typedef struct xtensa_tlb {
	300	unsigned nways;
	301	const unsigned way_size[10];
	302	bool varway56;
	303	unsigned nrefillentries;
	304	} xtensa_tlb;
	305
ccfcaba6 MF	306	typedef struct XtensaGdbReg {
	307	int targno;
	308	int type;
	309	int group;
ddd44279	310	unsigned size;
ccfcaba6 MF	311	} XtensaGdbReg;
	312
	313	typedef struct XtensaGdbRegmap {
	314	int num_regs;
	315	int num_core_regs;
	316	/* PC + a + ar + sr + ur */
	317	XtensaGdbReg reg[1 + 16 + 64 + 256 + 256];
	318	} XtensaGdbRegmap;
	319
59a71f75 MF	320	typedef struct XtensaCcompareTimer {
	321	struct CPUXtensaState *env;
	322	QEMUTimer *timer;
	323	} XtensaCcompareTimer;
	324
b68755c1 MF	325	typedef struct XtensaMemory {
	326	unsigned num;
	327	struct XtensaMemoryRegion {
	328	uint32_t addr;
	329	uint32_t size;
	330	} location[MAX_NMEMORY];
	331	} XtensaMemory;
	332
da374261	333	struct XtensaConfig {
dedc5eae MF	334	const char *name;
dedc5eae MF	335	uint64_t options;
ccfcaba6	336	XtensaGdbRegmap gdb_regmap;
553e44f9	337	unsigned nareg;
40643d7c MF	338	int excm_level;
40643d7c MF	339	int ndepc;
97836cee	340	uint32_t vecbase;
40643d7c	341	uint32_t exception_vector[EXC_MAX];
b994e91b MF	342	unsigned ninterrupt;
	343	unsigned nlevel;
	344	uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1];
	345	uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1];
	346	uint32_t inttype_mask[INTTYPE_MAX];
	347	struct {
	348	uint32_t level;
	349	interrupt_type inttype;
	350	} interrupt[MAX_NINTERRUPT];
	351	unsigned nccompare;
	352	uint32_t timerint[MAX_NCCOMPARE];
b8929a54 MF	353	unsigned nextint;
b8929a54 MF	354	unsigned extint[MAX_NINTERRUPT];
ab58c5b4 MF	355
	356	unsigned debug_level;
	357	unsigned nibreak;
	358	unsigned ndbreak;
	359
9e03ade4 MF	360	unsigned icache_ways;
	361	unsigned dcache_ways;
	362	uint32_t memctl_mask;
	363
b68755c1 MF	364	XtensaMemory instrom;
	365	XtensaMemory instram;
	366	XtensaMemory datarom;
	367	XtensaMemory dataram;
	368	XtensaMemory sysrom;
	369	XtensaMemory sysram;
	370
604e1f9c MF	371	uint32_t configid[2];
604e1f9c MF	372
b994e91b	373	uint32_t clock_freq_khz;
b67ea0cd MF	374
	375	xtensa_tlb itlb;
	376	xtensa_tlb dtlb;
da374261	377	};
dedc5eae	378
ac8b7db4 MF	379	typedef struct XtensaConfigList {
	380	const XtensaConfig *config;
	381	struct XtensaConfigList *next;
	382	} XtensaConfigList;
	383
ddd44279 MF	384	#ifdef HOST_WORDS_BIGENDIAN
	385	enum {
	386	FP_F32_HIGH,
	387	FP_F32_LOW,
	388	};
	389	#else
	390	enum {
	391	FP_F32_LOW,
	392	FP_F32_HIGH,
	393	};
	394	#endif
	395
2328826b	396	typedef struct CPUXtensaState {
dedc5eae	397	const XtensaConfig *config;
2328826b MF	398	uint32_t regs[16];
	399	uint32_t pc;
	400	uint32_t sregs[256];
2af3da91	401	uint32_t uregs[256];
553e44f9	402	uint32_t phys_regs[MAX_NAREG];
ddd44279 MF	403	union {
	404	float32 f32[2];
	405	float64 f64;
	406	} fregs[16];
dd519cbe	407	float_status fp_status;
2328826b	408
b67ea0cd MF	409	xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE];
	410	xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE];
	411	unsigned autorefill_idx;
bd527a83	412	bool runstall;
3a3c9dc4 MF	413	AddressSpace *address_space_er;
3a3c9dc4 MF	414	MemoryRegion *system_er;
b994e91b MF	415	int pending_irq_level; /* level of last raised IRQ */
b994e91b MF	416	void **irq_inputs;
59a71f75 MF	417	XtensaCcompareTimer ccompare[MAX_NCCOMPARE];
	418	uint64_t time_base;
	419	uint64_t ccount_time;
	420	uint32_t ccount_base;
b994e91b	421
40643d7c	422	int exception_taken;
d2132510	423	int yield_needed;
17ab14ac	424	unsigned static_vectors;
40643d7c	425
f14c4b5f	426	/* Watchpoints for DBREAK registers */
ff4700b0	427	struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK];
f14c4b5f	428
2328826b MF	429	CPU_COMMON
	430	} CPUXtensaState;
	431
da374261 PB	432	/**
	433	* XtensaCPU:
	434	* @env: #CPUXtensaState
	435	*
	436	* An Xtensa CPU.
	437	*/
	438	struct XtensaCPU {
	439	/< private >/
	440	CPUState parent_obj;
	441	/< public >/
	442
	443	CPUXtensaState env;
	444	};
	445
	446	static inline XtensaCPU xtensa_env_get_cpu(const CPUXtensaState env)
	447	{
	448	return container_of(env, XtensaCPU, env);
	449	}
	450
	451	#define ENV_GET_CPU(e) CPU(xtensa_env_get_cpu(e))
	452
	453	#define ENV_OFFSET offsetof(XtensaCPU, env)
	454
	455	void xtensa_cpu_do_interrupt(CPUState *cpu);
	456	bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request);
	457	void xtensa_cpu_do_unassigned_access(CPUState *cpu, hwaddr addr,
	458	bool is_write, bool is_exec, int opaque,
	459	unsigned size);
	460	void xtensa_cpu_dump_state(CPUState cpu, FILE f,
	461	fprintf_function cpu_fprintf, int flags);
	462	hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
	463	int xtensa_cpu_gdb_read_register(CPUState cpu, uint8_t buf, int reg);
	464	int xtensa_cpu_gdb_write_register(CPUState cpu, uint8_t buf, int reg);
	465	void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
b35399bb SS	466	MMUAccessType access_type,
b35399bb SS	467	int mmu_idx, uintptr_t retaddr);
15be3171	468
2328826b MF	469	#define cpu_signal_handler cpu_xtensa_signal_handler
	470	#define cpu_list xtensa_cpu_list
	471
e38077ff MF	472	#ifdef TARGET_WORDS_BIGENDIAN
	473	#define XTENSA_DEFAULT_CPU_MODEL "fsf"
	474	#else
	475	#define XTENSA_DEFAULT_CPU_MODEL "dc232b"
	476	#endif
	477
8e36271b	478	#define cpu_init(cpu_model) cpu_generic_init(TYPE_XTENSA_CPU, cpu_model)
15be3171	479
2328826b	480	void xtensa_translate_init(void);
86025ee4	481	void xtensa_breakpoint_handler(CPUState *cs);
1479073b	482	void xtensa_finalize_config(XtensaConfig *config);
ac8b7db4	483	void xtensa_register_core(XtensaConfigList *node);
8128b3e0	484	void xtensa_sim_open_console(Chardev *chr);
b994e91b	485	void check_interrupts(CPUXtensaState *s);
97129ac8 AF	486	void xtensa_irq_init(CPUXtensaState *env);
97129ac8 AF	487	void xtensa_get_extint(CPUXtensaState env, unsigned extint);
97129ac8	488	void xtensa_timer_irq(CPUXtensaState *env, uint32_t id, uint32_t active);
2328826b MF	489	int cpu_xtensa_signal_handler(int host_signum, void pinfo, void puc);
2328826b MF	490	void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf);
97129ac8 AF	491	void xtensa_sync_window_from_phys(CPUXtensaState *env);
	492	void xtensa_sync_phys_from_window(CPUXtensaState *env);
	493	uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way);
	494	void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb,
b67ea0cd	495	uint32_t vpn, uint32_t wi, uint32_t ei);
97129ac8	496	int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
b67ea0cd	497	uint32_t pwi, uint32_t pei, uint8_t *pring);
16bde77a MF	498	void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
	499	xtensa_tlb_entry *entry, bool dtlb,
	500	unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
97129ac8	501	void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
b67ea0cd	502	unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
ae4e7982	503	int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
b67ea0cd MF	504	uint32_t vaddr, int is_write, int mmu_idx,
b67ea0cd MF	505	uint32_t paddr, uint32_t page_size, unsigned *access);
5087a72c	506	void reset_mmu(CPUXtensaState *env);
97129ac8 AF	507	void dump_mmu(FILE f, fprintf_function cpu_fprintf, CPUXtensaState env);
97129ac8 AF	508	void debug_exception_env(CPUXtensaState *new_env, uint32_t cause);
3a3c9dc4 MF	509	static inline MemoryRegion xtensa_get_er_region(CPUXtensaState env)
	510	{
	511	return env->system_er;
	512	}
b67ea0cd	513
17ab14ac MF	514	static inline void xtensa_select_static_vectors(CPUXtensaState *env,
	515	unsigned n)
	516	{
	517	assert(n < 2);
	518	env->static_vectors = n;
	519	}
bd527a83	520	void xtensa_runstall(CPUXtensaState *env, bool runstall);
2328826b	521
dedc5eae	522	#define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
fe0bd475	523	#define XTENSA_OPTION_ALL (~(uint64_t)0)
dedc5eae	524
b67ea0cd MF	525	static inline bool xtensa_option_bits_enabled(const XtensaConfig *config,
	526	uint64_t opt)
	527	{
	528	return (config->options & opt) != 0;
	529	}
	530
dedc5eae MF	531	static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt)
dedc5eae MF	532	{
b67ea0cd	533	return xtensa_option_bits_enabled(config, XTENSA_OPTION_BIT(opt));
dedc5eae MF	534	}
dedc5eae MF	535
97129ac8	536	static inline int xtensa_get_cintlevel(const CPUXtensaState *env)
40643d7c MF	537	{
	538	int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT;
	539	if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) {
	540	level = env->config->excm_level;
	541	}
	542	return level;
	543	}
	544
97129ac8	545	static inline int xtensa_get_ring(const CPUXtensaState *env)
f0a548b9 MF	546	{
	547	if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
	548	return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
	549	} else {
	550	return 0;
	551	}
	552	}
	553
97129ac8	554	static inline int xtensa_get_cring(const CPUXtensaState *env)
f0a548b9 MF	555	{
	556	if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) &&
	557	(env->sregs[PS] & PS_EXCM) == 0) {
	558	return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
	559	} else {
	560	return 0;
	561	}
	562	}
	563
97129ac8	564	static inline xtensa_tlb_entry xtensa_tlb_get_entry(CPUXtensaState env,
b67ea0cd MF	565	bool dtlb, unsigned wi, unsigned ei)
	566	{
	567	return dtlb ?
	568	env->dtlb[wi] + ei :
	569	env->itlb[wi] + ei;
	570	}
	571
1b3e71f8 MF	572	static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env)
	573	{
	574	return env->sregs[WINDOW_START] \|
	575	(env->sregs[WINDOW_START] << env->config->nareg / 4);
	576	}
	577
f0a548b9 MF	578	/* MMU modes definitions */
	579	#define MMU_MODE0_SUFFIX _ring0
	580	#define MMU_MODE1_SUFFIX _ring1
	581	#define MMU_MODE2_SUFFIX _ring2
	582	#define MMU_MODE3_SUFFIX _ring3
	583
97ed5ccd	584	static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch)
2328826b	585	{
f0a548b9	586	return xtensa_get_cring(env);
2328826b MF	587	}
2328826b MF	588
f0a548b9 MF	589	#define XTENSA_TBFLAG_RING_MASK 0x3
f0a548b9 MF	590	#define XTENSA_TBFLAG_EXCM 0x4
6ad6dbf7	591	#define XTENSA_TBFLAG_LITBASE 0x8
e61dc8f7	592	#define XTENSA_TBFLAG_DEBUG 0x10
35b5c044	593	#define XTENSA_TBFLAG_ICOUNT 0x20
ef04a846 MF	594	#define XTENSA_TBFLAG_CPENABLE_MASK 0x3fc0
ef04a846 MF	595	#define XTENSA_TBFLAG_CPENABLE_SHIFT 6
a00817cc	596	#define XTENSA_TBFLAG_EXCEPTION 0x4000
2db59a76 MF	597	#define XTENSA_TBFLAG_WINDOW_MASK 0x18000
2db59a76 MF	598	#define XTENSA_TBFLAG_WINDOW_SHIFT 15
d2132510	599	#define XTENSA_TBFLAG_YIELD 0x20000
f0a548b9	600
97129ac8	601	static inline void cpu_get_tb_cpu_state(CPUXtensaState env, target_ulong pc,
89fee74a	602	target_ulong cs_base, uint32_t flags)
2328826b	603	{
1cf5ccbc AF	604	CPUState *cs = CPU(xtensa_env_get_cpu(env));
1cf5ccbc AF	605
2328826b MF	606	*pc = env->pc;
	607	*cs_base = 0;
	608	*flags = 0;
f0a548b9 MF	609	*flags \|= xtensa_get_ring(env);
	610	if (env->sregs[PS] & PS_EXCM) {
	611	*flags \|= XTENSA_TBFLAG_EXCM;
	612	}
6ad6dbf7 MF	613	if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&
	614	(env->sregs[LITBASE] & 1)) {
	615	*flags \|= XTENSA_TBFLAG_LITBASE;
	616	}
e61dc8f7 MF	617	if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) {
	618	if (xtensa_get_cintlevel(env) < env->config->debug_level) {
	619	*flags \|= XTENSA_TBFLAG_DEBUG;
	620	}
35b5c044 MF	621	if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) {
	622	*flags \|= XTENSA_TBFLAG_ICOUNT;
	623	}
e61dc8f7	624	}
ef04a846 MF	625	if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) {
	626	*flags \|= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT;
	627	}
1cf5ccbc	628	if (cs->singlestep_enabled && env->exception_taken) {
a00817cc MF	629	*flags \|= XTENSA_TBFLAG_EXCEPTION;
a00817cc MF	630	}
2db59a76 MF	631	if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER) &&
	632	(env->sregs[PS] & (PS_WOE \| PS_EXCM)) == PS_WOE) {
	633	uint32_t windowstart = xtensa_replicate_windowstart(env) >>
	634	(env->sregs[WINDOW_BASE] + 1);
	635	uint32_t w = ctz32(windowstart \| 0x8);
	636
	637	*flags \|= w << XTENSA_TBFLAG_WINDOW_SHIFT;
	638	} else {
	639	*flags \|= 3 << XTENSA_TBFLAG_WINDOW_SHIFT;
	640	}
d2132510 MF	641	if (env->yield_needed) {
	642	*flags \|= XTENSA_TBFLAG_YIELD;
	643	}
2328826b MF	644	}
2328826b MF	645
022c62cb	646	#include "exec/cpu-all.h"
2328826b	647
2328826b	648	#endif