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2328826b MF |
1 | /* |
2 | * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. | |
3 | * All rights reserved. | |
4 | * | |
5 | * Redistribution and use in source and binary forms, with or without | |
6 | * modification, are permitted provided that the following conditions are met: | |
7 | * * Redistributions of source code must retain the above copyright | |
8 | * notice, this list of conditions and the following disclaimer. | |
9 | * * Redistributions in binary form must reproduce the above copyright | |
10 | * notice, this list of conditions and the following disclaimer in the | |
11 | * documentation and/or other materials provided with the distribution. | |
12 | * * Neither the name of the Open Source and Linux Lab nor the | |
13 | * names of its contributors may be used to endorse or promote products | |
14 | * derived from this software without specific prior written permission. | |
15 | * | |
16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY | |
20 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
21 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
22 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
23 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
24 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
25 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
26 | */ | |
27 | ||
07f5a258 MA |
28 | #ifndef XTENSA_CPU_H |
29 | #define XTENSA_CPU_H | |
2328826b | 30 | |
da374261 | 31 | #include "cpu-qom.h" |
69242e7e | 32 | #include "qemu/cpu-float.h" |
022c62cb | 33 | #include "exec/cpu-defs.h" |
168c12b0 | 34 | #include "xtensa-isa.h" |
2328826b | 35 | |
74433bf0 RH |
36 | /* Xtensa processors have a weak memory model */ |
37 | #define TCG_GUEST_DEFAULT_MO (0) | |
2328826b | 38 | |
dedc5eae MF |
39 | enum { |
40 | /* Additional instructions */ | |
41 | XTENSA_OPTION_CODE_DENSITY, | |
42 | XTENSA_OPTION_LOOP, | |
43 | XTENSA_OPTION_EXTENDED_L32R, | |
44 | XTENSA_OPTION_16_BIT_IMUL, | |
45 | XTENSA_OPTION_32_BIT_IMUL, | |
7f65f4b0 | 46 | XTENSA_OPTION_32_BIT_IMUL_HIGH, |
dedc5eae MF |
47 | XTENSA_OPTION_32_BIT_IDIV, |
48 | XTENSA_OPTION_MAC16, | |
7f65f4b0 MF |
49 | XTENSA_OPTION_MISC_OP_NSA, |
50 | XTENSA_OPTION_MISC_OP_MINMAX, | |
51 | XTENSA_OPTION_MISC_OP_SEXT, | |
52 | XTENSA_OPTION_MISC_OP_CLAMPS, | |
dedc5eae MF |
53 | XTENSA_OPTION_COPROCESSOR, |
54 | XTENSA_OPTION_BOOLEAN, | |
55 | XTENSA_OPTION_FP_COPROCESSOR, | |
de6b55cb MF |
56 | XTENSA_OPTION_DFP_COPROCESSOR, |
57 | XTENSA_OPTION_DFPU_SINGLE_ONLY, | |
dedc5eae MF |
58 | XTENSA_OPTION_MP_SYNCHRO, |
59 | XTENSA_OPTION_CONDITIONAL_STORE, | |
fcc803d1 | 60 | XTENSA_OPTION_ATOMCTL, |
5eeb40c5 | 61 | XTENSA_OPTION_DEPBITS, |
dedc5eae MF |
62 | |
63 | /* Interrupts and exceptions */ | |
64 | XTENSA_OPTION_EXCEPTION, | |
65 | XTENSA_OPTION_RELOCATABLE_VECTOR, | |
66 | XTENSA_OPTION_UNALIGNED_EXCEPTION, | |
67 | XTENSA_OPTION_INTERRUPT, | |
68 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, | |
69 | XTENSA_OPTION_TIMER_INTERRUPT, | |
70 | ||
71 | /* Local memory */ | |
72 | XTENSA_OPTION_ICACHE, | |
73 | XTENSA_OPTION_ICACHE_TEST, | |
74 | XTENSA_OPTION_ICACHE_INDEX_LOCK, | |
75 | XTENSA_OPTION_DCACHE, | |
76 | XTENSA_OPTION_DCACHE_TEST, | |
77 | XTENSA_OPTION_DCACHE_INDEX_LOCK, | |
78 | XTENSA_OPTION_IRAM, | |
79 | XTENSA_OPTION_IROM, | |
80 | XTENSA_OPTION_DRAM, | |
81 | XTENSA_OPTION_DROM, | |
82 | XTENSA_OPTION_XLMI, | |
83 | XTENSA_OPTION_HW_ALIGNMENT, | |
84 | XTENSA_OPTION_MEMORY_ECC_PARITY, | |
85 | ||
86 | /* Memory protection and translation */ | |
87 | XTENSA_OPTION_REGION_PROTECTION, | |
88 | XTENSA_OPTION_REGION_TRANSLATION, | |
4d04ea35 | 89 | XTENSA_OPTION_MPU, |
dedc5eae | 90 | XTENSA_OPTION_MMU, |
4e41d2f5 | 91 | XTENSA_OPTION_CACHEATTR, |
dedc5eae MF |
92 | |
93 | /* Other */ | |
94 | XTENSA_OPTION_WINDOWED_REGISTER, | |
95 | XTENSA_OPTION_PROCESSOR_INTERFACE, | |
96 | XTENSA_OPTION_MISC_SR, | |
97 | XTENSA_OPTION_THREAD_POINTER, | |
98 | XTENSA_OPTION_PROCESSOR_ID, | |
99 | XTENSA_OPTION_DEBUG, | |
100 | XTENSA_OPTION_TRACE_PORT, | |
3a3c9dc4 | 101 | XTENSA_OPTION_EXTERN_REGS, |
dedc5eae MF |
102 | }; |
103 | ||
2af3da91 | 104 | enum { |
e9872741 | 105 | EXPSTATE = 230, |
2af3da91 MF |
106 | THREADPTR = 231, |
107 | FCR = 232, | |
108 | FSR = 233, | |
109 | }; | |
110 | ||
3580ecad | 111 | enum { |
797d780b MF |
112 | LBEG = 0, |
113 | LEND = 1, | |
114 | LCOUNT = 2, | |
3580ecad | 115 | SAR = 3, |
4dd85b6b | 116 | BR = 4, |
6ad6dbf7 | 117 | LITBASE = 5, |
809377aa | 118 | SCOMPARE1 = 12, |
6825b6c3 MF |
119 | ACCLO = 16, |
120 | ACCHI = 17, | |
121 | MR = 32, | |
eb3f4298 | 122 | PREFCTL = 40, |
553e44f9 MF |
123 | WINDOW_BASE = 72, |
124 | WINDOW_START = 73, | |
b67ea0cd | 125 | PTEVADDR = 83, |
13f6a7cd | 126 | MMID = 89, |
b67ea0cd | 127 | RASID = 90, |
4d04ea35 | 128 | MPUENB = 90, |
b67ea0cd MF |
129 | ITLBCFG = 91, |
130 | DTLBCFG = 92, | |
4d04ea35 MF |
131 | MPUCFG = 92, |
132 | ERACCESS = 95, | |
e61dc8f7 | 133 | IBREAKENABLE = 96, |
9e03ade4 | 134 | MEMCTL = 97, |
4e41d2f5 | 135 | CACHEATTR = 98, |
4d04ea35 | 136 | CACHEADRDIS = 98, |
fcc803d1 | 137 | ATOMCTL = 99, |
13f6a7cd | 138 | DDR = 104, |
631a77a0 MF |
139 | MEPC = 106, |
140 | MEPS = 107, | |
141 | MESAVE = 108, | |
142 | MESR = 109, | |
143 | MECR = 110, | |
144 | MEVADDR = 111, | |
e61dc8f7 | 145 | IBREAKA = 128, |
f14c4b5f MF |
146 | DBREAKA = 144, |
147 | DBREAKC = 160, | |
604e1f9c | 148 | CONFIGID0 = 176, |
40643d7c MF |
149 | EPC1 = 177, |
150 | DEPC = 192, | |
b994e91b | 151 | EPS2 = 194, |
604e1f9c | 152 | CONFIGID1 = 208, |
40643d7c | 153 | EXCSAVE1 = 209, |
f3df4c04 | 154 | CPENABLE = 224, |
b994e91b MF |
155 | INTSET = 226, |
156 | INTCLEAR = 227, | |
157 | INTENABLE = 228, | |
f0a548b9 | 158 | PS = 230, |
97836cee | 159 | VECBASE = 231, |
40643d7c | 160 | EXCCAUSE = 232, |
ab58c5b4 | 161 | DEBUGCAUSE = 233, |
b994e91b | 162 | CCOUNT = 234, |
f3df4c04 | 163 | PRID = 235, |
35b5c044 MF |
164 | ICOUNT = 236, |
165 | ICOUNTLEVEL = 237, | |
40643d7c | 166 | EXCVADDR = 238, |
b994e91b | 167 | CCOMPARE = 240, |
b7909d81 | 168 | MISC = 244, |
3580ecad MF |
169 | }; |
170 | ||
f0a548b9 MF |
171 | #define PS_INTLEVEL 0xf |
172 | #define PS_INTLEVEL_SHIFT 0 | |
173 | ||
174 | #define PS_EXCM 0x10 | |
175 | #define PS_UM 0x20 | |
176 | ||
177 | #define PS_RING 0xc0 | |
178 | #define PS_RING_SHIFT 6 | |
179 | ||
180 | #define PS_OWB 0xf00 | |
181 | #define PS_OWB_SHIFT 8 | |
ba7651fb | 182 | #define PS_OWB_LEN 4 |
f0a548b9 MF |
183 | |
184 | #define PS_CALLINC 0x30000 | |
185 | #define PS_CALLINC_SHIFT 16 | |
186 | #define PS_CALLINC_LEN 2 | |
187 | ||
188 | #define PS_WOE 0x40000 | |
189 | ||
ab58c5b4 MF |
190 | #define DEBUGCAUSE_IC 0x1 |
191 | #define DEBUGCAUSE_IB 0x2 | |
192 | #define DEBUGCAUSE_DB 0x4 | |
193 | #define DEBUGCAUSE_BI 0x8 | |
194 | #define DEBUGCAUSE_BN 0x10 | |
195 | #define DEBUGCAUSE_DI 0x20 | |
196 | #define DEBUGCAUSE_DBNUM 0xf00 | |
197 | #define DEBUGCAUSE_DBNUM_SHIFT 8 | |
198 | ||
f14c4b5f MF |
199 | #define DBREAKC_SB 0x80000000 |
200 | #define DBREAKC_LB 0x40000000 | |
201 | #define DBREAKC_SB_LB (DBREAKC_SB | DBREAKC_LB) | |
202 | #define DBREAKC_MASK 0x3f | |
203 | ||
9e03ade4 MF |
204 | #define MEMCTL_INIT 0x00800000 |
205 | #define MEMCTL_IUSEWAYS_SHIFT 18 | |
206 | #define MEMCTL_IUSEWAYS_LEN 5 | |
207 | #define MEMCTL_IUSEWAYS_MASK 0x007c0000 | |
208 | #define MEMCTL_DALLOCWAYS_SHIFT 13 | |
209 | #define MEMCTL_DALLOCWAYS_LEN 5 | |
210 | #define MEMCTL_DALLOCWAYS_MASK 0x0003e000 | |
211 | #define MEMCTL_DUSEWAYS_SHIFT 8 | |
212 | #define MEMCTL_DUSEWAYS_LEN 5 | |
213 | #define MEMCTL_DUSEWAYS_MASK 0x00001f00 | |
214 | #define MEMCTL_ISNP 0x4 | |
215 | #define MEMCTL_DSNP 0x2 | |
216 | #define MEMCTL_IL0EN 0x1 | |
217 | ||
168c12b0 | 218 | #define MAX_INSN_LENGTH 64 |
fde557ad MF |
219 | #define MAX_INSNBUF_LENGTH \ |
220 | ((MAX_INSN_LENGTH + sizeof(xtensa_insnbuf_word) - 1) / \ | |
221 | sizeof(xtensa_insnbuf_word)) | |
09460970 | 222 | #define MAX_INSN_SLOTS 32 |
168c12b0 | 223 | #define MAX_OPCODE_ARGS 16 |
553e44f9 | 224 | #define MAX_NAREG 64 |
b994e91b MF |
225 | #define MAX_NINTERRUPT 32 |
226 | #define MAX_NLEVEL 6 | |
227 | #define MAX_NNMI 1 | |
228 | #define MAX_NCCOMPARE 3 | |
b67ea0cd | 229 | #define MAX_TLB_WAY_SIZE 8 |
f14c4b5f | 230 | #define MAX_NDBREAK 2 |
b68755c1 | 231 | #define MAX_NMEMORY 4 |
4d04ea35 | 232 | #define MAX_MPU_FOREGROUND_SEGMENTS 32 |
b67ea0cd MF |
233 | |
234 | #define REGION_PAGE_MASK 0xe0000000 | |
553e44f9 | 235 | |
fcc803d1 MF |
236 | #define PAGE_CACHE_MASK 0x700 |
237 | #define PAGE_CACHE_SHIFT 8 | |
238 | #define PAGE_CACHE_INVALID 0x000 | |
239 | #define PAGE_CACHE_BYPASS 0x100 | |
240 | #define PAGE_CACHE_WT 0x200 | |
241 | #define PAGE_CACHE_WB 0x400 | |
242 | #define PAGE_CACHE_ISOLATE 0x600 | |
243 | ||
40643d7c MF |
244 | enum { |
245 | /* Static vectors */ | |
17ab14ac MF |
246 | EXC_RESET0, |
247 | EXC_RESET1, | |
40643d7c MF |
248 | EXC_MEMORY_ERROR, |
249 | ||
250 | /* Dynamic vectors */ | |
251 | EXC_WINDOW_OVERFLOW4, | |
252 | EXC_WINDOW_UNDERFLOW4, | |
253 | EXC_WINDOW_OVERFLOW8, | |
254 | EXC_WINDOW_UNDERFLOW8, | |
255 | EXC_WINDOW_OVERFLOW12, | |
256 | EXC_WINDOW_UNDERFLOW12, | |
257 | EXC_IRQ, | |
258 | EXC_KERNEL, | |
259 | EXC_USER, | |
260 | EXC_DOUBLE, | |
e61dc8f7 | 261 | EXC_DEBUG, |
40643d7c MF |
262 | EXC_MAX |
263 | }; | |
264 | ||
265 | enum { | |
266 | ILLEGAL_INSTRUCTION_CAUSE = 0, | |
267 | SYSCALL_CAUSE, | |
268 | INSTRUCTION_FETCH_ERROR_CAUSE, | |
269 | LOAD_STORE_ERROR_CAUSE, | |
270 | LEVEL1_INTERRUPT_CAUSE, | |
271 | ALLOCA_CAUSE, | |
272 | INTEGER_DIVIDE_BY_ZERO_CAUSE, | |
98736654 MF |
273 | PC_VALUE_ERROR_CAUSE, |
274 | PRIVILEGED_CAUSE, | |
40643d7c | 275 | LOAD_STORE_ALIGNMENT_CAUSE, |
98736654 MF |
276 | EXTERNAL_REG_PRIVILEGE_CAUSE, |
277 | EXCLUSIVE_ERROR_CAUSE, | |
278 | INSTR_PIF_DATA_ERROR_CAUSE, | |
40643d7c MF |
279 | LOAD_STORE_PIF_DATA_ERROR_CAUSE, |
280 | INSTR_PIF_ADDR_ERROR_CAUSE, | |
281 | LOAD_STORE_PIF_ADDR_ERROR_CAUSE, | |
40643d7c MF |
282 | INST_TLB_MISS_CAUSE, |
283 | INST_TLB_MULTI_HIT_CAUSE, | |
284 | INST_FETCH_PRIVILEGE_CAUSE, | |
285 | INST_FETCH_PROHIBITED_CAUSE = 20, | |
286 | LOAD_STORE_TLB_MISS_CAUSE = 24, | |
287 | LOAD_STORE_TLB_MULTI_HIT_CAUSE, | |
288 | LOAD_STORE_PRIVILEGE_CAUSE, | |
289 | LOAD_PROHIBITED_CAUSE = 28, | |
290 | STORE_PROHIBITED_CAUSE, | |
291 | ||
292 | COPROCESSOR0_DISABLED = 32, | |
293 | }; | |
294 | ||
b994e91b MF |
295 | typedef enum { |
296 | INTTYPE_LEVEL, | |
297 | INTTYPE_EDGE, | |
298 | INTTYPE_NMI, | |
299 | INTTYPE_SOFTWARE, | |
300 | INTTYPE_TIMER, | |
301 | INTTYPE_DEBUG, | |
302 | INTTYPE_WRITE_ERR, | |
dec71d2d | 303 | INTTYPE_PROFILING, |
944bb332 MF |
304 | INTTYPE_IDMA_DONE, |
305 | INTTYPE_IDMA_ERR, | |
306 | INTTYPE_GS_ERR, | |
b994e91b MF |
307 | INTTYPE_MAX |
308 | } interrupt_type; | |
309 | ||
1ea4a06a | 310 | typedef struct CPUArchState CPUXtensaState; |
59a71f75 | 311 | |
b67ea0cd MF |
312 | typedef struct xtensa_tlb_entry { |
313 | uint32_t vaddr; | |
314 | uint32_t paddr; | |
315 | uint8_t asid; | |
316 | uint8_t attr; | |
317 | bool variable; | |
318 | } xtensa_tlb_entry; | |
319 | ||
320 | typedef struct xtensa_tlb { | |
321 | unsigned nways; | |
322 | const unsigned way_size[10]; | |
323 | bool varway56; | |
324 | unsigned nrefillentries; | |
325 | } xtensa_tlb; | |
326 | ||
4d04ea35 MF |
327 | typedef struct xtensa_mpu_entry { |
328 | uint32_t vaddr; | |
329 | uint32_t attr; | |
330 | } xtensa_mpu_entry; | |
331 | ||
ccfcaba6 MF |
332 | typedef struct XtensaGdbReg { |
333 | int targno; | |
1b7b26e4 | 334 | unsigned flags; |
ccfcaba6 MF |
335 | int type; |
336 | int group; | |
ddd44279 | 337 | unsigned size; |
ccfcaba6 MF |
338 | } XtensaGdbReg; |
339 | ||
340 | typedef struct XtensaGdbRegmap { | |
341 | int num_regs; | |
342 | int num_core_regs; | |
343 | /* PC + a + ar + sr + ur */ | |
344 | XtensaGdbReg reg[1 + 16 + 64 + 256 + 256]; | |
345 | } XtensaGdbRegmap; | |
346 | ||
59a71f75 | 347 | typedef struct XtensaCcompareTimer { |
36861198 | 348 | CPUXtensaState *env; |
59a71f75 MF |
349 | QEMUTimer *timer; |
350 | } XtensaCcompareTimer; | |
351 | ||
b68755c1 MF |
352 | typedef struct XtensaMemory { |
353 | unsigned num; | |
354 | struct XtensaMemoryRegion { | |
355 | uint32_t addr; | |
356 | uint32_t size; | |
357 | } location[MAX_NMEMORY]; | |
358 | } XtensaMemory; | |
359 | ||
b0b24bdc MF |
360 | typedef struct opcode_arg { |
361 | uint32_t imm; | |
362 | uint32_t raw_imm; | |
363 | void *in; | |
364 | void *out; | |
ed07f685 | 365 | uint32_t num_bits; |
b0b24bdc MF |
366 | } OpcodeArg; |
367 | ||
168c12b0 | 368 | typedef struct DisasContext DisasContext; |
b0b24bdc | 369 | typedef void (*XtensaOpcodeOp)(DisasContext *dc, const OpcodeArg arg[], |
168c12b0 | 370 | const uint32_t par[]); |
6416d16f | 371 | typedef uint32_t (*XtensaOpcodeUintTest)(DisasContext *dc, |
b0b24bdc | 372 | const OpcodeArg arg[], |
6416d16f | 373 | const uint32_t par[]); |
09460970 MF |
374 | |
375 | enum { | |
376 | XTENSA_OP_ILL = 0x1, | |
377 | XTENSA_OP_PRIVILEGED = 0x2, | |
378 | XTENSA_OP_SYSCALL = 0x4, | |
379 | XTENSA_OP_DEBUG_BREAK = 0x8, | |
380 | ||
381 | XTENSA_OP_OVERFLOW = 0x10, | |
382 | XTENSA_OP_UNDERFLOW = 0x20, | |
383 | XTENSA_OP_ALLOCA = 0x40, | |
384 | XTENSA_OP_COPROCESSOR = 0x80, | |
385 | ||
386 | XTENSA_OP_DIVIDE_BY_ZERO = 0x100, | |
387 | ||
45b71a79 | 388 | /* Postprocessing flags */ |
09460970 MF |
389 | XTENSA_OP_CHECK_INTERRUPTS = 0x200, |
390 | XTENSA_OP_EXIT_TB_M1 = 0x400, | |
391 | XTENSA_OP_EXIT_TB_0 = 0x800, | |
45b71a79 MF |
392 | XTENSA_OP_SYNC_REGISTER_WINDOW = 0x1000, |
393 | ||
394 | XTENSA_OP_POSTPROCESS = | |
395 | XTENSA_OP_CHECK_INTERRUPTS | | |
396 | XTENSA_OP_EXIT_TB_M1 | | |
397 | XTENSA_OP_EXIT_TB_0 | | |
398 | XTENSA_OP_SYNC_REGISTER_WINDOW, | |
d863fcf7 MF |
399 | |
400 | XTENSA_OP_NAME_ARRAY = 0x8000, | |
20e9fd0f MF |
401 | |
402 | XTENSA_OP_CONTROL_FLOW = 0x10000, | |
068e538a MF |
403 | XTENSA_OP_STORE = 0x20000, |
404 | XTENSA_OP_LOAD = 0x40000, | |
405 | XTENSA_OP_LOAD_STORE = | |
406 | XTENSA_OP_LOAD | XTENSA_OP_STORE, | |
09460970 | 407 | }; |
168c12b0 MF |
408 | |
409 | typedef struct XtensaOpcodeOps { | |
d863fcf7 | 410 | const void *name; |
168c12b0 | 411 | XtensaOpcodeOp translate; |
91dc2b2d | 412 | XtensaOpcodeUintTest test_exceptions; |
6416d16f | 413 | XtensaOpcodeUintTest test_overflow; |
168c12b0 | 414 | const uint32_t *par; |
09460970 | 415 | uint32_t op_flags; |
582fef0f | 416 | uint32_t coprocessor; |
168c12b0 MF |
417 | } XtensaOpcodeOps; |
418 | ||
419 | typedef struct XtensaOpcodeTranslators { | |
420 | unsigned num_opcodes; | |
421 | const XtensaOpcodeOps *opcode; | |
422 | } XtensaOpcodeTranslators; | |
423 | ||
424 | extern const XtensaOpcodeTranslators xtensa_core_opcodes; | |
c04e1692 | 425 | extern const XtensaOpcodeTranslators xtensa_fpu2000_opcodes; |
cfa9f051 | 426 | extern const XtensaOpcodeTranslators xtensa_fpu_opcodes; |
168c12b0 | 427 | |
da374261 | 428 | struct XtensaConfig { |
dedc5eae MF |
429 | const char *name; |
430 | uint64_t options; | |
ccfcaba6 | 431 | XtensaGdbRegmap gdb_regmap; |
553e44f9 | 432 | unsigned nareg; |
40643d7c MF |
433 | int excm_level; |
434 | int ndepc; | |
f40385c9 | 435 | unsigned inst_fetch_width; |
5d630cef | 436 | unsigned max_insn_size; |
97836cee | 437 | uint32_t vecbase; |
40643d7c | 438 | uint32_t exception_vector[EXC_MAX]; |
b994e91b MF |
439 | unsigned ninterrupt; |
440 | unsigned nlevel; | |
a7d479ee | 441 | unsigned nmi_level; |
b994e91b MF |
442 | uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1]; |
443 | uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1]; | |
444 | uint32_t inttype_mask[INTTYPE_MAX]; | |
445 | struct { | |
446 | uint32_t level; | |
447 | interrupt_type inttype; | |
448 | } interrupt[MAX_NINTERRUPT]; | |
449 | unsigned nccompare; | |
450 | uint32_t timerint[MAX_NCCOMPARE]; | |
b8929a54 MF |
451 | unsigned nextint; |
452 | unsigned extint[MAX_NINTERRUPT]; | |
ab58c5b4 MF |
453 | |
454 | unsigned debug_level; | |
455 | unsigned nibreak; | |
456 | unsigned ndbreak; | |
457 | ||
9e03ade4 MF |
458 | unsigned icache_ways; |
459 | unsigned dcache_ways; | |
75eed0e5 | 460 | unsigned dcache_line_bytes; |
9e03ade4 MF |
461 | uint32_t memctl_mask; |
462 | ||
b68755c1 MF |
463 | XtensaMemory instrom; |
464 | XtensaMemory instram; | |
465 | XtensaMemory datarom; | |
466 | XtensaMemory dataram; | |
467 | XtensaMemory sysrom; | |
468 | XtensaMemory sysram; | |
469 | ||
2cc2278e | 470 | unsigned hw_version; |
604e1f9c MF |
471 | uint32_t configid[2]; |
472 | ||
168c12b0 | 473 | void *isa_internal; |
33071f68 MF |
474 | xtensa_isa isa; |
475 | XtensaOpcodeOps **opcode_ops; | |
476 | const XtensaOpcodeTranslators **opcode_translators; | |
fe7869d6 | 477 | xtensa_regfile a_regfile; |
b0b24bdc | 478 | void ***regfile; |
168c12b0 | 479 | |
b994e91b | 480 | uint32_t clock_freq_khz; |
b67ea0cd MF |
481 | |
482 | xtensa_tlb itlb; | |
483 | xtensa_tlb dtlb; | |
4d04ea35 MF |
484 | |
485 | uint32_t mpu_align; | |
486 | unsigned n_mpu_fg_segments; | |
487 | unsigned n_mpu_bg_segments; | |
488 | const xtensa_mpu_entry *mpu_bg; | |
cfa9f051 MF |
489 | |
490 | bool use_first_nan; | |
da374261 | 491 | }; |
dedc5eae | 492 | |
ac8b7db4 MF |
493 | typedef struct XtensaConfigList { |
494 | const XtensaConfig *config; | |
495 | struct XtensaConfigList *next; | |
496 | } XtensaConfigList; | |
497 | ||
e03b5686 | 498 | #if HOST_BIG_ENDIAN |
ddd44279 MF |
499 | enum { |
500 | FP_F32_HIGH, | |
501 | FP_F32_LOW, | |
502 | }; | |
503 | #else | |
504 | enum { | |
505 | FP_F32_LOW, | |
506 | FP_F32_HIGH, | |
507 | }; | |
508 | #endif | |
509 | ||
1ea4a06a | 510 | struct CPUArchState { |
dedc5eae | 511 | const XtensaConfig *config; |
2328826b MF |
512 | uint32_t regs[16]; |
513 | uint32_t pc; | |
514 | uint32_t sregs[256]; | |
2af3da91 | 515 | uint32_t uregs[256]; |
553e44f9 | 516 | uint32_t phys_regs[MAX_NAREG]; |
ddd44279 MF |
517 | union { |
518 | float32 f32[2]; | |
519 | float64 f64; | |
520 | } fregs[16]; | |
dd519cbe | 521 | float_status fp_status; |
8df3fd35 | 522 | uint32_t windowbase_next; |
b345e140 MF |
523 | uint32_t exclusive_addr; |
524 | uint32_t exclusive_val; | |
2328826b | 525 | |
ba7651fb | 526 | #ifndef CONFIG_USER_ONLY |
b67ea0cd MF |
527 | xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE]; |
528 | xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE]; | |
4d04ea35 | 529 | xtensa_mpu_entry mpu_fg[MAX_MPU_FOREGROUND_SEGMENTS]; |
b67ea0cd | 530 | unsigned autorefill_idx; |
bd527a83 | 531 | bool runstall; |
3a3c9dc4 MF |
532 | AddressSpace *address_space_er; |
533 | MemoryRegion *system_er; | |
b994e91b | 534 | int pending_irq_level; /* level of last raised IRQ */ |
66f03d7e MF |
535 | qemu_irq *irq_inputs; |
536 | qemu_irq ext_irq_inputs[MAX_NINTERRUPT]; | |
17a86b0e | 537 | qemu_irq runstall_irq; |
59a71f75 MF |
538 | XtensaCcompareTimer ccompare[MAX_NCCOMPARE]; |
539 | uint64_t time_base; | |
540 | uint64_t ccount_time; | |
541 | uint32_t ccount_base; | |
ba7651fb | 542 | #endif |
b994e91b | 543 | |
d2132510 | 544 | int yield_needed; |
17ab14ac | 545 | unsigned static_vectors; |
40643d7c | 546 | |
f14c4b5f | 547 | /* Watchpoints for DBREAK registers */ |
ff4700b0 | 548 | struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK]; |
1ea4a06a | 549 | }; |
2328826b | 550 | |
da374261 PB |
551 | /** |
552 | * XtensaCPU: | |
553 | * @env: #CPUXtensaState | |
554 | * | |
555 | * An Xtensa CPU. | |
556 | */ | |
b36e239e | 557 | struct ArchCPU { |
da374261 PB |
558 | /*< private >*/ |
559 | CPUState parent_obj; | |
560 | /*< public >*/ | |
561 | ||
5b146dc7 | 562 | CPUNegativeOffsetState neg; |
da374261 PB |
563 | CPUXtensaState env; |
564 | }; | |
565 | ||
ba7651fb | 566 | |
6407f64f | 567 | #ifndef CONFIG_USER_ONLY |
b008c456 RH |
568 | bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
569 | MMUAccessType access_type, int mmu_idx, | |
570 | bool probe, uintptr_t retaddr); | |
da374261 PB |
571 | void xtensa_cpu_do_interrupt(CPUState *cpu); |
572 | bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request); | |
76b7dd64 MF |
573 | void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, |
574 | unsigned size, MMUAccessType access_type, | |
575 | int mmu_idx, MemTxAttrs attrs, | |
576 | MemTxResult response, uintptr_t retaddr); | |
f364a7f9 | 577 | #endif |
90c84c56 | 578 | void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, int flags); |
da374261 | 579 | hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); |
a7ac06fd MF |
580 | void xtensa_count_regs(const XtensaConfig *config, |
581 | unsigned *n_regs, unsigned *n_core_regs); | |
a010bdbe | 582 | int xtensa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); |
da374261 | 583 | int xtensa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); |
8905770b MAL |
584 | G_NORETURN void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, |
585 | MMUAccessType access_type, int mmu_idx, | |
586 | uintptr_t retaddr); | |
15be3171 | 587 | |
2328826b MF |
588 | #define cpu_list xtensa_cpu_list |
589 | ||
a5247d76 IM |
590 | #define XTENSA_CPU_TYPE_SUFFIX "-" TYPE_XTENSA_CPU |
591 | #define XTENSA_CPU_TYPE_NAME(model) model XTENSA_CPU_TYPE_SUFFIX | |
0dacec87 | 592 | #define CPU_RESOLVING_TYPE TYPE_XTENSA_CPU |
a5247d76 | 593 | |
ee3eb3a7 | 594 | #if TARGET_BIG_ENDIAN |
e38077ff | 595 | #define XTENSA_DEFAULT_CPU_MODEL "fsf" |
a3c5e49d | 596 | #define XTENSA_DEFAULT_CPU_NOMMU_MODEL "fsf" |
e38077ff MF |
597 | #else |
598 | #define XTENSA_DEFAULT_CPU_MODEL "dc232b" | |
a3c5e49d | 599 | #define XTENSA_DEFAULT_CPU_NOMMU_MODEL "de212" |
e38077ff | 600 | #endif |
a3c5e49d MF |
601 | #define XTENSA_DEFAULT_CPU_TYPE \ |
602 | XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_MODEL) | |
603 | #define XTENSA_DEFAULT_CPU_NOMMU_TYPE \ | |
604 | XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_NOMMU_MODEL) | |
e38077ff | 605 | |
59419607 | 606 | void xtensa_collect_sr_names(const XtensaConfig *config); |
2328826b | 607 | void xtensa_translate_init(void); |
ee659da2 | 608 | void **xtensa_get_regfile_by_name(const char *name, int entries, int bits); |
86025ee4 | 609 | void xtensa_breakpoint_handler(CPUState *cs); |
ac8b7db4 | 610 | void xtensa_register_core(XtensaConfigList *node); |
8128b3e0 | 611 | void xtensa_sim_open_console(Chardev *chr); |
b994e91b | 612 | void check_interrupts(CPUXtensaState *s); |
97129ac8 | 613 | void xtensa_irq_init(CPUXtensaState *env); |
66f03d7e | 614 | qemu_irq *xtensa_get_extints(CPUXtensaState *env); |
17a86b0e | 615 | qemu_irq xtensa_get_runstall(CPUXtensaState *env); |
0442428a | 616 | void xtensa_cpu_list(void); |
97129ac8 AF |
617 | void xtensa_sync_window_from_phys(CPUXtensaState *env); |
618 | void xtensa_sync_phys_from_window(CPUXtensaState *env); | |
ba7651fb MF |
619 | void xtensa_rotate_window(CPUXtensaState *env, uint32_t delta); |
620 | void xtensa_restore_owb(CPUXtensaState *env); | |
97129ac8 | 621 | void debug_exception_env(CPUXtensaState *new_env, uint32_t cause); |
b67ea0cd | 622 | |
17ab14ac MF |
623 | static inline void xtensa_select_static_vectors(CPUXtensaState *env, |
624 | unsigned n) | |
625 | { | |
626 | assert(n < 2); | |
627 | env->static_vectors = n; | |
628 | } | |
bd527a83 | 629 | void xtensa_runstall(CPUXtensaState *env, bool runstall); |
2328826b | 630 | |
dedc5eae | 631 | #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt)) |
fe0bd475 | 632 | #define XTENSA_OPTION_ALL (~(uint64_t)0) |
dedc5eae | 633 | |
b67ea0cd MF |
634 | static inline bool xtensa_option_bits_enabled(const XtensaConfig *config, |
635 | uint64_t opt) | |
636 | { | |
637 | return (config->options & opt) != 0; | |
638 | } | |
639 | ||
dedc5eae MF |
640 | static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt) |
641 | { | |
b67ea0cd | 642 | return xtensa_option_bits_enabled(config, XTENSA_OPTION_BIT(opt)); |
dedc5eae MF |
643 | } |
644 | ||
97129ac8 | 645 | static inline int xtensa_get_cintlevel(const CPUXtensaState *env) |
40643d7c MF |
646 | { |
647 | int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT; | |
648 | if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) { | |
649 | level = env->config->excm_level; | |
650 | } | |
651 | return level; | |
652 | } | |
653 | ||
97129ac8 | 654 | static inline int xtensa_get_ring(const CPUXtensaState *env) |
f0a548b9 | 655 | { |
6c438056 MF |
656 | if (xtensa_option_bits_enabled(env->config, |
657 | XTENSA_OPTION_BIT(XTENSA_OPTION_MMU) | | |
658 | XTENSA_OPTION_BIT(XTENSA_OPTION_MPU))) { | |
f0a548b9 MF |
659 | return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT; |
660 | } else { | |
661 | return 0; | |
662 | } | |
663 | } | |
664 | ||
97129ac8 | 665 | static inline int xtensa_get_cring(const CPUXtensaState *env) |
f0a548b9 | 666 | { |
6c438056 MF |
667 | if (xtensa_option_bits_enabled(env->config, |
668 | XTENSA_OPTION_BIT(XTENSA_OPTION_MMU) | | |
669 | XTENSA_OPTION_BIT(XTENSA_OPTION_MPU)) && | |
670 | (env->sregs[PS] & PS_EXCM) == 0) { | |
f0a548b9 MF |
671 | return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT; |
672 | } else { | |
673 | return 0; | |
674 | } | |
675 | } | |
676 | ||
ba7651fb | 677 | #ifndef CONFIG_USER_ONLY |
ba7651fb MF |
678 | int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb, |
679 | uint32_t vaddr, int is_write, int mmu_idx, | |
680 | uint32_t *paddr, uint32_t *page_size, unsigned *access); | |
681 | void reset_mmu(CPUXtensaState *env); | |
fad866da | 682 | void dump_mmu(CPUXtensaState *env); |
ba7651fb MF |
683 | |
684 | static inline MemoryRegion *xtensa_get_er_region(CPUXtensaState *env) | |
685 | { | |
686 | return env->system_er; | |
687 | } | |
130ea832 MF |
688 | #else |
689 | void xtensa_set_abi_call0(void); | |
690 | bool xtensa_abi_call0(void); | |
ba7651fb | 691 | #endif |
b67ea0cd | 692 | |
1b3e71f8 MF |
693 | static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env) |
694 | { | |
695 | return env->sregs[WINDOW_START] | | |
696 | (env->sregs[WINDOW_START] << env->config->nareg / 4); | |
697 | } | |
698 | ||
f0a548b9 | 699 | /* MMU modes definitions */ |
ba7651fb | 700 | #define MMU_USER_IDX 3 |
f0a548b9 | 701 | |
97ed5ccd | 702 | static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch) |
2328826b | 703 | { |
f0a548b9 | 704 | return xtensa_get_cring(env); |
2328826b MF |
705 | } |
706 | ||
f0a548b9 MF |
707 | #define XTENSA_TBFLAG_RING_MASK 0x3 |
708 | #define XTENSA_TBFLAG_EXCM 0x4 | |
6ad6dbf7 | 709 | #define XTENSA_TBFLAG_LITBASE 0x8 |
e61dc8f7 | 710 | #define XTENSA_TBFLAG_DEBUG 0x10 |
35b5c044 | 711 | #define XTENSA_TBFLAG_ICOUNT 0x20 |
ef04a846 MF |
712 | #define XTENSA_TBFLAG_CPENABLE_MASK 0x3fc0 |
713 | #define XTENSA_TBFLAG_CPENABLE_SHIFT 6 | |
2db59a76 MF |
714 | #define XTENSA_TBFLAG_WINDOW_MASK 0x18000 |
715 | #define XTENSA_TBFLAG_WINDOW_SHIFT 15 | |
d2132510 | 716 | #define XTENSA_TBFLAG_YIELD 0x20000 |
09460970 | 717 | #define XTENSA_TBFLAG_CWOE 0x40000 |
6416d16f MF |
718 | #define XTENSA_TBFLAG_CALLINC_MASK 0x180000 |
719 | #define XTENSA_TBFLAG_CALLINC_SHIFT 19 | |
f0a548b9 | 720 | |
5d630cef MF |
721 | #define XTENSA_CSBASE_LEND_MASK 0x0000ffff |
722 | #define XTENSA_CSBASE_LEND_SHIFT 0 | |
723 | #define XTENSA_CSBASE_LBEG_OFF_MASK 0x00ff0000 | |
724 | #define XTENSA_CSBASE_LBEG_OFF_SHIFT 16 | |
725 | ||
92fddfbd RH |
726 | #include "exec/cpu-all.h" |
727 | ||
97129ac8 | 728 | static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc, |
89fee74a | 729 | target_ulong *cs_base, uint32_t *flags) |
2328826b MF |
730 | { |
731 | *pc = env->pc; | |
732 | *cs_base = 0; | |
733 | *flags = 0; | |
f0a548b9 MF |
734 | *flags |= xtensa_get_ring(env); |
735 | if (env->sregs[PS] & PS_EXCM) { | |
736 | *flags |= XTENSA_TBFLAG_EXCM; | |
5d630cef MF |
737 | } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) { |
738 | target_ulong lend_dist = | |
739 | env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS)); | |
740 | ||
741 | /* | |
742 | * 0 in the csbase_lend field means that there may not be a loopback | |
743 | * for any instruction that starts inside this page. Any other value | |
744 | * means that an instruction that ends at this offset from the page | |
745 | * start may loop back and will need loopback code to be generated. | |
746 | * | |
747 | * lend_dist is 0 when LEND points to the start of the page, but | |
748 | * no instruction that starts inside this page may end at offset 0, | |
749 | * so it's still correct. | |
750 | * | |
751 | * When an instruction ends at a page boundary it may only start in | |
752 | * the previous page. lend_dist will be encoded as TARGET_PAGE_SIZE | |
753 | * for the TB that contains this instruction. | |
754 | */ | |
755 | if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_size) { | |
756 | target_ulong lbeg_off = env->sregs[LEND] - env->sregs[LBEG]; | |
757 | ||
758 | *cs_base = lend_dist; | |
759 | if (lbeg_off < 256) { | |
760 | *cs_base |= lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT; | |
761 | } | |
762 | } | |
f0a548b9 | 763 | } |
6ad6dbf7 MF |
764 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) && |
765 | (env->sregs[LITBASE] & 1)) { | |
766 | *flags |= XTENSA_TBFLAG_LITBASE; | |
767 | } | |
e61dc8f7 MF |
768 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) { |
769 | if (xtensa_get_cintlevel(env) < env->config->debug_level) { | |
770 | *flags |= XTENSA_TBFLAG_DEBUG; | |
771 | } | |
35b5c044 MF |
772 | if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) { |
773 | *flags |= XTENSA_TBFLAG_ICOUNT; | |
774 | } | |
e61dc8f7 | 775 | } |
ef04a846 MF |
776 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) { |
777 | *flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT; | |
778 | } | |
2db59a76 MF |
779 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER) && |
780 | (env->sregs[PS] & (PS_WOE | PS_EXCM)) == PS_WOE) { | |
781 | uint32_t windowstart = xtensa_replicate_windowstart(env) >> | |
782 | (env->sregs[WINDOW_BASE] + 1); | |
783 | uint32_t w = ctz32(windowstart | 0x8); | |
784 | ||
09460970 | 785 | *flags |= (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE; |
6416d16f MF |
786 | *flags |= extract32(env->sregs[PS], PS_CALLINC_SHIFT, |
787 | PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT; | |
2db59a76 MF |
788 | } else { |
789 | *flags |= 3 << XTENSA_TBFLAG_WINDOW_SHIFT; | |
790 | } | |
d2132510 MF |
791 | if (env->yield_needed) { |
792 | *flags |= XTENSA_TBFLAG_YIELD; | |
793 | } | |
2328826b MF |
794 | } |
795 | ||
2328826b | 796 | #endif |