[mirror_qemu.git] / target / xtensa / overlay_tool.h

/*
 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in the
 *       documentation and/or other materials provided with the distribution.
 *     * Neither the name of the Open Source and Linux Lab nor the
 *       names of its contributors may be used to endorse or promote products
 *       derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#define XTREG(idx, ofs, bi, sz, al, no, flags, cp, typ, grp, name, \
        a1, a2, a3, a4, a5, a6) \
    { .targno = (no), .type = (typ), .group = (grp), .size = (sz) },
#define XTREG_END { .targno = -1 },

#ifndef XCHAL_HAVE_DEPBITS
#define XCHAL_HAVE_DEPBITS 0
#endif

#ifndef XCHAL_HAVE_DIV32
#define XCHAL_HAVE_DIV32 0
#endif

#ifndef XCHAL_UNALIGNED_LOAD_HW
#define XCHAL_UNALIGNED_LOAD_HW 0
#endif

#ifndef XCHAL_HAVE_VECBASE
#define XCHAL_HAVE_VECBASE 0
#define XCHAL_VECBASE_RESET_VADDR 0
#endif

#ifndef XCHAL_RESET_VECTOR0_VADDR
#define XCHAL_RESET_VECTOR0_VADDR XCHAL_RESET_VECTOR_VADDR
#endif

#ifndef XCHAL_RESET_VECTOR1_VADDR
#define XCHAL_RESET_VECTOR1_VADDR XCHAL_RESET_VECTOR_VADDR
#endif

#ifndef XCHAL_HW_MIN_VERSION
#define XCHAL_HW_MIN_VERSION 0
#endif

#ifndef XCHAL_LOOP_BUFFER_SIZE
#define XCHAL_LOOP_BUFFER_SIZE 0
#endif

#ifndef XCHAL_HAVE_EXTERN_REGS
#define XCHAL_HAVE_EXTERN_REGS 0
#endif

#define XCHAL_OPTION(xchal, qemu) ((xchal) ? XTENSA_OPTION_BIT(qemu) : 0)

#define XTENSA_OPTIONS ( \
    XCHAL_OPTION(XCHAL_HAVE_DENSITY, XTENSA_OPTION_CODE_DENSITY) | \
    XCHAL_OPTION(XCHAL_HAVE_LOOPS, XTENSA_OPTION_LOOP) | \
    XCHAL_OPTION(XCHAL_HAVE_ABSOLUTE_LITERALS, XTENSA_OPTION_EXTENDED_L32R) | \
    XCHAL_OPTION(XCHAL_HAVE_MUL16, XTENSA_OPTION_16_BIT_IMUL) | \
    XCHAL_OPTION(XCHAL_HAVE_MUL32, XTENSA_OPTION_32_BIT_IMUL) | \
    XCHAL_OPTION(XCHAL_HAVE_MUL32_HIGH, XTENSA_OPTION_32_BIT_IMUL_HIGH) | \
    XCHAL_OPTION(XCHAL_HAVE_DIV32, XTENSA_OPTION_32_BIT_IDIV) | \
    XCHAL_OPTION(XCHAL_HAVE_MAC16, XTENSA_OPTION_MAC16) | \
    XCHAL_OPTION(XCHAL_HAVE_NSA, XTENSA_OPTION_MISC_OP_NSA) | \
    XCHAL_OPTION(XCHAL_HAVE_MINMAX, XTENSA_OPTION_MISC_OP_MINMAX) | \
    XCHAL_OPTION(XCHAL_HAVE_SEXT, XTENSA_OPTION_MISC_OP_SEXT) | \
    XCHAL_OPTION(XCHAL_HAVE_CLAMPS, XTENSA_OPTION_MISC_OP_CLAMPS) | \
    XCHAL_OPTION(XCHAL_HAVE_CP, XTENSA_OPTION_COPROCESSOR) | \
    XCHAL_OPTION(XCHAL_HAVE_BOOLEANS, XTENSA_OPTION_BOOLEAN) | \
    XCHAL_OPTION(XCHAL_HAVE_FP, XTENSA_OPTION_FP_COPROCESSOR) | \
    XCHAL_OPTION(XCHAL_HAVE_RELEASE_SYNC, XTENSA_OPTION_MP_SYNCHRO) | \
    XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) | \
    XCHAL_OPTION(XCHAL_HAVE_S32C1I && XCHAL_HW_MIN_VERSION >= 230000, \
        XTENSA_OPTION_ATOMCTL) | \
    XCHAL_OPTION(XCHAL_HAVE_DEPBITS, XTENSA_OPTION_DEPBITS) | \
    /* Interrupts and exceptions */ \
    XCHAL_OPTION(XCHAL_HAVE_EXCEPTIONS, XTENSA_OPTION_EXCEPTION) | \
    XCHAL_OPTION(XCHAL_HAVE_VECBASE, XTENSA_OPTION_RELOCATABLE_VECTOR) | \
    XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_EXCEPTION, \
        XTENSA_OPTION_UNALIGNED_EXCEPTION) | \
    XCHAL_OPTION(XCHAL_HAVE_INTERRUPTS, XTENSA_OPTION_INTERRUPT) | \
    XCHAL_OPTION(XCHAL_HAVE_HIGHPRI_INTERRUPTS, \
        XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT) | \
    XCHAL_OPTION(XCHAL_HAVE_CCOUNT, XTENSA_OPTION_TIMER_INTERRUPT) | \
    /* Local memory, TODO */ \
    XCHAL_OPTION(XCHAL_ICACHE_SIZE, XTENSA_OPTION_ICACHE) | \
    XCHAL_OPTION(XCHAL_ICACHE_LINE_LOCKABLE, \
            XTENSA_OPTION_ICACHE_INDEX_LOCK) | \
    XCHAL_OPTION(XCHAL_DCACHE_SIZE, XTENSA_OPTION_DCACHE) | \
    XCHAL_OPTION(XCHAL_DCACHE_LINE_LOCKABLE, \
            XTENSA_OPTION_DCACHE_INDEX_LOCK) | \
    XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_HW, XTENSA_OPTION_HW_ALIGNMENT) | \
    /* Memory protection and translation */ \
    XCHAL_OPTION(XCHAL_HAVE_MIMIC_CACHEATTR, \
            XTENSA_OPTION_REGION_PROTECTION) | \
    XCHAL_OPTION(XCHAL_HAVE_XLT_CACHEATTR, \
            XTENSA_OPTION_REGION_TRANSLATION) | \
    XCHAL_OPTION(XCHAL_HAVE_PTP_MMU, XTENSA_OPTION_MMU) | \
    XCHAL_OPTION(XCHAL_HAVE_CACHEATTR, XTENSA_OPTION_CACHEATTR) | \
    /* Other, TODO */ \
    XCHAL_OPTION(XCHAL_HAVE_WINDOWED, XTENSA_OPTION_WINDOWED_REGISTER) | \
    XCHAL_OPTION(XCHAL_HAVE_DEBUG, XTENSA_OPTION_DEBUG) |\
    XCHAL_OPTION(XCHAL_NUM_MISC_REGS > 0, XTENSA_OPTION_MISC_SR) | \
    XCHAL_OPTION(XCHAL_HAVE_THREADPTR, XTENSA_OPTION_THREAD_POINTER) | \
    XCHAL_OPTION(XCHAL_HAVE_PRID, XTENSA_OPTION_PROCESSOR_ID) | \
    XCHAL_OPTION(XCHAL_HAVE_EXTERN_REGS, XTENSA_OPTION_EXTERN_REGS))

#ifndef XCHAL_WINDOW_OF4_VECOFS
#define XCHAL_WINDOW_OF4_VECOFS         0x00000000
#define XCHAL_WINDOW_UF4_VECOFS         0x00000040
#define XCHAL_WINDOW_OF8_VECOFS         0x00000080
#define XCHAL_WINDOW_UF8_VECOFS         0x000000C0
#define XCHAL_WINDOW_OF12_VECOFS        0x00000100
#define XCHAL_WINDOW_UF12_VECOFS        0x00000140
#endif

#if XCHAL_HAVE_WINDOWED
#define WINDOW_VECTORS \
   [EXC_WINDOW_OVERFLOW4] = XCHAL_WINDOW_OF4_VECOFS + \
       XCHAL_WINDOW_VECTORS_VADDR, \
   [EXC_WINDOW_UNDERFLOW4] = XCHAL_WINDOW_UF4_VECOFS + \
       XCHAL_WINDOW_VECTORS_VADDR, \
   [EXC_WINDOW_OVERFLOW8] = XCHAL_WINDOW_OF8_VECOFS + \
       XCHAL_WINDOW_VECTORS_VADDR, \
   [EXC_WINDOW_UNDERFLOW8] = XCHAL_WINDOW_UF8_VECOFS + \
       XCHAL_WINDOW_VECTORS_VADDR, \
   [EXC_WINDOW_OVERFLOW12] = XCHAL_WINDOW_OF12_VECOFS + \
       XCHAL_WINDOW_VECTORS_VADDR, \
   [EXC_WINDOW_UNDERFLOW12] = XCHAL_WINDOW_UF12_VECOFS + \
       XCHAL_WINDOW_VECTORS_VADDR,
#else
#define WINDOW_VECTORS
#endif

#define EXCEPTION_VECTORS { \
        [EXC_RESET0] = XCHAL_RESET_VECTOR0_VADDR, \
        [EXC_RESET1] = XCHAL_RESET_VECTOR1_VADDR, \
        WINDOW_VECTORS \
        [EXC_KERNEL] = XCHAL_KERNEL_VECTOR_VADDR, \
        [EXC_USER] = XCHAL_USER_VECTOR_VADDR, \
        [EXC_DOUBLE] = XCHAL_DOUBLEEXC_VECTOR_VADDR, \
        [EXC_DEBUG] = XCHAL_DEBUG_VECTOR_VADDR, \
    }

#define INTERRUPT_VECTORS { \
        0, \
        0, \
        XCHAL_INTLEVEL2_VECTOR_VADDR, \
        XCHAL_INTLEVEL3_VECTOR_VADDR, \
        XCHAL_INTLEVEL4_VECTOR_VADDR, \
        XCHAL_INTLEVEL5_VECTOR_VADDR, \
        XCHAL_INTLEVEL6_VECTOR_VADDR, \
        XCHAL_INTLEVEL7_VECTOR_VADDR, \
    }

#define LEVEL_MASKS { \
        [1] = XCHAL_INTLEVEL1_MASK, \
        [2] = XCHAL_INTLEVEL2_MASK, \
        [3] = XCHAL_INTLEVEL3_MASK, \
        [4] = XCHAL_INTLEVEL4_MASK, \
        [5] = XCHAL_INTLEVEL5_MASK, \
        [6] = XCHAL_INTLEVEL6_MASK, \
        [7] = XCHAL_INTLEVEL7_MASK, \
    }

#define INTTYPE_MASKS { \
        [INTTYPE_EDGE] = XCHAL_INTTYPE_MASK_EXTERN_EDGE, \
        [INTTYPE_NMI] = XCHAL_INTTYPE_MASK_NMI, \
        [INTTYPE_SOFTWARE] = XCHAL_INTTYPE_MASK_SOFTWARE, \
    }

#define XTHAL_INTTYPE_EXTERN_LEVEL INTTYPE_LEVEL
#define XTHAL_INTTYPE_EXTERN_EDGE INTTYPE_EDGE
#define XTHAL_INTTYPE_NMI INTTYPE_NMI
#define XTHAL_INTTYPE_SOFTWARE INTTYPE_SOFTWARE
#define XTHAL_INTTYPE_TIMER INTTYPE_TIMER
#define XTHAL_INTTYPE_TBD1 INTTYPE_DEBUG
#define XTHAL_INTTYPE_TBD2 INTTYPE_WRITE_ERR
#define XTHAL_INTTYPE_WRITE_ERROR INTTYPE_WRITE_ERR
#define XTHAL_INTTYPE_PROFILING INTTYPE_PROFILING


#define INTERRUPT(i) { \
        .level = XCHAL_INT ## i ## _LEVEL, \
        .inttype = XCHAL_INT ## i ## _TYPE, \
    }

#define INTERRUPTS { \
        [0] = INTERRUPT(0), \
        [1] = INTERRUPT(1), \
        [2] = INTERRUPT(2), \
        [3] = INTERRUPT(3), \
        [4] = INTERRUPT(4), \
        [5] = INTERRUPT(5), \
        [6] = INTERRUPT(6), \
        [7] = INTERRUPT(7), \
        [8] = INTERRUPT(8), \
        [9] = INTERRUPT(9), \
        [10] = INTERRUPT(10), \
        [11] = INTERRUPT(11), \
        [12] = INTERRUPT(12), \
        [13] = INTERRUPT(13), \
        [14] = INTERRUPT(14), \
        [15] = INTERRUPT(15), \
        [16] = INTERRUPT(16), \
        [17] = INTERRUPT(17), \
        [18] = INTERRUPT(18), \
        [19] = INTERRUPT(19), \
        [20] = INTERRUPT(20), \
        [21] = INTERRUPT(21), \
        [22] = INTERRUPT(22), \
        [23] = INTERRUPT(23), \
        [24] = INTERRUPT(24), \
        [25] = INTERRUPT(25), \
        [26] = INTERRUPT(26), \
        [27] = INTERRUPT(27), \
        [28] = INTERRUPT(28), \
        [29] = INTERRUPT(29), \
        [30] = INTERRUPT(30), \
        [31] = INTERRUPT(31), \
    }

#define TIMERINTS { \
        [0] = XCHAL_TIMER0_INTERRUPT, \
        [1] = XCHAL_TIMER1_INTERRUPT, \
        [2] = XCHAL_TIMER2_INTERRUPT, \
    }

#define EXTINTS { \
        [0] = XCHAL_EXTINT0_NUM, \
        [1] = XCHAL_EXTINT1_NUM, \
        [2] = XCHAL_EXTINT2_NUM, \
        [3] = XCHAL_EXTINT3_NUM, \
        [4] = XCHAL_EXTINT4_NUM, \
        [5] = XCHAL_EXTINT5_NUM, \
        [6] = XCHAL_EXTINT6_NUM, \
        [7] = XCHAL_EXTINT7_NUM, \
        [8] = XCHAL_EXTINT8_NUM, \
        [9] = XCHAL_EXTINT9_NUM, \
        [10] = XCHAL_EXTINT10_NUM, \
        [11] = XCHAL_EXTINT11_NUM, \
        [12] = XCHAL_EXTINT12_NUM, \
        [13] = XCHAL_EXTINT13_NUM, \
        [14] = XCHAL_EXTINT14_NUM, \
        [15] = XCHAL_EXTINT15_NUM, \
        [16] = XCHAL_EXTINT16_NUM, \
        [17] = XCHAL_EXTINT17_NUM, \
        [18] = XCHAL_EXTINT18_NUM, \
        [19] = XCHAL_EXTINT19_NUM, \
        [20] = XCHAL_EXTINT20_NUM, \
        [21] = XCHAL_EXTINT21_NUM, \
        [22] = XCHAL_EXTINT22_NUM, \
        [23] = XCHAL_EXTINT23_NUM, \
        [24] = XCHAL_EXTINT24_NUM, \
        [25] = XCHAL_EXTINT25_NUM, \
        [26] = XCHAL_EXTINT26_NUM, \
        [27] = XCHAL_EXTINT27_NUM, \
        [28] = XCHAL_EXTINT28_NUM, \
        [29] = XCHAL_EXTINT29_NUM, \
        [30] = XCHAL_EXTINT30_NUM, \
        [31] = XCHAL_EXTINT31_NUM, \
    }

#define EXCEPTIONS_SECTION \
    .excm_level = XCHAL_EXCM_LEVEL, \
    .vecbase = XCHAL_VECBASE_RESET_VADDR, \
    .exception_vector = EXCEPTION_VECTORS

#define INTERRUPTS_SECTION \
    .ninterrupt = XCHAL_NUM_INTERRUPTS, \
    .nlevel = XCHAL_NUM_INTLEVELS, \
    .interrupt_vector = INTERRUPT_VECTORS, \
    .level_mask = LEVEL_MASKS, \
    .inttype_mask = INTTYPE_MASKS, \
    .interrupt = INTERRUPTS, \
    .nccompare = XCHAL_NUM_TIMERS, \
    .timerint = TIMERINTS, \
    .nextint = XCHAL_NUM_EXTINTERRUPTS, \
    .extint = EXTINTS

#if XCHAL_HAVE_PTP_MMU

#define TLB_TEMPLATE(ways, refill_way_size, way56) { \
        .nways = ways, \
        .way_size = { \
            (refill_way_size), (refill_way_size), \
            (refill_way_size), (refill_way_size), \
            4, (way56) ? 4 : 2, (way56) ? 8 : 2, 1, 1, 1, \
        }, \
        .varway56 = (way56), \
        .nrefillentries = (refill_way_size) * 4, \
    }

#define ITLB(varway56) \
    TLB_TEMPLATE(7, 1 << XCHAL_ITLB_ARF_ENTRIES_LOG2, varway56)

#define DTLB(varway56) \
    TLB_TEMPLATE(10, 1 << XCHAL_DTLB_ARF_ENTRIES_LOG2, varway56)

#define TLB_SECTION \
    .itlb = ITLB(XCHAL_HAVE_SPANNING_WAY), \
    .dtlb = DTLB(XCHAL_HAVE_SPANNING_WAY)

#elif XCHAL_HAVE_XLT_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR

#define TLB_TEMPLATE { \
        .nways = 1, \
        .way_size = { \
            8, \
        } \
    }

#define TLB_SECTION \
    .itlb = TLB_TEMPLATE, \
    .dtlb = TLB_TEMPLATE

#endif

#if (defined(TARGET_WORDS_BIGENDIAN) != 0) == (XCHAL_HAVE_BE != 0)
#define REGISTER_CORE(core) \
    static void __attribute__((constructor)) register_core(void) \
    { \
        static XtensaConfigList node = { \
            .config = &core, \
        }; \
        xtensa_finalize_config(&core); \
        xtensa_register_core(&node); \
    }
#else
#define REGISTER_CORE(core)
#endif

#define DEBUG_SECTION \
    .debug_level = XCHAL_DEBUGLEVEL, \
    .nibreak = XCHAL_NUM_IBREAK, \
    .ndbreak = XCHAL_NUM_DBREAK

#define CACHE_SECTION \
    .icache_ways = XCHAL_ICACHE_WAYS, \
    .dcache_ways = XCHAL_DCACHE_WAYS, \
    .memctl_mask = \
        (XCHAL_ICACHE_SIZE ? MEMCTL_IUSEWAYS_MASK : 0) | \
        (XCHAL_DCACHE_SIZE ? \
         MEMCTL_DALLOCWAYS_MASK | MEMCTL_DUSEWAYS_MASK : 0) | \
        MEMCTL_ISNP | MEMCTL_DSNP | \
        (XCHAL_HAVE_LOOPS && XCHAL_LOOP_BUFFER_SIZE ? MEMCTL_IL0EN : 0)

#define CONFIG_SECTION \
    .configid = { \
        XCHAL_HW_CONFIGID0, \
        XCHAL_HW_CONFIGID1, \
    }

#define DEFAULT_SECTIONS \
    .options = XTENSA_OPTIONS, \
    .nareg = XCHAL_NUM_AREGS, \
    .ndepc = (XCHAL_XEA_VERSION >= 2), \
    EXCEPTIONS_SECTION, \
    INTERRUPTS_SECTION, \
    TLB_SECTION, \
    DEBUG_SECTION, \
    CACHE_SECTION, \
    CONFIG_SECTION


#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 2
#define XCHAL_INTLEVEL2_VECTOR_VADDR 0
#endif
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 3
#define XCHAL_INTLEVEL3_VECTOR_VADDR 0
#endif
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 4
#define XCHAL_INTLEVEL4_VECTOR_VADDR 0
#endif
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 5
#define XCHAL_INTLEVEL5_VECTOR_VADDR 0
#endif
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 6
#define XCHAL_INTLEVEL6_VECTOR_VADDR 0
#endif
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 7
#define XCHAL_INTLEVEL7_VECTOR_VADDR 0
#endif


#if XCHAL_NUM_INTERRUPTS <= 0
#define XCHAL_INT0_LEVEL 0
#define XCHAL_INT0_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 1
#define XCHAL_INT1_LEVEL 0
#define XCHAL_INT1_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 2
#define XCHAL_INT2_LEVEL 0
#define XCHAL_INT2_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 3
#define XCHAL_INT3_LEVEL 0
#define XCHAL_INT3_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 4
#define XCHAL_INT4_LEVEL 0
#define XCHAL_INT4_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 5
#define XCHAL_INT5_LEVEL 0
#define XCHAL_INT5_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 6
#define XCHAL_INT6_LEVEL 0
#define XCHAL_INT6_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 7
#define XCHAL_INT7_LEVEL 0
#define XCHAL_INT7_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 8
#define XCHAL_INT8_LEVEL 0
#define XCHAL_INT8_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 9
#define XCHAL_INT9_LEVEL 0
#define XCHAL_INT9_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 10
#define XCHAL_INT10_LEVEL 0
#define XCHAL_INT10_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 11
#define XCHAL_INT11_LEVEL 0
#define XCHAL_INT11_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 12
#define XCHAL_INT12_LEVEL 0
#define XCHAL_INT12_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 13
#define XCHAL_INT13_LEVEL 0
#define XCHAL_INT13_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 14
#define XCHAL_INT14_LEVEL 0
#define XCHAL_INT14_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 15
#define XCHAL_INT15_LEVEL 0
#define XCHAL_INT15_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 16
#define XCHAL_INT16_LEVEL 0
#define XCHAL_INT16_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 17
#define XCHAL_INT17_LEVEL 0
#define XCHAL_INT17_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 18
#define XCHAL_INT18_LEVEL 0
#define XCHAL_INT18_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 19
#define XCHAL_INT19_LEVEL 0
#define XCHAL_INT19_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 20
#define XCHAL_INT20_LEVEL 0
#define XCHAL_INT20_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 21
#define XCHAL_INT21_LEVEL 0
#define XCHAL_INT21_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 22
#define XCHAL_INT22_LEVEL 0
#define XCHAL_INT22_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 23
#define XCHAL_INT23_LEVEL 0
#define XCHAL_INT23_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 24
#define XCHAL_INT24_LEVEL 0
#define XCHAL_INT24_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 25
#define XCHAL_INT25_LEVEL 0
#define XCHAL_INT25_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 26
#define XCHAL_INT26_LEVEL 0
#define XCHAL_INT26_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 27
#define XCHAL_INT27_LEVEL 0
#define XCHAL_INT27_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 28
#define XCHAL_INT28_LEVEL 0
#define XCHAL_INT28_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 29
#define XCHAL_INT29_LEVEL 0
#define XCHAL_INT29_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 30
#define XCHAL_INT30_LEVEL 0
#define XCHAL_INT30_TYPE 0
#endif
#if XCHAL_NUM_INTERRUPTS <= 31
#define XCHAL_INT31_LEVEL 0
#define XCHAL_INT31_TYPE 0
#endif


#if XCHAL_NUM_EXTINTERRUPTS <= 0
#define XCHAL_EXTINT0_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 1
#define XCHAL_EXTINT1_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 2
#define XCHAL_EXTINT2_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 3
#define XCHAL_EXTINT3_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 4
#define XCHAL_EXTINT4_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 5
#define XCHAL_EXTINT5_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 6
#define XCHAL_EXTINT6_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 7
#define XCHAL_EXTINT7_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 8
#define XCHAL_EXTINT8_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 9
#define XCHAL_EXTINT9_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 10
#define XCHAL_EXTINT10_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 11
#define XCHAL_EXTINT11_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 12
#define XCHAL_EXTINT12_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 13
#define XCHAL_EXTINT13_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 14
#define XCHAL_EXTINT14_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 15
#define XCHAL_EXTINT15_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 16
#define XCHAL_EXTINT16_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 17
#define XCHAL_EXTINT17_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 18
#define XCHAL_EXTINT18_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 19
#define XCHAL_EXTINT19_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 20
#define XCHAL_EXTINT20_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 21
#define XCHAL_EXTINT21_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 22
#define XCHAL_EXTINT22_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 23
#define XCHAL_EXTINT23_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 24
#define XCHAL_EXTINT24_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 25
#define XCHAL_EXTINT25_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 26
#define XCHAL_EXTINT26_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 27
#define XCHAL_EXTINT27_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 28
#define XCHAL_EXTINT28_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 29
#define XCHAL_EXTINT29_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 30
#define XCHAL_EXTINT30_NUM 0
#endif
#if XCHAL_NUM_EXTINTERRUPTS <= 31
#define XCHAL_EXTINT31_NUM 0
#endif


#define XTHAL_TIMER_UNCONFIGURED 0
Commit	Line	Data
ac8b7db4 MF	1	/*
	2	* Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
	3	* All rights reserved.
	4	*
	5	* Redistribution and use in source and binary forms, with or without
	6	* modification, are permitted provided that the following conditions are met:
	7	* * Redistributions of source code must retain the above copyright
	8	* notice, this list of conditions and the following disclaimer.
	9	* * Redistributions in binary form must reproduce the above copyright
	10	* notice, this list of conditions and the following disclaimer in the
	11	* documentation and/or other materials provided with the distribution.
	12	* * Neither the name of the Open Source and Linux Lab nor the
	13	* names of its contributors may be used to endorse or promote products
	14	* derived from this software without specific prior written permission.
	15	*
	16	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	17	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	18	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	19	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
	20	* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	21	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	22	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
	23	* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	24	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	25	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	26	*/
	27
	28	#define XTREG(idx, ofs, bi, sz, al, no, flags, cp, typ, grp, name, \
	29	a1, a2, a3, a4, a5, a6) \
ddd44279	30	{ .targno = (no), .type = (typ), .group = (grp), .size = (sz) },
1479073b	31	#define XTREG_END { .targno = -1 },
ac8b7db4	32
5eeb40c5 MF	33	#ifndef XCHAL_HAVE_DEPBITS
	34	#define XCHAL_HAVE_DEPBITS 0
	35	#endif
	36
ac8b7db4 MF	37	#ifndef XCHAL_HAVE_DIV32
	38	#define XCHAL_HAVE_DIV32 0
	39	#endif
	40
	41	#ifndef XCHAL_UNALIGNED_LOAD_HW
	42	#define XCHAL_UNALIGNED_LOAD_HW 0
	43	#endif
	44
	45	#ifndef XCHAL_HAVE_VECBASE
	46	#define XCHAL_HAVE_VECBASE 0
	47	#define XCHAL_VECBASE_RESET_VADDR 0
	48	#endif
	49
17ab14ac MF	50	#ifndef XCHAL_RESET_VECTOR0_VADDR
	51	#define XCHAL_RESET_VECTOR0_VADDR XCHAL_RESET_VECTOR_VADDR
	52	#endif
	53
	54	#ifndef XCHAL_RESET_VECTOR1_VADDR
	55	#define XCHAL_RESET_VECTOR1_VADDR XCHAL_RESET_VECTOR_VADDR
	56	#endif
	57
fcc803d1 MF	58	#ifndef XCHAL_HW_MIN_VERSION
	59	#define XCHAL_HW_MIN_VERSION 0
	60	#endif
	61
9e03ade4 MF	62	#ifndef XCHAL_LOOP_BUFFER_SIZE
	63	#define XCHAL_LOOP_BUFFER_SIZE 0
	64	#endif
	65
3a3c9dc4 MF	66	#ifndef XCHAL_HAVE_EXTERN_REGS
	67	#define XCHAL_HAVE_EXTERN_REGS 0
	68	#endif
	69
ac8b7db4 MF	70	#define XCHAL_OPTION(xchal, qemu) ((xchal) ? XTENSA_OPTION_BIT(qemu) : 0)
	71
	72	#define XTENSA_OPTIONS ( \
	73	XCHAL_OPTION(XCHAL_HAVE_DENSITY, XTENSA_OPTION_CODE_DENSITY) \| \
	74	XCHAL_OPTION(XCHAL_HAVE_LOOPS, XTENSA_OPTION_LOOP) \| \
	75	XCHAL_OPTION(XCHAL_HAVE_ABSOLUTE_LITERALS, XTENSA_OPTION_EXTENDED_L32R) \| \
	76	XCHAL_OPTION(XCHAL_HAVE_MUL16, XTENSA_OPTION_16_BIT_IMUL) \| \
	77	XCHAL_OPTION(XCHAL_HAVE_MUL32, XTENSA_OPTION_32_BIT_IMUL) \| \
	78	XCHAL_OPTION(XCHAL_HAVE_MUL32_HIGH, XTENSA_OPTION_32_BIT_IMUL_HIGH) \| \
	79	XCHAL_OPTION(XCHAL_HAVE_DIV32, XTENSA_OPTION_32_BIT_IDIV) \| \
	80	XCHAL_OPTION(XCHAL_HAVE_MAC16, XTENSA_OPTION_MAC16) \| \
	81	XCHAL_OPTION(XCHAL_HAVE_NSA, XTENSA_OPTION_MISC_OP_NSA) \| \
	82	XCHAL_OPTION(XCHAL_HAVE_MINMAX, XTENSA_OPTION_MISC_OP_MINMAX) \| \
	83	XCHAL_OPTION(XCHAL_HAVE_SEXT, XTENSA_OPTION_MISC_OP_SEXT) \| \
	84	XCHAL_OPTION(XCHAL_HAVE_CLAMPS, XTENSA_OPTION_MISC_OP_CLAMPS) \| \
	85	XCHAL_OPTION(XCHAL_HAVE_CP, XTENSA_OPTION_COPROCESSOR) \| \
10f6ca03	86	XCHAL_OPTION(XCHAL_HAVE_BOOLEANS, XTENSA_OPTION_BOOLEAN) \| \
ac8b7db4 MF	87	XCHAL_OPTION(XCHAL_HAVE_FP, XTENSA_OPTION_FP_COPROCESSOR) \| \
	88	XCHAL_OPTION(XCHAL_HAVE_RELEASE_SYNC, XTENSA_OPTION_MP_SYNCHRO) \| \
	89	XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) \| \
fcc803d1 MF	90	XCHAL_OPTION(XCHAL_HAVE_S32C1I && XCHAL_HW_MIN_VERSION >= 230000, \
fcc803d1 MF	91	XTENSA_OPTION_ATOMCTL) \| \
5eeb40c5	92	XCHAL_OPTION(XCHAL_HAVE_DEPBITS, XTENSA_OPTION_DEPBITS) \| \
ac8b7db4 MF	93	/* Interrupts and exceptions */ \
	94	XCHAL_OPTION(XCHAL_HAVE_EXCEPTIONS, XTENSA_OPTION_EXCEPTION) \| \
	95	XCHAL_OPTION(XCHAL_HAVE_VECBASE, XTENSA_OPTION_RELOCATABLE_VECTOR) \| \
	96	XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_EXCEPTION, \
	97	XTENSA_OPTION_UNALIGNED_EXCEPTION) \| \
	98	XCHAL_OPTION(XCHAL_HAVE_INTERRUPTS, XTENSA_OPTION_INTERRUPT) \| \
	99	XCHAL_OPTION(XCHAL_HAVE_HIGHPRI_INTERRUPTS, \
	100	XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT) \| \
	101	XCHAL_OPTION(XCHAL_HAVE_CCOUNT, XTENSA_OPTION_TIMER_INTERRUPT) \| \
	102	/* Local memory, TODO */ \
4b37aaa8	103	XCHAL_OPTION(XCHAL_ICACHE_SIZE, XTENSA_OPTION_ICACHE) \| \
0c852e17 MF	104	XCHAL_OPTION(XCHAL_ICACHE_LINE_LOCKABLE, \
0c852e17 MF	105	XTENSA_OPTION_ICACHE_INDEX_LOCK) \| \
4b37aaa8	106	XCHAL_OPTION(XCHAL_DCACHE_SIZE, XTENSA_OPTION_DCACHE) \| \
0c852e17 MF	107	XCHAL_OPTION(XCHAL_DCACHE_LINE_LOCKABLE, \
0c852e17 MF	108	XTENSA_OPTION_DCACHE_INDEX_LOCK) \| \
ac8b7db4 MF	109	XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_HW, XTENSA_OPTION_HW_ALIGNMENT) \| \
	110	/* Memory protection and translation */ \
	111	XCHAL_OPTION(XCHAL_HAVE_MIMIC_CACHEATTR, \
	112	XTENSA_OPTION_REGION_PROTECTION) \| \
	113	XCHAL_OPTION(XCHAL_HAVE_XLT_CACHEATTR, \
	114	XTENSA_OPTION_REGION_TRANSLATION) \| \
	115	XCHAL_OPTION(XCHAL_HAVE_PTP_MMU, XTENSA_OPTION_MMU) \| \
4e41d2f5	116	XCHAL_OPTION(XCHAL_HAVE_CACHEATTR, XTENSA_OPTION_CACHEATTR) \| \
ac8b7db4 MF	117	/* Other, TODO */ \
ac8b7db4 MF	118	XCHAL_OPTION(XCHAL_HAVE_WINDOWED, XTENSA_OPTION_WINDOWED_REGISTER) \| \
fe0bd475	119	XCHAL_OPTION(XCHAL_HAVE_DEBUG, XTENSA_OPTION_DEBUG) \|\
b7909d81	120	XCHAL_OPTION(XCHAL_NUM_MISC_REGS > 0, XTENSA_OPTION_MISC_SR) \| \
fe0bd475	121	XCHAL_OPTION(XCHAL_HAVE_THREADPTR, XTENSA_OPTION_THREAD_POINTER) \| \
3a3c9dc4 MF	122	XCHAL_OPTION(XCHAL_HAVE_PRID, XTENSA_OPTION_PROCESSOR_ID) \| \
3a3c9dc4 MF	123	XCHAL_OPTION(XCHAL_HAVE_EXTERN_REGS, XTENSA_OPTION_EXTERN_REGS))
ac8b7db4 MF	124
	125	#ifndef XCHAL_WINDOW_OF4_VECOFS
	126	#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
	127	#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
	128	#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
	129	#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
	130	#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
	131	#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
	132	#endif
	133
ab582413 MF	134	#if XCHAL_HAVE_WINDOWED
	135	#define WINDOW_VECTORS \
	136	[EXC_WINDOW_OVERFLOW4] = XCHAL_WINDOW_OF4_VECOFS + \
	137	XCHAL_WINDOW_VECTORS_VADDR, \
	138	[EXC_WINDOW_UNDERFLOW4] = XCHAL_WINDOW_UF4_VECOFS + \
	139	XCHAL_WINDOW_VECTORS_VADDR, \
	140	[EXC_WINDOW_OVERFLOW8] = XCHAL_WINDOW_OF8_VECOFS + \
	141	XCHAL_WINDOW_VECTORS_VADDR, \
	142	[EXC_WINDOW_UNDERFLOW8] = XCHAL_WINDOW_UF8_VECOFS + \
	143	XCHAL_WINDOW_VECTORS_VADDR, \
	144	[EXC_WINDOW_OVERFLOW12] = XCHAL_WINDOW_OF12_VECOFS + \
	145	XCHAL_WINDOW_VECTORS_VADDR, \
	146	[EXC_WINDOW_UNDERFLOW12] = XCHAL_WINDOW_UF12_VECOFS + \
	147	XCHAL_WINDOW_VECTORS_VADDR,
	148	#else
	149	#define WINDOW_VECTORS
	150	#endif
	151
ac8b7db4	152	#define EXCEPTION_VECTORS { \
17ab14ac MF	153	[EXC_RESET0] = XCHAL_RESET_VECTOR0_VADDR, \
17ab14ac MF	154	[EXC_RESET1] = XCHAL_RESET_VECTOR1_VADDR, \
ab582413	155	WINDOW_VECTORS \
ac8b7db4 MF	156	[EXC_KERNEL] = XCHAL_KERNEL_VECTOR_VADDR, \
	157	[EXC_USER] = XCHAL_USER_VECTOR_VADDR, \
	158	[EXC_DOUBLE] = XCHAL_DOUBLEEXC_VECTOR_VADDR, \
18da9326	159	[EXC_DEBUG] = XCHAL_DEBUG_VECTOR_VADDR, \
ac8b7db4 MF	160	}
	161
	162	#define INTERRUPT_VECTORS { \
	163	0, \
	164	0, \
	165	XCHAL_INTLEVEL2_VECTOR_VADDR, \
	166	XCHAL_INTLEVEL3_VECTOR_VADDR, \
	167	XCHAL_INTLEVEL4_VECTOR_VADDR, \
	168	XCHAL_INTLEVEL5_VECTOR_VADDR, \
	169	XCHAL_INTLEVEL6_VECTOR_VADDR, \
	170	XCHAL_INTLEVEL7_VECTOR_VADDR, \
	171	}
	172
	173	#define LEVEL_MASKS { \
	174	[1] = XCHAL_INTLEVEL1_MASK, \
	175	[2] = XCHAL_INTLEVEL2_MASK, \
	176	[3] = XCHAL_INTLEVEL3_MASK, \
	177	[4] = XCHAL_INTLEVEL4_MASK, \
	178	[5] = XCHAL_INTLEVEL5_MASK, \
	179	[6] = XCHAL_INTLEVEL6_MASK, \
	180	[7] = XCHAL_INTLEVEL7_MASK, \
	181	}
	182
	183	#define INTTYPE_MASKS { \
	184	[INTTYPE_EDGE] = XCHAL_INTTYPE_MASK_EXTERN_EDGE, \
	185	[INTTYPE_NMI] = XCHAL_INTTYPE_MASK_NMI, \
	186	[INTTYPE_SOFTWARE] = XCHAL_INTTYPE_MASK_SOFTWARE, \
	187	}
	188
	189	#define XTHAL_INTTYPE_EXTERN_LEVEL INTTYPE_LEVEL
	190	#define XTHAL_INTTYPE_EXTERN_EDGE INTTYPE_EDGE
	191	#define XTHAL_INTTYPE_NMI INTTYPE_NMI
	192	#define XTHAL_INTTYPE_SOFTWARE INTTYPE_SOFTWARE
	193	#define XTHAL_INTTYPE_TIMER INTTYPE_TIMER
	194	#define XTHAL_INTTYPE_TBD1 INTTYPE_DEBUG
	195	#define XTHAL_INTTYPE_TBD2 INTTYPE_WRITE_ERR
	196	#define XTHAL_INTTYPE_WRITE_ERROR INTTYPE_WRITE_ERR
dec71d2d	197	#define XTHAL_INTTYPE_PROFILING INTTYPE_PROFILING
ac8b7db4 MF	198
	199
	200	#define INTERRUPT(i) { \
	201	.level = XCHAL_INT ## i ## _LEVEL, \
	202	.inttype = XCHAL_INT ## i ## _TYPE, \
	203	}
	204
	205	#define INTERRUPTS { \
	206	[0] = INTERRUPT(0), \
	207	[1] = INTERRUPT(1), \
	208	[2] = INTERRUPT(2), \
	209	[3] = INTERRUPT(3), \
	210	[4] = INTERRUPT(4), \
	211	[5] = INTERRUPT(5), \
	212	[6] = INTERRUPT(6), \
	213	[7] = INTERRUPT(7), \
	214	[8] = INTERRUPT(8), \
	215	[9] = INTERRUPT(9), \
	216	[10] = INTERRUPT(10), \
	217	[11] = INTERRUPT(11), \
	218	[12] = INTERRUPT(12), \
	219	[13] = INTERRUPT(13), \
	220	[14] = INTERRUPT(14), \
	221	[15] = INTERRUPT(15), \
	222	[16] = INTERRUPT(16), \
	223	[17] = INTERRUPT(17), \
	224	[18] = INTERRUPT(18), \
	225	[19] = INTERRUPT(19), \
	226	[20] = INTERRUPT(20), \
	227	[21] = INTERRUPT(21), \
	228	[22] = INTERRUPT(22), \
	229	[23] = INTERRUPT(23), \
	230	[24] = INTERRUPT(24), \
	231	[25] = INTERRUPT(25), \
	232	[26] = INTERRUPT(26), \
	233	[27] = INTERRUPT(27), \
	234	[28] = INTERRUPT(28), \
	235	[29] = INTERRUPT(29), \
	236	[30] = INTERRUPT(30), \
	237	[31] = INTERRUPT(31), \
	238	}
	239
	240	#define TIMERINTS { \
	241	[0] = XCHAL_TIMER0_INTERRUPT, \
	242	[1] = XCHAL_TIMER1_INTERRUPT, \
	243	[2] = XCHAL_TIMER2_INTERRUPT, \
	244	}
	245
	246	#define EXTINTS { \
	247	[0] = XCHAL_EXTINT0_NUM, \
	248	[1] = XCHAL_EXTINT1_NUM, \
	249	[2] = XCHAL_EXTINT2_NUM, \
	250	[3] = XCHAL_EXTINT3_NUM, \
	251	[4] = XCHAL_EXTINT4_NUM, \
	252	[5] = XCHAL_EXTINT5_NUM, \
	253	[6] = XCHAL_EXTINT6_NUM, \
	254	[7] = XCHAL_EXTINT7_NUM, \
	255	[8] = XCHAL_EXTINT8_NUM, \
	256	[9] = XCHAL_EXTINT9_NUM, \
	257	[10] = XCHAL_EXTINT10_NUM, \
	258	[11] = XCHAL_EXTINT11_NUM, \
	259	[12] = XCHAL_EXTINT12_NUM, \
	260	[13] = XCHAL_EXTINT13_NUM, \
	261	[14] = XCHAL_EXTINT14_NUM, \
262	[15] = XCHAL_EXTINT15_NUM, \
263	[16] = XCHAL_EXTINT16_NUM, \
264	[17] = XCHAL_EXTINT17_NUM, \
265	[18] = XCHAL_EXTINT18_NUM, \
266	[19] = XCHAL_EXTINT19_NUM, \
267	[20] = XCHAL_EXTINT20_NUM, \
268	[21] = XCHAL_EXTINT21_NUM, \
269	[22] = XCHAL_EXTINT22_NUM, \
270	[23] = XCHAL_EXTINT23_NUM, \
271	[24] = XCHAL_EXTINT24_NUM, \
272	[25] = XCHAL_EXTINT25_NUM, \
273	[26] = XCHAL_EXTINT26_NUM, \
274	[27] = XCHAL_EXTINT27_NUM, \
275	[28] = XCHAL_EXTINT28_NUM, \
276	[29] = XCHAL_EXTINT29_NUM, \
277	[30] = XCHAL_EXTINT30_NUM, \
278	[31] = XCHAL_EXTINT31_NUM, \
279	}
280
281	#define EXCEPTIONS_SECTION \
282	.excm_level = XCHAL_EXCM_LEVEL, \
283	.vecbase = XCHAL_VECBASE_RESET_VADDR, \
284	.exception_vector = EXCEPTION_VECTORS
285
286	#define INTERRUPTS_SECTION \
287	.ninterrupt = XCHAL_NUM_INTERRUPTS, \
288	.nlevel = XCHAL_NUM_INTLEVELS, \
289	.interrupt_vector = INTERRUPT_VECTORS, \
290	.level_mask = LEVEL_MASKS, \
291	.inttype_mask = INTTYPE_MASKS, \
292	.interrupt = INTERRUPTS, \
293	.nccompare = XCHAL_NUM_TIMERS, \
294	.timerint = TIMERINTS, \
295	.nextint = XCHAL_NUM_EXTINTERRUPTS, \
296	.extint = EXTINTS
297
b96ac3e4 MF	298	#if XCHAL_HAVE_PTP_MMU
b96ac3e4 MF	299
ac8b7db4 MF	300	#define TLB_TEMPLATE(ways, refill_way_size, way56) { \
	301	.nways = ways, \
	302	.way_size = { \
	303	(refill_way_size), (refill_way_size), \
	304	(refill_way_size), (refill_way_size), \
0fdd2e1d	305	4, (way56) ? 4 : 2, (way56) ? 8 : 2, 1, 1, 1, \
ac8b7db4 MF	306	}, \
	307	.varway56 = (way56), \
	308	.nrefillentries = (refill_way_size) * 4, \
	309	}
	310
	311	#define ITLB(varway56) \
	312	TLB_TEMPLATE(7, 1 << XCHAL_ITLB_ARF_ENTRIES_LOG2, varway56)
	313
	314	#define DTLB(varway56) \
	315	TLB_TEMPLATE(10, 1 << XCHAL_DTLB_ARF_ENTRIES_LOG2, varway56)
	316
ac8b7db4 MF	317	#define TLB_SECTION \
	318	.itlb = ITLB(XCHAL_HAVE_SPANNING_WAY), \
	319	.dtlb = DTLB(XCHAL_HAVE_SPANNING_WAY)
b96ac3e4 MF	320
	321	#elif XCHAL_HAVE_XLT_CACHEATTR \|\| XCHAL_HAVE_MIMIC_CACHEATTR
	322
	323	#define TLB_TEMPLATE { \
	324	.nways = 1, \
	325	.way_size = { \
	326	8, \
	327	} \
	328	}
	329
	330	#define TLB_SECTION \
	331	.itlb = TLB_TEMPLATE, \
	332	.dtlb = TLB_TEMPLATE
	333
ac8b7db4 MF	334	#endif
	335
	336	#if (defined(TARGET_WORDS_BIGENDIAN) != 0) == (XCHAL_HAVE_BE != 0)
	337	#define REGISTER_CORE(core) \
	338	static void __attribute__((constructor)) register_core(void) \
	339	{ \
	340	static XtensaConfigList node = { \
	341	.config = &core, \
	342	}; \
1479073b	343	xtensa_finalize_config(&core); \
ac8b7db4 MF	344	xtensa_register_core(&node); \
	345	}
	346	#else
	347	#define REGISTER_CORE(core)
	348	#endif
	349
18da9326 MF	350	#define DEBUG_SECTION \
	351	.debug_level = XCHAL_DEBUGLEVEL, \
	352	.nibreak = XCHAL_NUM_IBREAK, \
	353	.ndbreak = XCHAL_NUM_DBREAK
ac8b7db4	354
9e03ade4 MF	355	#define CACHE_SECTION \
	356	.icache_ways = XCHAL_ICACHE_WAYS, \
	357	.dcache_ways = XCHAL_DCACHE_WAYS, \
	358	.memctl_mask = \
	359	(XCHAL_ICACHE_SIZE ? MEMCTL_IUSEWAYS_MASK : 0) \| \
	360	(XCHAL_DCACHE_SIZE ? \
	361	MEMCTL_DALLOCWAYS_MASK \| MEMCTL_DUSEWAYS_MASK : 0) \| \
	362	MEMCTL_ISNP \| MEMCTL_DSNP \| \
	363	(XCHAL_HAVE_LOOPS && XCHAL_LOOP_BUFFER_SIZE ? MEMCTL_IL0EN : 0)
	364
604e1f9c MF	365	#define CONFIG_SECTION \
	366	.configid = { \
	367	XCHAL_HW_CONFIGID0, \
	368	XCHAL_HW_CONFIGID1, \
	369	}
	370
676056d4 MF	371	#define DEFAULT_SECTIONS \
	372	.options = XTENSA_OPTIONS, \
	373	.nareg = XCHAL_NUM_AREGS, \
	374	.ndepc = (XCHAL_XEA_VERSION >= 2), \
	375	EXCEPTIONS_SECTION, \
	376	INTERRUPTS_SECTION, \
	377	TLB_SECTION, \
604e1f9c	378	DEBUG_SECTION, \
9e03ade4	379	CACHE_SECTION, \
604e1f9c	380	CONFIG_SECTION
676056d4 MF	381
676056d4 MF	382
ac8b7db4 MF	383	#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 2
	384	#define XCHAL_INTLEVEL2_VECTOR_VADDR 0
	385	#endif
	386	#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 3
	387	#define XCHAL_INTLEVEL3_VECTOR_VADDR 0
	388	#endif
	389	#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 4
	390	#define XCHAL_INTLEVEL4_VECTOR_VADDR 0
	391	#endif
	392	#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 5
	393	#define XCHAL_INTLEVEL5_VECTOR_VADDR 0
	394	#endif
	395	#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 6
	396	#define XCHAL_INTLEVEL6_VECTOR_VADDR 0
	397	#endif
	398	#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 7
	399	#define XCHAL_INTLEVEL7_VECTOR_VADDR 0
	400	#endif
	401
	402
	403	#if XCHAL_NUM_INTERRUPTS <= 0
	404	#define XCHAL_INT0_LEVEL 0
	405	#define XCHAL_INT0_TYPE 0
	406	#endif
	407	#if XCHAL_NUM_INTERRUPTS <= 1
	408	#define XCHAL_INT1_LEVEL 0
	409	#define XCHAL_INT1_TYPE 0
	410	#endif
	411	#if XCHAL_NUM_INTERRUPTS <= 2
	412	#define XCHAL_INT2_LEVEL 0
	413	#define XCHAL_INT2_TYPE 0
	414	#endif
	415	#if XCHAL_NUM_INTERRUPTS <= 3
	416	#define XCHAL_INT3_LEVEL 0
	417	#define XCHAL_INT3_TYPE 0
	418	#endif
	419	#if XCHAL_NUM_INTERRUPTS <= 4
	420	#define XCHAL_INT4_LEVEL 0
	421	#define XCHAL_INT4_TYPE 0
	422	#endif
	423	#if XCHAL_NUM_INTERRUPTS <= 5
	424	#define XCHAL_INT5_LEVEL 0
	425	#define XCHAL_INT5_TYPE 0
	426	#endif
	427	#if XCHAL_NUM_INTERRUPTS <= 6
	428	#define XCHAL_INT6_LEVEL 0
	429	#define XCHAL_INT6_TYPE 0
	430	#endif
	431	#if XCHAL_NUM_INTERRUPTS <= 7
	432	#define XCHAL_INT7_LEVEL 0
	433	#define XCHAL_INT7_TYPE 0
	434	#endif
	435	#if XCHAL_NUM_INTERRUPTS <= 8
	436	#define XCHAL_INT8_LEVEL 0
	437	#define XCHAL_INT8_TYPE 0
	438	#endif
	439	#if XCHAL_NUM_INTERRUPTS <= 9
	440	#define XCHAL_INT9_LEVEL 0
	441	#define XCHAL_INT9_TYPE 0
	442	#endif
	443	#if XCHAL_NUM_INTERRUPTS <= 10
	444	#define XCHAL_INT10_LEVEL 0
	445	#define XCHAL_INT10_TYPE 0
	446	#endif
447	#if XCHAL_NUM_INTERRUPTS <= 11
448	#define XCHAL_INT11_LEVEL 0
449	#define XCHAL_INT11_TYPE 0
450	#endif
451	#if XCHAL_NUM_INTERRUPTS <= 12
452	#define XCHAL_INT12_LEVEL 0
453	#define XCHAL_INT12_TYPE 0
454	#endif
455	#if XCHAL_NUM_INTERRUPTS <= 13
456	#define XCHAL_INT13_LEVEL 0
457	#define XCHAL_INT13_TYPE 0
458	#endif
459	#if XCHAL_NUM_INTERRUPTS <= 14
460	#define XCHAL_INT14_LEVEL 0
461	#define XCHAL_INT14_TYPE 0
462	#endif
463	#if XCHAL_NUM_INTERRUPTS <= 15
464	#define XCHAL_INT15_LEVEL 0
465	#define XCHAL_INT15_TYPE 0
466	#endif
467	#if XCHAL_NUM_INTERRUPTS <= 16
468	#define XCHAL_INT16_LEVEL 0
469	#define XCHAL_INT16_TYPE 0
470	#endif
471	#if XCHAL_NUM_INTERRUPTS <= 17
472	#define XCHAL_INT17_LEVEL 0
473	#define XCHAL_INT17_TYPE 0
474	#endif
475	#if XCHAL_NUM_INTERRUPTS <= 18
476	#define XCHAL_INT18_LEVEL 0
477	#define XCHAL_INT18_TYPE 0
478	#endif
479	#if XCHAL_NUM_INTERRUPTS <= 19
480	#define XCHAL_INT19_LEVEL 0
481	#define XCHAL_INT19_TYPE 0
482	#endif
483	#if XCHAL_NUM_INTERRUPTS <= 20
484	#define XCHAL_INT20_LEVEL 0
485	#define XCHAL_INT20_TYPE 0
486	#endif
487	#if XCHAL_NUM_INTERRUPTS <= 21
488	#define XCHAL_INT21_LEVEL 0
489	#define XCHAL_INT21_TYPE 0
490	#endif
491	#if XCHAL_NUM_INTERRUPTS <= 22
492	#define XCHAL_INT22_LEVEL 0
493	#define XCHAL_INT22_TYPE 0
494	#endif
495	#if XCHAL_NUM_INTERRUPTS <= 23
496	#define XCHAL_INT23_LEVEL 0
497	#define XCHAL_INT23_TYPE 0
498	#endif
499	#if XCHAL_NUM_INTERRUPTS <= 24
500	#define XCHAL_INT24_LEVEL 0
501	#define XCHAL_INT24_TYPE 0
502	#endif
503	#if XCHAL_NUM_INTERRUPTS <= 25
504	#define XCHAL_INT25_LEVEL 0
505	#define XCHAL_INT25_TYPE 0
506	#endif
507	#if XCHAL_NUM_INTERRUPTS <= 26
508	#define XCHAL_INT26_LEVEL 0
509	#define XCHAL_INT26_TYPE 0
510	#endif
511	#if XCHAL_NUM_INTERRUPTS <= 27
512	#define XCHAL_INT27_LEVEL 0
513	#define XCHAL_INT27_TYPE 0
514	#endif
515	#if XCHAL_NUM_INTERRUPTS <= 28
516	#define XCHAL_INT28_LEVEL 0
517	#define XCHAL_INT28_TYPE 0
518	#endif
519	#if XCHAL_NUM_INTERRUPTS <= 29
520	#define XCHAL_INT29_LEVEL 0
521	#define XCHAL_INT29_TYPE 0
522	#endif
523	#if XCHAL_NUM_INTERRUPTS <= 30
524	#define XCHAL_INT30_LEVEL 0
525	#define XCHAL_INT30_TYPE 0
526	#endif
527	#if XCHAL_NUM_INTERRUPTS <= 31
528	#define XCHAL_INT31_LEVEL 0
529	#define XCHAL_INT31_TYPE 0
530	#endif
531
532
533	#if XCHAL_NUM_EXTINTERRUPTS <= 0
534	#define XCHAL_EXTINT0_NUM 0
535	#endif
536	#if XCHAL_NUM_EXTINTERRUPTS <= 1
537	#define XCHAL_EXTINT1_NUM 0
538	#endif
539	#if XCHAL_NUM_EXTINTERRUPTS <= 2
540	#define XCHAL_EXTINT2_NUM 0
541	#endif
542	#if XCHAL_NUM_EXTINTERRUPTS <= 3
543	#define XCHAL_EXTINT3_NUM 0
544	#endif
545	#if XCHAL_NUM_EXTINTERRUPTS <= 4
546	#define XCHAL_EXTINT4_NUM 0
547	#endif
548	#if XCHAL_NUM_EXTINTERRUPTS <= 5
549	#define XCHAL_EXTINT5_NUM 0
550	#endif
551	#if XCHAL_NUM_EXTINTERRUPTS <= 6
552	#define XCHAL_EXTINT6_NUM 0
553	#endif
554	#if XCHAL_NUM_EXTINTERRUPTS <= 7
555	#define XCHAL_EXTINT7_NUM 0
556	#endif
557	#if XCHAL_NUM_EXTINTERRUPTS <= 8
558	#define XCHAL_EXTINT8_NUM 0
559	#endif
560	#if XCHAL_NUM_EXTINTERRUPTS <= 9
561	#define XCHAL_EXTINT9_NUM 0
562	#endif
563	#if XCHAL_NUM_EXTINTERRUPTS <= 10
564	#define XCHAL_EXTINT10_NUM 0
565	#endif
566	#if XCHAL_NUM_EXTINTERRUPTS <= 11
567	#define XCHAL_EXTINT11_NUM 0
568	#endif
569	#if XCHAL_NUM_EXTINTERRUPTS <= 12
570	#define XCHAL_EXTINT12_NUM 0
571	#endif
572	#if XCHAL_NUM_EXTINTERRUPTS <= 13
573	#define XCHAL_EXTINT13_NUM 0
574	#endif
575	#if XCHAL_NUM_EXTINTERRUPTS <= 14
576	#define XCHAL_EXTINT14_NUM 0
577	#endif
578	#if XCHAL_NUM_EXTINTERRUPTS <= 15
579	#define XCHAL_EXTINT15_NUM 0
580	#endif
581	#if XCHAL_NUM_EXTINTERRUPTS <= 16
582	#define XCHAL_EXTINT16_NUM 0
583	#endif
584	#if XCHAL_NUM_EXTINTERRUPTS <= 17
585	#define XCHAL_EXTINT17_NUM 0
586	#endif
587	#if XCHAL_NUM_EXTINTERRUPTS <= 18
588	#define XCHAL_EXTINT18_NUM 0
589	#endif
590	#if XCHAL_NUM_EXTINTERRUPTS <= 19
591	#define XCHAL_EXTINT19_NUM 0
592	#endif
593	#if XCHAL_NUM_EXTINTERRUPTS <= 20
594	#define XCHAL_EXTINT20_NUM 0
595	#endif
596	#if XCHAL_NUM_EXTINTERRUPTS <= 21
597	#define XCHAL_EXTINT21_NUM 0
598	#endif
599	#if XCHAL_NUM_EXTINTERRUPTS <= 22
600	#define XCHAL_EXTINT22_NUM 0
601	#endif
602	#if XCHAL_NUM_EXTINTERRUPTS <= 23
603	#define XCHAL_EXTINT23_NUM 0
604	#endif
605	#if XCHAL_NUM_EXTINTERRUPTS <= 24
606	#define XCHAL_EXTINT24_NUM 0
607	#endif
608	#if XCHAL_NUM_EXTINTERRUPTS <= 25
609	#define XCHAL_EXTINT25_NUM 0
610	#endif
611	#if XCHAL_NUM_EXTINTERRUPTS <= 26
612	#define XCHAL_EXTINT26_NUM 0
613	#endif
614	#if XCHAL_NUM_EXTINTERRUPTS <= 27
615	#define XCHAL_EXTINT27_NUM 0
616	#endif
617	#if XCHAL_NUM_EXTINTERRUPTS <= 28
618	#define XCHAL_EXTINT28_NUM 0
619	#endif
620	#if XCHAL_NUM_EXTINTERRUPTS <= 29
621	#define XCHAL_EXTINT29_NUM 0
622	#endif
623	#if XCHAL_NUM_EXTINTERRUPTS <= 30
624	#define XCHAL_EXTINT30_NUM 0
625	#endif
626	#if XCHAL_NUM_EXTINTERRUPTS <= 31
627	#define XCHAL_EXTINT31_NUM 0
628	#endif
629
630
631	#define XTHAL_TIMER_UNCONFIGURED 0