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target/xtensa: fix ICACHE/DCACHE options detection
[mirror_qemu.git] / target / xtensa / translate.c
CommitLineData
2328826b
MF		 1/*
2 * Xtensa ISA:
3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
4 *
5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
09aae23d 31#include "qemu/osdep.h"
2328826b
MF		 32
33#include "cpu.h"
022c62cb 34#include "exec/exec-all.h"
76cad711 35#include "disas/disas.h"
2328826b 36#include "tcg-op.h"
1de7afc9 37#include "qemu/log.h"
9c17d615 38#include "sysemu/sysemu.h"
f08b6170 39#include "exec/cpu_ldst.h"
cfe67cef 40#include "exec/semihost.h"
2328826b 41
2ef6175a
RH		 42#include "exec/helper-proto.h"
43#include "exec/helper-gen.h"
dedc5eae 44
a7e30d84 45#include "trace-tcg.h"
508127e2 46#include "exec/log.h"
a7e30d84
LV		 47
48
dedc5eae
MF		 49typedef struct DisasContext {
50 const XtensaConfig *config;
51 TranslationBlock *tb;
52 uint32_t pc;
53 uint32_t next_pc;
f0a548b9
MF		 54 int cring;
55 int ring;
797d780b
MF		 56 uint32_t lbeg;
57 uint32_t lend;
6ad6dbf7 58 TCGv_i32 litbase;
dedc5eae
MF		 59 int is_jmp;
60 int singlestep_enabled;
3580ecad
MF		 61
62 bool sar_5bit;
63 bool sar_m32_5bit;
64 bool sar_m32_allocated;
65 TCGv_i32 sar_m32;
b994e91b 66
2db59a76 67 unsigned window;
e61dc8f7
MF		 68
69 bool debug;
35b5c044
MF		 70 bool icount;
71 TCGv_i32 next_icount;
ef04a846
MF		 72
73 unsigned cpenable;
dedc5eae
MF		 74} DisasContext;
75
1bcea73e 76static TCGv_env cpu_env;
dedc5eae
MF		 77static TCGv_i32 cpu_pc;
78static TCGv_i32 cpu_R[16];
dd519cbe 79static TCGv_i32 cpu_FR[16];
2af3da91
MF		 80static TCGv_i32 cpu_SR[256];
81static TCGv_i32 cpu_UR[256];
dedc5eae 82
022c62cb 83#include "exec/gen-icount.h"
2328826b 84
fe0bd475
MF		 85typedef struct XtensaReg {
86 const char *name;
87 uint64_t opt_bits;
53593e90
MF		 88 enum {
89 SR_R = 1,
90 SR_W = 2,
91 SR_X = 4,
92 SR_RW = 3,
93 SR_RWX = 7,
94 } access;
fe0bd475
MF		 95} XtensaReg;
96
53593e90 97#define XTENSA_REG_ACCESS(regname, opt, acc) { \
fe0bd475
MF		 98 .name = (regname), \
99 .opt_bits = XTENSA_OPTION_BIT(opt), \
53593e90 100 .access = (acc), \
fe0bd475
MF		 101 }
102
53593e90
MF		 103#define XTENSA_REG(regname, opt) XTENSA_REG_ACCESS(regname, opt, SR_RWX)
104
604e1f9c 105#define XTENSA_REG_BITS_ACCESS(regname, opt, acc) { \
fe0bd475
MF		 106 .name = (regname), \
107 .opt_bits = (opt), \
604e1f9c 108 .access = (acc), \
fe0bd475
MF		 109 }
110
604e1f9c
MF		 111#define XTENSA_REG_BITS(regname, opt) \
112 XTENSA_REG_BITS_ACCESS(regname, opt, SR_RWX)
113
fe0bd475
MF		 114static const XtensaReg sregnames[256] = {
115 [LBEG] = XTENSA_REG("LBEG", XTENSA_OPTION_LOOP),
116 [LEND] = XTENSA_REG("LEND", XTENSA_OPTION_LOOP),
117 [LCOUNT] = XTENSA_REG("LCOUNT", XTENSA_OPTION_LOOP),
118 [SAR] = XTENSA_REG_BITS("SAR", XTENSA_OPTION_ALL),
119 [BR] = XTENSA_REG("BR", XTENSA_OPTION_BOOLEAN),
120 [LITBASE] = XTENSA_REG("LITBASE", XTENSA_OPTION_EXTENDED_L32R),
121 [SCOMPARE1] = XTENSA_REG("SCOMPARE1", XTENSA_OPTION_CONDITIONAL_STORE),
122 [ACCLO] = XTENSA_REG("ACCLO", XTENSA_OPTION_MAC16),
123 [ACCHI] = XTENSA_REG("ACCHI", XTENSA_OPTION_MAC16),
124 [MR] = XTENSA_REG("MR0", XTENSA_OPTION_MAC16),
125 [MR + 1] = XTENSA_REG("MR1", XTENSA_OPTION_MAC16),
126 [MR + 2] = XTENSA_REG("MR2", XTENSA_OPTION_MAC16),
127 [MR + 3] = XTENSA_REG("MR3", XTENSA_OPTION_MAC16),
128 [WINDOW_BASE] = XTENSA_REG("WINDOW_BASE", XTENSA_OPTION_WINDOWED_REGISTER),
129 [WINDOW_START] = XTENSA_REG("WINDOW_START",
130 XTENSA_OPTION_WINDOWED_REGISTER),
131 [PTEVADDR] = XTENSA_REG("PTEVADDR", XTENSA_OPTION_MMU),
132 [RASID] = XTENSA_REG("RASID", XTENSA_OPTION_MMU),
133 [ITLBCFG] = XTENSA_REG("ITLBCFG", XTENSA_OPTION_MMU),
134 [DTLBCFG] = XTENSA_REG("DTLBCFG", XTENSA_OPTION_MMU),
135 [IBREAKENABLE] = XTENSA_REG("IBREAKENABLE", XTENSA_OPTION_DEBUG),
136 [CACHEATTR] = XTENSA_REG("CACHEATTR", XTENSA_OPTION_CACHEATTR),
137 [ATOMCTL] = XTENSA_REG("ATOMCTL", XTENSA_OPTION_ATOMCTL),
138 [IBREAKA] = XTENSA_REG("IBREAKA0", XTENSA_OPTION_DEBUG),
139 [IBREAKA + 1] = XTENSA_REG("IBREAKA1", XTENSA_OPTION_DEBUG),
140 [DBREAKA] = XTENSA_REG("DBREAKA0", XTENSA_OPTION_DEBUG),
141 [DBREAKA + 1] = XTENSA_REG("DBREAKA1", XTENSA_OPTION_DEBUG),
142 [DBREAKC] = XTENSA_REG("DBREAKC0", XTENSA_OPTION_DEBUG),
143 [DBREAKC + 1] = XTENSA_REG("DBREAKC1", XTENSA_OPTION_DEBUG),
604e1f9c 144 [CONFIGID0] = XTENSA_REG_BITS_ACCESS("CONFIGID0", XTENSA_OPTION_ALL, SR_R),
fe0bd475
MF		 145 [EPC1] = XTENSA_REG("EPC1", XTENSA_OPTION_EXCEPTION),
146 [EPC1 + 1] = XTENSA_REG("EPC2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
147 [EPC1 + 2] = XTENSA_REG("EPC3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
148 [EPC1 + 3] = XTENSA_REG("EPC4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
149 [EPC1 + 4] = XTENSA_REG("EPC5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
150 [EPC1 + 5] = XTENSA_REG("EPC6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
151 [EPC1 + 6] = XTENSA_REG("EPC7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
152 [DEPC] = XTENSA_REG("DEPC", XTENSA_OPTION_EXCEPTION),
153 [EPS2] = XTENSA_REG("EPS2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
154 [EPS2 + 1] = XTENSA_REG("EPS3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
155 [EPS2 + 2] = XTENSA_REG("EPS4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
156 [EPS2 + 3] = XTENSA_REG("EPS5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
157 [EPS2 + 4] = XTENSA_REG("EPS6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
158 [EPS2 + 5] = XTENSA_REG("EPS7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
604e1f9c 159 [CONFIGID1] = XTENSA_REG_BITS_ACCESS("CONFIGID1", XTENSA_OPTION_ALL, SR_R),
fe0bd475
MF		 160 [EXCSAVE1] = XTENSA_REG("EXCSAVE1", XTENSA_OPTION_EXCEPTION),
161 [EXCSAVE1 + 1] = XTENSA_REG("EXCSAVE2",
162 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
163 [EXCSAVE1 + 2] = XTENSA_REG("EXCSAVE3",
164 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
165 [EXCSAVE1 + 3] = XTENSA_REG("EXCSAVE4",
166 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
167 [EXCSAVE1 + 4] = XTENSA_REG("EXCSAVE5",
168 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
169 [EXCSAVE1 + 5] = XTENSA_REG("EXCSAVE6",
170 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
171 [EXCSAVE1 + 6] = XTENSA_REG("EXCSAVE7",
172 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
173 [CPENABLE] = XTENSA_REG("CPENABLE", XTENSA_OPTION_COPROCESSOR),
53593e90
MF		 174 [INTSET] = XTENSA_REG_ACCESS("INTSET", XTENSA_OPTION_INTERRUPT, SR_RW),
175 [INTCLEAR] = XTENSA_REG_ACCESS("INTCLEAR", XTENSA_OPTION_INTERRUPT, SR_W),
fe0bd475
MF		 176 [INTENABLE] = XTENSA_REG("INTENABLE", XTENSA_OPTION_INTERRUPT),
177 [PS] = XTENSA_REG_BITS("PS", XTENSA_OPTION_ALL),
178 [VECBASE] = XTENSA_REG("VECBASE", XTENSA_OPTION_RELOCATABLE_VECTOR),
179 [EXCCAUSE] = XTENSA_REG("EXCCAUSE", XTENSA_OPTION_EXCEPTION),
53593e90 180 [DEBUGCAUSE] = XTENSA_REG_ACCESS("DEBUGCAUSE", XTENSA_OPTION_DEBUG, SR_R),
fe0bd475 181 [CCOUNT] = XTENSA_REG("CCOUNT", XTENSA_OPTION_TIMER_INTERRUPT),
53593e90 182 [PRID] = XTENSA_REG_ACCESS("PRID", XTENSA_OPTION_PROCESSOR_ID, SR_R),
fe0bd475
MF		 183 [ICOUNT] = XTENSA_REG("ICOUNT", XTENSA_OPTION_DEBUG),
184 [ICOUNTLEVEL] = XTENSA_REG("ICOUNTLEVEL", XTENSA_OPTION_DEBUG),
185 [EXCVADDR] = XTENSA_REG("EXCVADDR", XTENSA_OPTION_EXCEPTION),
186 [CCOMPARE] = XTENSA_REG("CCOMPARE0", XTENSA_OPTION_TIMER_INTERRUPT),
187 [CCOMPARE + 1] = XTENSA_REG("CCOMPARE1",
188 XTENSA_OPTION_TIMER_INTERRUPT),
189 [CCOMPARE + 2] = XTENSA_REG("CCOMPARE2",
190 XTENSA_OPTION_TIMER_INTERRUPT),
b7909d81
MF		 191 [MISC] = XTENSA_REG("MISC0", XTENSA_OPTION_MISC_SR),
192 [MISC + 1] = XTENSA_REG("MISC1", XTENSA_OPTION_MISC_SR),
193 [MISC + 2] = XTENSA_REG("MISC2", XTENSA_OPTION_MISC_SR),
194 [MISC + 3] = XTENSA_REG("MISC3", XTENSA_OPTION_MISC_SR),
2af3da91
MF		 195};
196
fe0bd475
MF		 197static const XtensaReg uregnames[256] = {
198 [THREADPTR] = XTENSA_REG("THREADPTR", XTENSA_OPTION_THREAD_POINTER),
199 [FCR] = XTENSA_REG("FCR", XTENSA_OPTION_FP_COPROCESSOR),
200 [FSR] = XTENSA_REG("FSR", XTENSA_OPTION_FP_COPROCESSOR),
2af3da91
MF		 201};
202
2328826b
MF		 203void xtensa_translate_init(void)
204{
dedc5eae
MF		 205 static const char * const regnames[] = {
206 "ar0", "ar1", "ar2", "ar3",
207 "ar4", "ar5", "ar6", "ar7",
208 "ar8", "ar9", "ar10", "ar11",
209 "ar12", "ar13", "ar14", "ar15",
210 };
dd519cbe
MF		 211 static const char * const fregnames[] = {
212 "f0", "f1", "f2", "f3",
213 "f4", "f5", "f6", "f7",
214 "f8", "f9", "f10", "f11",
215 "f12", "f13", "f14", "f15",
216 };
dedc5eae
MF		 217 int i;
218
219 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
7c255043 220 tcg_ctx.tcg_env = cpu_env;
e1ccc054 221 cpu_pc = tcg_global_mem_new_i32(cpu_env,
97129ac8 222 offsetof(CPUXtensaState, pc), "pc");
dedc5eae
MF		 223
224 for (i = 0; i < 16; i++) {
e1ccc054 225 cpu_R[i] = tcg_global_mem_new_i32(cpu_env,
97129ac8 226 offsetof(CPUXtensaState, regs[i]),
dedc5eae
MF		 227 regnames[i]);
228 }
2af3da91 229
dd519cbe 230 for (i = 0; i < 16; i++) {
e1ccc054 231 cpu_FR[i] = tcg_global_mem_new_i32(cpu_env,
ddd44279 232 offsetof(CPUXtensaState, fregs[i].f32[FP_F32_LOW]),
dd519cbe
MF		 233 fregnames[i]);
234 }
235
2af3da91 236 for (i = 0; i < 256; ++i) {
fe0bd475 237 if (sregnames[i].name) {
e1ccc054 238 cpu_SR[i] = tcg_global_mem_new_i32(cpu_env,
97129ac8 239 offsetof(CPUXtensaState, sregs[i]),
fe0bd475 240 sregnames[i].name);
2af3da91
MF		 241 }
242 }
243
244 for (i = 0; i < 256; ++i) {
fe0bd475 245 if (uregnames[i].name) {
e1ccc054 246 cpu_UR[i] = tcg_global_mem_new_i32(cpu_env,
97129ac8 247 offsetof(CPUXtensaState, uregs[i]),
fe0bd475 248 uregnames[i].name);
2af3da91
MF		 249 }
250 }
dedc5eae
MF		 251}
252
b67ea0cd
MF		 253static inline bool option_bits_enabled(DisasContext *dc, uint64_t opt)
254{
255 return xtensa_option_bits_enabled(dc->config, opt);
256}
257
dedc5eae
MF		 258static inline bool option_enabled(DisasContext *dc, int opt)
259{
260 return xtensa_option_enabled(dc->config, opt);
261}
262
6ad6dbf7
MF		 263static void init_litbase(DisasContext *dc)
264{
265 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
266 dc->litbase = tcg_temp_local_new_i32();
267 tcg_gen_andi_i32(dc->litbase, cpu_SR[LITBASE], 0xfffff000);
268 }
269}
270
271static void reset_litbase(DisasContext *dc)
272{
273 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
274 tcg_temp_free(dc->litbase);
275 }
276}
277
3580ecad
MF		 278static void init_sar_tracker(DisasContext *dc)
279{
280 dc->sar_5bit = false;
281 dc->sar_m32_5bit = false;
282 dc->sar_m32_allocated = false;
283}
284
285static void reset_sar_tracker(DisasContext *dc)
286{
287 if (dc->sar_m32_allocated) {
288 tcg_temp_free(dc->sar_m32);
289 }
290}
291
292static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa)
293{
294 tcg_gen_andi_i32(cpu_SR[SAR], sa, 0x1f);
295 if (dc->sar_m32_5bit) {
296 tcg_gen_discard_i32(dc->sar_m32);
297 }
298 dc->sar_5bit = true;
299 dc->sar_m32_5bit = false;
300}
301
302static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa)
303{
304 TCGv_i32 tmp = tcg_const_i32(32);
305 if (!dc->sar_m32_allocated) {
306 dc->sar_m32 = tcg_temp_local_new_i32();
307 dc->sar_m32_allocated = true;
308 }
309 tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f);
310 tcg_gen_sub_i32(cpu_SR[SAR], tmp, dc->sar_m32);
311 dc->sar_5bit = false;
312 dc->sar_m32_5bit = true;
313 tcg_temp_free(tmp);
314}
315
b994e91b 316static void gen_exception(DisasContext *dc, int excp)
dedc5eae
MF		 317{
318 TCGv_i32 tmp = tcg_const_i32(excp);
f492b82d 319 gen_helper_exception(cpu_env, tmp);
dedc5eae
MF		 320 tcg_temp_free(tmp);
321}
322
40643d7c
MF		 323static void gen_exception_cause(DisasContext *dc, uint32_t cause)
324{
325 TCGv_i32 tpc = tcg_const_i32(dc->pc);
326 TCGv_i32 tcause = tcg_const_i32(cause);
f492b82d 327 gen_helper_exception_cause(cpu_env, tpc, tcause);
40643d7c
MF		 328 tcg_temp_free(tpc);
329 tcg_temp_free(tcause);
6b814719
MF		 330 if (cause == ILLEGAL_INSTRUCTION_CAUSE ||
331 cause == SYSCALL_CAUSE) {
332 dc->is_jmp = DISAS_UPDATE;
333 }
40643d7c
MF		 334}
335
5b4e481b
MF		 336static void gen_exception_cause_vaddr(DisasContext *dc, uint32_t cause,
337 TCGv_i32 vaddr)
338{
339 TCGv_i32 tpc = tcg_const_i32(dc->pc);
340 TCGv_i32 tcause = tcg_const_i32(cause);
f492b82d 341 gen_helper_exception_cause_vaddr(cpu_env, tpc, tcause, vaddr);
5b4e481b
MF		 342 tcg_temp_free(tpc);
343 tcg_temp_free(tcause);
344}
345
e61dc8f7
MF		 346static void gen_debug_exception(DisasContext *dc, uint32_t cause)
347{
348 TCGv_i32 tpc = tcg_const_i32(dc->pc);
349 TCGv_i32 tcause = tcg_const_i32(cause);
f492b82d 350 gen_helper_debug_exception(cpu_env, tpc, tcause);
e61dc8f7
MF		 351 tcg_temp_free(tpc);
352 tcg_temp_free(tcause);
353 if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) {
354 dc->is_jmp = DISAS_UPDATE;
355 }
356}
357
97e89ee9 358static bool gen_check_privilege(DisasContext *dc)
40643d7c
MF		 359{
360 if (dc->cring) {
361 gen_exception_cause(dc, PRIVILEGED_CAUSE);
6b814719 362 dc->is_jmp = DISAS_UPDATE;
97e89ee9 363 return false;
40643d7c 364 }
97e89ee9 365 return true;
40643d7c
MF		 366}
367
97e89ee9 368static bool gen_check_cpenable(DisasContext *dc, unsigned cp)
ef04a846
MF		 369{
370 if (option_enabled(dc, XTENSA_OPTION_COPROCESSOR) &&
371 !(dc->cpenable & (1 << cp))) {
372 gen_exception_cause(dc, COPROCESSOR0_DISABLED + cp);
373 dc->is_jmp = DISAS_UPDATE;
97e89ee9 374 return false;
ef04a846 375 }
97e89ee9 376 return true;
ef04a846
MF		 377}
378
dedc5eae
MF		 379static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
380{
381 tcg_gen_mov_i32(cpu_pc, dest);
35b5c044
MF		 382 if (dc->icount) {
383 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount);
384 }
dedc5eae 385 if (dc->singlestep_enabled) {
b994e91b 386 gen_exception(dc, EXCP_DEBUG);
dedc5eae
MF		 387 } else {
388 if (slot >= 0) {
389 tcg_gen_goto_tb(slot);
8cfd0495 390 tcg_gen_exit_tb((uintptr_t)dc->tb + slot);
dedc5eae
MF		 391 } else {
392 tcg_gen_exit_tb(0);
393 }
394 }
395 dc->is_jmp = DISAS_UPDATE;
396}
397
67882fd1
MF		 398static void gen_jump(DisasContext *dc, TCGv dest)
399{
400 gen_jump_slot(dc, dest, -1);
401}
402
dedc5eae
MF		 403static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)
404{
405 TCGv_i32 tmp = tcg_const_i32(dest);
90aa39a1 406#ifndef CONFIG_USER_ONLY
433d33c5 407 if (((dc->tb->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
dedc5eae
MF		 408 slot = -1;
409 }
90aa39a1 410#endif
dedc5eae
MF		 411 gen_jump_slot(dc, tmp, slot);
412 tcg_temp_free(tmp);
413}
414
553e44f9
MF		 415static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest,
416 int slot)
417{
418 TCGv_i32 tcallinc = tcg_const_i32(callinc);
419
420 tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS],
421 tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN);
422 tcg_temp_free(tcallinc);
423 tcg_gen_movi_i32(cpu_R[callinc << 2],
424 (callinc << 30) | (dc->next_pc & 0x3fffffff));
425 gen_jump_slot(dc, dest, slot);
426}
427
428static void gen_callw(DisasContext *dc, int callinc, TCGv_i32 dest)
429{
430 gen_callw_slot(dc, callinc, dest, -1);
431}
432
433static void gen_callwi(DisasContext *dc, int callinc, uint32_t dest, int slot)
434{
435 TCGv_i32 tmp = tcg_const_i32(dest);
90aa39a1 436#ifndef CONFIG_USER_ONLY
433d33c5 437 if (((dc->tb->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
553e44f9
MF		 438 slot = -1;
439 }
90aa39a1 440#endif
553e44f9
MF		 441 gen_callw_slot(dc, callinc, tmp, slot);
442 tcg_temp_free(tmp);
443}
444
797d780b
MF		 445static bool gen_check_loop_end(DisasContext *dc, int slot)
446{
447 if (option_enabled(dc, XTENSA_OPTION_LOOP) &&
448 !(dc->tb->flags & XTENSA_TBFLAG_EXCM) &&
449 dc->next_pc == dc->lend) {
42a268c2 450 TCGLabel *label = gen_new_label();
797d780b
MF		 451
452 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label);
453 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1);
454 gen_jumpi(dc, dc->lbeg, slot);
455 gen_set_label(label);
456 gen_jumpi(dc, dc->next_pc, -1);
457 return true;
458 }
459 return false;
460}
461
462static void gen_jumpi_check_loop_end(DisasContext *dc, int slot)
463{
464 if (!gen_check_loop_end(dc, slot)) {
465 gen_jumpi(dc, dc->next_pc, slot);
466 }
467}
468
bd57fb91
MF		 469static void gen_brcond(DisasContext *dc, TCGCond cond,
470 TCGv_i32 t0, TCGv_i32 t1, uint32_t offset)
471{
42a268c2 472 TCGLabel *label = gen_new_label();
bd57fb91
MF		 473
474 tcg_gen_brcond_i32(cond, t0, t1, label);
797d780b 475 gen_jumpi_check_loop_end(dc, 0);
bd57fb91
MF		 476 gen_set_label(label);
477 gen_jumpi(dc, dc->pc + offset, 1);
478}
479
480static void gen_brcondi(DisasContext *dc, TCGCond cond,
481 TCGv_i32 t0, uint32_t t1, uint32_t offset)
482{
483 TCGv_i32 tmp = tcg_const_i32(t1);
484 gen_brcond(dc, cond, t0, tmp, offset);
485 tcg_temp_free(tmp);
486}
487
0857a06e 488static bool gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access)
fe0bd475
MF		 489{
490 if (!xtensa_option_bits_enabled(dc->config, sregnames[sr].opt_bits)) {
491 if (sregnames[sr].name) {
c30f0d18 492 qemu_log_mask(LOG_GUEST_ERROR, "SR %s is not configured\n", sregnames[sr].name);
fe0bd475 493 } else {
c30f0d18 494 qemu_log_mask(LOG_UNIMP, "SR %d is not implemented\n", sr);
fe0bd475
MF		 495 }
496 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
0857a06e 497 return false;
53593e90
MF		 498 } else if (!(sregnames[sr].access & access)) {
499 static const char * const access_text[] = {
500 [SR_R] = "rsr",
501 [SR_W] = "wsr",
502 [SR_X] = "xsr",
503 };
504 assert(access < ARRAY_SIZE(access_text) && access_text[access]);
c30f0d18
PB		 505 qemu_log_mask(LOG_GUEST_ERROR, "SR %s is not available for %s\n", sregnames[sr].name,
506 access_text[access]);
53593e90 507 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
0857a06e 508 return false;
fe0bd475 509 }
0857a06e 510 return true;
fe0bd475
MF		 511}
512
d2132510 513static bool gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr)
b994e91b 514{
d2132510
MF		 515 if (dc->tb->cflags & CF_USE_ICOUNT) {
516 gen_io_start();
517 }
59a71f75 518 gen_helper_update_ccount(cpu_env);
b994e91b 519 tcg_gen_mov_i32(d, cpu_SR[sr]);
d2132510
MF		 520 if (dc->tb->cflags & CF_USE_ICOUNT) {
521 gen_io_end();
522 return true;
523 }
524 return false;
b994e91b
MF		 525}
526
d2132510 527static bool gen_rsr_ptevaddr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
b67ea0cd
MF		 528{
529 tcg_gen_shri_i32(d, cpu_SR[EXCVADDR], 10);
530 tcg_gen_or_i32(d, d, cpu_SR[sr]);
531 tcg_gen_andi_i32(d, d, 0xfffffffc);
d2132510 532 return false;
b67ea0cd
MF		 533}
534
d2132510 535static bool gen_rsr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
b8132eff 536{
d2132510 537 static bool (* const rsr_handler[256])(DisasContext *dc,
b8132eff 538 TCGv_i32 d, uint32_t sr) = {
b994e91b 539 [CCOUNT] = gen_rsr_ccount,
59a71f75 540 [INTSET] = gen_rsr_ccount,
b67ea0cd 541 [PTEVADDR] = gen_rsr_ptevaddr,
b8132eff
MF		 542 };
543
fe0bd475 544 if (rsr_handler[sr]) {
d2132510 545 return rsr_handler[sr](dc, d, sr);
b8132eff 546 } else {
fe0bd475 547 tcg_gen_mov_i32(d, cpu_SR[sr]);
d2132510 548 return false;
b8132eff
MF		 549 }
550}
551
d2132510 552static bool gen_wsr_lbeg(DisasContext *dc, uint32_t sr, TCGv_i32 s)
797d780b 553{
f492b82d 554 gen_helper_wsr_lbeg(cpu_env, s);
3d0be8a5 555 gen_jumpi_check_loop_end(dc, 0);
d2132510 556 return false;
797d780b
MF		 557}
558
d2132510 559static bool gen_wsr_lend(DisasContext *dc, uint32_t sr, TCGv_i32 s)
797d780b 560{
f492b82d 561 gen_helper_wsr_lend(cpu_env, s);
3d0be8a5 562 gen_jumpi_check_loop_end(dc, 0);
d2132510 563 return false;
797d780b
MF		 564}
565
d2132510 566static bool gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s)
3580ecad
MF		 567{
568 tcg_gen_andi_i32(cpu_SR[sr], s, 0x3f);
569 if (dc->sar_m32_5bit) {
570 tcg_gen_discard_i32(dc->sar_m32);
571 }
572 dc->sar_5bit = false;
573 dc->sar_m32_5bit = false;
d2132510 574 return false;
3580ecad
MF		 575}
576
d2132510 577static bool gen_wsr_br(DisasContext *dc, uint32_t sr, TCGv_i32 s)
4dd85b6b
MF		 578{
579 tcg_gen_andi_i32(cpu_SR[sr], s, 0xffff);
d2132510 580 return false;
4dd85b6b
MF		 581}
582
d2132510 583static bool gen_wsr_litbase(DisasContext *dc, uint32_t sr, TCGv_i32 s)
6ad6dbf7
MF		 584{
585 tcg_gen_andi_i32(cpu_SR[sr], s, 0xfffff001);
586 /* This can change tb->flags, so exit tb */
587 gen_jumpi_check_loop_end(dc, -1);
d2132510 588 return true;
6ad6dbf7
MF		 589}
590
d2132510 591static bool gen_wsr_acchi(DisasContext *dc, uint32_t sr, TCGv_i32 s)
6825b6c3
MF		 592{
593 tcg_gen_ext8s_i32(cpu_SR[sr], s);
d2132510 594 return false;
6825b6c3
MF		 595}
596
d2132510 597static bool gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v)
553e44f9 598{
f492b82d 599 gen_helper_wsr_windowbase(cpu_env, v);
2db59a76
MF		 600 /* This can change tb->flags, so exit tb */
601 gen_jumpi_check_loop_end(dc, -1);
d2132510 602 return true;
772177c1
MF		 603}
604
d2132510 605static bool gen_wsr_windowstart(DisasContext *dc, uint32_t sr, TCGv_i32 v)
772177c1 606{
53a72dfd 607 tcg_gen_andi_i32(cpu_SR[sr], v, (1 << dc->config->nareg / 4) - 1);
2db59a76
MF		 608 /* This can change tb->flags, so exit tb */
609 gen_jumpi_check_loop_end(dc, -1);
d2132510 610 return true;
553e44f9
MF		 611}
612
d2132510 613static bool gen_wsr_ptevaddr(DisasContext *dc, uint32_t sr, TCGv_i32 v)
b67ea0cd
MF		 614{
615 tcg_gen_andi_i32(cpu_SR[sr], v, 0xffc00000);
d2132510 616 return false;
b67ea0cd
MF		 617}
618
d2132510 619static bool gen_wsr_rasid(DisasContext *dc, uint32_t sr, TCGv_i32 v)
b67ea0cd 620{
f492b82d 621 gen_helper_wsr_rasid(cpu_env, v);
b67ea0cd
MF		 622 /* This can change tb->flags, so exit tb */
623 gen_jumpi_check_loop_end(dc, -1);
d2132510 624 return true;
b67ea0cd
MF		 625}
626
d2132510 627static bool gen_wsr_tlbcfg(DisasContext *dc, uint32_t sr, TCGv_i32 v)
b67ea0cd
MF		 628{
629 tcg_gen_andi_i32(cpu_SR[sr], v, 0x01130000);
d2132510 630 return false;
b67ea0cd
MF		 631}
632
d2132510 633static bool gen_wsr_ibreakenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
e61dc8f7 634{
f492b82d 635 gen_helper_wsr_ibreakenable(cpu_env, v);
e61dc8f7 636 gen_jumpi_check_loop_end(dc, 0);
d2132510 637 return true;
e61dc8f7
MF		 638}
639
d2132510 640static bool gen_wsr_atomctl(DisasContext *dc, uint32_t sr, TCGv_i32 v)
fcc803d1
MF		 641{
642 tcg_gen_andi_i32(cpu_SR[sr], v, 0x3f);
d2132510 643 return false;
fcc803d1
MF		 644}
645
d2132510 646static bool gen_wsr_ibreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
e61dc8f7
MF		 647{
648 unsigned id = sr - IBREAKA;
649
650 if (id < dc->config->nibreak) {
651 TCGv_i32 tmp = tcg_const_i32(id);
f492b82d 652 gen_helper_wsr_ibreaka(cpu_env, tmp, v);
e61dc8f7
MF		 653 tcg_temp_free(tmp);
654 gen_jumpi_check_loop_end(dc, 0);
d2132510 655 return true;
e61dc8f7 656 }
d2132510 657 return false;
e61dc8f7
MF		 658}
659
d2132510 660static bool gen_wsr_dbreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
f14c4b5f
MF		 661{
662 unsigned id = sr - DBREAKA;
663
664 if (id < dc->config->ndbreak) {
665 TCGv_i32 tmp = tcg_const_i32(id);
f492b82d 666 gen_helper_wsr_dbreaka(cpu_env, tmp, v);
f14c4b5f
MF		 667 tcg_temp_free(tmp);
668 }
d2132510 669 return false;
f14c4b5f
MF		 670}
671
d2132510 672static bool gen_wsr_dbreakc(DisasContext *dc, uint32_t sr, TCGv_i32 v)
f14c4b5f
MF		 673{
674 unsigned id = sr - DBREAKC;
675
676 if (id < dc->config->ndbreak) {
677 TCGv_i32 tmp = tcg_const_i32(id);
f492b82d 678 gen_helper_wsr_dbreakc(cpu_env, tmp, v);
f14c4b5f
MF		 679 tcg_temp_free(tmp);
680 }
d2132510 681 return false;
f14c4b5f
MF		 682}
683
d2132510 684static bool gen_wsr_cpenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
ef04a846
MF		 685{
686 tcg_gen_andi_i32(cpu_SR[sr], v, 0xff);
687 /* This can change tb->flags, so exit tb */
688 gen_jumpi_check_loop_end(dc, -1);
d2132510 689 return true;
ef04a846
MF		 690}
691
d2132510
MF		 692static void gen_check_interrupts(DisasContext *dc)
693{
694 if (dc->tb->cflags & CF_USE_ICOUNT) {
695 gen_io_start();
696 }
697 gen_helper_check_interrupts(cpu_env);
698 if (dc->tb->cflags & CF_USE_ICOUNT) {
699 gen_io_end();
700 }
701}
702
703static bool gen_wsr_intset(DisasContext *dc, uint32_t sr, TCGv_i32 v)
b994e91b
MF		 704{
705 tcg_gen_andi_i32(cpu_SR[sr], v,
706 dc->config->inttype_mask[INTTYPE_SOFTWARE]);
d2132510 707 gen_check_interrupts(dc);
b994e91b 708 gen_jumpi_check_loop_end(dc, 0);
d2132510 709 return true;
b994e91b
MF		 710}
711
d2132510 712static bool gen_wsr_intclear(DisasContext *dc, uint32_t sr, TCGv_i32 v)
b994e91b
MF		 713{
714 TCGv_i32 tmp = tcg_temp_new_i32();
715
716 tcg_gen_andi_i32(tmp, v,
717 dc->config->inttype_mask[INTTYPE_EDGE] |
718 dc->config->inttype_mask[INTTYPE_NMI] |
719 dc->config->inttype_mask[INTTYPE_SOFTWARE]);
720 tcg_gen_andc_i32(cpu_SR[INTSET], cpu_SR[INTSET], tmp);
721 tcg_temp_free(tmp);
d2132510
MF		 722 gen_check_interrupts(dc);
723 gen_jumpi_check_loop_end(dc, 0);
724 return true;
b994e91b
MF		 725}
726
d2132510 727static bool gen_wsr_intenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
b994e91b
MF		 728{
729 tcg_gen_mov_i32(cpu_SR[sr], v);
d2132510 730 gen_check_interrupts(dc);
b994e91b 731 gen_jumpi_check_loop_end(dc, 0);
d2132510 732 return true;
b994e91b
MF		 733}
734
d2132510 735static bool gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v)
f0a548b9
MF		 736{
737 uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB |
738 PS_UM | PS_EXCM | PS_INTLEVEL;
739
740 if (option_enabled(dc, XTENSA_OPTION_MMU)) {
741 mask |= PS_RING;
742 }
743 tcg_gen_andi_i32(cpu_SR[sr], v, mask);
d2132510 744 gen_check_interrupts(dc);
b994e91b 745 /* This can change mmu index and tb->flags, so exit tb */
797d780b 746 gen_jumpi_check_loop_end(dc, -1);
d2132510 747 return true;
f0a548b9
MF		 748}
749
d2132510 750static bool gen_wsr_ccount(DisasContext *dc, uint32_t sr, TCGv_i32 v)
59a71f75 751{
d2132510
MF		 752 if (dc->tb->cflags & CF_USE_ICOUNT) {
753 gen_io_start();
754 }
59a71f75 755 gen_helper_wsr_ccount(cpu_env, v);
d2132510
MF		 756 if (dc->tb->cflags & CF_USE_ICOUNT) {
757 gen_io_end();
758 gen_jumpi_check_loop_end(dc, 0);
759 return true;
760 }
761 return false;
59a71f75
MF		 762}
763
d2132510 764static bool gen_wsr_icount(DisasContext *dc, uint32_t sr, TCGv_i32 v)
35b5c044
MF		 765{
766 if (dc->icount) {
767 tcg_gen_mov_i32(dc->next_icount, v);
768 } else {
769 tcg_gen_mov_i32(cpu_SR[sr], v);
770 }
d2132510 771 return false;
35b5c044
MF		 772}
773
d2132510 774static bool gen_wsr_icountlevel(DisasContext *dc, uint32_t sr, TCGv_i32 v)
35b5c044
MF		 775{
776 tcg_gen_andi_i32(cpu_SR[sr], v, 0xf);
777 /* This can change tb->flags, so exit tb */
778 gen_jumpi_check_loop_end(dc, -1);
d2132510 779 return true;
35b5c044
MF		 780}
781
d2132510 782static bool gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v)
b994e91b
MF		 783{
784 uint32_t id = sr - CCOMPARE;
d2132510
MF		 785 bool ret = false;
786
b994e91b
MF		 787 if (id < dc->config->nccompare) {
788 uint32_t int_bit = 1 << dc->config->timerint[id];
59a71f75
MF		 789 TCGv_i32 tmp = tcg_const_i32(id);
790
b994e91b
MF		 791 tcg_gen_mov_i32(cpu_SR[sr], v);
792 tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit);
d2132510
MF		 793 if (dc->tb->cflags & CF_USE_ICOUNT) {
794 gen_io_start();
795 }
59a71f75 796 gen_helper_update_ccompare(cpu_env, tmp);
d2132510
MF		 797 if (dc->tb->cflags & CF_USE_ICOUNT) {
798 gen_io_end();
799 gen_jumpi_check_loop_end(dc, 0);
800 ret = true;
801 }
59a71f75 802 tcg_temp_free(tmp);
b994e91b 803 }
d2132510 804 return ret;
b994e91b
MF		 805}
806
d2132510 807static bool gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s)
b8132eff 808{
d2132510 809 static bool (* const wsr_handler[256])(DisasContext *dc,
b8132eff 810 uint32_t sr, TCGv_i32 v) = {
797d780b
MF		 811 [LBEG] = gen_wsr_lbeg,
812 [LEND] = gen_wsr_lend,
3580ecad 813 [SAR] = gen_wsr_sar,
4dd85b6b 814 [BR] = gen_wsr_br,
6ad6dbf7 815 [LITBASE] = gen_wsr_litbase,
6825b6c3 816 [ACCHI] = gen_wsr_acchi,
553e44f9 817 [WINDOW_BASE] = gen_wsr_windowbase,
772177c1 818 [WINDOW_START] = gen_wsr_windowstart,
b67ea0cd
MF		 819 [PTEVADDR] = gen_wsr_ptevaddr,
820 [RASID] = gen_wsr_rasid,
821 [ITLBCFG] = gen_wsr_tlbcfg,
822 [DTLBCFG] = gen_wsr_tlbcfg,
e61dc8f7 823 [IBREAKENABLE] = gen_wsr_ibreakenable,
fcc803d1 824 [ATOMCTL] = gen_wsr_atomctl,
e61dc8f7
MF		 825 [IBREAKA] = gen_wsr_ibreaka,
826 [IBREAKA + 1] = gen_wsr_ibreaka,
f14c4b5f
MF		 827 [DBREAKA] = gen_wsr_dbreaka,
828 [DBREAKA + 1] = gen_wsr_dbreaka,
829 [DBREAKC] = gen_wsr_dbreakc,
830 [DBREAKC + 1] = gen_wsr_dbreakc,
ef04a846 831 [CPENABLE] = gen_wsr_cpenable,
b994e91b
MF		 832 [INTSET] = gen_wsr_intset,
833 [INTCLEAR] = gen_wsr_intclear,
834 [INTENABLE] = gen_wsr_intenable,
f0a548b9 835 [PS] = gen_wsr_ps,
59a71f75 836 [CCOUNT] = gen_wsr_ccount,
35b5c044
MF		 837 [ICOUNT] = gen_wsr_icount,
838 [ICOUNTLEVEL] = gen_wsr_icountlevel,
b994e91b
MF		 839 [CCOMPARE] = gen_wsr_ccompare,
840 [CCOMPARE + 1] = gen_wsr_ccompare,
841 [CCOMPARE + 2] = gen_wsr_ccompare,
b8132eff
MF		 842 };
843
fe0bd475 844 if (wsr_handler[sr]) {
d2132510 845 return wsr_handler[sr](dc, sr, s);
b8132eff 846 } else {
fe0bd475 847 tcg_gen_mov_i32(cpu_SR[sr], s);
d2132510 848 return false;
b8132eff
MF		 849 }
850}
851
dd519cbe
MF		 852static void gen_wur(uint32_t ur, TCGv_i32 s)
853{
854 switch (ur) {
855 case FCR:
856 gen_helper_wur_fcr(cpu_env, s);
857 break;
858
859 case FSR:
860 tcg_gen_andi_i32(cpu_UR[ur], s, 0xffffff80);
861 break;
862
863 default:
864 tcg_gen_mov_i32(cpu_UR[ur], s);
865 break;
866 }
867}
868
5b4e481b
MF		 869static void gen_load_store_alignment(DisasContext *dc, int shift,
870 TCGv_i32 addr, bool no_hw_alignment)
871{
872 if (!option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) {
873 tcg_gen_andi_i32(addr, addr, ~0 << shift);
874 } else if (option_enabled(dc, XTENSA_OPTION_HW_ALIGNMENT) &&
875 no_hw_alignment) {
42a268c2 876 TCGLabel *label = gen_new_label();
5b4e481b
MF		 877 TCGv_i32 tmp = tcg_temp_new_i32();
878 tcg_gen_andi_i32(tmp, addr, ~(~0 << shift));
879 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
880 gen_exception_cause_vaddr(dc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
881 gen_set_label(label);
882 tcg_temp_free(tmp);
883 }
884}
885
b994e91b
MF		 886static void gen_waiti(DisasContext *dc, uint32_t imm4)
887{
888 TCGv_i32 pc = tcg_const_i32(dc->next_pc);
889 TCGv_i32 intlevel = tcg_const_i32(imm4);
d2132510
MF		 890
891 if (dc->tb->cflags & CF_USE_ICOUNT) {
892 gen_io_start();
893 }
f492b82d 894 gen_helper_waiti(cpu_env, pc, intlevel);
d2132510
MF		 895 if (dc->tb->cflags & CF_USE_ICOUNT) {
896 gen_io_end();
897 }
b994e91b
MF		 898 tcg_temp_free(pc);
899 tcg_temp_free(intlevel);
d2132510 900 gen_jumpi_check_loop_end(dc, 0);
b994e91b
MF		 901}
902
97e89ee9 903static bool gen_window_check1(DisasContext *dc, unsigned r1)
772177c1 904{
2db59a76
MF		 905 if (r1 / 4 > dc->window) {
906 TCGv_i32 pc = tcg_const_i32(dc->pc);
907 TCGv_i32 w = tcg_const_i32(r1 / 4);
908c67fc 908
2db59a76
MF		 909 gen_helper_window_check(cpu_env, pc, w);
910 dc->is_jmp = DISAS_UPDATE;
97e89ee9 911 return false;
772177c1 912 }
97e89ee9 913 return true;
772177c1
MF		 914}
915
97e89ee9 916static bool gen_window_check2(DisasContext *dc, unsigned r1, unsigned r2)
772177c1 917{
97e89ee9 918 return gen_window_check1(dc, r1 > r2 ? r1 : r2);
772177c1
MF		 919}
920
97e89ee9 921static bool gen_window_check3(DisasContext *dc, unsigned r1, unsigned r2,
772177c1
MF		 922 unsigned r3)
923{
97e89ee9 924 return gen_window_check2(dc, r1, r2 > r3 ? r2 : r3);
772177c1
MF		 925}
926
6825b6c3
MF		 927static TCGv_i32 gen_mac16_m(TCGv_i32 v, bool hi, bool is_unsigned)
928{
929 TCGv_i32 m = tcg_temp_new_i32();
930
931 if (hi) {
932 (is_unsigned ? tcg_gen_shri_i32 : tcg_gen_sari_i32)(m, v, 16);
933 } else {
934 (is_unsigned ? tcg_gen_ext16u_i32 : tcg_gen_ext16s_i32)(m, v);
935 }
936 return m;
937}
938
01673a34
MF		 939static inline unsigned xtensa_op0_insn_len(unsigned op0)
940{
941 return op0 >= 8 ? 2 : 3;
942}
943
0c4fabea 944static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
dedc5eae 945{
b67ea0cd
MF		 946#define HAS_OPTION_BITS(opt) do { \
947 if (!option_bits_enabled(dc, opt)) { \
c30f0d18
PB		 948 qemu_log_mask(LOG_GUEST_ERROR, "Option is not enabled %s:%d\n", \
949 __FILE__, __LINE__); \
dedc5eae
MF		 950 goto invalid_opcode; \
951 } \
952 } while (0)
953
b67ea0cd
MF		 954#define HAS_OPTION(opt) HAS_OPTION_BITS(XTENSA_OPTION_BIT(opt))
955
c30f0d18 956#define TBD() qemu_log_mask(LOG_UNIMP, "TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__)
91a5bb76 957#define RESERVED() do { \
c30f0d18
PB		 958 qemu_log_mask(LOG_GUEST_ERROR, "RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \
959 dc->pc, b0, b1, b2, __FILE__, __LINE__); \
91a5bb76
MF		 960 goto invalid_opcode; \
961 } while (0)
962
963
dedc5eae
MF		 964#ifdef TARGET_WORDS_BIGENDIAN
965#define OP0 (((b0) & 0xf0) >> 4)
966#define OP1 (((b2) & 0xf0) >> 4)
967#define OP2 ((b2) & 0xf)
968#define RRR_R ((b1) & 0xf)
969#define RRR_S (((b1) & 0xf0) >> 4)
970#define RRR_T ((b0) & 0xf)
971#else
972#define OP0 (((b0) & 0xf))
973#define OP1 (((b2) & 0xf))
974#define OP2 (((b2) & 0xf0) >> 4)
975#define RRR_R (((b1) & 0xf0) >> 4)
976#define RRR_S (((b1) & 0xf))
977#define RRR_T (((b0) & 0xf0) >> 4)
978#endif
6825b6c3
MF		 979#define RRR_X ((RRR_R & 0x4) >> 2)
980#define RRR_Y ((RRR_T & 0x4) >> 2)
981#define RRR_W (RRR_R & 0x3)
dedc5eae
MF		 982
983#define RRRN_R RRR_R
984#define RRRN_S RRR_S
985#define RRRN_T RRR_T
986
65026682
MF		 987#define RRI4_R RRR_R
988#define RRI4_S RRR_S
989#define RRI4_T RRR_T
990#ifdef TARGET_WORDS_BIGENDIAN
991#define RRI4_IMM4 ((b2) & 0xf)
992#else
993#define RRI4_IMM4 (((b2) & 0xf0) >> 4)
994#endif
995
dedc5eae
MF		 996#define RRI8_R RRR_R
997#define RRI8_S RRR_S
998#define RRI8_T RRR_T
999#define RRI8_IMM8 (b2)
1000#define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8)
1001
1002#ifdef TARGET_WORDS_BIGENDIAN
1003#define RI16_IMM16 (((b1) << 8) | (b2))
1004#else
1005#define RI16_IMM16 (((b2) << 8) | (b1))
1006#endif
1007
1008#ifdef TARGET_WORDS_BIGENDIAN
1009#define CALL_N (((b0) & 0xc) >> 2)
1010#define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2))
1011#else
1012#define CALL_N (((b0) & 0x30) >> 4)
1013#define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10))
1014#endif
1015#define CALL_OFFSET_SE \
1016 (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET)
1017
1018#define CALLX_N CALL_N
1019#ifdef TARGET_WORDS_BIGENDIAN
1020#define CALLX_M ((b0) & 0x3)
1021#else
1022#define CALLX_M (((b0) & 0xc0) >> 6)
1023#endif
1024#define CALLX_S RRR_S
1025
1026#define BRI12_M CALLX_M
1027#define BRI12_S RRR_S
1028#ifdef TARGET_WORDS_BIGENDIAN
1029#define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2))
1030#else
1031#define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4))
1032#endif
1033#define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12)
1034
1035#define BRI8_M BRI12_M
1036#define BRI8_R RRI8_R
1037#define BRI8_S RRI8_S
1038#define BRI8_IMM8 RRI8_IMM8
1039#define BRI8_IMM8_SE RRI8_IMM8_SE
1040
1041#define RSR_SR (b1)
1042
0c4fabea
BS		 1043 uint8_t b0 = cpu_ldub_code(env, dc->pc);
1044 uint8_t b1 = cpu_ldub_code(env, dc->pc + 1);
a044ec2a 1045 uint8_t b2 = 0;
01673a34 1046 unsigned len = xtensa_op0_insn_len(OP0);
dedc5eae 1047
bd57fb91
MF		 1048 static const uint32_t B4CONST[] = {
1049 0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
1050 };
1051
1052 static const uint32_t B4CONSTU[] = {
1053 32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
1054 };
1055
01673a34
MF		 1056 switch (len) {
1057 case 2:
dedc5eae 1058 HAS_OPTION(XTENSA_OPTION_CODE_DENSITY);
01673a34
MF		 1059 break;
1060
1061 case 3:
0c4fabea 1062 b2 = cpu_ldub_code(env, dc->pc + 2);
01673a34
MF		 1063 break;
1064
1065 default:
1066 RESERVED();
dedc5eae 1067 }
01673a34 1068 dc->next_pc = dc->pc + len;
dedc5eae
MF		 1069
1070 switch (OP0) {
1071 case 0: /*QRST*/
1072 switch (OP1) {
1073 case 0: /*RST0*/
1074 switch (OP2) {
1075 case 0: /*ST0*/
1076 if ((RRR_R & 0xc) == 0x8) {
1077 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
1078 }
1079
1080 switch (RRR_R) {
1081 case 0: /*SNM0*/
5da4a6a8
MF		 1082 switch (CALLX_M) {
1083 case 0: /*ILL*/
40643d7c 1084 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
5da4a6a8
MF		 1085 break;
1086
1087 case 1: /*reserved*/
91a5bb76 1088 RESERVED();
5da4a6a8
MF		 1089 break;
1090
1091 case 2: /*JR*/
1092 switch (CALLX_N) {
1093 case 0: /*RET*/
1094 case 2: /*JX*/
97e89ee9
MF		 1095 if (gen_window_check1(dc, CALLX_S)) {
1096 gen_jump(dc, cpu_R[CALLX_S]);
1097 }
5da4a6a8
MF		 1098 break;
1099
1100 case 1: /*RETWw*/
1101 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 1102 {
1103 TCGv_i32 tmp = tcg_const_i32(dc->pc);
f492b82d 1104 gen_helper_retw(tmp, cpu_env, tmp);
553e44f9
MF		 1105 gen_jump(dc, tmp);
1106 tcg_temp_free(tmp);
1107 }
5da4a6a8
MF		 1108 break;
1109
1110 case 3: /*reserved*/
91a5bb76 1111 RESERVED();
5da4a6a8
MF		 1112 break;
1113 }
1114 break;
1115
1116 case 3: /*CALLX*/
97e89ee9
MF		 1117 if (!gen_window_check2(dc, CALLX_S, CALLX_N << 2)) {
1118 break;
1119 }
5da4a6a8
MF		 1120 switch (CALLX_N) {
1121 case 0: /*CALLX0*/
1122 {
1123 TCGv_i32 tmp = tcg_temp_new_i32();
1124 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
1125 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
1126 gen_jump(dc, tmp);
1127 tcg_temp_free(tmp);
1128 }
1129 break;
1130
1131 case 1: /*CALLX4w*/
1132 case 2: /*CALLX8w*/
1133 case 3: /*CALLX12w*/
1134 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 1135 {
1136 TCGv_i32 tmp = tcg_temp_new_i32();
1137
1138 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
1139 gen_callw(dc, CALLX_N, tmp);
1140 tcg_temp_free(tmp);
1141 }
5da4a6a8
MF		 1142 break;
1143 }
1144 break;
1145 }
dedc5eae
MF		 1146 break;
1147
1148 case 1: /*MOVSPw*/
1149 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
97e89ee9 1150 if (gen_window_check2(dc, RRR_T, RRR_S)) {
553e44f9 1151 TCGv_i32 pc = tcg_const_i32(dc->pc);
f492b82d 1152 gen_helper_movsp(cpu_env, pc);
553e44f9
MF		 1153 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_R[RRR_S]);
1154 tcg_temp_free(pc);
1155 }
dedc5eae
MF		 1156 break;
1157
1158 case 2: /*SYNC*/
28067b22
MF		 1159 switch (RRR_T) {
1160 case 0: /*ISYNC*/
1161 break;
1162
1163 case 1: /*RSYNC*/
1164 break;
1165
1166 case 2: /*ESYNC*/
1167 break;
1168
1169 case 3: /*DSYNC*/
1170 break;
1171
1172 case 8: /*EXCW*/
1173 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
1174 break;
1175
1176 case 12: /*MEMW*/
1177 break;
1178
1179 case 13: /*EXTW*/
1180 break;
1181
1182 case 15: /*NOP*/
1183 break;
1184
1185 default: /*reserved*/
1186 RESERVED();
1187 break;
1188 }
91a5bb76
MF		 1189 break;
1190
1191 case 3: /*RFEIx*/
40643d7c
MF		 1192 switch (RRR_T) {
1193 case 0: /*RFETx*/
1194 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
1195 switch (RRR_S) {
1196 case 0: /*RFEx*/
97e89ee9
MF		 1197 if (gen_check_privilege(dc)) {
1198 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
d2132510 1199 gen_check_interrupts(dc);
97e89ee9
MF		 1200 gen_jump(dc, cpu_SR[EPC1]);
1201 }
40643d7c
MF		 1202 break;
1203
1204 case 1: /*RFUEx*/
1205 RESERVED();
1206 break;
1207
1208 case 2: /*RFDEx*/
97e89ee9
MF		 1209 if (gen_check_privilege(dc)) {
1210 gen_jump(dc, cpu_SR[
1211 dc->config->ndepc ? DEPC : EPC1]);
1212 }
40643d7c
MF		 1213 break;
1214
1215 case 4: /*RFWOw*/
1216 case 5: /*RFWUw*/
1217 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
97e89ee9 1218 if (gen_check_privilege(dc)) {
553e44f9
MF		 1219 TCGv_i32 tmp = tcg_const_i32(1);
1220
1221 tcg_gen_andi_i32(
1222 cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
1223 tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]);
1224
1225 if (RRR_S == 4) {
1226 tcg_gen_andc_i32(cpu_SR[WINDOW_START],
1227 cpu_SR[WINDOW_START], tmp);
1228 } else {
1229 tcg_gen_or_i32(cpu_SR[WINDOW_START],
1230 cpu_SR[WINDOW_START], tmp);
1231 }
1232
f492b82d 1233 gen_helper_restore_owb(cpu_env);
d2132510 1234 gen_check_interrupts(dc);
553e44f9
MF		 1235 gen_jump(dc, cpu_SR[EPC1]);
1236
1237 tcg_temp_free(tmp);
1238 }
40643d7c
MF		 1239 break;
1240
1241 default: /*reserved*/
1242 RESERVED();
1243 break;
1244 }
1245 break;
1246
1247 case 1: /*RFIx*/
1248 HAS_OPTION(XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT);
b994e91b 1249 if (RRR_S >= 2 && RRR_S <= dc->config->nlevel) {
97e89ee9
MF		 1250 if (gen_check_privilege(dc)) {
1251 tcg_gen_mov_i32(cpu_SR[PS],
1252 cpu_SR[EPS2 + RRR_S - 2]);
d2132510 1253 gen_check_interrupts(dc);
97e89ee9
MF		 1254 gen_jump(dc, cpu_SR[EPC1 + RRR_S - 1]);
1255 }
b994e91b 1256 } else {
c30f0d18 1257 qemu_log_mask(LOG_GUEST_ERROR, "RFI %d is illegal\n", RRR_S);
b994e91b
MF		 1258 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1259 }
40643d7c
MF		 1260 break;
1261
1262 case 2: /*RFME*/
1263 TBD();
1264 break;
1265
1266 default: /*reserved*/
1267 RESERVED();
1268 break;
1269
1270 }
91a5bb76
MF		 1271 break;
1272
1273 case 4: /*BREAKx*/
e61dc8f7
MF		 1274 HAS_OPTION(XTENSA_OPTION_DEBUG);
1275 if (dc->debug) {
1276 gen_debug_exception(dc, DEBUGCAUSE_BI);
1277 }
91a5bb76
MF		 1278 break;
1279
1280 case 5: /*SYSCALLx*/
1281 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
40643d7c
MF		 1282 switch (RRR_S) {
1283 case 0: /*SYSCALLx*/
1284 gen_exception_cause(dc, SYSCALL_CAUSE);
1285 break;
1286
1287 case 1: /*SIMCALL*/
cfe67cef 1288 if (semihosting_enabled()) {
97e89ee9
MF		 1289 if (gen_check_privilege(dc)) {
1290 gen_helper_simcall(cpu_env);
1291 }
1ddeaa5d 1292 } else {
c30f0d18 1293 qemu_log_mask(LOG_GUEST_ERROR, "SIMCALL but semihosting is disabled\n");
1ddeaa5d
MF		 1294 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1295 }
40643d7c
MF		 1296 break;
1297
1298 default:
1299 RESERVED();
1300 break;
1301 }
91a5bb76
MF		 1302 break;
1303
1304 case 6: /*RSILx*/
1305 HAS_OPTION(XTENSA_OPTION_INTERRUPT);
97e89ee9
MF		 1306 if (gen_check_privilege(dc) &&
1307 gen_window_check1(dc, RRR_T)) {
1308 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_SR[PS]);
1309 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL);
1310 tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], RRR_S);
d2132510 1311 gen_check_interrupts(dc);
97e89ee9
MF		 1312 gen_jumpi_check_loop_end(dc, 0);
1313 }
91a5bb76
MF		 1314 break;
1315
1316 case 7: /*WAITIx*/
1317 HAS_OPTION(XTENSA_OPTION_INTERRUPT);
97e89ee9
MF		 1318 if (gen_check_privilege(dc)) {
1319 gen_waiti(dc, RRR_S);
1320 }
91a5bb76
MF		 1321 break;
1322
1323 case 8: /*ANY4p*/
91a5bb76 1324 case 9: /*ALL4p*/
91a5bb76 1325 case 10: /*ANY8p*/
91a5bb76
MF		 1326 case 11: /*ALL8p*/
1327 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
4dd85b6b
MF		 1328 {
1329 const unsigned shift = (RRR_R & 2) ? 8 : 4;
1330 TCGv_i32 mask = tcg_const_i32(
1331 ((1 << shift) - 1) << RRR_S);
1332 TCGv_i32 tmp = tcg_temp_new_i32();
1333
1334 tcg_gen_and_i32(tmp, cpu_SR[BR], mask);
1335 if (RRR_R & 1) { /*ALL*/
1336 tcg_gen_addi_i32(tmp, tmp, 1 << RRR_S);
1337 } else { /*ANY*/
1338 tcg_gen_add_i32(tmp, tmp, mask);
1339 }
1340 tcg_gen_shri_i32(tmp, tmp, RRR_S + shift);
1341 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR],
1342 tmp, RRR_T, 1);
1343 tcg_temp_free(mask);
1344 tcg_temp_free(tmp);
1345 }
91a5bb76
MF		 1346 break;
1347
1348 default: /*reserved*/
1349 RESERVED();
dedc5eae
MF		 1350 break;
1351
1352 }
1353 break;
1354
1355 case 1: /*AND*/
97e89ee9
MF		 1356 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1357 tcg_gen_and_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1358 }
dedc5eae
MF		 1359 break;
1360
1361 case 2: /*OR*/
97e89ee9
MF		 1362 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1363 tcg_gen_or_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1364 }
dedc5eae
MF		 1365 break;
1366
1367 case 3: /*XOR*/
97e89ee9
MF		 1368 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1369 tcg_gen_xor_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1370 }
dedc5eae
MF		 1371 break;
1372
1373 case 4: /*ST1*/
3580ecad
MF		 1374 switch (RRR_R) {
1375 case 0: /*SSR*/
97e89ee9
MF		 1376 if (gen_window_check1(dc, RRR_S)) {
1377 gen_right_shift_sar(dc, cpu_R[RRR_S]);
1378 }
3580ecad
MF		 1379 break;
1380
1381 case 1: /*SSL*/
97e89ee9
MF		 1382 if (gen_window_check1(dc, RRR_S)) {
1383 gen_left_shift_sar(dc, cpu_R[RRR_S]);
1384 }
3580ecad
MF		 1385 break;
1386
1387 case 2: /*SSA8L*/
97e89ee9 1388 if (gen_window_check1(dc, RRR_S)) {
3580ecad
MF		 1389 TCGv_i32 tmp = tcg_temp_new_i32();
1390 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
1391 gen_right_shift_sar(dc, tmp);
1392 tcg_temp_free(tmp);
1393 }
1394 break;
1395
1396 case 3: /*SSA8B*/
97e89ee9 1397 if (gen_window_check1(dc, RRR_S)) {
3580ecad
MF		 1398 TCGv_i32 tmp = tcg_temp_new_i32();
1399 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
1400 gen_left_shift_sar(dc, tmp);
1401 tcg_temp_free(tmp);
1402 }
1403 break;
1404
1405 case 4: /*SSAI*/
1406 {
1407 TCGv_i32 tmp = tcg_const_i32(
1408 RRR_S | ((RRR_T & 1) << 4));
1409 gen_right_shift_sar(dc, tmp);
1410 tcg_temp_free(tmp);
1411 }
1412 break;
1413
1414 case 6: /*RER*/
91a5bb76 1415 TBD();
3580ecad
MF		 1416 break;
1417
1418 case 7: /*WER*/
91a5bb76 1419 TBD();
3580ecad
MF		 1420 break;
1421
1422 case 8: /*ROTWw*/
1423 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
97e89ee9 1424 if (gen_check_privilege(dc)) {
553e44f9
MF		 1425 TCGv_i32 tmp = tcg_const_i32(
1426 RRR_T | ((RRR_T & 8) ? 0xfffffff0 : 0));
f492b82d 1427 gen_helper_rotw(cpu_env, tmp);
553e44f9 1428 tcg_temp_free(tmp);
2db59a76
MF		 1429 /* This can change tb->flags, so exit tb */
1430 gen_jumpi_check_loop_end(dc, -1);
553e44f9 1431 }
3580ecad
MF		 1432 break;
1433
1434 case 14: /*NSAu*/
7f65f4b0 1435 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA);
97e89ee9
MF		 1436 if (gen_window_check2(dc, RRR_S, RRR_T)) {
1437 gen_helper_nsa(cpu_R[RRR_T], cpu_R[RRR_S]);
1438 }
3580ecad
MF		 1439 break;
1440
1441 case 15: /*NSAUu*/
7f65f4b0 1442 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA);
97e89ee9
MF		 1443 if (gen_window_check2(dc, RRR_S, RRR_T)) {
1444 gen_helper_nsau(cpu_R[RRR_T], cpu_R[RRR_S]);
1445 }
3580ecad
MF		 1446 break;
1447
1448 default: /*reserved*/
91a5bb76 1449 RESERVED();
3580ecad
MF		 1450 break;
1451 }
dedc5eae
MF		 1452 break;
1453
1454 case 5: /*TLB*/
b67ea0cd
MF		 1455 HAS_OPTION_BITS(
1456 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU) |
1457 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
1458 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION));
97e89ee9
MF		 1459 if (gen_check_privilege(dc) &&
1460 gen_window_check2(dc, RRR_S, RRR_T)) {
b67ea0cd
MF		 1461 TCGv_i32 dtlb = tcg_const_i32((RRR_R & 8) != 0);
1462
1463 switch (RRR_R & 7) {
1464 case 3: /*RITLB0*/ /*RDTLB0*/
f492b82d
MF		 1465 gen_helper_rtlb0(cpu_R[RRR_T],
1466 cpu_env, cpu_R[RRR_S], dtlb);
b67ea0cd
MF		 1467 break;
1468
1469 case 4: /*IITLB*/ /*IDTLB*/
f492b82d 1470 gen_helper_itlb(cpu_env, cpu_R[RRR_S], dtlb);
b67ea0cd
MF		 1471 /* This could change memory mapping, so exit tb */
1472 gen_jumpi_check_loop_end(dc, -1);
1473 break;
1474
1475 case 5: /*PITLB*/ /*PDTLB*/
1476 tcg_gen_movi_i32(cpu_pc, dc->pc);
f492b82d
MF		 1477 gen_helper_ptlb(cpu_R[RRR_T],
1478 cpu_env, cpu_R[RRR_S], dtlb);
b67ea0cd
MF		 1479 break;
1480
1481 case 6: /*WITLB*/ /*WDTLB*/
f492b82d
MF		 1482 gen_helper_wtlb(
1483 cpu_env, cpu_R[RRR_T], cpu_R[RRR_S], dtlb);
b67ea0cd
MF		 1484 /* This could change memory mapping, so exit tb */
1485 gen_jumpi_check_loop_end(dc, -1);
1486 break;
1487
1488 case 7: /*RITLB1*/ /*RDTLB1*/
f492b82d
MF		 1489 gen_helper_rtlb1(cpu_R[RRR_T],
1490 cpu_env, cpu_R[RRR_S], dtlb);
b67ea0cd
MF		 1491 break;
1492
1493 default:
1494 tcg_temp_free(dtlb);
1495 RESERVED();
1496 break;
1497 }
1498 tcg_temp_free(dtlb);
1499 }
dedc5eae
MF		 1500 break;
1501
1502 case 6: /*RT0*/
97e89ee9
MF		 1503 if (!gen_window_check2(dc, RRR_R, RRR_T)) {
1504 break;
1505 }
f331fe5e
MF		 1506 switch (RRR_S) {
1507 case 0: /*NEG*/
1508 tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1509 break;
1510
1511 case 1: /*ABS*/
1512 {
f877d09e
MF		 1513 TCGv_i32 zero = tcg_const_i32(0);
1514 TCGv_i32 neg = tcg_temp_new_i32();
1515
1516 tcg_gen_neg_i32(neg, cpu_R[RRR_T]);
1517 tcg_gen_movcond_i32(TCG_COND_GE, cpu_R[RRR_R],
1518 cpu_R[RRR_T], zero, cpu_R[RRR_T], neg);
1519 tcg_temp_free(neg);
1520 tcg_temp_free(zero);
f331fe5e
MF		 1521 }
1522 break;
1523
1524 default: /*reserved*/
91a5bb76 1525 RESERVED();
f331fe5e
MF		 1526 break;
1527 }
dedc5eae
MF		 1528 break;
1529
1530 case 7: /*reserved*/
91a5bb76 1531 RESERVED();
dedc5eae
MF		 1532 break;
1533
1534 case 8: /*ADD*/
97e89ee9
MF		 1535 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1536 tcg_gen_add_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1537 }
dedc5eae
MF		 1538 break;
1539
1540 case 9: /*ADD**/
1541 case 10:
1542 case 11:
97e89ee9 1543 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
dedc5eae
MF		 1544 TCGv_i32 tmp = tcg_temp_new_i32();
1545 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 8);
1546 tcg_gen_add_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
1547 tcg_temp_free(tmp);
1548 }
1549 break;
1550
1551 case 12: /*SUB*/
97e89ee9
MF		 1552 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1553 tcg_gen_sub_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1554 }
dedc5eae
MF		 1555 break;
1556
1557 case 13: /*SUB**/
1558 case 14:
1559 case 15:
97e89ee9 1560 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
dedc5eae
MF		 1561 TCGv_i32 tmp = tcg_temp_new_i32();
1562 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 12);
1563 tcg_gen_sub_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
1564 tcg_temp_free(tmp);
1565 }
1566 break;
1567 }
1568 break;
1569
1570 case 1: /*RST1*/
3580ecad
MF		 1571 switch (OP2) {
1572 case 0: /*SLLI*/
1573 case 1:
97e89ee9
MF		 1574 if (gen_window_check2(dc, RRR_R, RRR_S)) {
1575 tcg_gen_shli_i32(cpu_R[RRR_R], cpu_R[RRR_S],
1576 32 - (RRR_T | ((OP2 & 1) << 4)));
1577 }
3580ecad
MF		 1578 break;
1579
1580 case 2: /*SRAI*/
1581 case 3:
97e89ee9
MF		 1582 if (gen_window_check2(dc, RRR_R, RRR_T)) {
1583 tcg_gen_sari_i32(cpu_R[RRR_R], cpu_R[RRR_T],
1584 RRR_S | ((OP2 & 1) << 4));
1585 }
3580ecad
MF		 1586 break;
1587
1588 case 4: /*SRLI*/
97e89ee9
MF		 1589 if (gen_window_check2(dc, RRR_R, RRR_T)) {
1590 tcg_gen_shri_i32(cpu_R[RRR_R], cpu_R[RRR_T], RRR_S);
1591 }
3580ecad
MF		 1592 break;
1593
1594 case 6: /*XSR*/
97e89ee9
MF		 1595 if (gen_check_sr(dc, RSR_SR, SR_X) &&
1596 (RSR_SR < 64 || gen_check_privilege(dc)) &&
1597 gen_window_check1(dc, RRR_T)) {
3580ecad 1598 TCGv_i32 tmp = tcg_temp_new_i32();
d2132510 1599 bool rsr_end, wsr_end;
0857a06e 1600
3580ecad 1601 tcg_gen_mov_i32(tmp, cpu_R[RRR_T]);
d2132510
MF		 1602 rsr_end = gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
1603 wsr_end = gen_wsr(dc, RSR_SR, tmp);
3580ecad 1604 tcg_temp_free(tmp);
d2132510
MF		 1605 if (rsr_end && !wsr_end) {
1606 gen_jumpi_check_loop_end(dc, 0);
1607 }
3580ecad
MF		 1608 }
1609 break;
1610
1611 /*
1612 * Note: 64 bit ops are used here solely because SAR values
1613 * have range 0..63
1614 */
1615#define gen_shift_reg(cmd, reg) do { \
1616 TCGv_i64 tmp = tcg_temp_new_i64(); \
1617 tcg_gen_extu_i32_i64(tmp, reg); \
1618 tcg_gen_##cmd##_i64(v, v, tmp); \
ecc7b3aa 1619 tcg_gen_extrl_i64_i32(cpu_R[RRR_R], v); \
3580ecad
MF		 1620 tcg_temp_free_i64(v); \
1621 tcg_temp_free_i64(tmp); \
1622 } while (0)
1623
1624#define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
1625
1626 case 8: /*SRC*/
97e89ee9 1627 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
3580ecad
MF		 1628 TCGv_i64 v = tcg_temp_new_i64();
1629 tcg_gen_concat_i32_i64(v, cpu_R[RRR_T], cpu_R[RRR_S]);
1630 gen_shift(shr);
1631 }
1632 break;
1633
1634 case 9: /*SRL*/
97e89ee9
MF		 1635 if (!gen_window_check2(dc, RRR_R, RRR_T)) {
1636 break;
1637 }
3580ecad
MF		 1638 if (dc->sar_5bit) {
1639 tcg_gen_shr_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
1640 } else {
1641 TCGv_i64 v = tcg_temp_new_i64();
1642 tcg_gen_extu_i32_i64(v, cpu_R[RRR_T]);
1643 gen_shift(shr);
1644 }
1645 break;
1646
1647 case 10: /*SLL*/
97e89ee9
MF		 1648 if (!gen_window_check2(dc, RRR_R, RRR_S)) {
1649 break;
1650 }
3580ecad
MF		 1651 if (dc->sar_m32_5bit) {
1652 tcg_gen_shl_i32(cpu_R[RRR_R], cpu_R[RRR_S], dc->sar_m32);
1653 } else {
1654 TCGv_i64 v = tcg_temp_new_i64();
1655 TCGv_i32 s = tcg_const_i32(32);
1656 tcg_gen_sub_i32(s, s, cpu_SR[SAR]);
1657 tcg_gen_andi_i32(s, s, 0x3f);
1658 tcg_gen_extu_i32_i64(v, cpu_R[RRR_S]);
1659 gen_shift_reg(shl, s);
1660 tcg_temp_free(s);
1661 }
1662 break;
1663
1664 case 11: /*SRA*/
97e89ee9
MF		 1665 if (!gen_window_check2(dc, RRR_R, RRR_T)) {
1666 break;
1667 }
3580ecad
MF		 1668 if (dc->sar_5bit) {
1669 tcg_gen_sar_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
1670 } else {
1671 TCGv_i64 v = tcg_temp_new_i64();
1672 tcg_gen_ext_i32_i64(v, cpu_R[RRR_T]);
1673 gen_shift(sar);
1674 }
1675 break;
1676#undef gen_shift
1677#undef gen_shift_reg
1678
1679 case 12: /*MUL16U*/
1680 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
97e89ee9 1681 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
3580ecad
MF		 1682 TCGv_i32 v1 = tcg_temp_new_i32();
1683 TCGv_i32 v2 = tcg_temp_new_i32();
1684 tcg_gen_ext16u_i32(v1, cpu_R[RRR_S]);
1685 tcg_gen_ext16u_i32(v2, cpu_R[RRR_T]);
1686 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1687 tcg_temp_free(v2);
1688 tcg_temp_free(v1);
1689 }
1690 break;
1691
1692 case 13: /*MUL16S*/
1693 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
97e89ee9 1694 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
3580ecad
MF		 1695 TCGv_i32 v1 = tcg_temp_new_i32();
1696 TCGv_i32 v2 = tcg_temp_new_i32();
1697 tcg_gen_ext16s_i32(v1, cpu_R[RRR_S]);
1698 tcg_gen_ext16s_i32(v2, cpu_R[RRR_T]);
1699 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1700 tcg_temp_free(v2);
1701 tcg_temp_free(v1);
1702 }
1703 break;
1704
1705 default: /*reserved*/
91a5bb76 1706 RESERVED();
3580ecad
MF		 1707 break;
1708 }
dedc5eae
MF		 1709 break;
1710
1711 case 2: /*RST2*/
97e89ee9
MF		 1712 if (OP2 >= 8 && !gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1713 break;
4dd85b6b 1714 }
772177c1 1715
f76ebf55
MF		 1716 if (OP2 >= 12) {
1717 HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV);
42a268c2 1718 TCGLabel *label = gen_new_label();
f76ebf55
MF		 1719 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0, label);
1720 gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE);
1721 gen_set_label(label);
1722 }
1723
1724 switch (OP2) {
4dd85b6b
MF		 1725#define BOOLEAN_LOGIC(fn, r, s, t) \
1726 do { \
1727 HAS_OPTION(XTENSA_OPTION_BOOLEAN); \
1728 TCGv_i32 tmp1 = tcg_temp_new_i32(); \
1729 TCGv_i32 tmp2 = tcg_temp_new_i32(); \
1730 \
1731 tcg_gen_shri_i32(tmp1, cpu_SR[BR], s); \
1732 tcg_gen_shri_i32(tmp2, cpu_SR[BR], t); \
1733 tcg_gen_##fn##_i32(tmp1, tmp1, tmp2); \
1734 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, r, 1); \
1735 tcg_temp_free(tmp1); \
1736 tcg_temp_free(tmp2); \
1737 } while (0)
1738
1739 case 0: /*ANDBp*/
1740 BOOLEAN_LOGIC(and, RRR_R, RRR_S, RRR_T);
1741 break;
1742
1743 case 1: /*ANDBCp*/
1744 BOOLEAN_LOGIC(andc, RRR_R, RRR_S, RRR_T);
1745 break;
1746
1747 case 2: /*ORBp*/
1748 BOOLEAN_LOGIC(or, RRR_R, RRR_S, RRR_T);
1749 break;
1750
1751 case 3: /*ORBCp*/
1752 BOOLEAN_LOGIC(orc, RRR_R, RRR_S, RRR_T);
1753 break;
1754
1755 case 4: /*XORBp*/
1756 BOOLEAN_LOGIC(xor, RRR_R, RRR_S, RRR_T);
1757 break;
1758
1759#undef BOOLEAN_LOGIC
1760
f76ebf55
MF		 1761 case 8: /*MULLi*/
1762 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL);
1763 tcg_gen_mul_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1764 break;
1765
1766 case 10: /*MULUHi*/
1767 case 11: /*MULSHi*/
7f65f4b0 1768 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL_HIGH);
f76ebf55 1769 {
c9cda20b 1770 TCGv lo = tcg_temp_new();
f76ebf55
MF		 1771
1772 if (OP2 == 10) {
c9cda20b
RH		 1773 tcg_gen_mulu2_i32(lo, cpu_R[RRR_R],
1774 cpu_R[RRR_S], cpu_R[RRR_T]);
f76ebf55 1775 } else {
c9cda20b
RH		 1776 tcg_gen_muls2_i32(lo, cpu_R[RRR_R],
1777 cpu_R[RRR_S], cpu_R[RRR_T]);
f76ebf55 1778 }
c9cda20b 1779 tcg_temp_free(lo);
f76ebf55
MF		 1780 }
1781 break;
1782
1783 case 12: /*QUOUi*/
1784 tcg_gen_divu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1785 break;
1786
1787 case 13: /*QUOSi*/
1788 case 15: /*REMSi*/
1789 {
42a268c2
RH		 1790 TCGLabel *label1 = gen_new_label();
1791 TCGLabel *label2 = gen_new_label();
f76ebf55
MF		 1792
1793 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_S], 0x80000000,
1794 label1);
1795 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0xffffffff,
1796 label1);
1797 tcg_gen_movi_i32(cpu_R[RRR_R],
1798 OP2 == 13 ? 0x80000000 : 0);
1799 tcg_gen_br(label2);
1800 gen_set_label(label1);
1801 if (OP2 == 13) {
1802 tcg_gen_div_i32(cpu_R[RRR_R],
1803 cpu_R[RRR_S], cpu_R[RRR_T]);
1804 } else {
1805 tcg_gen_rem_i32(cpu_R[RRR_R],
1806 cpu_R[RRR_S], cpu_R[RRR_T]);
1807 }
1808 gen_set_label(label2);
1809 }
1810 break;
1811
1812 case 14: /*REMUi*/
1813 tcg_gen_remu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1814 break;
1815
1816 default: /*reserved*/
1817 RESERVED();
1818 break;
1819 }
dedc5eae
MF		 1820 break;
1821
1822 case 3: /*RST3*/
b8132eff
MF		 1823 switch (OP2) {
1824 case 0: /*RSR*/
97e89ee9
MF		 1825 if (gen_check_sr(dc, RSR_SR, SR_R) &&
1826 (RSR_SR < 64 || gen_check_privilege(dc)) &&
1827 gen_window_check1(dc, RRR_T)) {
d2132510
MF		 1828 if (gen_rsr(dc, cpu_R[RRR_T], RSR_SR)) {
1829 gen_jumpi_check_loop_end(dc, 0);
1830 }
40643d7c 1831 }
b8132eff
MF		 1832 break;
1833
1834 case 1: /*WSR*/
97e89ee9
MF		 1835 if (gen_check_sr(dc, RSR_SR, SR_W) &&
1836 (RSR_SR < 64 || gen_check_privilege(dc)) &&
1837 gen_window_check1(dc, RRR_T)) {
0857a06e 1838 gen_wsr(dc, RSR_SR, cpu_R[RRR_T]);
40643d7c 1839 }
b8132eff
MF		 1840 break;
1841
1842 case 2: /*SEXTu*/
7f65f4b0 1843 HAS_OPTION(XTENSA_OPTION_MISC_OP_SEXT);
97e89ee9 1844 if (gen_window_check2(dc, RRR_R, RRR_S)) {
b8132eff
MF		 1845 int shift = 24 - RRR_T;
1846
1847 if (shift == 24) {
1848 tcg_gen_ext8s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1849 } else if (shift == 16) {
1850 tcg_gen_ext16s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1851 } else {
1852 TCGv_i32 tmp = tcg_temp_new_i32();
1853 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], shift);
1854 tcg_gen_sari_i32(cpu_R[RRR_R], tmp, shift);
1855 tcg_temp_free(tmp);
1856 }
1857 }
1858 break;
1859
1860 case 3: /*CLAMPSu*/
7f65f4b0 1861 HAS_OPTION(XTENSA_OPTION_MISC_OP_CLAMPS);
97e89ee9 1862 if (gen_window_check2(dc, RRR_R, RRR_S)) {
b8132eff
MF		 1863 TCGv_i32 tmp1 = tcg_temp_new_i32();
1864 TCGv_i32 tmp2 = tcg_temp_new_i32();
f877d09e 1865 TCGv_i32 zero = tcg_const_i32(0);
b8132eff
MF		 1866
1867 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 24 - RRR_T);
1868 tcg_gen_xor_i32(tmp2, tmp1, cpu_R[RRR_S]);
1869 tcg_gen_andi_i32(tmp2, tmp2, 0xffffffff << (RRR_T + 7));
b8132eff
MF		 1870
1871 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 31);
f877d09e 1872 tcg_gen_xori_i32(tmp1, tmp1, 0xffffffff >> (25 - RRR_T));
b8132eff 1873
f877d09e
MF		 1874 tcg_gen_movcond_i32(TCG_COND_EQ, cpu_R[RRR_R], tmp2, zero,
1875 cpu_R[RRR_S], tmp1);
b8132eff
MF		 1876 tcg_temp_free(tmp1);
1877 tcg_temp_free(tmp2);
f877d09e 1878 tcg_temp_free(zero);
b8132eff
MF		 1879 }
1880 break;
1881
1882 case 4: /*MINu*/
1883 case 5: /*MAXu*/
1884 case 6: /*MINUu*/
1885 case 7: /*MAXUu*/
7f65f4b0 1886 HAS_OPTION(XTENSA_OPTION_MISC_OP_MINMAX);
97e89ee9 1887 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
b8132eff
MF		 1888 static const TCGCond cond[] = {
1889 TCG_COND_LE,
1890 TCG_COND_GE,
1891 TCG_COND_LEU,
1892 TCG_COND_GEU
1893 };
f877d09e
MF		 1894 tcg_gen_movcond_i32(cond[OP2 - 4], cpu_R[RRR_R],
1895 cpu_R[RRR_S], cpu_R[RRR_T],
1896 cpu_R[RRR_S], cpu_R[RRR_T]);
b8132eff
MF		 1897 }
1898 break;
1899
1900 case 8: /*MOVEQZ*/
1901 case 9: /*MOVNEZ*/
1902 case 10: /*MOVLTZ*/
1903 case 11: /*MOVGEZ*/
97e89ee9 1904 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
b8132eff 1905 static const TCGCond cond[] = {
b8132eff 1906 TCG_COND_EQ,
f877d09e
MF		 1907 TCG_COND_NE,
1908 TCG_COND_LT,
b8132eff 1909 TCG_COND_GE,
b8132eff 1910 };
f877d09e
MF		 1911 TCGv_i32 zero = tcg_const_i32(0);
1912
1913 tcg_gen_movcond_i32(cond[OP2 - 8], cpu_R[RRR_R],
1914 cpu_R[RRR_T], zero, cpu_R[RRR_S], cpu_R[RRR_R]);
1915 tcg_temp_free(zero);
b8132eff
MF		 1916 }
1917 break;
1918
1919 case 12: /*MOVFp*/
b8132eff
MF		 1920 case 13: /*MOVTp*/
1921 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
97e89ee9 1922 if (gen_window_check2(dc, RRR_R, RRR_S)) {
f877d09e 1923 TCGv_i32 zero = tcg_const_i32(0);
4dd85b6b
MF		 1924 TCGv_i32 tmp = tcg_temp_new_i32();
1925
1926 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T);
f877d09e
MF		 1927 tcg_gen_movcond_i32(OP2 & 1 ? TCG_COND_NE : TCG_COND_EQ,
1928 cpu_R[RRR_R], tmp, zero,
1929 cpu_R[RRR_S], cpu_R[RRR_R]);
1930
4dd85b6b 1931 tcg_temp_free(tmp);
f877d09e 1932 tcg_temp_free(zero);
4dd85b6b 1933 }
b8132eff
MF		 1934 break;
1935
1936 case 14: /*RUR*/
97e89ee9 1937 if (gen_window_check1(dc, RRR_R)) {
b8132eff 1938 int st = (RRR_S << 4) + RRR_T;
fe0bd475 1939 if (uregnames[st].name) {
b8132eff
MF		 1940 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_UR[st]);
1941 } else {
c30f0d18 1942 qemu_log_mask(LOG_UNIMP, "RUR %d not implemented, ", st);
91a5bb76 1943 TBD();
b8132eff
MF		 1944 }
1945 }
1946 break;
1947
1948 case 15: /*WUR*/
97e89ee9
MF		 1949 if (gen_window_check1(dc, RRR_T)) {
1950 if (uregnames[RSR_SR].name) {
1951 gen_wur(RSR_SR, cpu_R[RRR_T]);
1952 } else {
c30f0d18 1953 qemu_log_mask(LOG_UNIMP, "WUR %d not implemented, ", RSR_SR);
97e89ee9
MF		 1954 TBD();
1955 }
b8132eff
MF		 1956 }
1957 break;
1958
1959 }
dedc5eae
MF		 1960 break;
1961
1962 case 4: /*EXTUI*/
1963 case 5:
97e89ee9 1964 if (gen_window_check2(dc, RRR_R, RRR_T)) {
f9cb5045 1965 int shiftimm = RRR_S | ((OP1 & 1) << 4);
3580ecad
MF		 1966 int maskimm = (1 << (OP2 + 1)) - 1;
1967
1968 TCGv_i32 tmp = tcg_temp_new_i32();
f783cb22
AJ		 1969 tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm);
1970 tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm);
3580ecad
MF		 1971 tcg_temp_free(tmp);
1972 }
dedc5eae
MF		 1973 break;
1974
1975 case 6: /*CUST0*/
91a5bb76 1976 RESERVED();
dedc5eae
MF		 1977 break;
1978
1979 case 7: /*CUST1*/
91a5bb76 1980 RESERVED();
dedc5eae
MF		 1981 break;
1982
1983 case 8: /*LSCXp*/
9ed7ae12
MF		 1984 switch (OP2) {
1985 case 0: /*LSXf*/
1986 case 1: /*LSXUf*/
1987 case 4: /*SSXf*/
1988 case 5: /*SSXUf*/
1989 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
97e89ee9
MF		 1990 if (gen_window_check2(dc, RRR_S, RRR_T) &&
1991 gen_check_cpenable(dc, 0)) {
9ed7ae12
MF		 1992 TCGv_i32 addr = tcg_temp_new_i32();
1993 tcg_gen_add_i32(addr, cpu_R[RRR_S], cpu_R[RRR_T]);
1994 gen_load_store_alignment(dc, 2, addr, false);
1995 if (OP2 & 0x4) {
1996 tcg_gen_qemu_st32(cpu_FR[RRR_R], addr, dc->cring);
1997 } else {
1998 tcg_gen_qemu_ld32u(cpu_FR[RRR_R], addr, dc->cring);
1999 }
2000 if (OP2 & 0x1) {
2001 tcg_gen_mov_i32(cpu_R[RRR_S], addr);
2002 }
2003 tcg_temp_free(addr);
2004 }
2005 break;
2006
2007 default: /*reserved*/
2008 RESERVED();
2009 break;
2010 }
dedc5eae
MF		 2011 break;
2012
2013 case 9: /*LSC4*/
97e89ee9
MF		 2014 if (!gen_window_check2(dc, RRR_S, RRR_T)) {
2015 break;
2016 }
553e44f9
MF		 2017 switch (OP2) {
2018 case 0: /*L32E*/
2019 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
f822b7e4
MF		 2020 if (gen_check_privilege(dc) &&
2021 gen_window_check2(dc, RRR_S, RRR_T)) {
553e44f9
MF		 2022 TCGv_i32 addr = tcg_temp_new_i32();
2023 tcg_gen_addi_i32(addr, cpu_R[RRR_S],
2024 (0xffffffc0 | (RRR_R << 2)));
2025 tcg_gen_qemu_ld32u(cpu_R[RRR_T], addr, dc->ring);
2026 tcg_temp_free(addr);
2027 }
2028 break;
2029
2030 case 4: /*S32E*/
2031 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
f822b7e4
MF		 2032 if (gen_check_privilege(dc) &&
2033 gen_window_check2(dc, RRR_S, RRR_T)) {
553e44f9
MF		 2034 TCGv_i32 addr = tcg_temp_new_i32();
2035 tcg_gen_addi_i32(addr, cpu_R[RRR_S],
2036 (0xffffffc0 | (RRR_R << 2)));
2037 tcg_gen_qemu_st32(cpu_R[RRR_T], addr, dc->ring);
2038 tcg_temp_free(addr);
2039 }
2040 break;
2041
19b7bec4
MF		 2042 case 5: /*S32N*/
2043 if (gen_window_check2(dc, RRI4_S, RRI4_T)) {
2044 TCGv_i32 addr = tcg_temp_new_i32();
2045
2046 tcg_gen_addi_i32(addr, cpu_R[RRI4_S], RRI4_IMM4 << 2);
2047 gen_load_store_alignment(dc, 2, addr, false);
2048 tcg_gen_qemu_st32(cpu_R[RRI4_T], addr, dc->cring);
2049 tcg_temp_free(addr);
2050 }
2051 break;
2052
553e44f9
MF		 2053 default:
2054 RESERVED();
2055 break;
2056 }
dedc5eae
MF		 2057 break;
2058
2059 case 10: /*FP0*/
5eeb40c5
MF		 2060 /*DEPBITS*/
2061 if (option_enabled(dc, XTENSA_OPTION_DEPBITS)) {
2062 if (!gen_window_check2(dc, RRR_S, RRR_T)) {
2063 break;
2064 }
2065 tcg_gen_deposit_i32(cpu_R[RRR_T], cpu_R[RRR_T], cpu_R[RRR_S],
2066 OP2, RRR_R + 1);
2067 break;
2068 }
2069
dedc5eae 2070 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
0b6df838
MF		 2071 switch (OP2) {
2072 case 0: /*ADD.Sf*/
97e89ee9
MF		 2073 if (gen_check_cpenable(dc, 0)) {
2074 gen_helper_add_s(cpu_FR[RRR_R], cpu_env,
2075 cpu_FR[RRR_S], cpu_FR[RRR_T]);
2076 }
0b6df838
MF		 2077 break;
2078
2079 case 1: /*SUB.Sf*/
97e89ee9
MF		 2080 if (gen_check_cpenable(dc, 0)) {
2081 gen_helper_sub_s(cpu_FR[RRR_R], cpu_env,
2082 cpu_FR[RRR_S], cpu_FR[RRR_T]);
2083 }
0b6df838
MF		 2084 break;
2085
2086 case 2: /*MUL.Sf*/
97e89ee9
MF		 2087 if (gen_check_cpenable(dc, 0)) {
2088 gen_helper_mul_s(cpu_FR[RRR_R], cpu_env,
2089 cpu_FR[RRR_S], cpu_FR[RRR_T]);
2090 }
0b6df838
MF		 2091 break;
2092
2093 case 4: /*MADD.Sf*/
97e89ee9
MF		 2094 if (gen_check_cpenable(dc, 0)) {
2095 gen_helper_madd_s(cpu_FR[RRR_R], cpu_env,
2096 cpu_FR[RRR_R], cpu_FR[RRR_S],
2097 cpu_FR[RRR_T]);
2098 }
0b6df838
MF		 2099 break;
2100
2101 case 5: /*MSUB.Sf*/
97e89ee9
MF		 2102 if (gen_check_cpenable(dc, 0)) {
2103 gen_helper_msub_s(cpu_FR[RRR_R], cpu_env,
2104 cpu_FR[RRR_R], cpu_FR[RRR_S],
2105 cpu_FR[RRR_T]);
2106 }
0b6df838
MF		 2107 break;
2108
b7ee8c6a
MF		 2109 case 8: /*ROUND.Sf*/
2110 case 9: /*TRUNC.Sf*/
2111 case 10: /*FLOOR.Sf*/
2112 case 11: /*CEIL.Sf*/
2113 case 14: /*UTRUNC.Sf*/
97e89ee9
MF		 2114 if (gen_window_check1(dc, RRR_R) &&
2115 gen_check_cpenable(dc, 0)) {
b7ee8c6a
MF		 2116 static const unsigned rounding_mode_const[] = {
2117 float_round_nearest_even,
2118 float_round_to_zero,
2119 float_round_down,
2120 float_round_up,
2121 [6] = float_round_to_zero,
2122 };
2123 TCGv_i32 rounding_mode = tcg_const_i32(
2124 rounding_mode_const[OP2 & 7]);
2125 TCGv_i32 scale = tcg_const_i32(RRR_T);
2126
2127 if (OP2 == 14) {
2128 gen_helper_ftoui(cpu_R[RRR_R], cpu_FR[RRR_S],
2129 rounding_mode, scale);
2130 } else {
2131 gen_helper_ftoi(cpu_R[RRR_R], cpu_FR[RRR_S],
2132 rounding_mode, scale);
2133 }
2134
2135 tcg_temp_free(rounding_mode);
2136 tcg_temp_free(scale);
2137 }
2138 break;
2139
2140 case 12: /*FLOAT.Sf*/
2141 case 13: /*UFLOAT.Sf*/
97e89ee9
MF		 2142 if (gen_window_check1(dc, RRR_S) &&
2143 gen_check_cpenable(dc, 0)) {
b7ee8c6a
MF		 2144 TCGv_i32 scale = tcg_const_i32(-RRR_T);
2145
2146 if (OP2 == 13) {
2147 gen_helper_uitof(cpu_FR[RRR_R], cpu_env,
2148 cpu_R[RRR_S], scale);
2149 } else {
2150 gen_helper_itof(cpu_FR[RRR_R], cpu_env,
2151 cpu_R[RRR_S], scale);
2152 }
2153 tcg_temp_free(scale);
2154 }
2155 break;
2156
0b6df838
MF		 2157 case 15: /*FP1OP*/
2158 switch (RRR_T) {
2159 case 0: /*MOV.Sf*/
97e89ee9
MF		 2160 if (gen_check_cpenable(dc, 0)) {
2161 tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2162 }
0b6df838
MF		 2163 break;
2164
2165 case 1: /*ABS.Sf*/
97e89ee9
MF		 2166 if (gen_check_cpenable(dc, 0)) {
2167 gen_helper_abs_s(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2168 }
0b6df838
MF		 2169 break;
2170
2171 case 4: /*RFRf*/
97e89ee9
MF		 2172 if (gen_window_check1(dc, RRR_R) &&
2173 gen_check_cpenable(dc, 0)) {
2174 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_FR[RRR_S]);
2175 }
0b6df838
MF		 2176 break;
2177
2178 case 5: /*WFRf*/
97e89ee9
MF		 2179 if (gen_window_check1(dc, RRR_S) &&
2180 gen_check_cpenable(dc, 0)) {
2181 tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_R[RRR_S]);
2182 }
0b6df838
MF		 2183 break;
2184
2185 case 6: /*NEG.Sf*/
97e89ee9
MF		 2186 if (gen_check_cpenable(dc, 0)) {
2187 gen_helper_neg_s(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2188 }
0b6df838
MF		 2189 break;
2190
2191 default: /*reserved*/
2192 RESERVED();
2193 break;
2194 }
2195 break;
2196
2197 default: /*reserved*/
2198 RESERVED();
2199 break;
2200 }
dedc5eae
MF		 2201 break;
2202
2203 case 11: /*FP1*/
5eeb40c5
MF		 2204 /*DEPBITS*/
2205 if (option_enabled(dc, XTENSA_OPTION_DEPBITS)) {
2206 if (!gen_window_check2(dc, RRR_S, RRR_T)) {
2207 break;
2208 }
2209 tcg_gen_deposit_i32(cpu_R[RRR_T], cpu_R[RRR_T], cpu_R[RRR_S],
2210 OP2 + 16, RRR_R + 1);
2211 break;
2212 }
2213
dedc5eae 2214 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
4e273869
MF		 2215
2216#define gen_compare(rel, br, a, b) \
2217 do { \
97e89ee9
MF		 2218 if (gen_check_cpenable(dc, 0)) { \
2219 TCGv_i32 bit = tcg_const_i32(1 << br); \
2220 \
2221 gen_helper_##rel(cpu_env, bit, cpu_FR[a], cpu_FR[b]); \
2222 tcg_temp_free(bit); \
2223 } \
4e273869
MF		 2224 } while (0)
2225
2226 switch (OP2) {
2227 case 1: /*UN.Sf*/
2228 gen_compare(un_s, RRR_R, RRR_S, RRR_T);
2229 break;
2230
2231 case 2: /*OEQ.Sf*/
2232 gen_compare(oeq_s, RRR_R, RRR_S, RRR_T);
2233 break;
2234
2235 case 3: /*UEQ.Sf*/
2236 gen_compare(ueq_s, RRR_R, RRR_S, RRR_T);
2237 break;
2238
2239 case 4: /*OLT.Sf*/
2240 gen_compare(olt_s, RRR_R, RRR_S, RRR_T);
2241 break;
2242
2243 case 5: /*ULT.Sf*/
2244 gen_compare(ult_s, RRR_R, RRR_S, RRR_T);
2245 break;
2246
2247 case 6: /*OLE.Sf*/
2248 gen_compare(ole_s, RRR_R, RRR_S, RRR_T);
2249 break;
2250
2251 case 7: /*ULE.Sf*/
2252 gen_compare(ule_s, RRR_R, RRR_S, RRR_T);
2253 break;
2254
2255#undef gen_compare
2256
2257 case 8: /*MOVEQZ.Sf*/
2258 case 9: /*MOVNEZ.Sf*/
2259 case 10: /*MOVLTZ.Sf*/
2260 case 11: /*MOVGEZ.Sf*/
97e89ee9
MF		 2261 if (gen_window_check1(dc, RRR_T) &&
2262 gen_check_cpenable(dc, 0)) {
4e273869 2263 static const TCGCond cond[] = {
4e273869 2264 TCG_COND_EQ,
f877d09e
MF		 2265 TCG_COND_NE,
2266 TCG_COND_LT,
4e273869 2267 TCG_COND_GE,
4e273869 2268 };
f877d09e
MF		 2269 TCGv_i32 zero = tcg_const_i32(0);
2270
2271 tcg_gen_movcond_i32(cond[OP2 - 8], cpu_FR[RRR_R],
2272 cpu_R[RRR_T], zero, cpu_FR[RRR_S], cpu_FR[RRR_R]);
2273 tcg_temp_free(zero);
4e273869
MF		 2274 }
2275 break;
2276
2277 case 12: /*MOVF.Sf*/
2278 case 13: /*MOVT.Sf*/
2279 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
97e89ee9 2280 if (gen_check_cpenable(dc, 0)) {
f877d09e 2281 TCGv_i32 zero = tcg_const_i32(0);
4e273869
MF		 2282 TCGv_i32 tmp = tcg_temp_new_i32();
2283
2284 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T);
f877d09e
MF		 2285 tcg_gen_movcond_i32(OP2 & 1 ? TCG_COND_NE : TCG_COND_EQ,
2286 cpu_FR[RRR_R], tmp, zero,
2287 cpu_FR[RRR_S], cpu_FR[RRR_R]);
2288
4e273869 2289 tcg_temp_free(tmp);
f877d09e 2290 tcg_temp_free(zero);
4e273869
MF		 2291 }
2292 break;
2293
2294 default: /*reserved*/
2295 RESERVED();
2296 break;
2297 }
dedc5eae
MF		 2298 break;
2299
2300 default: /*reserved*/
91a5bb76 2301 RESERVED();
dedc5eae
MF		 2302 break;
2303 }
2304 break;
2305
2306 case 1: /*L32R*/
97e89ee9 2307 if (gen_window_check1(dc, RRR_T)) {
dedc5eae 2308 TCGv_i32 tmp = tcg_const_i32(
6ad6dbf7
MF		 2309 ((dc->tb->flags & XTENSA_TBFLAG_LITBASE) ?
2310 0 : ((dc->pc + 3) & ~3)) +
2311 (0xfffc0000 | (RI16_IMM16 << 2)));
dedc5eae 2312
6ad6dbf7
MF		 2313 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
2314 tcg_gen_add_i32(tmp, tmp, dc->litbase);
2315 }
f0a548b9 2316 tcg_gen_qemu_ld32u(cpu_R[RRR_T], tmp, dc->cring);
dedc5eae
MF		 2317 tcg_temp_free(tmp);
2318 }
2319 break;
2320
2321 case 2: /*LSAI*/
809377aa 2322#define gen_load_store(type, shift) do { \
97e89ee9
MF		 2323 if (gen_window_check2(dc, RRI8_S, RRI8_T)) { \
2324 TCGv_i32 addr = tcg_temp_new_i32(); \
2325 \
2326 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << shift); \
2327 if (shift) { \
2328 gen_load_store_alignment(dc, shift, addr, false); \
2329 } \
2330 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
2331 tcg_temp_free(addr); \
5b4e481b 2332 } \
809377aa
MF		 2333 } while (0)
2334
2335 switch (RRI8_R) {
2336 case 0: /*L8UI*/
2337 gen_load_store(ld8u, 0);
2338 break;
2339
2340 case 1: /*L16UI*/
2341 gen_load_store(ld16u, 1);
2342 break;
2343
2344 case 2: /*L32I*/
2345 gen_load_store(ld32u, 2);
2346 break;
2347
2348 case 4: /*S8I*/
2349 gen_load_store(st8, 0);
2350 break;
2351
2352 case 5: /*S16I*/
2353 gen_load_store(st16, 1);
2354 break;
2355
2356 case 6: /*S32I*/
2357 gen_load_store(st32, 2);
2358 break;
2359
7c842590 2360#define gen_dcache_hit_test(w, shift) do { \
97e89ee9
MF		 2361 if (gen_window_check1(dc, RRI##w##_S)) { \
2362 TCGv_i32 addr = tcg_temp_new_i32(); \
2363 TCGv_i32 res = tcg_temp_new_i32(); \
2364 tcg_gen_addi_i32(addr, cpu_R[RRI##w##_S], \
2365 RRI##w##_IMM##w << shift); \
2366 tcg_gen_qemu_ld8u(res, addr, dc->cring); \
2367 tcg_temp_free(addr); \
2368 tcg_temp_free(res); \
2369 } \
7c842590
MF		 2370 } while (0)
2371
2372#define gen_dcache_hit_test4() gen_dcache_hit_test(4, 4)
2373#define gen_dcache_hit_test8() gen_dcache_hit_test(8, 2)
2374
809377aa 2375 case 7: /*CACHEc*/
8ffc2d0d
MF		 2376 if (RRI8_T < 8) {
2377 HAS_OPTION(XTENSA_OPTION_DCACHE);
2378 }
2379
2380 switch (RRI8_T) {
2381 case 0: /*DPFRc*/
7c842590 2382 gen_window_check1(dc, RRI8_S);
8ffc2d0d
MF		 2383 break;
2384
2385 case 1: /*DPFWc*/
7c842590 2386 gen_window_check1(dc, RRI8_S);
8ffc2d0d
MF		 2387 break;
2388
2389 case 2: /*DPFROc*/
7c842590 2390 gen_window_check1(dc, RRI8_S);
8ffc2d0d
MF		 2391 break;
2392
2393 case 3: /*DPFWOc*/
7c842590 2394 gen_window_check1(dc, RRI8_S);
8ffc2d0d
MF		 2395 break;
2396
2397 case 4: /*DHWBc*/
7c842590 2398 gen_dcache_hit_test8();
8ffc2d0d
MF		 2399 break;
2400
2401 case 5: /*DHWBIc*/
7c842590 2402 gen_dcache_hit_test8();
8ffc2d0d
MF		 2403 break;
2404
2405 case 6: /*DHIc*/
97e89ee9
MF		 2406 if (gen_check_privilege(dc)) {
2407 gen_dcache_hit_test8();
2408 }
8ffc2d0d
MF		 2409 break;
2410
2411 case 7: /*DIIc*/
97e89ee9
MF		 2412 if (gen_check_privilege(dc)) {
2413 gen_window_check1(dc, RRI8_S);
2414 }
8ffc2d0d
MF		 2415 break;
2416
2417 case 8: /*DCEc*/
2418 switch (OP1) {
2419 case 0: /*DPFLl*/
2420 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
97e89ee9
MF		 2421 if (gen_check_privilege(dc)) {
2422 gen_dcache_hit_test4();
2423 }
8ffc2d0d
MF		 2424 break;
2425
2426 case 2: /*DHUl*/
2427 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
97e89ee9
MF		 2428 if (gen_check_privilege(dc)) {
2429 gen_dcache_hit_test4();
2430 }
8ffc2d0d
MF		 2431 break;
2432
2433 case 3: /*DIUl*/
2434 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
97e89ee9
MF		 2435 if (gen_check_privilege(dc)) {
2436 gen_window_check1(dc, RRI4_S);
2437 }
8ffc2d0d
MF		 2438 break;
2439
2440 case 4: /*DIWBc*/
2441 HAS_OPTION(XTENSA_OPTION_DCACHE);
97e89ee9
MF		 2442 if (gen_check_privilege(dc)) {
2443 gen_window_check1(dc, RRI4_S);
2444 }
8ffc2d0d
MF		 2445 break;
2446
2447 case 5: /*DIWBIc*/
2448 HAS_OPTION(XTENSA_OPTION_DCACHE);
97e89ee9
MF		 2449 if (gen_check_privilege(dc)) {
2450 gen_window_check1(dc, RRI4_S);
2451 }
8ffc2d0d
MF		 2452 break;
2453
2454 default: /*reserved*/
2455 RESERVED();
2456 break;
2457
2458 }
2459 break;
2460
7c842590
MF		 2461#undef gen_dcache_hit_test
2462#undef gen_dcache_hit_test4
2463#undef gen_dcache_hit_test8
2464
e848dd42 2465#define gen_icache_hit_test(w, shift) do { \
97e89ee9
MF		 2466 if (gen_window_check1(dc, RRI##w##_S)) { \
2467 TCGv_i32 addr = tcg_temp_new_i32(); \
2468 tcg_gen_movi_i32(cpu_pc, dc->pc); \
2469 tcg_gen_addi_i32(addr, cpu_R[RRI##w##_S], \
2470 RRI##w##_IMM##w << shift); \
2471 gen_helper_itlb_hit_test(cpu_env, addr); \
2472 tcg_temp_free(addr); \
2473 }\
e848dd42
MF		 2474 } while (0)
2475
2476#define gen_icache_hit_test4() gen_icache_hit_test(4, 4)
2477#define gen_icache_hit_test8() gen_icache_hit_test(8, 2)
2478
8ffc2d0d
MF		 2479 case 12: /*IPFc*/
2480 HAS_OPTION(XTENSA_OPTION_ICACHE);
e848dd42 2481 gen_window_check1(dc, RRI8_S);
8ffc2d0d
MF		 2482 break;
2483
2484 case 13: /*ICEc*/
2485 switch (OP1) {
2486 case 0: /*IPFLl*/
2487 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
97e89ee9
MF		 2488 if (gen_check_privilege(dc)) {
2489 gen_icache_hit_test4();
2490 }
8ffc2d0d
MF		 2491 break;
2492
2493 case 2: /*IHUl*/
2494 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
97e89ee9
MF		 2495 if (gen_check_privilege(dc)) {
2496 gen_icache_hit_test4();
2497 }
8ffc2d0d
MF		 2498 break;
2499
2500 case 3: /*IIUl*/
2501 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
97e89ee9
MF		 2502 if (gen_check_privilege(dc)) {
2503 gen_window_check1(dc, RRI4_S);
2504 }
8ffc2d0d
MF		 2505 break;
2506
2507 default: /*reserved*/
2508 RESERVED();
2509 break;
2510 }
2511 break;
2512
2513 case 14: /*IHIc*/
2514 HAS_OPTION(XTENSA_OPTION_ICACHE);
e848dd42 2515 gen_icache_hit_test8();
8ffc2d0d
MF		 2516 break;
2517
2518 case 15: /*IIIc*/
2519 HAS_OPTION(XTENSA_OPTION_ICACHE);
97e89ee9
MF		 2520 if (gen_check_privilege(dc)) {
2521 gen_window_check1(dc, RRI8_S);
2522 }
8ffc2d0d
MF		 2523 break;
2524
2525 default: /*reserved*/
2526 RESERVED();
2527 break;
2528 }
809377aa
MF		 2529 break;
2530
e848dd42
MF		 2531#undef gen_icache_hit_test
2532#undef gen_icache_hit_test4
2533#undef gen_icache_hit_test8
2534
809377aa
MF		 2535 case 9: /*L16SI*/
2536 gen_load_store(ld16s, 1);
2537 break;
5b4e481b 2538#undef gen_load_store
809377aa
MF		 2539
2540 case 10: /*MOVI*/
97e89ee9
MF		 2541 if (gen_window_check1(dc, RRI8_T)) {
2542 tcg_gen_movi_i32(cpu_R[RRI8_T],
2543 RRI8_IMM8 | (RRI8_S << 8) |
2544 ((RRI8_S & 0x8) ? 0xfffff000 : 0));
2545 }
809377aa
MF		 2546 break;
2547
5b4e481b 2548#define gen_load_store_no_hw_align(type) do { \
97e89ee9
MF		 2549 if (gen_window_check2(dc, RRI8_S, RRI8_T)) { \
2550 TCGv_i32 addr = tcg_temp_local_new_i32(); \
2551 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); \
2552 gen_load_store_alignment(dc, 2, addr, true); \
2553 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
2554 tcg_temp_free(addr); \
2555 } \
5b4e481b
MF		 2556 } while (0)
2557
809377aa
MF		 2558 case 11: /*L32AIy*/
2559 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
5b4e481b 2560 gen_load_store_no_hw_align(ld32u); /*TODO acquire?*/
809377aa
MF		 2561 break;
2562
2563 case 12: /*ADDI*/
97e89ee9
MF		 2564 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
2565 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE);
2566 }
809377aa
MF		 2567 break;
2568
2569 case 13: /*ADDMI*/
97e89ee9
MF		 2570 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
2571 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S],
2572 RRI8_IMM8_SE << 8);
2573 }
809377aa
MF		 2574 break;
2575
2576 case 14: /*S32C1Iy*/
7f65f4b0 2577 HAS_OPTION(XTENSA_OPTION_CONDITIONAL_STORE);
97e89ee9 2578 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
42a268c2 2579 TCGLabel *label = gen_new_label();
809377aa
MF		 2580 TCGv_i32 tmp = tcg_temp_local_new_i32();
2581 TCGv_i32 addr = tcg_temp_local_new_i32();
fcc803d1 2582 TCGv_i32 tpc;
809377aa
MF		 2583
2584 tcg_gen_mov_i32(tmp, cpu_R[RRI8_T]);
2585 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2);
5b4e481b 2586 gen_load_store_alignment(dc, 2, addr, true);
fcc803d1 2587
fcc803d1
MF		 2588 tpc = tcg_const_i32(dc->pc);
2589 gen_helper_check_atomctl(cpu_env, tpc, addr);
f0a548b9 2590 tcg_gen_qemu_ld32u(cpu_R[RRI8_T], addr, dc->cring);
809377aa
MF		 2591 tcg_gen_brcond_i32(TCG_COND_NE, cpu_R[RRI8_T],
2592 cpu_SR[SCOMPARE1], label);
2593
f0a548b9 2594 tcg_gen_qemu_st32(tmp, addr, dc->cring);
809377aa
MF		 2595
2596 gen_set_label(label);
fcc803d1 2597 tcg_temp_free(tpc);
809377aa
MF		 2598 tcg_temp_free(addr);
2599 tcg_temp_free(tmp);
2600 }
2601 break;
2602
2603 case 15: /*S32RIy*/
2604 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
5b4e481b 2605 gen_load_store_no_hw_align(st32); /*TODO release?*/
809377aa 2606 break;
5b4e481b 2607#undef gen_load_store_no_hw_align
809377aa
MF		 2608
2609 default: /*reserved*/
91a5bb76 2610 RESERVED();
809377aa
MF		 2611 break;
2612 }
dedc5eae
MF		 2613 break;
2614
2615 case 3: /*LSCIp*/
9ed7ae12
MF		 2616 switch (RRI8_R) {
2617 case 0: /*LSIf*/
2618 case 4: /*SSIf*/
2619 case 8: /*LSIUf*/
2620 case 12: /*SSIUf*/
2621 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
97e89ee9
MF		 2622 if (gen_window_check1(dc, RRI8_S) &&
2623 gen_check_cpenable(dc, 0)) {
9ed7ae12
MF		 2624 TCGv_i32 addr = tcg_temp_new_i32();
2625 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2);
2626 gen_load_store_alignment(dc, 2, addr, false);
2627 if (RRI8_R & 0x4) {
2628 tcg_gen_qemu_st32(cpu_FR[RRI8_T], addr, dc->cring);
2629 } else {
2630 tcg_gen_qemu_ld32u(cpu_FR[RRI8_T], addr, dc->cring);
2631 }
2632 if (RRI8_R & 0x8) {
2633 tcg_gen_mov_i32(cpu_R[RRI8_S], addr);
2634 }
2635 tcg_temp_free(addr);
2636 }
2637 break;
2638
2639 default: /*reserved*/
2640 RESERVED();
2641 break;
2642 }
dedc5eae
MF		 2643 break;
2644
2645 case 4: /*MAC16d*/
2646 HAS_OPTION(XTENSA_OPTION_MAC16);
6825b6c3
MF		 2647 {
2648 enum {
2649 MAC16_UMUL = 0x0,
2650 MAC16_MUL = 0x4,
2651 MAC16_MULA = 0x8,
2652 MAC16_MULS = 0xc,
2653 MAC16_NONE = 0xf,
2654 } op = OP1 & 0xc;
2655 bool is_m1_sr = (OP2 & 0x3) == 2;
2656 bool is_m2_sr = (OP2 & 0xc) == 0;
2657 uint32_t ld_offset = 0;
2658
2659 if (OP2 > 9) {
2660 RESERVED();
2661 }
2662
2663 switch (OP2 & 2) {
2664 case 0: /*MACI?/MACC?*/
2665 is_m1_sr = true;
2666 ld_offset = (OP2 & 1) ? -4 : 4;
2667
2668 if (OP2 >= 8) { /*MACI/MACC*/
2669 if (OP1 == 0) { /*LDINC/LDDEC*/
2670 op = MAC16_NONE;
2671 } else {
2672 RESERVED();
2673 }
2674 } else if (op != MAC16_MULA) { /*MULA.*.*.LDINC/LDDEC*/
2675 RESERVED();
2676 }
2677 break;
2678
2679 case 2: /*MACD?/MACA?*/
2680 if (op == MAC16_UMUL && OP2 != 7) { /*UMUL only in MACAA*/
2681 RESERVED();
2682 }
2683 break;
2684 }
2685
2686 if (op != MAC16_NONE) {
97e89ee9
MF		 2687 if (!is_m1_sr && !gen_window_check1(dc, RRR_S)) {
2688 break;
6825b6c3 2689 }
97e89ee9
MF		 2690 if (!is_m2_sr && !gen_window_check1(dc, RRR_T)) {
2691 break;
6825b6c3
MF		 2692 }
2693 }
2694
97e89ee9
MF		 2695 if (ld_offset && !gen_window_check1(dc, RRR_S)) {
2696 break;
2697 }
2698
6825b6c3
MF		 2699 {
2700 TCGv_i32 vaddr = tcg_temp_new_i32();
2701 TCGv_i32 mem32 = tcg_temp_new_i32();
2702
2703 if (ld_offset) {
6825b6c3
MF		 2704 tcg_gen_addi_i32(vaddr, cpu_R[RRR_S], ld_offset);
2705 gen_load_store_alignment(dc, 2, vaddr, false);
2706 tcg_gen_qemu_ld32u(mem32, vaddr, dc->cring);
2707 }
2708 if (op != MAC16_NONE) {
2709 TCGv_i32 m1 = gen_mac16_m(
2710 is_m1_sr ? cpu_SR[MR + RRR_X] : cpu_R[RRR_S],
2711 OP1 & 1, op == MAC16_UMUL);
2712 TCGv_i32 m2 = gen_mac16_m(
2713 is_m2_sr ? cpu_SR[MR + 2 + RRR_Y] : cpu_R[RRR_T],
2714 OP1 & 2, op == MAC16_UMUL);
2715
2716 if (op == MAC16_MUL || op == MAC16_UMUL) {
2717 tcg_gen_mul_i32(cpu_SR[ACCLO], m1, m2);
2718 if (op == MAC16_UMUL) {
2719 tcg_gen_movi_i32(cpu_SR[ACCHI], 0);
2720 } else {
2721 tcg_gen_sari_i32(cpu_SR[ACCHI], cpu_SR[ACCLO], 31);
2722 }
2723 } else {
d2123a07
RH		 2724 TCGv_i32 lo = tcg_temp_new_i32();
2725 TCGv_i32 hi = tcg_temp_new_i32();
2726
2727 tcg_gen_mul_i32(lo, m1, m2);
2728 tcg_gen_sari_i32(hi, lo, 31);
6825b6c3 2729 if (op == MAC16_MULA) {
d2123a07
RH		 2730 tcg_gen_add2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI],
2731 cpu_SR[ACCLO], cpu_SR[ACCHI],
2732 lo, hi);
6825b6c3 2733 } else {
d2123a07
RH		 2734 tcg_gen_sub2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI],
2735 cpu_SR[ACCLO], cpu_SR[ACCHI],
2736 lo, hi);
6825b6c3 2737 }
6825b6c3
MF		 2738 tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]);
2739
d2123a07
RH		 2740 tcg_temp_free_i32(lo);
2741 tcg_temp_free_i32(hi);
6825b6c3
MF		 2742 }
2743 tcg_temp_free(m1);
2744 tcg_temp_free(m2);
2745 }
2746 if (ld_offset) {
2747 tcg_gen_mov_i32(cpu_R[RRR_S], vaddr);
2748 tcg_gen_mov_i32(cpu_SR[MR + RRR_W], mem32);
2749 }
2750 tcg_temp_free(vaddr);
2751 tcg_temp_free(mem32);
2752 }
2753 }
dedc5eae
MF		 2754 break;
2755
2756 case 5: /*CALLN*/
2757 switch (CALL_N) {
2758 case 0: /*CALL0*/
2759 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
2760 gen_jumpi(dc, (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
2761 break;
2762
2763 case 1: /*CALL4w*/
2764 case 2: /*CALL8w*/
2765 case 3: /*CALL12w*/
2766 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
97e89ee9
MF		 2767 if (gen_window_check1(dc, CALL_N << 2)) {
2768 gen_callwi(dc, CALL_N,
2769 (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
2770 }
dedc5eae
MF		 2771 break;
2772 }
2773 break;
2774
2775 case 6: /*SI*/
2776 switch (CALL_N) {
2777 case 0: /*J*/
2778 gen_jumpi(dc, dc->pc + 4 + CALL_OFFSET_SE, 0);
2779 break;
2780
bd57fb91 2781 case 1: /*BZ*/
97e89ee9 2782 if (gen_window_check1(dc, BRI12_S)) {
bd57fb91
MF		 2783 static const TCGCond cond[] = {
2784 TCG_COND_EQ, /*BEQZ*/
2785 TCG_COND_NE, /*BNEZ*/
2786 TCG_COND_LT, /*BLTZ*/
2787 TCG_COND_GE, /*BGEZ*/
2788 };
2789
2790 gen_brcondi(dc, cond[BRI12_M & 3], cpu_R[BRI12_S], 0,
2791 4 + BRI12_IMM12_SE);
2792 }
2793 break;
2794
2795 case 2: /*BI0*/
97e89ee9 2796 if (gen_window_check1(dc, BRI8_S)) {
bd57fb91
MF		 2797 static const TCGCond cond[] = {
2798 TCG_COND_EQ, /*BEQI*/
2799 TCG_COND_NE, /*BNEI*/
2800 TCG_COND_LT, /*BLTI*/
2801 TCG_COND_GE, /*BGEI*/
2802 };
2803
2804 gen_brcondi(dc, cond[BRI8_M & 3],
2805 cpu_R[BRI8_S], B4CONST[BRI8_R], 4 + BRI8_IMM8_SE);
2806 }
2807 break;
2808
2809 case 3: /*BI1*/
2810 switch (BRI8_M) {
2811 case 0: /*ENTRYw*/
2812 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 2813 {
2814 TCGv_i32 pc = tcg_const_i32(dc->pc);
2815 TCGv_i32 s = tcg_const_i32(BRI12_S);
2816 TCGv_i32 imm = tcg_const_i32(BRI12_IMM12);
f492b82d 2817 gen_helper_entry(cpu_env, pc, s, imm);
553e44f9
MF		 2818 tcg_temp_free(imm);
2819 tcg_temp_free(s);
2820 tcg_temp_free(pc);
2db59a76
MF		 2821 /* This can change tb->flags, so exit tb */
2822 gen_jumpi_check_loop_end(dc, -1);
553e44f9 2823 }
bd57fb91
MF		 2824 break;
2825
2826 case 1: /*B1*/
2827 switch (BRI8_R) {
2828 case 0: /*BFp*/
bd57fb91
MF		 2829 case 1: /*BTp*/
2830 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
4dd85b6b
MF		 2831 {
2832 TCGv_i32 tmp = tcg_temp_new_i32();
2833 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRI8_S);
2834 gen_brcondi(dc,
2835 BRI8_R == 1 ? TCG_COND_NE : TCG_COND_EQ,
2836 tmp, 0, 4 + RRI8_IMM8_SE);
2837 tcg_temp_free(tmp);
2838 }
bd57fb91
MF		 2839 break;
2840
2841 case 8: /*LOOP*/
bd57fb91 2842 case 9: /*LOOPNEZ*/
bd57fb91 2843 case 10: /*LOOPGTZ*/
797d780b 2844 HAS_OPTION(XTENSA_OPTION_LOOP);
97e89ee9 2845 if (gen_window_check1(dc, RRI8_S)) {
797d780b
MF		 2846 uint32_t lend = dc->pc + RRI8_IMM8 + 4;
2847 TCGv_i32 tmp = tcg_const_i32(lend);
2848
2849 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_R[RRI8_S], 1);
2850 tcg_gen_movi_i32(cpu_SR[LBEG], dc->next_pc);
f492b82d 2851 gen_helper_wsr_lend(cpu_env, tmp);
797d780b
MF		 2852 tcg_temp_free(tmp);
2853
2854 if (BRI8_R > 8) {
42a268c2 2855 TCGLabel *label = gen_new_label();
797d780b
MF		 2856 tcg_gen_brcondi_i32(
2857 BRI8_R == 9 ? TCG_COND_NE : TCG_COND_GT,
2858 cpu_R[RRI8_S], 0, label);
2859 gen_jumpi(dc, lend, 1);
2860 gen_set_label(label);
2861 }
2862
2863 gen_jumpi(dc, dc->next_pc, 0);
2864 }
bd57fb91
MF		 2865 break;
2866
2867 default: /*reserved*/
91a5bb76 2868 RESERVED();
bd57fb91
MF		 2869 break;
2870
2871 }
2872 break;
2873
2874 case 2: /*BLTUI*/
2875 case 3: /*BGEUI*/
97e89ee9
MF		 2876 if (gen_window_check1(dc, BRI8_S)) {
2877 gen_brcondi(dc, BRI8_M == 2 ? TCG_COND_LTU : TCG_COND_GEU,
2878 cpu_R[BRI8_S], B4CONSTU[BRI8_R],
2879 4 + BRI8_IMM8_SE);
2880 }
bd57fb91
MF		 2881 break;
2882 }
2883 break;
2884
dedc5eae
MF		 2885 }
2886 break;
2887
2888 case 7: /*B*/
bd57fb91
MF		 2889 {
2890 TCGCond eq_ne = (RRI8_R & 8) ? TCG_COND_NE : TCG_COND_EQ;
2891
2892 switch (RRI8_R & 7) {
2893 case 0: /*BNONE*/ /*BANY*/
97e89ee9 2894 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
bd57fb91
MF		 2895 TCGv_i32 tmp = tcg_temp_new_i32();
2896 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
2897 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2898 tcg_temp_free(tmp);
2899 }
2900 break;
2901
2902 case 1: /*BEQ*/ /*BNE*/
2903 case 2: /*BLT*/ /*BGE*/
2904 case 3: /*BLTU*/ /*BGEU*/
97e89ee9 2905 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
bd57fb91
MF		 2906 static const TCGCond cond[] = {
2907 [1] = TCG_COND_EQ,
2908 [2] = TCG_COND_LT,
2909 [3] = TCG_COND_LTU,
2910 [9] = TCG_COND_NE,
2911 [10] = TCG_COND_GE,
2912 [11] = TCG_COND_GEU,
2913 };
2914 gen_brcond(dc, cond[RRI8_R], cpu_R[RRI8_S], cpu_R[RRI8_T],
2915 4 + RRI8_IMM8_SE);
2916 }
2917 break;
2918
2919 case 4: /*BALL*/ /*BNALL*/
97e89ee9 2920 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
bd57fb91
MF		 2921 TCGv_i32 tmp = tcg_temp_new_i32();
2922 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
2923 gen_brcond(dc, eq_ne, tmp, cpu_R[RRI8_T],
2924 4 + RRI8_IMM8_SE);
2925 tcg_temp_free(tmp);
2926 }
2927 break;
2928
2929 case 5: /*BBC*/ /*BBS*/
97e89ee9 2930 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
7ff7563f
MF		 2931#ifdef TARGET_WORDS_BIGENDIAN
2932 TCGv_i32 bit = tcg_const_i32(0x80000000);
2933#else
2934 TCGv_i32 bit = tcg_const_i32(0x00000001);
2935#endif
bd57fb91
MF		 2936 TCGv_i32 tmp = tcg_temp_new_i32();
2937 tcg_gen_andi_i32(tmp, cpu_R[RRI8_T], 0x1f);
7ff7563f
MF		 2938#ifdef TARGET_WORDS_BIGENDIAN
2939 tcg_gen_shr_i32(bit, bit, tmp);
2940#else
bd57fb91 2941 tcg_gen_shl_i32(bit, bit, tmp);
7ff7563f 2942#endif
bd57fb91
MF		 2943 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], bit);
2944 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2945 tcg_temp_free(tmp);
2946 tcg_temp_free(bit);
2947 }
2948 break;
2949
2950 case 6: /*BBCI*/ /*BBSI*/
2951 case 7:
97e89ee9 2952 if (gen_window_check1(dc, RRI8_S)) {
bd57fb91
MF		 2953 TCGv_i32 tmp = tcg_temp_new_i32();
2954 tcg_gen_andi_i32(tmp, cpu_R[RRI8_S],
7ff7563f
MF		 2955#ifdef TARGET_WORDS_BIGENDIAN
2956 0x80000000 >> (((RRI8_R & 1) << 4) | RRI8_T));
2957#else
2958 0x00000001 << (((RRI8_R & 1) << 4) | RRI8_T));
2959#endif
bd57fb91
MF		 2960 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2961 tcg_temp_free(tmp);
2962 }
2963 break;
2964
2965 }
2966 }
dedc5eae
MF		 2967 break;
2968
67882fd1 2969#define gen_narrow_load_store(type) do { \
97e89ee9
MF		 2970 if (gen_window_check2(dc, RRRN_S, RRRN_T)) { \
2971 TCGv_i32 addr = tcg_temp_new_i32(); \
2972 tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
2973 gen_load_store_alignment(dc, 2, addr, false); \
2974 tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, dc->cring); \
2975 tcg_temp_free(addr); \
2976 } \
67882fd1
MF		 2977 } while (0)
2978
dedc5eae 2979 case 8: /*L32I.Nn*/
67882fd1 2980 gen_narrow_load_store(ld32u);
dedc5eae
MF		 2981 break;
2982
2983 case 9: /*S32I.Nn*/
67882fd1 2984 gen_narrow_load_store(st32);
dedc5eae 2985 break;
67882fd1 2986#undef gen_narrow_load_store
dedc5eae
MF		 2987
2988 case 10: /*ADD.Nn*/
97e89ee9
MF		 2989 if (gen_window_check3(dc, RRRN_R, RRRN_S, RRRN_T)) {
2990 tcg_gen_add_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], cpu_R[RRRN_T]);
2991 }
dedc5eae
MF		 2992 break;
2993
2994 case 11: /*ADDI.Nn*/
97e89ee9
MF		 2995 if (gen_window_check2(dc, RRRN_R, RRRN_S)) {
2996 tcg_gen_addi_i32(cpu_R[RRRN_R], cpu_R[RRRN_S],
2997 RRRN_T ? RRRN_T : -1);
2998 }
dedc5eae
MF		 2999 break;
3000
3001 case 12: /*ST2n*/
97e89ee9
MF		 3002 if (!gen_window_check1(dc, RRRN_S)) {
3003 break;
3004 }
67882fd1
MF		 3005 if (RRRN_T < 8) { /*MOVI.Nn*/
3006 tcg_gen_movi_i32(cpu_R[RRRN_S],
3007 RRRN_R | (RRRN_T << 4) |
3008 ((RRRN_T & 6) == 6 ? 0xffffff80 : 0));
3009 } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/
bd57fb91
MF		 3010 TCGCond eq_ne = (RRRN_T & 4) ? TCG_COND_NE : TCG_COND_EQ;
3011
3012 gen_brcondi(dc, eq_ne, cpu_R[RRRN_S], 0,
3013 4 + (RRRN_R | ((RRRN_T & 3) << 4)));
67882fd1 3014 }
dedc5eae
MF		 3015 break;
3016
3017 case 13: /*ST3n*/
67882fd1
MF		 3018 switch (RRRN_R) {
3019 case 0: /*MOV.Nn*/
97e89ee9
MF		 3020 if (gen_window_check2(dc, RRRN_S, RRRN_T)) {
3021 tcg_gen_mov_i32(cpu_R[RRRN_T], cpu_R[RRRN_S]);
3022 }
67882fd1
MF		 3023 break;
3024
3025 case 15: /*S3*/
3026 switch (RRRN_T) {
3027 case 0: /*RET.Nn*/
3028 gen_jump(dc, cpu_R[0]);
3029 break;
3030
3031 case 1: /*RETW.Nn*/
91a5bb76 3032 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 3033 {
3034 TCGv_i32 tmp = tcg_const_i32(dc->pc);
f492b82d 3035 gen_helper_retw(tmp, cpu_env, tmp);
553e44f9
MF		 3036 gen_jump(dc, tmp);
3037 tcg_temp_free(tmp);
3038 }
67882fd1
MF		 3039 break;
3040
3041 case 2: /*BREAK.Nn*/
e61dc8f7
MF		 3042 HAS_OPTION(XTENSA_OPTION_DEBUG);
3043 if (dc->debug) {
3044 gen_debug_exception(dc, DEBUGCAUSE_BN);
3045 }
67882fd1
MF		 3046 break;
3047
3048 case 3: /*NOP.Nn*/
3049 break;
3050
3051 case 6: /*ILL.Nn*/
40643d7c 3052 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
67882fd1
MF		 3053 break;
3054
3055 default: /*reserved*/
91a5bb76 3056 RESERVED();
67882fd1
MF		 3057 break;
3058 }
3059 break;
3060
3061 default: /*reserved*/
91a5bb76 3062 RESERVED();
67882fd1
MF		 3063 break;
3064 }
dedc5eae
MF		 3065 break;
3066
3067 default: /*reserved*/
91a5bb76 3068 RESERVED();
dedc5eae
MF		 3069 break;
3070 }
3071
c26032b2
MF		 3072 if (dc->is_jmp == DISAS_NEXT) {
3073 gen_check_loop_end(dc, 0);
3074 }
dedc5eae 3075 dc->pc = dc->next_pc;
797d780b 3076
dedc5eae
MF		 3077 return;
3078
3079invalid_opcode:
c30f0d18 3080 qemu_log_mask(LOG_GUEST_ERROR, "INVALID(pc = %08x)\n", dc->pc);
6b814719 3081 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
dedc5eae
MF		 3082#undef HAS_OPTION
3083}
3084
01673a34
MF		 3085static inline unsigned xtensa_insn_len(CPUXtensaState *env, DisasContext *dc)
3086{
3087 uint8_t b0 = cpu_ldub_code(env, dc->pc);
3088 return xtensa_op0_insn_len(OP0);
3089}
3090
97129ac8 3091static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc)
e61dc8f7
MF		 3092{
3093 unsigned i;
3094
3095 for (i = 0; i < dc->config->nibreak; ++i) {
3096 if ((env->sregs[IBREAKENABLE] & (1 << i)) &&
3097 env->sregs[IBREAKA + i] == dc->pc) {
3098 gen_debug_exception(dc, DEBUGCAUSE_IB);
3099 break;
3100 }
3101 }
3102}
3103
4e5e1215 3104void gen_intermediate_code(CPUXtensaState *env, TranslationBlock *tb)
dedc5eae 3105{
4e5e1215 3106 XtensaCPU *cpu = xtensa_env_get_cpu(env);
ed2803da 3107 CPUState *cs = CPU(cpu);
dedc5eae
MF		 3108 DisasContext dc;
3109 int insn_count = 0;
dedc5eae
MF		 3110 int max_insns = tb->cflags & CF_COUNT_MASK;
3111 uint32_t pc_start = tb->pc;
3112 uint32_t next_page_start =
3113 (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
3114
3115 if (max_insns == 0) {
3116 max_insns = CF_COUNT_MASK;
3117 }
190ce7fb
RH		 3118 if (max_insns > TCG_MAX_INSNS) {
3119 max_insns = TCG_MAX_INSNS;
3120 }
dedc5eae
MF		 3121
3122 dc.config = env->config;
ed2803da 3123 dc.singlestep_enabled = cs->singlestep_enabled;
dedc5eae
MF		 3124 dc.tb = tb;
3125 dc.pc = pc_start;
f0a548b9
MF		 3126 dc.ring = tb->flags & XTENSA_TBFLAG_RING_MASK;
3127 dc.cring = (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc.ring;
797d780b
MF		 3128 dc.lbeg = env->sregs[LBEG];
3129 dc.lend = env->sregs[LEND];
dedc5eae 3130 dc.is_jmp = DISAS_NEXT;
e61dc8f7 3131 dc.debug = tb->flags & XTENSA_TBFLAG_DEBUG;
35b5c044 3132 dc.icount = tb->flags & XTENSA_TBFLAG_ICOUNT;
ef04a846
MF		 3133 dc.cpenable = (tb->flags & XTENSA_TBFLAG_CPENABLE_MASK) >>
3134 XTENSA_TBFLAG_CPENABLE_SHIFT;
2db59a76
MF		 3135 dc.window = ((tb->flags & XTENSA_TBFLAG_WINDOW_MASK) >>
3136 XTENSA_TBFLAG_WINDOW_SHIFT);
dedc5eae 3137
6ad6dbf7 3138 init_litbase(&dc);
3580ecad 3139 init_sar_tracker(&dc);
35b5c044
MF		 3140 if (dc.icount) {
3141 dc.next_icount = tcg_temp_local_new_i32();
3142 }
3580ecad 3143
cd42d5b2 3144 gen_tb_start(tb);
dedc5eae 3145
d2132510
MF		 3146 if ((tb->cflags & CF_USE_ICOUNT) &&
3147 (tb->flags & XTENSA_TBFLAG_YIELD)) {
3148 tcg_gen_insn_start(dc.pc);
3149 ++insn_count;
3150 gen_exception(&dc, EXCP_YIELD);
3151 dc.is_jmp = DISAS_UPDATE;
3152 goto done;
3153 }
a00817cc 3154 if (tb->flags & XTENSA_TBFLAG_EXCEPTION) {
787eaa49
MF		 3155 tcg_gen_insn_start(dc.pc);
3156 ++insn_count;
b994e91b 3157 gen_exception(&dc, EXCP_DEBUG);
787eaa49
MF		 3158 dc.is_jmp = DISAS_UPDATE;
3159 goto done;
40643d7c
MF		 3160 }
3161
dedc5eae 3162 do {
667b8e29 3163 tcg_gen_insn_start(dc.pc);
959082fc 3164 ++insn_count;
dedc5eae 3165
b933066a
RH		 3166 if (unlikely(cpu_breakpoint_test(cs, dc.pc, BP_ANY))) {
3167 tcg_gen_movi_i32(cpu_pc, dc.pc);
3168 gen_exception(&dc, EXCP_DEBUG);
3169 dc.is_jmp = DISAS_UPDATE;
522a0d4e
RH		 3170 /* The address covered by the breakpoint must be included in
3171 [tb->pc, tb->pc + tb->size) in order to for it to be
3172 properly cleared -- thus we increment the PC here so that
3173 the logic setting tb->size below does the right thing. */
3174 dc.pc += 2;
b933066a
RH		 3175 break;
3176 }
3177
959082fc 3178 if (insn_count == max_insns && (tb->cflags & CF_LAST_IO)) {
b994e91b
MF		 3179 gen_io_start();
3180 }
3181
35b5c044 3182 if (dc.icount) {
42a268c2 3183 TCGLabel *label = gen_new_label();
35b5c044
MF		 3184
3185 tcg_gen_addi_i32(dc.next_icount, cpu_SR[ICOUNT], 1);
3186 tcg_gen_brcondi_i32(TCG_COND_NE, dc.next_icount, 0, label);
3187 tcg_gen_mov_i32(dc.next_icount, cpu_SR[ICOUNT]);
3188 if (dc.debug) {
3189 gen_debug_exception(&dc, DEBUGCAUSE_IC);
3190 }
3191 gen_set_label(label);
3192 }
3193
e61dc8f7
MF		 3194 if (dc.debug) {
3195 gen_ibreak_check(env, &dc);
3196 }
3197
0c4fabea 3198 disas_xtensa_insn(env, &dc);
35b5c044
MF		 3199 if (dc.icount) {
3200 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount);
3201 }
ed2803da 3202 if (cs->singlestep_enabled) {
dedc5eae 3203 tcg_gen_movi_i32(cpu_pc, dc.pc);
b994e91b 3204 gen_exception(&dc, EXCP_DEBUG);
dedc5eae
MF		 3205 break;
3206 }
3207 } while (dc.is_jmp == DISAS_NEXT &&
3208 insn_count < max_insns &&
3209 dc.pc < next_page_start &&
01673a34 3210 dc.pc + xtensa_insn_len(env, &dc) <= next_page_start &&
fe700adb 3211 !tcg_op_buf_full());
d2132510 3212done:
6ad6dbf7 3213 reset_litbase(&dc);
3580ecad 3214 reset_sar_tracker(&dc);
35b5c044
MF		 3215 if (dc.icount) {
3216 tcg_temp_free(dc.next_icount);
3217 }
3580ecad 3218
b994e91b
MF		 3219 if (tb->cflags & CF_LAST_IO) {
3220 gen_io_end();
3221 }
3222
dedc5eae
MF		 3223 if (dc.is_jmp == DISAS_NEXT) {
3224 gen_jumpi(&dc, dc.pc, 0);
3225 }
806f352d 3226 gen_tb_end(tb, insn_count);
dedc5eae 3227
ca529f8e 3228#ifdef DEBUG_DISAS
4910e6e4
RH		 3229 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
3230 && qemu_log_in_addr_range(pc_start)) {
1ee73216 3231 qemu_log_lock();
ca529f8e
MF		 3232 qemu_log("----------------\n");
3233 qemu_log("IN: %s\n", lookup_symbol(pc_start));
d49190c4 3234 log_target_disas(cs, pc_start, dc.pc - pc_start, 0);
ca529f8e 3235 qemu_log("\n");
1ee73216 3236 qemu_log_unlock();
ca529f8e
MF		 3237 }
3238#endif
4e5e1215
RH		 3239 tb->size = dc.pc - pc_start;
3240 tb->icount = insn_count;
2328826b
MF		 3241}
3242
878096ee
AF		 3243void xtensa_cpu_dump_state(CPUState *cs, FILE *f,
3244 fprintf_function cpu_fprintf, int flags)
2328826b 3245{
878096ee
AF		 3246 XtensaCPU *cpu = XTENSA_CPU(cs);
3247 CPUXtensaState *env = &cpu->env;
2af3da91
MF		 3248 int i, j;
3249
3250 cpu_fprintf(f, "PC=%08x\n\n", env->pc);
3251
3252 for (i = j = 0; i < 256; ++i) {
fe0bd475
MF		 3253 if (xtensa_option_bits_enabled(env->config, sregnames[i].opt_bits)) {
3254 cpu_fprintf(f, "%12s=%08x%c", sregnames[i].name, env->sregs[i],
2af3da91
MF		 3255 (j++ % 4) == 3 ? '\n' : ' ');
3256 }
3257 }
3258
3259 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
3260
3261 for (i = j = 0; i < 256; ++i) {
fe0bd475
MF		 3262 if (xtensa_option_bits_enabled(env->config, uregnames[i].opt_bits)) {
3263 cpu_fprintf(f, "%s=%08x%c", uregnames[i].name, env->uregs[i],
2af3da91
MF		 3264 (j++ % 4) == 3 ? '\n' : ' ');
3265 }
3266 }
2328826b 3267
2af3da91 3268 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
2328826b
MF		 3269
3270 for (i = 0; i < 16; ++i) {
fe0bd475 3271 cpu_fprintf(f, " A%02d=%08x%c", i, env->regs[i],
2328826b
MF		 3272 (i % 4) == 3 ? '\n' : ' ');
3273 }
553e44f9
MF		 3274
3275 cpu_fprintf(f, "\n");
3276
3277 for (i = 0; i < env->config->nareg; ++i) {
3278 cpu_fprintf(f, "AR%02d=%08x%c", i, env->phys_regs[i],
3279 (i % 4) == 3 ? '\n' : ' ');
3280 }
dd519cbe
MF		 3281
3282 if (xtensa_option_enabled(env->config, XTENSA_OPTION_FP_COPROCESSOR)) {
3283 cpu_fprintf(f, "\n");
3284
3285 for (i = 0; i < 16; ++i) {
3286 cpu_fprintf(f, "F%02d=%08x (%+10.8e)%c", i,
ddd44279
MF		 3287 float32_val(env->fregs[i].f32[FP_F32_LOW]),
3288 *(float *)(env->fregs[i].f32 + FP_F32_LOW),
3289 (i % 2) == 1 ? '\n' : ' ');
dd519cbe
MF		 3290 }
3291 }
2328826b
MF		 3292}
3293
bad729e2
RH		 3294void restore_state_to_opc(CPUXtensaState *env, TranslationBlock *tb,
3295 target_ulong *data)
2328826b 3296{
bad729e2 3297 env->pc = data[0];
2328826b 3298}
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