]> git.proxmox.com Git - mirror_qemu.git/blame - target/xtensa/translate.c
projects / mirror_qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
target/xtensa: tests: clean up interrupt tests
[mirror_qemu.git] / target / xtensa / translate.c
CommitLineData
2328826b
MF		 1/*
2 * Xtensa ISA:
3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
4 *
5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
09aae23d 31#include "qemu/osdep.h"
2328826b
MF		 32
33#include "cpu.h"
022c62cb 34#include "exec/exec-all.h"
76cad711 35#include "disas/disas.h"
2328826b 36#include "tcg-op.h"
1de7afc9 37#include "qemu/log.h"
9c17d615 38#include "sysemu/sysemu.h"
f08b6170 39#include "exec/cpu_ldst.h"
cfe67cef 40#include "exec/semihost.h"
2328826b 41
2ef6175a
RH		 42#include "exec/helper-proto.h"
43#include "exec/helper-gen.h"
dedc5eae 44
a7e30d84 45#include "trace-tcg.h"
508127e2 46#include "exec/log.h"
a7e30d84
LV		 47
48
dedc5eae
MF		 49typedef struct DisasContext {
50 const XtensaConfig *config;
51 TranslationBlock *tb;
52 uint32_t pc;
53 uint32_t next_pc;
f0a548b9
MF		 54 int cring;
55 int ring;
797d780b
MF		 56 uint32_t lbeg;
57 uint32_t lend;
6ad6dbf7 58 TCGv_i32 litbase;
dedc5eae
MF		 59 int is_jmp;
60 int singlestep_enabled;
3580ecad
MF		 61
62 bool sar_5bit;
63 bool sar_m32_5bit;
64 bool sar_m32_allocated;
65 TCGv_i32 sar_m32;
b994e91b 66
2db59a76 67 unsigned window;
e61dc8f7
MF		 68
69 bool debug;
35b5c044
MF		 70 bool icount;
71 TCGv_i32 next_icount;
ef04a846
MF		 72
73 unsigned cpenable;
dedc5eae
MF		 74} DisasContext;
75
1bcea73e 76static TCGv_env cpu_env;
dedc5eae
MF		 77static TCGv_i32 cpu_pc;
78static TCGv_i32 cpu_R[16];
dd519cbe 79static TCGv_i32 cpu_FR[16];
2af3da91
MF		 80static TCGv_i32 cpu_SR[256];
81static TCGv_i32 cpu_UR[256];
dedc5eae 82
022c62cb 83#include "exec/gen-icount.h"
2328826b 84
fe0bd475
MF		 85typedef struct XtensaReg {
86 const char *name;
87 uint64_t opt_bits;
53593e90
MF		 88 enum {
89 SR_R = 1,
90 SR_W = 2,
91 SR_X = 4,
92 SR_RW = 3,
93 SR_RWX = 7,
94 } access;
fe0bd475
MF		 95} XtensaReg;
96
53593e90 97#define XTENSA_REG_ACCESS(regname, opt, acc) { \
fe0bd475
MF		 98 .name = (regname), \
99 .opt_bits = XTENSA_OPTION_BIT(opt), \
53593e90 100 .access = (acc), \
fe0bd475
MF		 101 }
102
53593e90
MF		 103#define XTENSA_REG(regname, opt) XTENSA_REG_ACCESS(regname, opt, SR_RWX)
104
604e1f9c 105#define XTENSA_REG_BITS_ACCESS(regname, opt, acc) { \
fe0bd475
MF		 106 .name = (regname), \
107 .opt_bits = (opt), \
604e1f9c 108 .access = (acc), \
fe0bd475
MF		 109 }
110
604e1f9c
MF		 111#define XTENSA_REG_BITS(regname, opt) \
112 XTENSA_REG_BITS_ACCESS(regname, opt, SR_RWX)
113
fe0bd475
MF		 114static const XtensaReg sregnames[256] = {
115 [LBEG] = XTENSA_REG("LBEG", XTENSA_OPTION_LOOP),
116 [LEND] = XTENSA_REG("LEND", XTENSA_OPTION_LOOP),
117 [LCOUNT] = XTENSA_REG("LCOUNT", XTENSA_OPTION_LOOP),
118 [SAR] = XTENSA_REG_BITS("SAR", XTENSA_OPTION_ALL),
119 [BR] = XTENSA_REG("BR", XTENSA_OPTION_BOOLEAN),
120 [LITBASE] = XTENSA_REG("LITBASE", XTENSA_OPTION_EXTENDED_L32R),
121 [SCOMPARE1] = XTENSA_REG("SCOMPARE1", XTENSA_OPTION_CONDITIONAL_STORE),
122 [ACCLO] = XTENSA_REG("ACCLO", XTENSA_OPTION_MAC16),
123 [ACCHI] = XTENSA_REG("ACCHI", XTENSA_OPTION_MAC16),
124 [MR] = XTENSA_REG("MR0", XTENSA_OPTION_MAC16),
125 [MR + 1] = XTENSA_REG("MR1", XTENSA_OPTION_MAC16),
126 [MR + 2] = XTENSA_REG("MR2", XTENSA_OPTION_MAC16),
127 [MR + 3] = XTENSA_REG("MR3", XTENSA_OPTION_MAC16),
128 [WINDOW_BASE] = XTENSA_REG("WINDOW_BASE", XTENSA_OPTION_WINDOWED_REGISTER),
129 [WINDOW_START] = XTENSA_REG("WINDOW_START",
130 XTENSA_OPTION_WINDOWED_REGISTER),
131 [PTEVADDR] = XTENSA_REG("PTEVADDR", XTENSA_OPTION_MMU),
132 [RASID] = XTENSA_REG("RASID", XTENSA_OPTION_MMU),
133 [ITLBCFG] = XTENSA_REG("ITLBCFG", XTENSA_OPTION_MMU),
134 [DTLBCFG] = XTENSA_REG("DTLBCFG", XTENSA_OPTION_MMU),
135 [IBREAKENABLE] = XTENSA_REG("IBREAKENABLE", XTENSA_OPTION_DEBUG),
9e03ade4 136 [MEMCTL] = XTENSA_REG_BITS("MEMCTL", XTENSA_OPTION_ALL),
fe0bd475
MF		 137 [CACHEATTR] = XTENSA_REG("CACHEATTR", XTENSA_OPTION_CACHEATTR),
138 [ATOMCTL] = XTENSA_REG("ATOMCTL", XTENSA_OPTION_ATOMCTL),
139 [IBREAKA] = XTENSA_REG("IBREAKA0", XTENSA_OPTION_DEBUG),
140 [IBREAKA + 1] = XTENSA_REG("IBREAKA1", XTENSA_OPTION_DEBUG),
141 [DBREAKA] = XTENSA_REG("DBREAKA0", XTENSA_OPTION_DEBUG),
142 [DBREAKA + 1] = XTENSA_REG("DBREAKA1", XTENSA_OPTION_DEBUG),
143 [DBREAKC] = XTENSA_REG("DBREAKC0", XTENSA_OPTION_DEBUG),
144 [DBREAKC + 1] = XTENSA_REG("DBREAKC1", XTENSA_OPTION_DEBUG),
604e1f9c 145 [CONFIGID0] = XTENSA_REG_BITS_ACCESS("CONFIGID0", XTENSA_OPTION_ALL, SR_R),
fe0bd475
MF		 146 [EPC1] = XTENSA_REG("EPC1", XTENSA_OPTION_EXCEPTION),
147 [EPC1 + 1] = XTENSA_REG("EPC2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
148 [EPC1 + 2] = XTENSA_REG("EPC3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
149 [EPC1 + 3] = XTENSA_REG("EPC4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
150 [EPC1 + 4] = XTENSA_REG("EPC5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
151 [EPC1 + 5] = XTENSA_REG("EPC6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
152 [EPC1 + 6] = XTENSA_REG("EPC7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
153 [DEPC] = XTENSA_REG("DEPC", XTENSA_OPTION_EXCEPTION),
154 [EPS2] = XTENSA_REG("EPS2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
155 [EPS2 + 1] = XTENSA_REG("EPS3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
156 [EPS2 + 2] = XTENSA_REG("EPS4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
157 [EPS2 + 3] = XTENSA_REG("EPS5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
158 [EPS2 + 4] = XTENSA_REG("EPS6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
159 [EPS2 + 5] = XTENSA_REG("EPS7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
604e1f9c 160 [CONFIGID1] = XTENSA_REG_BITS_ACCESS("CONFIGID1", XTENSA_OPTION_ALL, SR_R),
fe0bd475
MF		 161 [EXCSAVE1] = XTENSA_REG("EXCSAVE1", XTENSA_OPTION_EXCEPTION),
162 [EXCSAVE1 + 1] = XTENSA_REG("EXCSAVE2",
163 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
164 [EXCSAVE1 + 2] = XTENSA_REG("EXCSAVE3",
165 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
166 [EXCSAVE1 + 3] = XTENSA_REG("EXCSAVE4",
167 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
168 [EXCSAVE1 + 4] = XTENSA_REG("EXCSAVE5",
169 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
170 [EXCSAVE1 + 5] = XTENSA_REG("EXCSAVE6",
171 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
172 [EXCSAVE1 + 6] = XTENSA_REG("EXCSAVE7",
173 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
174 [CPENABLE] = XTENSA_REG("CPENABLE", XTENSA_OPTION_COPROCESSOR),
53593e90
MF		 175 [INTSET] = XTENSA_REG_ACCESS("INTSET", XTENSA_OPTION_INTERRUPT, SR_RW),
176 [INTCLEAR] = XTENSA_REG_ACCESS("INTCLEAR", XTENSA_OPTION_INTERRUPT, SR_W),
fe0bd475
MF		 177 [INTENABLE] = XTENSA_REG("INTENABLE", XTENSA_OPTION_INTERRUPT),
178 [PS] = XTENSA_REG_BITS("PS", XTENSA_OPTION_ALL),
179 [VECBASE] = XTENSA_REG("VECBASE", XTENSA_OPTION_RELOCATABLE_VECTOR),
180 [EXCCAUSE] = XTENSA_REG("EXCCAUSE", XTENSA_OPTION_EXCEPTION),
53593e90 181 [DEBUGCAUSE] = XTENSA_REG_ACCESS("DEBUGCAUSE", XTENSA_OPTION_DEBUG, SR_R),
fe0bd475 182 [CCOUNT] = XTENSA_REG("CCOUNT", XTENSA_OPTION_TIMER_INTERRUPT),
53593e90 183 [PRID] = XTENSA_REG_ACCESS("PRID", XTENSA_OPTION_PROCESSOR_ID, SR_R),
fe0bd475
MF		 184 [ICOUNT] = XTENSA_REG("ICOUNT", XTENSA_OPTION_DEBUG),
185 [ICOUNTLEVEL] = XTENSA_REG("ICOUNTLEVEL", XTENSA_OPTION_DEBUG),
186 [EXCVADDR] = XTENSA_REG("EXCVADDR", XTENSA_OPTION_EXCEPTION),
187 [CCOMPARE] = XTENSA_REG("CCOMPARE0", XTENSA_OPTION_TIMER_INTERRUPT),
188 [CCOMPARE + 1] = XTENSA_REG("CCOMPARE1",
189 XTENSA_OPTION_TIMER_INTERRUPT),
190 [CCOMPARE + 2] = XTENSA_REG("CCOMPARE2",
191 XTENSA_OPTION_TIMER_INTERRUPT),
b7909d81
MF		 192 [MISC] = XTENSA_REG("MISC0", XTENSA_OPTION_MISC_SR),
193 [MISC + 1] = XTENSA_REG("MISC1", XTENSA_OPTION_MISC_SR),
194 [MISC + 2] = XTENSA_REG("MISC2", XTENSA_OPTION_MISC_SR),
195 [MISC + 3] = XTENSA_REG("MISC3", XTENSA_OPTION_MISC_SR),
2af3da91
MF		 196};
197
fe0bd475
MF		 198static const XtensaReg uregnames[256] = {
199 [THREADPTR] = XTENSA_REG("THREADPTR", XTENSA_OPTION_THREAD_POINTER),
200 [FCR] = XTENSA_REG("FCR", XTENSA_OPTION_FP_COPROCESSOR),
201 [FSR] = XTENSA_REG("FSR", XTENSA_OPTION_FP_COPROCESSOR),
2af3da91
MF		 202};
203
2328826b
MF		 204void xtensa_translate_init(void)
205{
dedc5eae
MF		 206 static const char * const regnames[] = {
207 "ar0", "ar1", "ar2", "ar3",
208 "ar4", "ar5", "ar6", "ar7",
209 "ar8", "ar9", "ar10", "ar11",
210 "ar12", "ar13", "ar14", "ar15",
211 };
dd519cbe
MF		 212 static const char * const fregnames[] = {
213 "f0", "f1", "f2", "f3",
214 "f4", "f5", "f6", "f7",
215 "f8", "f9", "f10", "f11",
216 "f12", "f13", "f14", "f15",
217 };
dedc5eae
MF		 218 int i;
219
220 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
7c255043 221 tcg_ctx.tcg_env = cpu_env;
e1ccc054 222 cpu_pc = tcg_global_mem_new_i32(cpu_env,
97129ac8 223 offsetof(CPUXtensaState, pc), "pc");
dedc5eae
MF		 224
225 for (i = 0; i < 16; i++) {
e1ccc054 226 cpu_R[i] = tcg_global_mem_new_i32(cpu_env,
97129ac8 227 offsetof(CPUXtensaState, regs[i]),
dedc5eae
MF		 228 regnames[i]);
229 }
2af3da91 230
dd519cbe 231 for (i = 0; i < 16; i++) {
e1ccc054 232 cpu_FR[i] = tcg_global_mem_new_i32(cpu_env,
ddd44279 233 offsetof(CPUXtensaState, fregs[i].f32[FP_F32_LOW]),
dd519cbe
MF		 234 fregnames[i]);
235 }
236
2af3da91 237 for (i = 0; i < 256; ++i) {
fe0bd475 238 if (sregnames[i].name) {
e1ccc054 239 cpu_SR[i] = tcg_global_mem_new_i32(cpu_env,
97129ac8 240 offsetof(CPUXtensaState, sregs[i]),
fe0bd475 241 sregnames[i].name);
2af3da91
MF		 242 }
243 }
244
245 for (i = 0; i < 256; ++i) {
fe0bd475 246 if (uregnames[i].name) {
e1ccc054 247 cpu_UR[i] = tcg_global_mem_new_i32(cpu_env,
97129ac8 248 offsetof(CPUXtensaState, uregs[i]),
fe0bd475 249 uregnames[i].name);
2af3da91
MF		 250 }
251 }
dedc5eae
MF		 252}
253
b67ea0cd
MF		 254static inline bool option_bits_enabled(DisasContext *dc, uint64_t opt)
255{
256 return xtensa_option_bits_enabled(dc->config, opt);
257}
258
dedc5eae
MF		 259static inline bool option_enabled(DisasContext *dc, int opt)
260{
261 return xtensa_option_enabled(dc->config, opt);
262}
263
6ad6dbf7
MF		 264static void init_litbase(DisasContext *dc)
265{
266 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
267 dc->litbase = tcg_temp_local_new_i32();
268 tcg_gen_andi_i32(dc->litbase, cpu_SR[LITBASE], 0xfffff000);
269 }
270}
271
272static void reset_litbase(DisasContext *dc)
273{
274 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
275 tcg_temp_free(dc->litbase);
276 }
277}
278
3580ecad
MF		 279static void init_sar_tracker(DisasContext *dc)
280{
281 dc->sar_5bit = false;
282 dc->sar_m32_5bit = false;
283 dc->sar_m32_allocated = false;
284}
285
286static void reset_sar_tracker(DisasContext *dc)
287{
288 if (dc->sar_m32_allocated) {
289 tcg_temp_free(dc->sar_m32);
290 }
291}
292
293static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa)
294{
295 tcg_gen_andi_i32(cpu_SR[SAR], sa, 0x1f);
296 if (dc->sar_m32_5bit) {
297 tcg_gen_discard_i32(dc->sar_m32);
298 }
299 dc->sar_5bit = true;
300 dc->sar_m32_5bit = false;
301}
302
303static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa)
304{
305 TCGv_i32 tmp = tcg_const_i32(32);
306 if (!dc->sar_m32_allocated) {
307 dc->sar_m32 = tcg_temp_local_new_i32();
308 dc->sar_m32_allocated = true;
309 }
310 tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f);
311 tcg_gen_sub_i32(cpu_SR[SAR], tmp, dc->sar_m32);
312 dc->sar_5bit = false;
313 dc->sar_m32_5bit = true;
314 tcg_temp_free(tmp);
315}
316
b994e91b 317static void gen_exception(DisasContext *dc, int excp)
dedc5eae
MF		 318{
319 TCGv_i32 tmp = tcg_const_i32(excp);
f492b82d 320 gen_helper_exception(cpu_env, tmp);
dedc5eae
MF		 321 tcg_temp_free(tmp);
322}
323
40643d7c
MF		 324static void gen_exception_cause(DisasContext *dc, uint32_t cause)
325{
326 TCGv_i32 tpc = tcg_const_i32(dc->pc);
327 TCGv_i32 tcause = tcg_const_i32(cause);
f492b82d 328 gen_helper_exception_cause(cpu_env, tpc, tcause);
40643d7c
MF		 329 tcg_temp_free(tpc);
330 tcg_temp_free(tcause);
6b814719
MF		 331 if (cause == ILLEGAL_INSTRUCTION_CAUSE ||
332 cause == SYSCALL_CAUSE) {
333 dc->is_jmp = DISAS_UPDATE;
334 }
40643d7c
MF		 335}
336
5b4e481b
MF		 337static void gen_exception_cause_vaddr(DisasContext *dc, uint32_t cause,
338 TCGv_i32 vaddr)
339{
340 TCGv_i32 tpc = tcg_const_i32(dc->pc);
341 TCGv_i32 tcause = tcg_const_i32(cause);
f492b82d 342 gen_helper_exception_cause_vaddr(cpu_env, tpc, tcause, vaddr);
5b4e481b
MF		 343 tcg_temp_free(tpc);
344 tcg_temp_free(tcause);
345}
346
e61dc8f7
MF		 347static void gen_debug_exception(DisasContext *dc, uint32_t cause)
348{
349 TCGv_i32 tpc = tcg_const_i32(dc->pc);
350 TCGv_i32 tcause = tcg_const_i32(cause);
f492b82d 351 gen_helper_debug_exception(cpu_env, tpc, tcause);
e61dc8f7
MF		 352 tcg_temp_free(tpc);
353 tcg_temp_free(tcause);
354 if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) {
355 dc->is_jmp = DISAS_UPDATE;
356 }
357}
358
97e89ee9 359static bool gen_check_privilege(DisasContext *dc)
40643d7c
MF		 360{
361 if (dc->cring) {
362 gen_exception_cause(dc, PRIVILEGED_CAUSE);
6b814719 363 dc->is_jmp = DISAS_UPDATE;
97e89ee9 364 return false;
40643d7c 365 }
97e89ee9 366 return true;
40643d7c
MF		 367}
368
97e89ee9 369static bool gen_check_cpenable(DisasContext *dc, unsigned cp)
ef04a846
MF		 370{
371 if (option_enabled(dc, XTENSA_OPTION_COPROCESSOR) &&
372 !(dc->cpenable & (1 << cp))) {
373 gen_exception_cause(dc, COPROCESSOR0_DISABLED + cp);
374 dc->is_jmp = DISAS_UPDATE;
97e89ee9 375 return false;
ef04a846 376 }
97e89ee9 377 return true;
ef04a846
MF		 378}
379
dedc5eae
MF		 380static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
381{
382 tcg_gen_mov_i32(cpu_pc, dest);
35b5c044
MF		 383 if (dc->icount) {
384 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount);
385 }
dedc5eae 386 if (dc->singlestep_enabled) {
b994e91b 387 gen_exception(dc, EXCP_DEBUG);
dedc5eae
MF		 388 } else {
389 if (slot >= 0) {
390 tcg_gen_goto_tb(slot);
8cfd0495 391 tcg_gen_exit_tb((uintptr_t)dc->tb + slot);
dedc5eae
MF		 392 } else {
393 tcg_gen_exit_tb(0);
394 }
395 }
396 dc->is_jmp = DISAS_UPDATE;
397}
398
67882fd1
MF		 399static void gen_jump(DisasContext *dc, TCGv dest)
400{
401 gen_jump_slot(dc, dest, -1);
402}
403
dedc5eae
MF		 404static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)
405{
406 TCGv_i32 tmp = tcg_const_i32(dest);
90aa39a1 407#ifndef CONFIG_USER_ONLY
433d33c5 408 if (((dc->tb->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
dedc5eae
MF		 409 slot = -1;
410 }
90aa39a1 411#endif
dedc5eae
MF		 412 gen_jump_slot(dc, tmp, slot);
413 tcg_temp_free(tmp);
414}
415
553e44f9
MF		 416static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest,
417 int slot)
418{
419 TCGv_i32 tcallinc = tcg_const_i32(callinc);
420
421 tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS],
422 tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN);
423 tcg_temp_free(tcallinc);
424 tcg_gen_movi_i32(cpu_R[callinc << 2],
425 (callinc << 30) | (dc->next_pc & 0x3fffffff));
426 gen_jump_slot(dc, dest, slot);
427}
428
429static void gen_callw(DisasContext *dc, int callinc, TCGv_i32 dest)
430{
431 gen_callw_slot(dc, callinc, dest, -1);
432}
433
434static void gen_callwi(DisasContext *dc, int callinc, uint32_t dest, int slot)
435{
436 TCGv_i32 tmp = tcg_const_i32(dest);
90aa39a1 437#ifndef CONFIG_USER_ONLY
433d33c5 438 if (((dc->tb->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
553e44f9
MF		 439 slot = -1;
440 }
90aa39a1 441#endif
553e44f9
MF		 442 gen_callw_slot(dc, callinc, tmp, slot);
443 tcg_temp_free(tmp);
444}
445
797d780b
MF		 446static bool gen_check_loop_end(DisasContext *dc, int slot)
447{
448 if (option_enabled(dc, XTENSA_OPTION_LOOP) &&
449 !(dc->tb->flags & XTENSA_TBFLAG_EXCM) &&
450 dc->next_pc == dc->lend) {
42a268c2 451 TCGLabel *label = gen_new_label();
797d780b
MF		 452
453 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label);
454 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1);
455 gen_jumpi(dc, dc->lbeg, slot);
456 gen_set_label(label);
457 gen_jumpi(dc, dc->next_pc, -1);
458 return true;
459 }
460 return false;
461}
462
463static void gen_jumpi_check_loop_end(DisasContext *dc, int slot)
464{
465 if (!gen_check_loop_end(dc, slot)) {
466 gen_jumpi(dc, dc->next_pc, slot);
467 }
468}
469
bd57fb91
MF		 470static void gen_brcond(DisasContext *dc, TCGCond cond,
471 TCGv_i32 t0, TCGv_i32 t1, uint32_t offset)
472{
42a268c2 473 TCGLabel *label = gen_new_label();
bd57fb91
MF		 474
475 tcg_gen_brcond_i32(cond, t0, t1, label);
797d780b 476 gen_jumpi_check_loop_end(dc, 0);
bd57fb91
MF		 477 gen_set_label(label);
478 gen_jumpi(dc, dc->pc + offset, 1);
479}
480
481static void gen_brcondi(DisasContext *dc, TCGCond cond,
482 TCGv_i32 t0, uint32_t t1, uint32_t offset)
483{
484 TCGv_i32 tmp = tcg_const_i32(t1);
485 gen_brcond(dc, cond, t0, tmp, offset);
486 tcg_temp_free(tmp);
487}
488
0857a06e 489static bool gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access)
fe0bd475
MF		 490{
491 if (!xtensa_option_bits_enabled(dc->config, sregnames[sr].opt_bits)) {
492 if (sregnames[sr].name) {
c30f0d18 493 qemu_log_mask(LOG_GUEST_ERROR, "SR %s is not configured\n", sregnames[sr].name);
fe0bd475 494 } else {
c30f0d18 495 qemu_log_mask(LOG_UNIMP, "SR %d is not implemented\n", sr);
fe0bd475
MF		 496 }
497 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
0857a06e 498 return false;
53593e90
MF		 499 } else if (!(sregnames[sr].access & access)) {
500 static const char * const access_text[] = {
501 [SR_R] = "rsr",
502 [SR_W] = "wsr",
503 [SR_X] = "xsr",
504 };
505 assert(access < ARRAY_SIZE(access_text) && access_text[access]);
c30f0d18
PB		 506 qemu_log_mask(LOG_GUEST_ERROR, "SR %s is not available for %s\n", sregnames[sr].name,
507 access_text[access]);
53593e90 508 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
0857a06e 509 return false;
fe0bd475 510 }
0857a06e 511 return true;
fe0bd475
MF		 512}
513
d2132510 514static bool gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr)
b994e91b 515{
d2132510
MF		 516 if (dc->tb->cflags & CF_USE_ICOUNT) {
517 gen_io_start();
518 }
59a71f75 519 gen_helper_update_ccount(cpu_env);
b994e91b 520 tcg_gen_mov_i32(d, cpu_SR[sr]);
d2132510
MF		 521 if (dc->tb->cflags & CF_USE_ICOUNT) {
522 gen_io_end();
523 return true;
524 }
525 return false;
b994e91b
MF		 526}
527
d2132510 528static bool gen_rsr_ptevaddr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
b67ea0cd
MF		 529{
530 tcg_gen_shri_i32(d, cpu_SR[EXCVADDR], 10);
531 tcg_gen_or_i32(d, d, cpu_SR[sr]);
532 tcg_gen_andi_i32(d, d, 0xfffffffc);
d2132510 533 return false;
b67ea0cd
MF		 534}
535
d2132510 536static bool gen_rsr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
b8132eff 537{
d2132510 538 static bool (* const rsr_handler[256])(DisasContext *dc,
b8132eff 539 TCGv_i32 d, uint32_t sr) = {
b994e91b 540 [CCOUNT] = gen_rsr_ccount,
59a71f75 541 [INTSET] = gen_rsr_ccount,
b67ea0cd 542 [PTEVADDR] = gen_rsr_ptevaddr,
b8132eff
MF		 543 };
544
fe0bd475 545 if (rsr_handler[sr]) {
d2132510 546 return rsr_handler[sr](dc, d, sr);
b8132eff 547 } else {
fe0bd475 548 tcg_gen_mov_i32(d, cpu_SR[sr]);
d2132510 549 return false;
b8132eff
MF		 550 }
551}
552
d2132510 553static bool gen_wsr_lbeg(DisasContext *dc, uint32_t sr, TCGv_i32 s)
797d780b 554{
f492b82d 555 gen_helper_wsr_lbeg(cpu_env, s);
3d0be8a5 556 gen_jumpi_check_loop_end(dc, 0);
d2132510 557 return false;
797d780b
MF		 558}
559
d2132510 560static bool gen_wsr_lend(DisasContext *dc, uint32_t sr, TCGv_i32 s)
797d780b 561{
f492b82d 562 gen_helper_wsr_lend(cpu_env, s);
3d0be8a5 563 gen_jumpi_check_loop_end(dc, 0);
d2132510 564 return false;
797d780b
MF		 565}
566
d2132510 567static bool gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s)
3580ecad
MF		 568{
569 tcg_gen_andi_i32(cpu_SR[sr], s, 0x3f);
570 if (dc->sar_m32_5bit) {
571 tcg_gen_discard_i32(dc->sar_m32);
572 }
573 dc->sar_5bit = false;
574 dc->sar_m32_5bit = false;
d2132510 575 return false;
3580ecad
MF		 576}
577
d2132510 578static bool gen_wsr_br(DisasContext *dc, uint32_t sr, TCGv_i32 s)
4dd85b6b
MF		 579{
580 tcg_gen_andi_i32(cpu_SR[sr], s, 0xffff);
d2132510 581 return false;
4dd85b6b
MF		 582}
583
d2132510 584static bool gen_wsr_litbase(DisasContext *dc, uint32_t sr, TCGv_i32 s)
6ad6dbf7
MF		 585{
586 tcg_gen_andi_i32(cpu_SR[sr], s, 0xfffff001);
587 /* This can change tb->flags, so exit tb */
588 gen_jumpi_check_loop_end(dc, -1);
d2132510 589 return true;
6ad6dbf7
MF		 590}
591
d2132510 592static bool gen_wsr_acchi(DisasContext *dc, uint32_t sr, TCGv_i32 s)
6825b6c3
MF		 593{
594 tcg_gen_ext8s_i32(cpu_SR[sr], s);
d2132510 595 return false;
6825b6c3
MF		 596}
597
d2132510 598static bool gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v)
553e44f9 599{
f492b82d 600 gen_helper_wsr_windowbase(cpu_env, v);
2db59a76
MF		 601 /* This can change tb->flags, so exit tb */
602 gen_jumpi_check_loop_end(dc, -1);
d2132510 603 return true;
772177c1
MF		 604}
605
d2132510 606static bool gen_wsr_windowstart(DisasContext *dc, uint32_t sr, TCGv_i32 v)
772177c1 607{
53a72dfd 608 tcg_gen_andi_i32(cpu_SR[sr], v, (1 << dc->config->nareg / 4) - 1);
2db59a76
MF		 609 /* This can change tb->flags, so exit tb */
610 gen_jumpi_check_loop_end(dc, -1);
d2132510 611 return true;
553e44f9
MF		 612}
613
d2132510 614static bool gen_wsr_ptevaddr(DisasContext *dc, uint32_t sr, TCGv_i32 v)
b67ea0cd
MF		 615{
616 tcg_gen_andi_i32(cpu_SR[sr], v, 0xffc00000);
d2132510 617 return false;
b67ea0cd
MF		 618}
619
d2132510 620static bool gen_wsr_rasid(DisasContext *dc, uint32_t sr, TCGv_i32 v)
b67ea0cd 621{
f492b82d 622 gen_helper_wsr_rasid(cpu_env, v);
b67ea0cd
MF		 623 /* This can change tb->flags, so exit tb */
624 gen_jumpi_check_loop_end(dc, -1);
d2132510 625 return true;
b67ea0cd
MF		 626}
627
d2132510 628static bool gen_wsr_tlbcfg(DisasContext *dc, uint32_t sr, TCGv_i32 v)
b67ea0cd
MF		 629{
630 tcg_gen_andi_i32(cpu_SR[sr], v, 0x01130000);
d2132510 631 return false;
b67ea0cd
MF		 632}
633
d2132510 634static bool gen_wsr_ibreakenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
e61dc8f7 635{
f492b82d 636 gen_helper_wsr_ibreakenable(cpu_env, v);
e61dc8f7 637 gen_jumpi_check_loop_end(dc, 0);
d2132510 638 return true;
e61dc8f7
MF		 639}
640
9e03ade4
MF		 641static bool gen_wsr_memctl(DisasContext *dc, uint32_t sr, TCGv_i32 v)
642{
643 gen_helper_wsr_memctl(cpu_env, v);
644 return false;
645}
646
d2132510 647static bool gen_wsr_atomctl(DisasContext *dc, uint32_t sr, TCGv_i32 v)
fcc803d1
MF		 648{
649 tcg_gen_andi_i32(cpu_SR[sr], v, 0x3f);
d2132510 650 return false;
fcc803d1
MF		 651}
652
d2132510 653static bool gen_wsr_ibreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
e61dc8f7
MF		 654{
655 unsigned id = sr - IBREAKA;
656
657 if (id < dc->config->nibreak) {
658 TCGv_i32 tmp = tcg_const_i32(id);
f492b82d 659 gen_helper_wsr_ibreaka(cpu_env, tmp, v);
e61dc8f7
MF		 660 tcg_temp_free(tmp);
661 gen_jumpi_check_loop_end(dc, 0);
d2132510 662 return true;
e61dc8f7 663 }
d2132510 664 return false;
e61dc8f7
MF		 665}
666
d2132510 667static bool gen_wsr_dbreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
f14c4b5f
MF		 668{
669 unsigned id = sr - DBREAKA;
670
671 if (id < dc->config->ndbreak) {
672 TCGv_i32 tmp = tcg_const_i32(id);
f492b82d 673 gen_helper_wsr_dbreaka(cpu_env, tmp, v);
f14c4b5f
MF		 674 tcg_temp_free(tmp);
675 }
d2132510 676 return false;
f14c4b5f
MF		 677}
678
d2132510 679static bool gen_wsr_dbreakc(DisasContext *dc, uint32_t sr, TCGv_i32 v)
f14c4b5f
MF		 680{
681 unsigned id = sr - DBREAKC;
682
683 if (id < dc->config->ndbreak) {
684 TCGv_i32 tmp = tcg_const_i32(id);
f492b82d 685 gen_helper_wsr_dbreakc(cpu_env, tmp, v);
f14c4b5f
MF		 686 tcg_temp_free(tmp);
687 }
d2132510 688 return false;
f14c4b5f
MF		 689}
690
d2132510 691static bool gen_wsr_cpenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
ef04a846
MF		 692{
693 tcg_gen_andi_i32(cpu_SR[sr], v, 0xff);
694 /* This can change tb->flags, so exit tb */
695 gen_jumpi_check_loop_end(dc, -1);
d2132510 696 return true;
ef04a846
MF		 697}
698
d2132510
MF		 699static void gen_check_interrupts(DisasContext *dc)
700{
701 if (dc->tb->cflags & CF_USE_ICOUNT) {
702 gen_io_start();
703 }
704 gen_helper_check_interrupts(cpu_env);
705 if (dc->tb->cflags & CF_USE_ICOUNT) {
706 gen_io_end();
707 }
708}
709
710static bool gen_wsr_intset(DisasContext *dc, uint32_t sr, TCGv_i32 v)
b994e91b
MF		 711{
712 tcg_gen_andi_i32(cpu_SR[sr], v,
713 dc->config->inttype_mask[INTTYPE_SOFTWARE]);
d2132510 714 gen_check_interrupts(dc);
b994e91b 715 gen_jumpi_check_loop_end(dc, 0);
d2132510 716 return true;
b994e91b
MF		 717}
718
d2132510 719static bool gen_wsr_intclear(DisasContext *dc, uint32_t sr, TCGv_i32 v)
b994e91b
MF		 720{
721 TCGv_i32 tmp = tcg_temp_new_i32();
722
723 tcg_gen_andi_i32(tmp, v,
724 dc->config->inttype_mask[INTTYPE_EDGE] |
725 dc->config->inttype_mask[INTTYPE_NMI] |
726 dc->config->inttype_mask[INTTYPE_SOFTWARE]);
727 tcg_gen_andc_i32(cpu_SR[INTSET], cpu_SR[INTSET], tmp);
728 tcg_temp_free(tmp);
d2132510
MF		 729 gen_check_interrupts(dc);
730 gen_jumpi_check_loop_end(dc, 0);
731 return true;
b994e91b
MF		 732}
733
d2132510 734static bool gen_wsr_intenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
b994e91b
MF		 735{
736 tcg_gen_mov_i32(cpu_SR[sr], v);
d2132510 737 gen_check_interrupts(dc);
b994e91b 738 gen_jumpi_check_loop_end(dc, 0);
d2132510 739 return true;
b994e91b
MF		 740}
741
d2132510 742static bool gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v)
f0a548b9
MF		 743{
744 uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB |
745 PS_UM | PS_EXCM | PS_INTLEVEL;
746
747 if (option_enabled(dc, XTENSA_OPTION_MMU)) {
748 mask |= PS_RING;
749 }
750 tcg_gen_andi_i32(cpu_SR[sr], v, mask);
d2132510 751 gen_check_interrupts(dc);
b994e91b 752 /* This can change mmu index and tb->flags, so exit tb */
797d780b 753 gen_jumpi_check_loop_end(dc, -1);
d2132510 754 return true;
f0a548b9
MF		 755}
756
d2132510 757static bool gen_wsr_ccount(DisasContext *dc, uint32_t sr, TCGv_i32 v)
59a71f75 758{
d2132510
MF		 759 if (dc->tb->cflags & CF_USE_ICOUNT) {
760 gen_io_start();
761 }
59a71f75 762 gen_helper_wsr_ccount(cpu_env, v);
d2132510
MF		 763 if (dc->tb->cflags & CF_USE_ICOUNT) {
764 gen_io_end();
765 gen_jumpi_check_loop_end(dc, 0);
766 return true;
767 }
768 return false;
59a71f75
MF		 769}
770
d2132510 771static bool gen_wsr_icount(DisasContext *dc, uint32_t sr, TCGv_i32 v)
35b5c044
MF		 772{
773 if (dc->icount) {
774 tcg_gen_mov_i32(dc->next_icount, v);
775 } else {
776 tcg_gen_mov_i32(cpu_SR[sr], v);
777 }
d2132510 778 return false;
35b5c044
MF		 779}
780
d2132510 781static bool gen_wsr_icountlevel(DisasContext *dc, uint32_t sr, TCGv_i32 v)
35b5c044
MF		 782{
783 tcg_gen_andi_i32(cpu_SR[sr], v, 0xf);
784 /* This can change tb->flags, so exit tb */
785 gen_jumpi_check_loop_end(dc, -1);
d2132510 786 return true;
35b5c044
MF		 787}
788
d2132510 789static bool gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v)
b994e91b
MF		 790{
791 uint32_t id = sr - CCOMPARE;
d2132510
MF		 792 bool ret = false;
793
b994e91b
MF		 794 if (id < dc->config->nccompare) {
795 uint32_t int_bit = 1 << dc->config->timerint[id];
59a71f75
MF		 796 TCGv_i32 tmp = tcg_const_i32(id);
797
b994e91b
MF		 798 tcg_gen_mov_i32(cpu_SR[sr], v);
799 tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit);
d2132510
MF		 800 if (dc->tb->cflags & CF_USE_ICOUNT) {
801 gen_io_start();
802 }
59a71f75 803 gen_helper_update_ccompare(cpu_env, tmp);
d2132510
MF		 804 if (dc->tb->cflags & CF_USE_ICOUNT) {
805 gen_io_end();
806 gen_jumpi_check_loop_end(dc, 0);
807 ret = true;
808 }
59a71f75 809 tcg_temp_free(tmp);
b994e91b 810 }
d2132510 811 return ret;
b994e91b
MF		 812}
813
d2132510 814static bool gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s)
b8132eff 815{
d2132510 816 static bool (* const wsr_handler[256])(DisasContext *dc,
b8132eff 817 uint32_t sr, TCGv_i32 v) = {
797d780b
MF		 818 [LBEG] = gen_wsr_lbeg,
819 [LEND] = gen_wsr_lend,
3580ecad 820 [SAR] = gen_wsr_sar,
4dd85b6b 821 [BR] = gen_wsr_br,
6ad6dbf7 822 [LITBASE] = gen_wsr_litbase,
6825b6c3 823 [ACCHI] = gen_wsr_acchi,
553e44f9 824 [WINDOW_BASE] = gen_wsr_windowbase,
772177c1 825 [WINDOW_START] = gen_wsr_windowstart,
b67ea0cd
MF		 826 [PTEVADDR] = gen_wsr_ptevaddr,
827 [RASID] = gen_wsr_rasid,
828 [ITLBCFG] = gen_wsr_tlbcfg,
829 [DTLBCFG] = gen_wsr_tlbcfg,
e61dc8f7 830 [IBREAKENABLE] = gen_wsr_ibreakenable,
9e03ade4 831 [MEMCTL] = gen_wsr_memctl,
fcc803d1 832 [ATOMCTL] = gen_wsr_atomctl,
e61dc8f7
MF		 833 [IBREAKA] = gen_wsr_ibreaka,
834 [IBREAKA + 1] = gen_wsr_ibreaka,
f14c4b5f
MF		 835 [DBREAKA] = gen_wsr_dbreaka,
836 [DBREAKA + 1] = gen_wsr_dbreaka,
837 [DBREAKC] = gen_wsr_dbreakc,
838 [DBREAKC + 1] = gen_wsr_dbreakc,
ef04a846 839 [CPENABLE] = gen_wsr_cpenable,
b994e91b
MF		 840 [INTSET] = gen_wsr_intset,
841 [INTCLEAR] = gen_wsr_intclear,
842 [INTENABLE] = gen_wsr_intenable,
f0a548b9 843 [PS] = gen_wsr_ps,
59a71f75 844 [CCOUNT] = gen_wsr_ccount,
35b5c044
MF		 845 [ICOUNT] = gen_wsr_icount,
846 [ICOUNTLEVEL] = gen_wsr_icountlevel,
b994e91b
MF		 847 [CCOMPARE] = gen_wsr_ccompare,
848 [CCOMPARE + 1] = gen_wsr_ccompare,
849 [CCOMPARE + 2] = gen_wsr_ccompare,
b8132eff
MF		 850 };
851
fe0bd475 852 if (wsr_handler[sr]) {
d2132510 853 return wsr_handler[sr](dc, sr, s);
b8132eff 854 } else {
fe0bd475 855 tcg_gen_mov_i32(cpu_SR[sr], s);
d2132510 856 return false;
b8132eff
MF		 857 }
858}
859
dd519cbe
MF		 860static void gen_wur(uint32_t ur, TCGv_i32 s)
861{
862 switch (ur) {
863 case FCR:
864 gen_helper_wur_fcr(cpu_env, s);
865 break;
866
867 case FSR:
868 tcg_gen_andi_i32(cpu_UR[ur], s, 0xffffff80);
869 break;
870
871 default:
872 tcg_gen_mov_i32(cpu_UR[ur], s);
873 break;
874 }
875}
876
5b4e481b
MF		 877static void gen_load_store_alignment(DisasContext *dc, int shift,
878 TCGv_i32 addr, bool no_hw_alignment)
879{
880 if (!option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) {
881 tcg_gen_andi_i32(addr, addr, ~0 << shift);
882 } else if (option_enabled(dc, XTENSA_OPTION_HW_ALIGNMENT) &&
883 no_hw_alignment) {
42a268c2 884 TCGLabel *label = gen_new_label();
5b4e481b
MF		 885 TCGv_i32 tmp = tcg_temp_new_i32();
886 tcg_gen_andi_i32(tmp, addr, ~(~0 << shift));
887 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
888 gen_exception_cause_vaddr(dc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
889 gen_set_label(label);
890 tcg_temp_free(tmp);
891 }
892}
893
b994e91b
MF		 894static void gen_waiti(DisasContext *dc, uint32_t imm4)
895{
896 TCGv_i32 pc = tcg_const_i32(dc->next_pc);
897 TCGv_i32 intlevel = tcg_const_i32(imm4);
d2132510
MF		 898
899 if (dc->tb->cflags & CF_USE_ICOUNT) {
900 gen_io_start();
901 }
f492b82d 902 gen_helper_waiti(cpu_env, pc, intlevel);
d2132510
MF		 903 if (dc->tb->cflags & CF_USE_ICOUNT) {
904 gen_io_end();
905 }
b994e91b
MF		 906 tcg_temp_free(pc);
907 tcg_temp_free(intlevel);
d2132510 908 gen_jumpi_check_loop_end(dc, 0);
b994e91b
MF		 909}
910
97e89ee9 911static bool gen_window_check1(DisasContext *dc, unsigned r1)
772177c1 912{
2db59a76
MF		 913 if (r1 / 4 > dc->window) {
914 TCGv_i32 pc = tcg_const_i32(dc->pc);
915 TCGv_i32 w = tcg_const_i32(r1 / 4);
908c67fc 916
2db59a76
MF		 917 gen_helper_window_check(cpu_env, pc, w);
918 dc->is_jmp = DISAS_UPDATE;
97e89ee9 919 return false;
772177c1 920 }
97e89ee9 921 return true;
772177c1
MF		 922}
923
97e89ee9 924static bool gen_window_check2(DisasContext *dc, unsigned r1, unsigned r2)
772177c1 925{
97e89ee9 926 return gen_window_check1(dc, r1 > r2 ? r1 : r2);
772177c1
MF		 927}
928
97e89ee9 929static bool gen_window_check3(DisasContext *dc, unsigned r1, unsigned r2,
772177c1
MF		 930 unsigned r3)
931{
97e89ee9 932 return gen_window_check2(dc, r1, r2 > r3 ? r2 : r3);
772177c1
MF		 933}
934
6825b6c3
MF		 935static TCGv_i32 gen_mac16_m(TCGv_i32 v, bool hi, bool is_unsigned)
936{
937 TCGv_i32 m = tcg_temp_new_i32();
938
939 if (hi) {
940 (is_unsigned ? tcg_gen_shri_i32 : tcg_gen_sari_i32)(m, v, 16);
941 } else {
942 (is_unsigned ? tcg_gen_ext16u_i32 : tcg_gen_ext16s_i32)(m, v);
943 }
944 return m;
945}
946
01673a34
MF		 947static inline unsigned xtensa_op0_insn_len(unsigned op0)
948{
949 return op0 >= 8 ? 2 : 3;
950}
951
0c4fabea 952static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
dedc5eae 953{
b67ea0cd
MF		 954#define HAS_OPTION_BITS(opt) do { \
955 if (!option_bits_enabled(dc, opt)) { \
c30f0d18
PB		 956 qemu_log_mask(LOG_GUEST_ERROR, "Option is not enabled %s:%d\n", \
957 __FILE__, __LINE__); \
dedc5eae
MF		 958 goto invalid_opcode; \
959 } \
960 } while (0)
961
b67ea0cd
MF		 962#define HAS_OPTION(opt) HAS_OPTION_BITS(XTENSA_OPTION_BIT(opt))
963
c30f0d18 964#define TBD() qemu_log_mask(LOG_UNIMP, "TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__)
91a5bb76 965#define RESERVED() do { \
c30f0d18
PB		 966 qemu_log_mask(LOG_GUEST_ERROR, "RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \
967 dc->pc, b0, b1, b2, __FILE__, __LINE__); \
91a5bb76
MF		 968 goto invalid_opcode; \
969 } while (0)
970
971
dedc5eae
MF		 972#ifdef TARGET_WORDS_BIGENDIAN
973#define OP0 (((b0) & 0xf0) >> 4)
974#define OP1 (((b2) & 0xf0) >> 4)
975#define OP2 ((b2) & 0xf)
976#define RRR_R ((b1) & 0xf)
977#define RRR_S (((b1) & 0xf0) >> 4)
978#define RRR_T ((b0) & 0xf)
979#else
980#define OP0 (((b0) & 0xf))
981#define OP1 (((b2) & 0xf))
982#define OP2 (((b2) & 0xf0) >> 4)
983#define RRR_R (((b1) & 0xf0) >> 4)
984#define RRR_S (((b1) & 0xf))
985#define RRR_T (((b0) & 0xf0) >> 4)
986#endif
6825b6c3
MF		 987#define RRR_X ((RRR_R & 0x4) >> 2)
988#define RRR_Y ((RRR_T & 0x4) >> 2)
989#define RRR_W (RRR_R & 0x3)
dedc5eae
MF		 990
991#define RRRN_R RRR_R
992#define RRRN_S RRR_S
993#define RRRN_T RRR_T
994
65026682
MF		 995#define RRI4_R RRR_R
996#define RRI4_S RRR_S
997#define RRI4_T RRR_T
998#ifdef TARGET_WORDS_BIGENDIAN
999#define RRI4_IMM4 ((b2) & 0xf)
1000#else
1001#define RRI4_IMM4 (((b2) & 0xf0) >> 4)
1002#endif
1003
dedc5eae
MF		 1004#define RRI8_R RRR_R
1005#define RRI8_S RRR_S
1006#define RRI8_T RRR_T
1007#define RRI8_IMM8 (b2)
1008#define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8)
1009
1010#ifdef TARGET_WORDS_BIGENDIAN
1011#define RI16_IMM16 (((b1) << 8) | (b2))
1012#else
1013#define RI16_IMM16 (((b2) << 8) | (b1))
1014#endif
1015
1016#ifdef TARGET_WORDS_BIGENDIAN
1017#define CALL_N (((b0) & 0xc) >> 2)
1018#define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2))
1019#else
1020#define CALL_N (((b0) & 0x30) >> 4)
1021#define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10))
1022#endif
1023#define CALL_OFFSET_SE \
1024 (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET)
1025
1026#define CALLX_N CALL_N
1027#ifdef TARGET_WORDS_BIGENDIAN
1028#define CALLX_M ((b0) & 0x3)
1029#else
1030#define CALLX_M (((b0) & 0xc0) >> 6)
1031#endif
1032#define CALLX_S RRR_S
1033
1034#define BRI12_M CALLX_M
1035#define BRI12_S RRR_S
1036#ifdef TARGET_WORDS_BIGENDIAN
1037#define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2))
1038#else
1039#define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4))
1040#endif
1041#define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12)
1042
1043#define BRI8_M BRI12_M
1044#define BRI8_R RRI8_R
1045#define BRI8_S RRI8_S
1046#define BRI8_IMM8 RRI8_IMM8
1047#define BRI8_IMM8_SE RRI8_IMM8_SE
1048
1049#define RSR_SR (b1)
1050
0c4fabea
BS		 1051 uint8_t b0 = cpu_ldub_code(env, dc->pc);
1052 uint8_t b1 = cpu_ldub_code(env, dc->pc + 1);
a044ec2a 1053 uint8_t b2 = 0;
01673a34 1054 unsigned len = xtensa_op0_insn_len(OP0);
dedc5eae 1055
bd57fb91
MF		 1056 static const uint32_t B4CONST[] = {
1057 0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
1058 };
1059
1060 static const uint32_t B4CONSTU[] = {
1061 32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
1062 };
1063
01673a34
MF		 1064 switch (len) {
1065 case 2:
dedc5eae 1066 HAS_OPTION(XTENSA_OPTION_CODE_DENSITY);
01673a34
MF		 1067 break;
1068
1069 case 3:
0c4fabea 1070 b2 = cpu_ldub_code(env, dc->pc + 2);
01673a34
MF		 1071 break;
1072
1073 default:
1074 RESERVED();
dedc5eae 1075 }
01673a34 1076 dc->next_pc = dc->pc + len;
dedc5eae
MF		 1077
1078 switch (OP0) {
1079 case 0: /*QRST*/
1080 switch (OP1) {
1081 case 0: /*RST0*/
1082 switch (OP2) {
1083 case 0: /*ST0*/
1084 if ((RRR_R & 0xc) == 0x8) {
1085 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
1086 }
1087
1088 switch (RRR_R) {
1089 case 0: /*SNM0*/
5da4a6a8
MF		 1090 switch (CALLX_M) {
1091 case 0: /*ILL*/
40643d7c 1092 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
5da4a6a8
MF		 1093 break;
1094
1095 case 1: /*reserved*/
91a5bb76 1096 RESERVED();
5da4a6a8
MF		 1097 break;
1098
1099 case 2: /*JR*/
1100 switch (CALLX_N) {
1101 case 0: /*RET*/
1102 case 2: /*JX*/
97e89ee9
MF		 1103 if (gen_window_check1(dc, CALLX_S)) {
1104 gen_jump(dc, cpu_R[CALLX_S]);
1105 }
5da4a6a8
MF		 1106 break;
1107
1108 case 1: /*RETWw*/
1109 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 1110 {
1111 TCGv_i32 tmp = tcg_const_i32(dc->pc);
f492b82d 1112 gen_helper_retw(tmp, cpu_env, tmp);
553e44f9
MF		 1113 gen_jump(dc, tmp);
1114 tcg_temp_free(tmp);
1115 }
5da4a6a8
MF		 1116 break;
1117
1118 case 3: /*reserved*/
91a5bb76 1119 RESERVED();
5da4a6a8
MF		 1120 break;
1121 }
1122 break;
1123
1124 case 3: /*CALLX*/
97e89ee9
MF		 1125 if (!gen_window_check2(dc, CALLX_S, CALLX_N << 2)) {
1126 break;
1127 }
5da4a6a8
MF		 1128 switch (CALLX_N) {
1129 case 0: /*CALLX0*/
1130 {
1131 TCGv_i32 tmp = tcg_temp_new_i32();
1132 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
1133 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
1134 gen_jump(dc, tmp);
1135 tcg_temp_free(tmp);
1136 }
1137 break;
1138
1139 case 1: /*CALLX4w*/
1140 case 2: /*CALLX8w*/
1141 case 3: /*CALLX12w*/
1142 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 1143 {
1144 TCGv_i32 tmp = tcg_temp_new_i32();
1145
1146 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
1147 gen_callw(dc, CALLX_N, tmp);
1148 tcg_temp_free(tmp);
1149 }
5da4a6a8
MF		 1150 break;
1151 }
1152 break;
1153 }
dedc5eae
MF		 1154 break;
1155
1156 case 1: /*MOVSPw*/
1157 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
97e89ee9 1158 if (gen_window_check2(dc, RRR_T, RRR_S)) {
553e44f9 1159 TCGv_i32 pc = tcg_const_i32(dc->pc);
f492b82d 1160 gen_helper_movsp(cpu_env, pc);
553e44f9
MF		 1161 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_R[RRR_S]);
1162 tcg_temp_free(pc);
1163 }
dedc5eae
MF		 1164 break;
1165
1166 case 2: /*SYNC*/
28067b22
MF		 1167 switch (RRR_T) {
1168 case 0: /*ISYNC*/
1169 break;
1170
1171 case 1: /*RSYNC*/
1172 break;
1173
1174 case 2: /*ESYNC*/
1175 break;
1176
1177 case 3: /*DSYNC*/
1178 break;
1179
1180 case 8: /*EXCW*/
1181 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
1182 break;
1183
1184 case 12: /*MEMW*/
1185 break;
1186
1187 case 13: /*EXTW*/
1188 break;
1189
1190 case 15: /*NOP*/
1191 break;
1192
1193 default: /*reserved*/
1194 RESERVED();
1195 break;
1196 }
91a5bb76
MF		 1197 break;
1198
1199 case 3: /*RFEIx*/
40643d7c
MF		 1200 switch (RRR_T) {
1201 case 0: /*RFETx*/
1202 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
1203 switch (RRR_S) {
1204 case 0: /*RFEx*/
97e89ee9
MF		 1205 if (gen_check_privilege(dc)) {
1206 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
d2132510 1207 gen_check_interrupts(dc);
97e89ee9
MF		 1208 gen_jump(dc, cpu_SR[EPC1]);
1209 }
40643d7c
MF		 1210 break;
1211
1212 case 1: /*RFUEx*/
1213 RESERVED();
1214 break;
1215
1216 case 2: /*RFDEx*/
97e89ee9
MF		 1217 if (gen_check_privilege(dc)) {
1218 gen_jump(dc, cpu_SR[
1219 dc->config->ndepc ? DEPC : EPC1]);
1220 }
40643d7c
MF		 1221 break;
1222
1223 case 4: /*RFWOw*/
1224 case 5: /*RFWUw*/
1225 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
97e89ee9 1226 if (gen_check_privilege(dc)) {
553e44f9
MF		 1227 TCGv_i32 tmp = tcg_const_i32(1);
1228
1229 tcg_gen_andi_i32(
1230 cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
1231 tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]);
1232
1233 if (RRR_S == 4) {
1234 tcg_gen_andc_i32(cpu_SR[WINDOW_START],
1235 cpu_SR[WINDOW_START], tmp);
1236 } else {
1237 tcg_gen_or_i32(cpu_SR[WINDOW_START],
1238 cpu_SR[WINDOW_START], tmp);
1239 }
1240
f492b82d 1241 gen_helper_restore_owb(cpu_env);
d2132510 1242 gen_check_interrupts(dc);
553e44f9
MF		 1243 gen_jump(dc, cpu_SR[EPC1]);
1244
1245 tcg_temp_free(tmp);
1246 }
40643d7c
MF		 1247 break;
1248
1249 default: /*reserved*/
1250 RESERVED();
1251 break;
1252 }
1253 break;
1254
1255 case 1: /*RFIx*/
1256 HAS_OPTION(XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT);
b994e91b 1257 if (RRR_S >= 2 && RRR_S <= dc->config->nlevel) {
97e89ee9
MF		 1258 if (gen_check_privilege(dc)) {
1259 tcg_gen_mov_i32(cpu_SR[PS],
1260 cpu_SR[EPS2 + RRR_S - 2]);
d2132510 1261 gen_check_interrupts(dc);
97e89ee9
MF		 1262 gen_jump(dc, cpu_SR[EPC1 + RRR_S - 1]);
1263 }
b994e91b 1264 } else {
c30f0d18 1265 qemu_log_mask(LOG_GUEST_ERROR, "RFI %d is illegal\n", RRR_S);
b994e91b
MF		 1266 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1267 }
40643d7c
MF		 1268 break;
1269
1270 case 2: /*RFME*/
1271 TBD();
1272 break;
1273
1274 default: /*reserved*/
1275 RESERVED();
1276 break;
1277
1278 }
91a5bb76
MF		 1279 break;
1280
1281 case 4: /*BREAKx*/
e61dc8f7
MF		 1282 HAS_OPTION(XTENSA_OPTION_DEBUG);
1283 if (dc->debug) {
1284 gen_debug_exception(dc, DEBUGCAUSE_BI);
1285 }
91a5bb76
MF		 1286 break;
1287
1288 case 5: /*SYSCALLx*/
1289 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
40643d7c
MF		 1290 switch (RRR_S) {
1291 case 0: /*SYSCALLx*/
1292 gen_exception_cause(dc, SYSCALL_CAUSE);
1293 break;
1294
1295 case 1: /*SIMCALL*/
cfe67cef 1296 if (semihosting_enabled()) {
97e89ee9
MF		 1297 if (gen_check_privilege(dc)) {
1298 gen_helper_simcall(cpu_env);
1299 }
1ddeaa5d 1300 } else {
c30f0d18 1301 qemu_log_mask(LOG_GUEST_ERROR, "SIMCALL but semihosting is disabled\n");
1ddeaa5d
MF		 1302 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1303 }
40643d7c
MF		 1304 break;
1305
1306 default:
1307 RESERVED();
1308 break;
1309 }
91a5bb76
MF		 1310 break;
1311
1312 case 6: /*RSILx*/
1313 HAS_OPTION(XTENSA_OPTION_INTERRUPT);
97e89ee9
MF		 1314 if (gen_check_privilege(dc) &&
1315 gen_window_check1(dc, RRR_T)) {
1316 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_SR[PS]);
1317 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL);
1318 tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], RRR_S);
d2132510 1319 gen_check_interrupts(dc);
97e89ee9
MF		 1320 gen_jumpi_check_loop_end(dc, 0);
1321 }
91a5bb76
MF		 1322 break;
1323
1324 case 7: /*WAITIx*/
1325 HAS_OPTION(XTENSA_OPTION_INTERRUPT);
97e89ee9
MF		 1326 if (gen_check_privilege(dc)) {
1327 gen_waiti(dc, RRR_S);
1328 }
91a5bb76
MF		 1329 break;
1330
1331 case 8: /*ANY4p*/
91a5bb76 1332 case 9: /*ALL4p*/
91a5bb76 1333 case 10: /*ANY8p*/
91a5bb76
MF		 1334 case 11: /*ALL8p*/
1335 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
4dd85b6b
MF		 1336 {
1337 const unsigned shift = (RRR_R & 2) ? 8 : 4;
1338 TCGv_i32 mask = tcg_const_i32(
1339 ((1 << shift) - 1) << RRR_S);
1340 TCGv_i32 tmp = tcg_temp_new_i32();
1341
1342 tcg_gen_and_i32(tmp, cpu_SR[BR], mask);
1343 if (RRR_R & 1) { /*ALL*/
1344 tcg_gen_addi_i32(tmp, tmp, 1 << RRR_S);
1345 } else { /*ANY*/
1346 tcg_gen_add_i32(tmp, tmp, mask);
1347 }
1348 tcg_gen_shri_i32(tmp, tmp, RRR_S + shift);
1349 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR],
1350 tmp, RRR_T, 1);
1351 tcg_temp_free(mask);
1352 tcg_temp_free(tmp);
1353 }
91a5bb76
MF		 1354 break;
1355
1356 default: /*reserved*/
1357 RESERVED();
dedc5eae
MF		 1358 break;
1359
1360 }
1361 break;
1362
1363 case 1: /*AND*/
97e89ee9
MF		 1364 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1365 tcg_gen_and_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1366 }
dedc5eae
MF		 1367 break;
1368
1369 case 2: /*OR*/
97e89ee9
MF		 1370 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1371 tcg_gen_or_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1372 }
dedc5eae
MF		 1373 break;
1374
1375 case 3: /*XOR*/
97e89ee9
MF		 1376 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1377 tcg_gen_xor_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1378 }
dedc5eae
MF		 1379 break;
1380
1381 case 4: /*ST1*/
3580ecad
MF		 1382 switch (RRR_R) {
1383 case 0: /*SSR*/
97e89ee9
MF		 1384 if (gen_window_check1(dc, RRR_S)) {
1385 gen_right_shift_sar(dc, cpu_R[RRR_S]);
1386 }
3580ecad
MF		 1387 break;
1388
1389 case 1: /*SSL*/
97e89ee9
MF		 1390 if (gen_window_check1(dc, RRR_S)) {
1391 gen_left_shift_sar(dc, cpu_R[RRR_S]);
1392 }
3580ecad
MF		 1393 break;
1394
1395 case 2: /*SSA8L*/
97e89ee9 1396 if (gen_window_check1(dc, RRR_S)) {
3580ecad
MF		 1397 TCGv_i32 tmp = tcg_temp_new_i32();
1398 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
1399 gen_right_shift_sar(dc, tmp);
1400 tcg_temp_free(tmp);
1401 }
1402 break;
1403
1404 case 3: /*SSA8B*/
97e89ee9 1405 if (gen_window_check1(dc, RRR_S)) {
3580ecad
MF		 1406 TCGv_i32 tmp = tcg_temp_new_i32();
1407 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
1408 gen_left_shift_sar(dc, tmp);
1409 tcg_temp_free(tmp);
1410 }
1411 break;
1412
1413 case 4: /*SSAI*/
1414 {
1415 TCGv_i32 tmp = tcg_const_i32(
1416 RRR_S | ((RRR_T & 1) << 4));
1417 gen_right_shift_sar(dc, tmp);
1418 tcg_temp_free(tmp);
1419 }
1420 break;
1421
1422 case 6: /*RER*/
91a5bb76 1423 TBD();
3580ecad
MF		 1424 break;
1425
1426 case 7: /*WER*/
91a5bb76 1427 TBD();
3580ecad
MF		 1428 break;
1429
1430 case 8: /*ROTWw*/
1431 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
97e89ee9 1432 if (gen_check_privilege(dc)) {
553e44f9
MF		 1433 TCGv_i32 tmp = tcg_const_i32(
1434 RRR_T | ((RRR_T & 8) ? 0xfffffff0 : 0));
f492b82d 1435 gen_helper_rotw(cpu_env, tmp);
553e44f9 1436 tcg_temp_free(tmp);
2db59a76
MF		 1437 /* This can change tb->flags, so exit tb */
1438 gen_jumpi_check_loop_end(dc, -1);
553e44f9 1439 }
3580ecad
MF		 1440 break;
1441
1442 case 14: /*NSAu*/
7f65f4b0 1443 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA);
97e89ee9
MF		 1444 if (gen_window_check2(dc, RRR_S, RRR_T)) {
1445 gen_helper_nsa(cpu_R[RRR_T], cpu_R[RRR_S]);
1446 }
3580ecad
MF		 1447 break;
1448
1449 case 15: /*NSAUu*/
7f65f4b0 1450 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA);
97e89ee9
MF		 1451 if (gen_window_check2(dc, RRR_S, RRR_T)) {
1452 gen_helper_nsau(cpu_R[RRR_T], cpu_R[RRR_S]);
1453 }
3580ecad
MF		 1454 break;
1455
1456 default: /*reserved*/
91a5bb76 1457 RESERVED();
3580ecad
MF		 1458 break;
1459 }
dedc5eae
MF		 1460 break;
1461
1462 case 5: /*TLB*/
b67ea0cd
MF		 1463 HAS_OPTION_BITS(
1464 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU) |
1465 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
1466 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION));
97e89ee9
MF		 1467 if (gen_check_privilege(dc) &&
1468 gen_window_check2(dc, RRR_S, RRR_T)) {
b67ea0cd
MF		 1469 TCGv_i32 dtlb = tcg_const_i32((RRR_R & 8) != 0);
1470
1471 switch (RRR_R & 7) {
1472 case 3: /*RITLB0*/ /*RDTLB0*/
f492b82d
MF		 1473 gen_helper_rtlb0(cpu_R[RRR_T],
1474 cpu_env, cpu_R[RRR_S], dtlb);
b67ea0cd
MF		 1475 break;
1476
1477 case 4: /*IITLB*/ /*IDTLB*/
f492b82d 1478 gen_helper_itlb(cpu_env, cpu_R[RRR_S], dtlb);
b67ea0cd
MF		 1479 /* This could change memory mapping, so exit tb */
1480 gen_jumpi_check_loop_end(dc, -1);
1481 break;
1482
1483 case 5: /*PITLB*/ /*PDTLB*/
1484 tcg_gen_movi_i32(cpu_pc, dc->pc);
f492b82d
MF		 1485 gen_helper_ptlb(cpu_R[RRR_T],
1486 cpu_env, cpu_R[RRR_S], dtlb);
b67ea0cd
MF		 1487 break;
1488
1489 case 6: /*WITLB*/ /*WDTLB*/
f492b82d
MF		 1490 gen_helper_wtlb(
1491 cpu_env, cpu_R[RRR_T], cpu_R[RRR_S], dtlb);
b67ea0cd
MF		 1492 /* This could change memory mapping, so exit tb */
1493 gen_jumpi_check_loop_end(dc, -1);
1494 break;
1495
1496 case 7: /*RITLB1*/ /*RDTLB1*/
f492b82d
MF		 1497 gen_helper_rtlb1(cpu_R[RRR_T],
1498 cpu_env, cpu_R[RRR_S], dtlb);
b67ea0cd
MF		 1499 break;
1500
1501 default:
1502 tcg_temp_free(dtlb);
1503 RESERVED();
1504 break;
1505 }
1506 tcg_temp_free(dtlb);
1507 }
dedc5eae
MF		 1508 break;
1509
1510 case 6: /*RT0*/
97e89ee9
MF		 1511 if (!gen_window_check2(dc, RRR_R, RRR_T)) {
1512 break;
1513 }
f331fe5e
MF		 1514 switch (RRR_S) {
1515 case 0: /*NEG*/
1516 tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1517 break;
1518
1519 case 1: /*ABS*/
1520 {
f877d09e
MF		 1521 TCGv_i32 zero = tcg_const_i32(0);
1522 TCGv_i32 neg = tcg_temp_new_i32();
1523
1524 tcg_gen_neg_i32(neg, cpu_R[RRR_T]);
1525 tcg_gen_movcond_i32(TCG_COND_GE, cpu_R[RRR_R],
1526 cpu_R[RRR_T], zero, cpu_R[RRR_T], neg);
1527 tcg_temp_free(neg);
1528 tcg_temp_free(zero);
f331fe5e
MF		 1529 }
1530 break;
1531
1532 default: /*reserved*/
91a5bb76 1533 RESERVED();
f331fe5e
MF		 1534 break;
1535 }
dedc5eae
MF		 1536 break;
1537
1538 case 7: /*reserved*/
91a5bb76 1539 RESERVED();
dedc5eae
MF		 1540 break;
1541
1542 case 8: /*ADD*/
97e89ee9
MF		 1543 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1544 tcg_gen_add_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1545 }
dedc5eae
MF		 1546 break;
1547
1548 case 9: /*ADD**/
1549 case 10:
1550 case 11:
97e89ee9 1551 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
dedc5eae
MF		 1552 TCGv_i32 tmp = tcg_temp_new_i32();
1553 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 8);
1554 tcg_gen_add_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
1555 tcg_temp_free(tmp);
1556 }
1557 break;
1558
1559 case 12: /*SUB*/
97e89ee9
MF		 1560 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1561 tcg_gen_sub_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1562 }
dedc5eae
MF		 1563 break;
1564
1565 case 13: /*SUB**/
1566 case 14:
1567 case 15:
97e89ee9 1568 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
dedc5eae
MF		 1569 TCGv_i32 tmp = tcg_temp_new_i32();
1570 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 12);
1571 tcg_gen_sub_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
1572 tcg_temp_free(tmp);
1573 }
1574 break;
1575 }
1576 break;
1577
1578 case 1: /*RST1*/
3580ecad
MF		 1579 switch (OP2) {
1580 case 0: /*SLLI*/
1581 case 1:
97e89ee9
MF		 1582 if (gen_window_check2(dc, RRR_R, RRR_S)) {
1583 tcg_gen_shli_i32(cpu_R[RRR_R], cpu_R[RRR_S],
1584 32 - (RRR_T | ((OP2 & 1) << 4)));
1585 }
3580ecad
MF		 1586 break;
1587
1588 case 2: /*SRAI*/
1589 case 3:
97e89ee9
MF		 1590 if (gen_window_check2(dc, RRR_R, RRR_T)) {
1591 tcg_gen_sari_i32(cpu_R[RRR_R], cpu_R[RRR_T],
1592 RRR_S | ((OP2 & 1) << 4));
1593 }
3580ecad
MF		 1594 break;
1595
1596 case 4: /*SRLI*/
97e89ee9
MF		 1597 if (gen_window_check2(dc, RRR_R, RRR_T)) {
1598 tcg_gen_shri_i32(cpu_R[RRR_R], cpu_R[RRR_T], RRR_S);
1599 }
3580ecad
MF		 1600 break;
1601
1602 case 6: /*XSR*/
97e89ee9
MF		 1603 if (gen_check_sr(dc, RSR_SR, SR_X) &&
1604 (RSR_SR < 64 || gen_check_privilege(dc)) &&
1605 gen_window_check1(dc, RRR_T)) {
3580ecad 1606 TCGv_i32 tmp = tcg_temp_new_i32();
d2132510 1607 bool rsr_end, wsr_end;
0857a06e 1608
3580ecad 1609 tcg_gen_mov_i32(tmp, cpu_R[RRR_T]);
d2132510
MF		 1610 rsr_end = gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
1611 wsr_end = gen_wsr(dc, RSR_SR, tmp);
3580ecad 1612 tcg_temp_free(tmp);
d2132510
MF		 1613 if (rsr_end && !wsr_end) {
1614 gen_jumpi_check_loop_end(dc, 0);
1615 }
3580ecad
MF		 1616 }
1617 break;
1618
1619 /*
1620 * Note: 64 bit ops are used here solely because SAR values
1621 * have range 0..63
1622 */
1623#define gen_shift_reg(cmd, reg) do { \
1624 TCGv_i64 tmp = tcg_temp_new_i64(); \
1625 tcg_gen_extu_i32_i64(tmp, reg); \
1626 tcg_gen_##cmd##_i64(v, v, tmp); \
ecc7b3aa 1627 tcg_gen_extrl_i64_i32(cpu_R[RRR_R], v); \
3580ecad
MF		 1628 tcg_temp_free_i64(v); \
1629 tcg_temp_free_i64(tmp); \
1630 } while (0)
1631
1632#define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
1633
1634 case 8: /*SRC*/
97e89ee9 1635 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
3580ecad
MF		 1636 TCGv_i64 v = tcg_temp_new_i64();
1637 tcg_gen_concat_i32_i64(v, cpu_R[RRR_T], cpu_R[RRR_S]);
1638 gen_shift(shr);
1639 }
1640 break;
1641
1642 case 9: /*SRL*/
97e89ee9
MF		 1643 if (!gen_window_check2(dc, RRR_R, RRR_T)) {
1644 break;
1645 }
3580ecad
MF		 1646 if (dc->sar_5bit) {
1647 tcg_gen_shr_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
1648 } else {
1649 TCGv_i64 v = tcg_temp_new_i64();
1650 tcg_gen_extu_i32_i64(v, cpu_R[RRR_T]);
1651 gen_shift(shr);
1652 }
1653 break;
1654
1655 case 10: /*SLL*/
97e89ee9
MF		 1656 if (!gen_window_check2(dc, RRR_R, RRR_S)) {
1657 break;
1658 }
3580ecad
MF		 1659 if (dc->sar_m32_5bit) {
1660 tcg_gen_shl_i32(cpu_R[RRR_R], cpu_R[RRR_S], dc->sar_m32);
1661 } else {
1662 TCGv_i64 v = tcg_temp_new_i64();
1663 TCGv_i32 s = tcg_const_i32(32);
1664 tcg_gen_sub_i32(s, s, cpu_SR[SAR]);
1665 tcg_gen_andi_i32(s, s, 0x3f);
1666 tcg_gen_extu_i32_i64(v, cpu_R[RRR_S]);
1667 gen_shift_reg(shl, s);
1668 tcg_temp_free(s);
1669 }
1670 break;
1671
1672 case 11: /*SRA*/
97e89ee9
MF		 1673 if (!gen_window_check2(dc, RRR_R, RRR_T)) {
1674 break;
1675 }
3580ecad
MF		 1676 if (dc->sar_5bit) {
1677 tcg_gen_sar_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
1678 } else {
1679 TCGv_i64 v = tcg_temp_new_i64();
1680 tcg_gen_ext_i32_i64(v, cpu_R[RRR_T]);
1681 gen_shift(sar);
1682 }
1683 break;
1684#undef gen_shift
1685#undef gen_shift_reg
1686
1687 case 12: /*MUL16U*/
1688 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
97e89ee9 1689 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
3580ecad
MF		 1690 TCGv_i32 v1 = tcg_temp_new_i32();
1691 TCGv_i32 v2 = tcg_temp_new_i32();
1692 tcg_gen_ext16u_i32(v1, cpu_R[RRR_S]);
1693 tcg_gen_ext16u_i32(v2, cpu_R[RRR_T]);
1694 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1695 tcg_temp_free(v2);
1696 tcg_temp_free(v1);
1697 }
1698 break;
1699
1700 case 13: /*MUL16S*/
1701 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
97e89ee9 1702 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
3580ecad
MF		 1703 TCGv_i32 v1 = tcg_temp_new_i32();
1704 TCGv_i32 v2 = tcg_temp_new_i32();
1705 tcg_gen_ext16s_i32(v1, cpu_R[RRR_S]);
1706 tcg_gen_ext16s_i32(v2, cpu_R[RRR_T]);
1707 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1708 tcg_temp_free(v2);
1709 tcg_temp_free(v1);
1710 }
1711 break;
1712
1713 default: /*reserved*/
91a5bb76 1714 RESERVED();
3580ecad
MF		 1715 break;
1716 }
dedc5eae
MF		 1717 break;
1718
1719 case 2: /*RST2*/
97e89ee9
MF		 1720 if (OP2 >= 8 && !gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1721 break;
4dd85b6b 1722 }
772177c1 1723
f76ebf55
MF		 1724 if (OP2 >= 12) {
1725 HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV);
42a268c2 1726 TCGLabel *label = gen_new_label();
f76ebf55
MF		 1727 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0, label);
1728 gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE);
1729 gen_set_label(label);
1730 }
1731
1732 switch (OP2) {
4dd85b6b
MF		 1733#define BOOLEAN_LOGIC(fn, r, s, t) \
1734 do { \
1735 HAS_OPTION(XTENSA_OPTION_BOOLEAN); \
1736 TCGv_i32 tmp1 = tcg_temp_new_i32(); \
1737 TCGv_i32 tmp2 = tcg_temp_new_i32(); \
1738 \
1739 tcg_gen_shri_i32(tmp1, cpu_SR[BR], s); \
1740 tcg_gen_shri_i32(tmp2, cpu_SR[BR], t); \
1741 tcg_gen_##fn##_i32(tmp1, tmp1, tmp2); \
1742 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, r, 1); \
1743 tcg_temp_free(tmp1); \
1744 tcg_temp_free(tmp2); \
1745 } while (0)
1746
1747 case 0: /*ANDBp*/
1748 BOOLEAN_LOGIC(and, RRR_R, RRR_S, RRR_T);
1749 break;
1750
1751 case 1: /*ANDBCp*/
1752 BOOLEAN_LOGIC(andc, RRR_R, RRR_S, RRR_T);
1753 break;
1754
1755 case 2: /*ORBp*/
1756 BOOLEAN_LOGIC(or, RRR_R, RRR_S, RRR_T);
1757 break;
1758
1759 case 3: /*ORBCp*/
1760 BOOLEAN_LOGIC(orc, RRR_R, RRR_S, RRR_T);
1761 break;
1762
1763 case 4: /*XORBp*/
1764 BOOLEAN_LOGIC(xor, RRR_R, RRR_S, RRR_T);
1765 break;
1766
1767#undef BOOLEAN_LOGIC
1768
f76ebf55
MF		 1769 case 8: /*MULLi*/
1770 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL);
1771 tcg_gen_mul_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1772 break;
1773
1774 case 10: /*MULUHi*/
1775 case 11: /*MULSHi*/
7f65f4b0 1776 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL_HIGH);
f76ebf55 1777 {
c9cda20b 1778 TCGv lo = tcg_temp_new();
f76ebf55
MF		 1779
1780 if (OP2 == 10) {
c9cda20b
RH		 1781 tcg_gen_mulu2_i32(lo, cpu_R[RRR_R],
1782 cpu_R[RRR_S], cpu_R[RRR_T]);
f76ebf55 1783 } else {
c9cda20b
RH		 1784 tcg_gen_muls2_i32(lo, cpu_R[RRR_R],
1785 cpu_R[RRR_S], cpu_R[RRR_T]);
f76ebf55 1786 }
c9cda20b 1787 tcg_temp_free(lo);
f76ebf55
MF		 1788 }
1789 break;
1790
1791 case 12: /*QUOUi*/
1792 tcg_gen_divu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1793 break;
1794
1795 case 13: /*QUOSi*/
1796 case 15: /*REMSi*/
1797 {
42a268c2
RH		 1798 TCGLabel *label1 = gen_new_label();
1799 TCGLabel *label2 = gen_new_label();
f76ebf55
MF		 1800
1801 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_S], 0x80000000,
1802 label1);
1803 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0xffffffff,
1804 label1);
1805 tcg_gen_movi_i32(cpu_R[RRR_R],
1806 OP2 == 13 ? 0x80000000 : 0);
1807 tcg_gen_br(label2);
1808 gen_set_label(label1);
1809 if (OP2 == 13) {
1810 tcg_gen_div_i32(cpu_R[RRR_R],
1811 cpu_R[RRR_S], cpu_R[RRR_T]);
1812 } else {
1813 tcg_gen_rem_i32(cpu_R[RRR_R],
1814 cpu_R[RRR_S], cpu_R[RRR_T]);
1815 }
1816 gen_set_label(label2);
1817 }
1818 break;
1819
1820 case 14: /*REMUi*/
1821 tcg_gen_remu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1822 break;
1823
1824 default: /*reserved*/
1825 RESERVED();
1826 break;
1827 }
dedc5eae
MF		 1828 break;
1829
1830 case 3: /*RST3*/
b8132eff
MF		 1831 switch (OP2) {
1832 case 0: /*RSR*/
97e89ee9
MF		 1833 if (gen_check_sr(dc, RSR_SR, SR_R) &&
1834 (RSR_SR < 64 || gen_check_privilege(dc)) &&
1835 gen_window_check1(dc, RRR_T)) {
d2132510
MF		 1836 if (gen_rsr(dc, cpu_R[RRR_T], RSR_SR)) {
1837 gen_jumpi_check_loop_end(dc, 0);
1838 }
40643d7c 1839 }
b8132eff
MF		 1840 break;
1841
1842 case 1: /*WSR*/
97e89ee9
MF		 1843 if (gen_check_sr(dc, RSR_SR, SR_W) &&
1844 (RSR_SR < 64 || gen_check_privilege(dc)) &&
1845 gen_window_check1(dc, RRR_T)) {
0857a06e 1846 gen_wsr(dc, RSR_SR, cpu_R[RRR_T]);
40643d7c 1847 }
b8132eff
MF		 1848 break;
1849
1850 case 2: /*SEXTu*/
7f65f4b0 1851 HAS_OPTION(XTENSA_OPTION_MISC_OP_SEXT);
97e89ee9 1852 if (gen_window_check2(dc, RRR_R, RRR_S)) {
b8132eff
MF		 1853 int shift = 24 - RRR_T;
1854
1855 if (shift == 24) {
1856 tcg_gen_ext8s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1857 } else if (shift == 16) {
1858 tcg_gen_ext16s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1859 } else {
1860 TCGv_i32 tmp = tcg_temp_new_i32();
1861 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], shift);
1862 tcg_gen_sari_i32(cpu_R[RRR_R], tmp, shift);
1863 tcg_temp_free(tmp);
1864 }
1865 }
1866 break;
1867
1868 case 3: /*CLAMPSu*/
7f65f4b0 1869 HAS_OPTION(XTENSA_OPTION_MISC_OP_CLAMPS);
97e89ee9 1870 if (gen_window_check2(dc, RRR_R, RRR_S)) {
b8132eff
MF		 1871 TCGv_i32 tmp1 = tcg_temp_new_i32();
1872 TCGv_i32 tmp2 = tcg_temp_new_i32();
f877d09e 1873 TCGv_i32 zero = tcg_const_i32(0);
b8132eff
MF		 1874
1875 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 24 - RRR_T);
1876 tcg_gen_xor_i32(tmp2, tmp1, cpu_R[RRR_S]);
1877 tcg_gen_andi_i32(tmp2, tmp2, 0xffffffff << (RRR_T + 7));
b8132eff
MF		 1878
1879 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 31);
f877d09e 1880 tcg_gen_xori_i32(tmp1, tmp1, 0xffffffff >> (25 - RRR_T));
b8132eff 1881
f877d09e
MF		 1882 tcg_gen_movcond_i32(TCG_COND_EQ, cpu_R[RRR_R], tmp2, zero,
1883 cpu_R[RRR_S], tmp1);
b8132eff
MF		 1884 tcg_temp_free(tmp1);
1885 tcg_temp_free(tmp2);
f877d09e 1886 tcg_temp_free(zero);
b8132eff
MF		 1887 }
1888 break;
1889
1890 case 4: /*MINu*/
1891 case 5: /*MAXu*/
1892 case 6: /*MINUu*/
1893 case 7: /*MAXUu*/
7f65f4b0 1894 HAS_OPTION(XTENSA_OPTION_MISC_OP_MINMAX);
97e89ee9 1895 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
b8132eff
MF		 1896 static const TCGCond cond[] = {
1897 TCG_COND_LE,
1898 TCG_COND_GE,
1899 TCG_COND_LEU,
1900 TCG_COND_GEU
1901 };
f877d09e
MF		 1902 tcg_gen_movcond_i32(cond[OP2 - 4], cpu_R[RRR_R],
1903 cpu_R[RRR_S], cpu_R[RRR_T],
1904 cpu_R[RRR_S], cpu_R[RRR_T]);
b8132eff
MF		 1905 }
1906 break;
1907
1908 case 8: /*MOVEQZ*/
1909 case 9: /*MOVNEZ*/
1910 case 10: /*MOVLTZ*/
1911 case 11: /*MOVGEZ*/
97e89ee9 1912 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
b8132eff 1913 static const TCGCond cond[] = {
b8132eff 1914 TCG_COND_EQ,
f877d09e
MF		 1915 TCG_COND_NE,
1916 TCG_COND_LT,
b8132eff 1917 TCG_COND_GE,
b8132eff 1918 };
f877d09e
MF		 1919 TCGv_i32 zero = tcg_const_i32(0);
1920
1921 tcg_gen_movcond_i32(cond[OP2 - 8], cpu_R[RRR_R],
1922 cpu_R[RRR_T], zero, cpu_R[RRR_S], cpu_R[RRR_R]);
1923 tcg_temp_free(zero);
b8132eff
MF		 1924 }
1925 break;
1926
1927 case 12: /*MOVFp*/
b8132eff
MF		 1928 case 13: /*MOVTp*/
1929 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
97e89ee9 1930 if (gen_window_check2(dc, RRR_R, RRR_S)) {
f877d09e 1931 TCGv_i32 zero = tcg_const_i32(0);
4dd85b6b
MF		 1932 TCGv_i32 tmp = tcg_temp_new_i32();
1933
1934 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T);
f877d09e
MF		 1935 tcg_gen_movcond_i32(OP2 & 1 ? TCG_COND_NE : TCG_COND_EQ,
1936 cpu_R[RRR_R], tmp, zero,
1937 cpu_R[RRR_S], cpu_R[RRR_R]);
1938
4dd85b6b 1939 tcg_temp_free(tmp);
f877d09e 1940 tcg_temp_free(zero);
4dd85b6b 1941 }
b8132eff
MF		 1942 break;
1943
1944 case 14: /*RUR*/
97e89ee9 1945 if (gen_window_check1(dc, RRR_R)) {
b8132eff 1946 int st = (RRR_S << 4) + RRR_T;
fe0bd475 1947 if (uregnames[st].name) {
b8132eff
MF		 1948 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_UR[st]);
1949 } else {
c30f0d18 1950 qemu_log_mask(LOG_UNIMP, "RUR %d not implemented, ", st);
91a5bb76 1951 TBD();
b8132eff
MF		 1952 }
1953 }
1954 break;
1955
1956 case 15: /*WUR*/
97e89ee9
MF		 1957 if (gen_window_check1(dc, RRR_T)) {
1958 if (uregnames[RSR_SR].name) {
1959 gen_wur(RSR_SR, cpu_R[RRR_T]);
1960 } else {
c30f0d18 1961 qemu_log_mask(LOG_UNIMP, "WUR %d not implemented, ", RSR_SR);
97e89ee9
MF		 1962 TBD();
1963 }
b8132eff
MF		 1964 }
1965 break;
1966
1967 }
dedc5eae
MF		 1968 break;
1969
1970 case 4: /*EXTUI*/
1971 case 5:
97e89ee9 1972 if (gen_window_check2(dc, RRR_R, RRR_T)) {
f9cb5045 1973 int shiftimm = RRR_S | ((OP1 & 1) << 4);
3580ecad
MF		 1974 int maskimm = (1 << (OP2 + 1)) - 1;
1975
1976 TCGv_i32 tmp = tcg_temp_new_i32();
f783cb22
AJ		 1977 tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm);
1978 tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm);
3580ecad
MF		 1979 tcg_temp_free(tmp);
1980 }
dedc5eae
MF		 1981 break;
1982
1983 case 6: /*CUST0*/
91a5bb76 1984 RESERVED();
dedc5eae
MF		 1985 break;
1986
1987 case 7: /*CUST1*/
91a5bb76 1988 RESERVED();
dedc5eae
MF		 1989 break;
1990
1991 case 8: /*LSCXp*/
9ed7ae12
MF		 1992 switch (OP2) {
1993 case 0: /*LSXf*/
1994 case 1: /*LSXUf*/
1995 case 4: /*SSXf*/
1996 case 5: /*SSXUf*/
1997 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
97e89ee9
MF		 1998 if (gen_window_check2(dc, RRR_S, RRR_T) &&
1999 gen_check_cpenable(dc, 0)) {
9ed7ae12
MF		 2000 TCGv_i32 addr = tcg_temp_new_i32();
2001 tcg_gen_add_i32(addr, cpu_R[RRR_S], cpu_R[RRR_T]);
2002 gen_load_store_alignment(dc, 2, addr, false);
2003 if (OP2 & 0x4) {
2004 tcg_gen_qemu_st32(cpu_FR[RRR_R], addr, dc->cring);
2005 } else {
2006 tcg_gen_qemu_ld32u(cpu_FR[RRR_R], addr, dc->cring);
2007 }
2008 if (OP2 & 0x1) {
2009 tcg_gen_mov_i32(cpu_R[RRR_S], addr);
2010 }
2011 tcg_temp_free(addr);
2012 }
2013 break;
2014
2015 default: /*reserved*/
2016 RESERVED();
2017 break;
2018 }
dedc5eae
MF		 2019 break;
2020
2021 case 9: /*LSC4*/
97e89ee9
MF		 2022 if (!gen_window_check2(dc, RRR_S, RRR_T)) {
2023 break;
2024 }
553e44f9
MF		 2025 switch (OP2) {
2026 case 0: /*L32E*/
2027 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
f822b7e4
MF		 2028 if (gen_check_privilege(dc) &&
2029 gen_window_check2(dc, RRR_S, RRR_T)) {
553e44f9
MF		 2030 TCGv_i32 addr = tcg_temp_new_i32();
2031 tcg_gen_addi_i32(addr, cpu_R[RRR_S],
2032 (0xffffffc0 | (RRR_R << 2)));
2033 tcg_gen_qemu_ld32u(cpu_R[RRR_T], addr, dc->ring);
2034 tcg_temp_free(addr);
2035 }
2036 break;
2037
2038 case 4: /*S32E*/
2039 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
f822b7e4
MF		 2040 if (gen_check_privilege(dc) &&
2041 gen_window_check2(dc, RRR_S, RRR_T)) {
553e44f9
MF		 2042 TCGv_i32 addr = tcg_temp_new_i32();
2043 tcg_gen_addi_i32(addr, cpu_R[RRR_S],
2044 (0xffffffc0 | (RRR_R << 2)));
2045 tcg_gen_qemu_st32(cpu_R[RRR_T], addr, dc->ring);
2046 tcg_temp_free(addr);
2047 }
2048 break;
2049
19b7bec4
MF		 2050 case 5: /*S32N*/
2051 if (gen_window_check2(dc, RRI4_S, RRI4_T)) {
2052 TCGv_i32 addr = tcg_temp_new_i32();
2053
2054 tcg_gen_addi_i32(addr, cpu_R[RRI4_S], RRI4_IMM4 << 2);
2055 gen_load_store_alignment(dc, 2, addr, false);
2056 tcg_gen_qemu_st32(cpu_R[RRI4_T], addr, dc->cring);
2057 tcg_temp_free(addr);
2058 }
2059 break;
2060
553e44f9
MF		 2061 default:
2062 RESERVED();
2063 break;
2064 }
dedc5eae
MF		 2065 break;
2066
2067 case 10: /*FP0*/
5eeb40c5
MF		 2068 /*DEPBITS*/
2069 if (option_enabled(dc, XTENSA_OPTION_DEPBITS)) {
2070 if (!gen_window_check2(dc, RRR_S, RRR_T)) {
2071 break;
2072 }
2073 tcg_gen_deposit_i32(cpu_R[RRR_T], cpu_R[RRR_T], cpu_R[RRR_S],
2074 OP2, RRR_R + 1);
2075 break;
2076 }
2077
dedc5eae 2078 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
0b6df838
MF		 2079 switch (OP2) {
2080 case 0: /*ADD.Sf*/
97e89ee9
MF		 2081 if (gen_check_cpenable(dc, 0)) {
2082 gen_helper_add_s(cpu_FR[RRR_R], cpu_env,
2083 cpu_FR[RRR_S], cpu_FR[RRR_T]);
2084 }
0b6df838
MF		 2085 break;
2086
2087 case 1: /*SUB.Sf*/
97e89ee9
MF		 2088 if (gen_check_cpenable(dc, 0)) {
2089 gen_helper_sub_s(cpu_FR[RRR_R], cpu_env,
2090 cpu_FR[RRR_S], cpu_FR[RRR_T]);
2091 }
0b6df838
MF		 2092 break;
2093
2094 case 2: /*MUL.Sf*/
97e89ee9
MF		 2095 if (gen_check_cpenable(dc, 0)) {
2096 gen_helper_mul_s(cpu_FR[RRR_R], cpu_env,
2097 cpu_FR[RRR_S], cpu_FR[RRR_T]);
2098 }
0b6df838
MF		 2099 break;
2100
2101 case 4: /*MADD.Sf*/
97e89ee9
MF		 2102 if (gen_check_cpenable(dc, 0)) {
2103 gen_helper_madd_s(cpu_FR[RRR_R], cpu_env,
2104 cpu_FR[RRR_R], cpu_FR[RRR_S],
2105 cpu_FR[RRR_T]);
2106 }
0b6df838
MF		 2107 break;
2108
2109 case 5: /*MSUB.Sf*/
97e89ee9
MF		 2110 if (gen_check_cpenable(dc, 0)) {
2111 gen_helper_msub_s(cpu_FR[RRR_R], cpu_env,
2112 cpu_FR[RRR_R], cpu_FR[RRR_S],
2113 cpu_FR[RRR_T]);
2114 }
0b6df838
MF		 2115 break;
2116
b7ee8c6a
MF		 2117 case 8: /*ROUND.Sf*/
2118 case 9: /*TRUNC.Sf*/
2119 case 10: /*FLOOR.Sf*/
2120 case 11: /*CEIL.Sf*/
2121 case 14: /*UTRUNC.Sf*/
97e89ee9
MF		 2122 if (gen_window_check1(dc, RRR_R) &&
2123 gen_check_cpenable(dc, 0)) {
b7ee8c6a
MF		 2124 static const unsigned rounding_mode_const[] = {
2125 float_round_nearest_even,
2126 float_round_to_zero,
2127 float_round_down,
2128 float_round_up,
2129 [6] = float_round_to_zero,
2130 };
2131 TCGv_i32 rounding_mode = tcg_const_i32(
2132 rounding_mode_const[OP2 & 7]);
2133 TCGv_i32 scale = tcg_const_i32(RRR_T);
2134
2135 if (OP2 == 14) {
2136 gen_helper_ftoui(cpu_R[RRR_R], cpu_FR[RRR_S],
2137 rounding_mode, scale);
2138 } else {
2139 gen_helper_ftoi(cpu_R[RRR_R], cpu_FR[RRR_S],
2140 rounding_mode, scale);
2141 }
2142
2143 tcg_temp_free(rounding_mode);
2144 tcg_temp_free(scale);
2145 }
2146 break;
2147
2148 case 12: /*FLOAT.Sf*/
2149 case 13: /*UFLOAT.Sf*/
97e89ee9
MF		 2150 if (gen_window_check1(dc, RRR_S) &&
2151 gen_check_cpenable(dc, 0)) {
b7ee8c6a
MF		 2152 TCGv_i32 scale = tcg_const_i32(-RRR_T);
2153
2154 if (OP2 == 13) {
2155 gen_helper_uitof(cpu_FR[RRR_R], cpu_env,
2156 cpu_R[RRR_S], scale);
2157 } else {
2158 gen_helper_itof(cpu_FR[RRR_R], cpu_env,
2159 cpu_R[RRR_S], scale);
2160 }
2161 tcg_temp_free(scale);
2162 }
2163 break;
2164
0b6df838
MF		 2165 case 15: /*FP1OP*/
2166 switch (RRR_T) {
2167 case 0: /*MOV.Sf*/
97e89ee9
MF		 2168 if (gen_check_cpenable(dc, 0)) {
2169 tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2170 }
0b6df838
MF		 2171 break;
2172
2173 case 1: /*ABS.Sf*/
97e89ee9
MF		 2174 if (gen_check_cpenable(dc, 0)) {
2175 gen_helper_abs_s(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2176 }
0b6df838
MF		 2177 break;
2178
2179 case 4: /*RFRf*/
97e89ee9
MF		 2180 if (gen_window_check1(dc, RRR_R) &&
2181 gen_check_cpenable(dc, 0)) {
2182 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_FR[RRR_S]);
2183 }
0b6df838
MF		 2184 break;
2185
2186 case 5: /*WFRf*/
97e89ee9
MF		 2187 if (gen_window_check1(dc, RRR_S) &&
2188 gen_check_cpenable(dc, 0)) {
2189 tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_R[RRR_S]);
2190 }
0b6df838
MF		 2191 break;
2192
2193 case 6: /*NEG.Sf*/
97e89ee9
MF		 2194 if (gen_check_cpenable(dc, 0)) {
2195 gen_helper_neg_s(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2196 }
0b6df838
MF		 2197 break;
2198
2199 default: /*reserved*/
2200 RESERVED();
2201 break;
2202 }
2203 break;
2204
2205 default: /*reserved*/
2206 RESERVED();
2207 break;
2208 }
dedc5eae
MF		 2209 break;
2210
2211 case 11: /*FP1*/
5eeb40c5
MF		 2212 /*DEPBITS*/
2213 if (option_enabled(dc, XTENSA_OPTION_DEPBITS)) {
2214 if (!gen_window_check2(dc, RRR_S, RRR_T)) {
2215 break;
2216 }
2217 tcg_gen_deposit_i32(cpu_R[RRR_T], cpu_R[RRR_T], cpu_R[RRR_S],
2218 OP2 + 16, RRR_R + 1);
2219 break;
2220 }
2221
dedc5eae 2222 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
4e273869
MF		 2223
2224#define gen_compare(rel, br, a, b) \
2225 do { \
97e89ee9
MF		 2226 if (gen_check_cpenable(dc, 0)) { \
2227 TCGv_i32 bit = tcg_const_i32(1 << br); \
2228 \
2229 gen_helper_##rel(cpu_env, bit, cpu_FR[a], cpu_FR[b]); \
2230 tcg_temp_free(bit); \
2231 } \
4e273869
MF		 2232 } while (0)
2233
2234 switch (OP2) {
2235 case 1: /*UN.Sf*/
2236 gen_compare(un_s, RRR_R, RRR_S, RRR_T);
2237 break;
2238
2239 case 2: /*OEQ.Sf*/
2240 gen_compare(oeq_s, RRR_R, RRR_S, RRR_T);
2241 break;
2242
2243 case 3: /*UEQ.Sf*/
2244 gen_compare(ueq_s, RRR_R, RRR_S, RRR_T);
2245 break;
2246
2247 case 4: /*OLT.Sf*/
2248 gen_compare(olt_s, RRR_R, RRR_S, RRR_T);
2249 break;
2250
2251 case 5: /*ULT.Sf*/
2252 gen_compare(ult_s, RRR_R, RRR_S, RRR_T);
2253 break;
2254
2255 case 6: /*OLE.Sf*/
2256 gen_compare(ole_s, RRR_R, RRR_S, RRR_T);
2257 break;
2258
2259 case 7: /*ULE.Sf*/
2260 gen_compare(ule_s, RRR_R, RRR_S, RRR_T);
2261 break;
2262
2263#undef gen_compare
2264
2265 case 8: /*MOVEQZ.Sf*/
2266 case 9: /*MOVNEZ.Sf*/
2267 case 10: /*MOVLTZ.Sf*/
2268 case 11: /*MOVGEZ.Sf*/
97e89ee9
MF		 2269 if (gen_window_check1(dc, RRR_T) &&
2270 gen_check_cpenable(dc, 0)) {
4e273869 2271 static const TCGCond cond[] = {
4e273869 2272 TCG_COND_EQ,
f877d09e
MF		 2273 TCG_COND_NE,
2274 TCG_COND_LT,
4e273869 2275 TCG_COND_GE,
4e273869 2276 };
f877d09e
MF		 2277 TCGv_i32 zero = tcg_const_i32(0);
2278
2279 tcg_gen_movcond_i32(cond[OP2 - 8], cpu_FR[RRR_R],
2280 cpu_R[RRR_T], zero, cpu_FR[RRR_S], cpu_FR[RRR_R]);
2281 tcg_temp_free(zero);
4e273869
MF		 2282 }
2283 break;
2284
2285 case 12: /*MOVF.Sf*/
2286 case 13: /*MOVT.Sf*/
2287 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
97e89ee9 2288 if (gen_check_cpenable(dc, 0)) {
f877d09e 2289 TCGv_i32 zero = tcg_const_i32(0);
4e273869
MF		 2290 TCGv_i32 tmp = tcg_temp_new_i32();
2291
2292 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T);
f877d09e
MF		 2293 tcg_gen_movcond_i32(OP2 & 1 ? TCG_COND_NE : TCG_COND_EQ,
2294 cpu_FR[RRR_R], tmp, zero,
2295 cpu_FR[RRR_S], cpu_FR[RRR_R]);
2296
4e273869 2297 tcg_temp_free(tmp);
f877d09e 2298 tcg_temp_free(zero);
4e273869
MF		 2299 }
2300 break;
2301
2302 default: /*reserved*/
2303 RESERVED();
2304 break;
2305 }
dedc5eae
MF		 2306 break;
2307
2308 default: /*reserved*/
91a5bb76 2309 RESERVED();
dedc5eae
MF		 2310 break;
2311 }
2312 break;
2313
2314 case 1: /*L32R*/
97e89ee9 2315 if (gen_window_check1(dc, RRR_T)) {
dedc5eae 2316 TCGv_i32 tmp = tcg_const_i32(
6ad6dbf7
MF		 2317 ((dc->tb->flags & XTENSA_TBFLAG_LITBASE) ?
2318 0 : ((dc->pc + 3) & ~3)) +
2319 (0xfffc0000 | (RI16_IMM16 << 2)));
dedc5eae 2320
6ad6dbf7
MF		 2321 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
2322 tcg_gen_add_i32(tmp, tmp, dc->litbase);
2323 }
f0a548b9 2324 tcg_gen_qemu_ld32u(cpu_R[RRR_T], tmp, dc->cring);
dedc5eae
MF		 2325 tcg_temp_free(tmp);
2326 }
2327 break;
2328
2329 case 2: /*LSAI*/
809377aa 2330#define gen_load_store(type, shift) do { \
97e89ee9
MF		 2331 if (gen_window_check2(dc, RRI8_S, RRI8_T)) { \
2332 TCGv_i32 addr = tcg_temp_new_i32(); \
2333 \
2334 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << shift); \
2335 if (shift) { \
2336 gen_load_store_alignment(dc, shift, addr, false); \
2337 } \
2338 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
2339 tcg_temp_free(addr); \
5b4e481b 2340 } \
809377aa
MF		 2341 } while (0)
2342
2343 switch (RRI8_R) {
2344 case 0: /*L8UI*/
2345 gen_load_store(ld8u, 0);
2346 break;
2347
2348 case 1: /*L16UI*/
2349 gen_load_store(ld16u, 1);
2350 break;
2351
2352 case 2: /*L32I*/
2353 gen_load_store(ld32u, 2);
2354 break;
2355
2356 case 4: /*S8I*/
2357 gen_load_store(st8, 0);
2358 break;
2359
2360 case 5: /*S16I*/
2361 gen_load_store(st16, 1);
2362 break;
2363
2364 case 6: /*S32I*/
2365 gen_load_store(st32, 2);
2366 break;
2367
7c842590 2368#define gen_dcache_hit_test(w, shift) do { \
97e89ee9
MF		 2369 if (gen_window_check1(dc, RRI##w##_S)) { \
2370 TCGv_i32 addr = tcg_temp_new_i32(); \
2371 TCGv_i32 res = tcg_temp_new_i32(); \
2372 tcg_gen_addi_i32(addr, cpu_R[RRI##w##_S], \
2373 RRI##w##_IMM##w << shift); \
2374 tcg_gen_qemu_ld8u(res, addr, dc->cring); \
2375 tcg_temp_free(addr); \
2376 tcg_temp_free(res); \
2377 } \
7c842590
MF		 2378 } while (0)
2379
2380#define gen_dcache_hit_test4() gen_dcache_hit_test(4, 4)
2381#define gen_dcache_hit_test8() gen_dcache_hit_test(8, 2)
2382
809377aa 2383 case 7: /*CACHEc*/
8ffc2d0d
MF		 2384 if (RRI8_T < 8) {
2385 HAS_OPTION(XTENSA_OPTION_DCACHE);
2386 }
2387
2388 switch (RRI8_T) {
2389 case 0: /*DPFRc*/
7c842590 2390 gen_window_check1(dc, RRI8_S);
8ffc2d0d
MF		 2391 break;
2392
2393 case 1: /*DPFWc*/
7c842590 2394 gen_window_check1(dc, RRI8_S);
8ffc2d0d
MF		 2395 break;
2396
2397 case 2: /*DPFROc*/
7c842590 2398 gen_window_check1(dc, RRI8_S);
8ffc2d0d
MF		 2399 break;
2400
2401 case 3: /*DPFWOc*/
7c842590 2402 gen_window_check1(dc, RRI8_S);
8ffc2d0d
MF		 2403 break;
2404
2405 case 4: /*DHWBc*/
7c842590 2406 gen_dcache_hit_test8();
8ffc2d0d
MF		 2407 break;
2408
2409 case 5: /*DHWBIc*/
7c842590 2410 gen_dcache_hit_test8();
8ffc2d0d
MF		 2411 break;
2412
2413 case 6: /*DHIc*/
97e89ee9
MF		 2414 if (gen_check_privilege(dc)) {
2415 gen_dcache_hit_test8();
2416 }
8ffc2d0d
MF		 2417 break;
2418
2419 case 7: /*DIIc*/
97e89ee9
MF		 2420 if (gen_check_privilege(dc)) {
2421 gen_window_check1(dc, RRI8_S);
2422 }
8ffc2d0d
MF		 2423 break;
2424
2425 case 8: /*DCEc*/
2426 switch (OP1) {
2427 case 0: /*DPFLl*/
2428 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
97e89ee9
MF		 2429 if (gen_check_privilege(dc)) {
2430 gen_dcache_hit_test4();
2431 }
8ffc2d0d
MF		 2432 break;
2433
2434 case 2: /*DHUl*/
2435 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
97e89ee9
MF		 2436 if (gen_check_privilege(dc)) {
2437 gen_dcache_hit_test4();
2438 }
8ffc2d0d
MF		 2439 break;
2440
2441 case 3: /*DIUl*/
2442 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
97e89ee9
MF		 2443 if (gen_check_privilege(dc)) {
2444 gen_window_check1(dc, RRI4_S);
2445 }
8ffc2d0d
MF		 2446 break;
2447
2448 case 4: /*DIWBc*/
2449 HAS_OPTION(XTENSA_OPTION_DCACHE);
97e89ee9
MF		 2450 if (gen_check_privilege(dc)) {
2451 gen_window_check1(dc, RRI4_S);
2452 }
8ffc2d0d
MF		 2453 break;
2454
2455 case 5: /*DIWBIc*/
2456 HAS_OPTION(XTENSA_OPTION_DCACHE);
97e89ee9
MF		 2457 if (gen_check_privilege(dc)) {
2458 gen_window_check1(dc, RRI4_S);
2459 }
8ffc2d0d
MF		 2460 break;
2461
2462 default: /*reserved*/
2463 RESERVED();
2464 break;
2465
2466 }
2467 break;
2468
7c842590
MF		 2469#undef gen_dcache_hit_test
2470#undef gen_dcache_hit_test4
2471#undef gen_dcache_hit_test8
2472
e848dd42 2473#define gen_icache_hit_test(w, shift) do { \
97e89ee9
MF		 2474 if (gen_window_check1(dc, RRI##w##_S)) { \
2475 TCGv_i32 addr = tcg_temp_new_i32(); \
2476 tcg_gen_movi_i32(cpu_pc, dc->pc); \
2477 tcg_gen_addi_i32(addr, cpu_R[RRI##w##_S], \
2478 RRI##w##_IMM##w << shift); \
2479 gen_helper_itlb_hit_test(cpu_env, addr); \
2480 tcg_temp_free(addr); \
2481 }\
e848dd42
MF		 2482 } while (0)
2483
2484#define gen_icache_hit_test4() gen_icache_hit_test(4, 4)
2485#define gen_icache_hit_test8() gen_icache_hit_test(8, 2)
2486
8ffc2d0d
MF		 2487 case 12: /*IPFc*/
2488 HAS_OPTION(XTENSA_OPTION_ICACHE);
e848dd42 2489 gen_window_check1(dc, RRI8_S);
8ffc2d0d
MF		 2490 break;
2491
2492 case 13: /*ICEc*/
2493 switch (OP1) {
2494 case 0: /*IPFLl*/
2495 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
97e89ee9
MF		 2496 if (gen_check_privilege(dc)) {
2497 gen_icache_hit_test4();
2498 }
8ffc2d0d
MF		 2499 break;
2500
2501 case 2: /*IHUl*/
2502 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
97e89ee9
MF		 2503 if (gen_check_privilege(dc)) {
2504 gen_icache_hit_test4();
2505 }
8ffc2d0d
MF		 2506 break;
2507
2508 case 3: /*IIUl*/
2509 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
97e89ee9
MF		 2510 if (gen_check_privilege(dc)) {
2511 gen_window_check1(dc, RRI4_S);
2512 }
8ffc2d0d
MF		 2513 break;
2514
2515 default: /*reserved*/
2516 RESERVED();
2517 break;
2518 }
2519 break;
2520
2521 case 14: /*IHIc*/
2522 HAS_OPTION(XTENSA_OPTION_ICACHE);
e848dd42 2523 gen_icache_hit_test8();
8ffc2d0d
MF		 2524 break;
2525
2526 case 15: /*IIIc*/
2527 HAS_OPTION(XTENSA_OPTION_ICACHE);
97e89ee9
MF		 2528 if (gen_check_privilege(dc)) {
2529 gen_window_check1(dc, RRI8_S);
2530 }
8ffc2d0d
MF		 2531 break;
2532
2533 default: /*reserved*/
2534 RESERVED();
2535 break;
2536 }
809377aa
MF		 2537 break;
2538
e848dd42
MF		 2539#undef gen_icache_hit_test
2540#undef gen_icache_hit_test4
2541#undef gen_icache_hit_test8
2542
809377aa
MF		 2543 case 9: /*L16SI*/
2544 gen_load_store(ld16s, 1);
2545 break;
5b4e481b 2546#undef gen_load_store
809377aa
MF		 2547
2548 case 10: /*MOVI*/
97e89ee9
MF		 2549 if (gen_window_check1(dc, RRI8_T)) {
2550 tcg_gen_movi_i32(cpu_R[RRI8_T],
2551 RRI8_IMM8 | (RRI8_S << 8) |
2552 ((RRI8_S & 0x8) ? 0xfffff000 : 0));
2553 }
809377aa
MF		 2554 break;
2555
5b4e481b 2556#define gen_load_store_no_hw_align(type) do { \
97e89ee9
MF		 2557 if (gen_window_check2(dc, RRI8_S, RRI8_T)) { \
2558 TCGv_i32 addr = tcg_temp_local_new_i32(); \
2559 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); \
2560 gen_load_store_alignment(dc, 2, addr, true); \
2561 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
2562 tcg_temp_free(addr); \
2563 } \
5b4e481b
MF		 2564 } while (0)
2565
809377aa
MF		 2566 case 11: /*L32AIy*/
2567 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
5b4e481b 2568 gen_load_store_no_hw_align(ld32u); /*TODO acquire?*/
809377aa
MF		 2569 break;
2570
2571 case 12: /*ADDI*/
97e89ee9
MF		 2572 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
2573 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE);
2574 }
809377aa
MF		 2575 break;
2576
2577 case 13: /*ADDMI*/
97e89ee9
MF		 2578 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
2579 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S],
2580 RRI8_IMM8_SE << 8);
2581 }
809377aa
MF		 2582 break;
2583
2584 case 14: /*S32C1Iy*/
7f65f4b0 2585 HAS_OPTION(XTENSA_OPTION_CONDITIONAL_STORE);
97e89ee9 2586 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
42a268c2 2587 TCGLabel *label = gen_new_label();
809377aa
MF		 2588 TCGv_i32 tmp = tcg_temp_local_new_i32();
2589 TCGv_i32 addr = tcg_temp_local_new_i32();
fcc803d1 2590 TCGv_i32 tpc;
809377aa
MF		 2591
2592 tcg_gen_mov_i32(tmp, cpu_R[RRI8_T]);
2593 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2);
5b4e481b 2594 gen_load_store_alignment(dc, 2, addr, true);
fcc803d1 2595
fcc803d1
MF		 2596 tpc = tcg_const_i32(dc->pc);
2597 gen_helper_check_atomctl(cpu_env, tpc, addr);
f0a548b9 2598 tcg_gen_qemu_ld32u(cpu_R[RRI8_T], addr, dc->cring);
809377aa
MF		 2599 tcg_gen_brcond_i32(TCG_COND_NE, cpu_R[RRI8_T],
2600 cpu_SR[SCOMPARE1], label);
2601
f0a548b9 2602 tcg_gen_qemu_st32(tmp, addr, dc->cring);
809377aa
MF		 2603
2604 gen_set_label(label);
fcc803d1 2605 tcg_temp_free(tpc);
809377aa
MF		 2606 tcg_temp_free(addr);
2607 tcg_temp_free(tmp);
2608 }
2609 break;
2610
2611 case 15: /*S32RIy*/
2612 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
5b4e481b 2613 gen_load_store_no_hw_align(st32); /*TODO release?*/
809377aa 2614 break;
5b4e481b 2615#undef gen_load_store_no_hw_align
809377aa
MF		 2616
2617 default: /*reserved*/
91a5bb76 2618 RESERVED();
809377aa
MF		 2619 break;
2620 }
dedc5eae
MF		 2621 break;
2622
2623 case 3: /*LSCIp*/
9ed7ae12
MF		 2624 switch (RRI8_R) {
2625 case 0: /*LSIf*/
2626 case 4: /*SSIf*/
2627 case 8: /*LSIUf*/
2628 case 12: /*SSIUf*/
2629 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
97e89ee9
MF		 2630 if (gen_window_check1(dc, RRI8_S) &&
2631 gen_check_cpenable(dc, 0)) {
9ed7ae12
MF		 2632 TCGv_i32 addr = tcg_temp_new_i32();
2633 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2);
2634 gen_load_store_alignment(dc, 2, addr, false);
2635 if (RRI8_R & 0x4) {
2636 tcg_gen_qemu_st32(cpu_FR[RRI8_T], addr, dc->cring);
2637 } else {
2638 tcg_gen_qemu_ld32u(cpu_FR[RRI8_T], addr, dc->cring);
2639 }
2640 if (RRI8_R & 0x8) {
2641 tcg_gen_mov_i32(cpu_R[RRI8_S], addr);
2642 }
2643 tcg_temp_free(addr);
2644 }
2645 break;
2646
2647 default: /*reserved*/
2648 RESERVED();
2649 break;
2650 }
dedc5eae
MF		 2651 break;
2652
2653 case 4: /*MAC16d*/
2654 HAS_OPTION(XTENSA_OPTION_MAC16);
6825b6c3
MF		 2655 {
2656 enum {
2657 MAC16_UMUL = 0x0,
2658 MAC16_MUL = 0x4,
2659 MAC16_MULA = 0x8,
2660 MAC16_MULS = 0xc,
2661 MAC16_NONE = 0xf,
2662 } op = OP1 & 0xc;
2663 bool is_m1_sr = (OP2 & 0x3) == 2;
2664 bool is_m2_sr = (OP2 & 0xc) == 0;
2665 uint32_t ld_offset = 0;
2666
2667 if (OP2 > 9) {
2668 RESERVED();
2669 }
2670
2671 switch (OP2 & 2) {
2672 case 0: /*MACI?/MACC?*/
2673 is_m1_sr = true;
2674 ld_offset = (OP2 & 1) ? -4 : 4;
2675
2676 if (OP2 >= 8) { /*MACI/MACC*/
2677 if (OP1 == 0) { /*LDINC/LDDEC*/
2678 op = MAC16_NONE;
2679 } else {
2680 RESERVED();
2681 }
2682 } else if (op != MAC16_MULA) { /*MULA.*.*.LDINC/LDDEC*/
2683 RESERVED();
2684 }
2685 break;
2686
2687 case 2: /*MACD?/MACA?*/
2688 if (op == MAC16_UMUL && OP2 != 7) { /*UMUL only in MACAA*/
2689 RESERVED();
2690 }
2691 break;
2692 }
2693
2694 if (op != MAC16_NONE) {
97e89ee9
MF		 2695 if (!is_m1_sr && !gen_window_check1(dc, RRR_S)) {
2696 break;
6825b6c3 2697 }
97e89ee9
MF		 2698 if (!is_m2_sr && !gen_window_check1(dc, RRR_T)) {
2699 break;
6825b6c3
MF		 2700 }
2701 }
2702
97e89ee9
MF		 2703 if (ld_offset && !gen_window_check1(dc, RRR_S)) {
2704 break;
2705 }
2706
6825b6c3
MF		 2707 {
2708 TCGv_i32 vaddr = tcg_temp_new_i32();
2709 TCGv_i32 mem32 = tcg_temp_new_i32();
2710
2711 if (ld_offset) {
6825b6c3
MF		 2712 tcg_gen_addi_i32(vaddr, cpu_R[RRR_S], ld_offset);
2713 gen_load_store_alignment(dc, 2, vaddr, false);
2714 tcg_gen_qemu_ld32u(mem32, vaddr, dc->cring);
2715 }
2716 if (op != MAC16_NONE) {
2717 TCGv_i32 m1 = gen_mac16_m(
2718 is_m1_sr ? cpu_SR[MR + RRR_X] : cpu_R[RRR_S],
2719 OP1 & 1, op == MAC16_UMUL);
2720 TCGv_i32 m2 = gen_mac16_m(
2721 is_m2_sr ? cpu_SR[MR + 2 + RRR_Y] : cpu_R[RRR_T],
2722 OP1 & 2, op == MAC16_UMUL);
2723
2724 if (op == MAC16_MUL || op == MAC16_UMUL) {
2725 tcg_gen_mul_i32(cpu_SR[ACCLO], m1, m2);
2726 if (op == MAC16_UMUL) {
2727 tcg_gen_movi_i32(cpu_SR[ACCHI], 0);
2728 } else {
2729 tcg_gen_sari_i32(cpu_SR[ACCHI], cpu_SR[ACCLO], 31);
2730 }
2731 } else {
d2123a07
RH		 2732 TCGv_i32 lo = tcg_temp_new_i32();
2733 TCGv_i32 hi = tcg_temp_new_i32();
2734
2735 tcg_gen_mul_i32(lo, m1, m2);
2736 tcg_gen_sari_i32(hi, lo, 31);
6825b6c3 2737 if (op == MAC16_MULA) {
d2123a07
RH		 2738 tcg_gen_add2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI],
2739 cpu_SR[ACCLO], cpu_SR[ACCHI],
2740 lo, hi);
6825b6c3 2741 } else {
d2123a07
RH		 2742 tcg_gen_sub2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI],
2743 cpu_SR[ACCLO], cpu_SR[ACCHI],
2744 lo, hi);
6825b6c3 2745 }
6825b6c3
MF		 2746 tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]);
2747
d2123a07
RH		 2748 tcg_temp_free_i32(lo);
2749 tcg_temp_free_i32(hi);
6825b6c3
MF		 2750 }
2751 tcg_temp_free(m1);
2752 tcg_temp_free(m2);
2753 }
2754 if (ld_offset) {
2755 tcg_gen_mov_i32(cpu_R[RRR_S], vaddr);
2756 tcg_gen_mov_i32(cpu_SR[MR + RRR_W], mem32);
2757 }
2758 tcg_temp_free(vaddr);
2759 tcg_temp_free(mem32);
2760 }
2761 }
dedc5eae
MF		 2762 break;
2763
2764 case 5: /*CALLN*/
2765 switch (CALL_N) {
2766 case 0: /*CALL0*/
2767 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
2768 gen_jumpi(dc, (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
2769 break;
2770
2771 case 1: /*CALL4w*/
2772 case 2: /*CALL8w*/
2773 case 3: /*CALL12w*/
2774 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
97e89ee9
MF		 2775 if (gen_window_check1(dc, CALL_N << 2)) {
2776 gen_callwi(dc, CALL_N,
2777 (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
2778 }
dedc5eae
MF		 2779 break;
2780 }
2781 break;
2782
2783 case 6: /*SI*/
2784 switch (CALL_N) {
2785 case 0: /*J*/
2786 gen_jumpi(dc, dc->pc + 4 + CALL_OFFSET_SE, 0);
2787 break;
2788
bd57fb91 2789 case 1: /*BZ*/
97e89ee9 2790 if (gen_window_check1(dc, BRI12_S)) {
bd57fb91
MF		 2791 static const TCGCond cond[] = {
2792 TCG_COND_EQ, /*BEQZ*/
2793 TCG_COND_NE, /*BNEZ*/
2794 TCG_COND_LT, /*BLTZ*/
2795 TCG_COND_GE, /*BGEZ*/
2796 };
2797
2798 gen_brcondi(dc, cond[BRI12_M & 3], cpu_R[BRI12_S], 0,
2799 4 + BRI12_IMM12_SE);
2800 }
2801 break;
2802
2803 case 2: /*BI0*/
97e89ee9 2804 if (gen_window_check1(dc, BRI8_S)) {
bd57fb91
MF		 2805 static const TCGCond cond[] = {
2806 TCG_COND_EQ, /*BEQI*/
2807 TCG_COND_NE, /*BNEI*/
2808 TCG_COND_LT, /*BLTI*/
2809 TCG_COND_GE, /*BGEI*/
2810 };
2811
2812 gen_brcondi(dc, cond[BRI8_M & 3],
2813 cpu_R[BRI8_S], B4CONST[BRI8_R], 4 + BRI8_IMM8_SE);
2814 }
2815 break;
2816
2817 case 3: /*BI1*/
2818 switch (BRI8_M) {
2819 case 0: /*ENTRYw*/
2820 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 2821 {
2822 TCGv_i32 pc = tcg_const_i32(dc->pc);
2823 TCGv_i32 s = tcg_const_i32(BRI12_S);
2824 TCGv_i32 imm = tcg_const_i32(BRI12_IMM12);
f492b82d 2825 gen_helper_entry(cpu_env, pc, s, imm);
553e44f9
MF		 2826 tcg_temp_free(imm);
2827 tcg_temp_free(s);
2828 tcg_temp_free(pc);
2db59a76
MF		 2829 /* This can change tb->flags, so exit tb */
2830 gen_jumpi_check_loop_end(dc, -1);
553e44f9 2831 }
bd57fb91
MF		 2832 break;
2833
2834 case 1: /*B1*/
2835 switch (BRI8_R) {
2836 case 0: /*BFp*/
bd57fb91
MF		 2837 case 1: /*BTp*/
2838 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
4dd85b6b
MF		 2839 {
2840 TCGv_i32 tmp = tcg_temp_new_i32();
2841 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRI8_S);
2842 gen_brcondi(dc,
2843 BRI8_R == 1 ? TCG_COND_NE : TCG_COND_EQ,
2844 tmp, 0, 4 + RRI8_IMM8_SE);
2845 tcg_temp_free(tmp);
2846 }
bd57fb91
MF		 2847 break;
2848
2849 case 8: /*LOOP*/
bd57fb91 2850 case 9: /*LOOPNEZ*/
bd57fb91 2851 case 10: /*LOOPGTZ*/
797d780b 2852 HAS_OPTION(XTENSA_OPTION_LOOP);
97e89ee9 2853 if (gen_window_check1(dc, RRI8_S)) {
797d780b
MF		 2854 uint32_t lend = dc->pc + RRI8_IMM8 + 4;
2855 TCGv_i32 tmp = tcg_const_i32(lend);
2856
2857 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_R[RRI8_S], 1);
2858 tcg_gen_movi_i32(cpu_SR[LBEG], dc->next_pc);
f492b82d 2859 gen_helper_wsr_lend(cpu_env, tmp);
797d780b
MF		 2860 tcg_temp_free(tmp);
2861
2862 if (BRI8_R > 8) {
42a268c2 2863 TCGLabel *label = gen_new_label();
797d780b
MF		 2864 tcg_gen_brcondi_i32(
2865 BRI8_R == 9 ? TCG_COND_NE : TCG_COND_GT,
2866 cpu_R[RRI8_S], 0, label);
2867 gen_jumpi(dc, lend, 1);
2868 gen_set_label(label);
2869 }
2870
2871 gen_jumpi(dc, dc->next_pc, 0);
2872 }
bd57fb91
MF		 2873 break;
2874
2875 default: /*reserved*/
91a5bb76 2876 RESERVED();
bd57fb91
MF		 2877 break;
2878
2879 }
2880 break;
2881
2882 case 2: /*BLTUI*/
2883 case 3: /*BGEUI*/
97e89ee9
MF		 2884 if (gen_window_check1(dc, BRI8_S)) {
2885 gen_brcondi(dc, BRI8_M == 2 ? TCG_COND_LTU : TCG_COND_GEU,
2886 cpu_R[BRI8_S], B4CONSTU[BRI8_R],
2887 4 + BRI8_IMM8_SE);
2888 }
bd57fb91
MF		 2889 break;
2890 }
2891 break;
2892
dedc5eae
MF		 2893 }
2894 break;
2895
2896 case 7: /*B*/
bd57fb91
MF		 2897 {
2898 TCGCond eq_ne = (RRI8_R & 8) ? TCG_COND_NE : TCG_COND_EQ;
2899
2900 switch (RRI8_R & 7) {
2901 case 0: /*BNONE*/ /*BANY*/
97e89ee9 2902 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
bd57fb91
MF		 2903 TCGv_i32 tmp = tcg_temp_new_i32();
2904 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
2905 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2906 tcg_temp_free(tmp);
2907 }
2908 break;
2909
2910 case 1: /*BEQ*/ /*BNE*/
2911 case 2: /*BLT*/ /*BGE*/
2912 case 3: /*BLTU*/ /*BGEU*/
97e89ee9 2913 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
bd57fb91
MF		 2914 static const TCGCond cond[] = {
2915 [1] = TCG_COND_EQ,
2916 [2] = TCG_COND_LT,
2917 [3] = TCG_COND_LTU,
2918 [9] = TCG_COND_NE,
2919 [10] = TCG_COND_GE,
2920 [11] = TCG_COND_GEU,
2921 };
2922 gen_brcond(dc, cond[RRI8_R], cpu_R[RRI8_S], cpu_R[RRI8_T],
2923 4 + RRI8_IMM8_SE);
2924 }
2925 break;
2926
2927 case 4: /*BALL*/ /*BNALL*/
97e89ee9 2928 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
bd57fb91
MF		 2929 TCGv_i32 tmp = tcg_temp_new_i32();
2930 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
2931 gen_brcond(dc, eq_ne, tmp, cpu_R[RRI8_T],
2932 4 + RRI8_IMM8_SE);
2933 tcg_temp_free(tmp);
2934 }
2935 break;
2936
2937 case 5: /*BBC*/ /*BBS*/
97e89ee9 2938 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
7ff7563f
MF		 2939#ifdef TARGET_WORDS_BIGENDIAN
2940 TCGv_i32 bit = tcg_const_i32(0x80000000);
2941#else
2942 TCGv_i32 bit = tcg_const_i32(0x00000001);
2943#endif
bd57fb91
MF		 2944 TCGv_i32 tmp = tcg_temp_new_i32();
2945 tcg_gen_andi_i32(tmp, cpu_R[RRI8_T], 0x1f);
7ff7563f
MF		 2946#ifdef TARGET_WORDS_BIGENDIAN
2947 tcg_gen_shr_i32(bit, bit, tmp);
2948#else
bd57fb91 2949 tcg_gen_shl_i32(bit, bit, tmp);
7ff7563f 2950#endif
bd57fb91
MF		 2951 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], bit);
2952 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2953 tcg_temp_free(tmp);
2954 tcg_temp_free(bit);
2955 }
2956 break;
2957
2958 case 6: /*BBCI*/ /*BBSI*/
2959 case 7:
97e89ee9 2960 if (gen_window_check1(dc, RRI8_S)) {
bd57fb91
MF		 2961 TCGv_i32 tmp = tcg_temp_new_i32();
2962 tcg_gen_andi_i32(tmp, cpu_R[RRI8_S],
7ff7563f
MF		 2963#ifdef TARGET_WORDS_BIGENDIAN
2964 0x80000000 >> (((RRI8_R & 1) << 4) | RRI8_T));
2965#else
2966 0x00000001 << (((RRI8_R & 1) << 4) | RRI8_T));
2967#endif
bd57fb91
MF		 2968 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2969 tcg_temp_free(tmp);
2970 }
2971 break;
2972
2973 }
2974 }
dedc5eae
MF		 2975 break;
2976
67882fd1 2977#define gen_narrow_load_store(type) do { \
97e89ee9
MF		 2978 if (gen_window_check2(dc, RRRN_S, RRRN_T)) { \
2979 TCGv_i32 addr = tcg_temp_new_i32(); \
2980 tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
2981 gen_load_store_alignment(dc, 2, addr, false); \
2982 tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, dc->cring); \
2983 tcg_temp_free(addr); \
2984 } \
67882fd1
MF		 2985 } while (0)
2986
dedc5eae 2987 case 8: /*L32I.Nn*/
67882fd1 2988 gen_narrow_load_store(ld32u);
dedc5eae
MF		 2989 break;
2990
2991 case 9: /*S32I.Nn*/
67882fd1 2992 gen_narrow_load_store(st32);
dedc5eae 2993 break;
67882fd1 2994#undef gen_narrow_load_store
dedc5eae
MF		 2995
2996 case 10: /*ADD.Nn*/
97e89ee9
MF		 2997 if (gen_window_check3(dc, RRRN_R, RRRN_S, RRRN_T)) {
2998 tcg_gen_add_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], cpu_R[RRRN_T]);
2999 }
dedc5eae
MF		 3000 break;
3001
3002 case 11: /*ADDI.Nn*/
97e89ee9
MF		 3003 if (gen_window_check2(dc, RRRN_R, RRRN_S)) {
3004 tcg_gen_addi_i32(cpu_R[RRRN_R], cpu_R[RRRN_S],
3005 RRRN_T ? RRRN_T : -1);
3006 }
dedc5eae
MF		 3007 break;
3008
3009 case 12: /*ST2n*/
97e89ee9
MF		 3010 if (!gen_window_check1(dc, RRRN_S)) {
3011 break;
3012 }
67882fd1
MF		 3013 if (RRRN_T < 8) { /*MOVI.Nn*/
3014 tcg_gen_movi_i32(cpu_R[RRRN_S],
3015 RRRN_R | (RRRN_T << 4) |
3016 ((RRRN_T & 6) == 6 ? 0xffffff80 : 0));
3017 } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/
bd57fb91
MF		 3018 TCGCond eq_ne = (RRRN_T & 4) ? TCG_COND_NE : TCG_COND_EQ;
3019
3020 gen_brcondi(dc, eq_ne, cpu_R[RRRN_S], 0,
3021 4 + (RRRN_R | ((RRRN_T & 3) << 4)));
67882fd1 3022 }
dedc5eae
MF		 3023 break;
3024
3025 case 13: /*ST3n*/
67882fd1
MF		 3026 switch (RRRN_R) {
3027 case 0: /*MOV.Nn*/
97e89ee9
MF		 3028 if (gen_window_check2(dc, RRRN_S, RRRN_T)) {
3029 tcg_gen_mov_i32(cpu_R[RRRN_T], cpu_R[RRRN_S]);
3030 }
67882fd1
MF		 3031 break;
3032
3033 case 15: /*S3*/
3034 switch (RRRN_T) {
3035 case 0: /*RET.Nn*/
3036 gen_jump(dc, cpu_R[0]);
3037 break;
3038
3039 case 1: /*RETW.Nn*/
91a5bb76 3040 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 3041 {
3042 TCGv_i32 tmp = tcg_const_i32(dc->pc);
f492b82d 3043 gen_helper_retw(tmp, cpu_env, tmp);
553e44f9
MF		 3044 gen_jump(dc, tmp);
3045 tcg_temp_free(tmp);
3046 }
67882fd1
MF		 3047 break;
3048
3049 case 2: /*BREAK.Nn*/
e61dc8f7
MF		 3050 HAS_OPTION(XTENSA_OPTION_DEBUG);
3051 if (dc->debug) {
3052 gen_debug_exception(dc, DEBUGCAUSE_BN);
3053 }
67882fd1
MF		 3054 break;
3055
3056 case 3: /*NOP.Nn*/
3057 break;
3058
3059 case 6: /*ILL.Nn*/
40643d7c 3060 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
67882fd1
MF		 3061 break;
3062
3063 default: /*reserved*/
91a5bb76 3064 RESERVED();
67882fd1
MF		 3065 break;
3066 }
3067 break;
3068
3069 default: /*reserved*/
91a5bb76 3070 RESERVED();
67882fd1
MF		 3071 break;
3072 }
dedc5eae
MF		 3073 break;
3074
3075 default: /*reserved*/
91a5bb76 3076 RESERVED();
dedc5eae
MF		 3077 break;
3078 }
3079
c26032b2
MF		 3080 if (dc->is_jmp == DISAS_NEXT) {
3081 gen_check_loop_end(dc, 0);
3082 }
dedc5eae 3083 dc->pc = dc->next_pc;
797d780b 3084
dedc5eae
MF		 3085 return;
3086
3087invalid_opcode:
c30f0d18 3088 qemu_log_mask(LOG_GUEST_ERROR, "INVALID(pc = %08x)\n", dc->pc);
6b814719 3089 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
dedc5eae
MF		 3090#undef HAS_OPTION
3091}
3092
01673a34
MF		 3093static inline unsigned xtensa_insn_len(CPUXtensaState *env, DisasContext *dc)
3094{
3095 uint8_t b0 = cpu_ldub_code(env, dc->pc);
3096 return xtensa_op0_insn_len(OP0);
3097}
3098
97129ac8 3099static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc)
e61dc8f7
MF		 3100{
3101 unsigned i;
3102
3103 for (i = 0; i < dc->config->nibreak; ++i) {
3104 if ((env->sregs[IBREAKENABLE] & (1 << i)) &&
3105 env->sregs[IBREAKA + i] == dc->pc) {
3106 gen_debug_exception(dc, DEBUGCAUSE_IB);
3107 break;
3108 }
3109 }
3110}
3111
4e5e1215 3112void gen_intermediate_code(CPUXtensaState *env, TranslationBlock *tb)
dedc5eae 3113{
4e5e1215 3114 XtensaCPU *cpu = xtensa_env_get_cpu(env);
ed2803da 3115 CPUState *cs = CPU(cpu);
dedc5eae
MF		 3116 DisasContext dc;
3117 int insn_count = 0;
dedc5eae
MF		 3118 int max_insns = tb->cflags & CF_COUNT_MASK;
3119 uint32_t pc_start = tb->pc;
3120 uint32_t next_page_start =
3121 (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
3122
3123 if (max_insns == 0) {
3124 max_insns = CF_COUNT_MASK;
3125 }
190ce7fb
RH		 3126 if (max_insns > TCG_MAX_INSNS) {
3127 max_insns = TCG_MAX_INSNS;
3128 }
dedc5eae
MF		 3129
3130 dc.config = env->config;
ed2803da 3131 dc.singlestep_enabled = cs->singlestep_enabled;
dedc5eae
MF		 3132 dc.tb = tb;
3133 dc.pc = pc_start;
f0a548b9
MF		 3134 dc.ring = tb->flags & XTENSA_TBFLAG_RING_MASK;
3135 dc.cring = (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc.ring;
797d780b
MF		 3136 dc.lbeg = env->sregs[LBEG];
3137 dc.lend = env->sregs[LEND];
dedc5eae 3138 dc.is_jmp = DISAS_NEXT;
e61dc8f7 3139 dc.debug = tb->flags & XTENSA_TBFLAG_DEBUG;
35b5c044 3140 dc.icount = tb->flags & XTENSA_TBFLAG_ICOUNT;
ef04a846
MF		 3141 dc.cpenable = (tb->flags & XTENSA_TBFLAG_CPENABLE_MASK) >>
3142 XTENSA_TBFLAG_CPENABLE_SHIFT;
2db59a76
MF		 3143 dc.window = ((tb->flags & XTENSA_TBFLAG_WINDOW_MASK) >>
3144 XTENSA_TBFLAG_WINDOW_SHIFT);
dedc5eae 3145
6ad6dbf7 3146 init_litbase(&dc);
3580ecad 3147 init_sar_tracker(&dc);
35b5c044
MF		 3148 if (dc.icount) {
3149 dc.next_icount = tcg_temp_local_new_i32();
3150 }
3580ecad 3151
cd42d5b2 3152 gen_tb_start(tb);
dedc5eae 3153
d2132510
MF		 3154 if ((tb->cflags & CF_USE_ICOUNT) &&
3155 (tb->flags & XTENSA_TBFLAG_YIELD)) {
3156 tcg_gen_insn_start(dc.pc);
3157 ++insn_count;
3158 gen_exception(&dc, EXCP_YIELD);
3159 dc.is_jmp = DISAS_UPDATE;
3160 goto done;
3161 }
a00817cc 3162 if (tb->flags & XTENSA_TBFLAG_EXCEPTION) {
787eaa49
MF		 3163 tcg_gen_insn_start(dc.pc);
3164 ++insn_count;
b994e91b 3165 gen_exception(&dc, EXCP_DEBUG);
787eaa49
MF		 3166 dc.is_jmp = DISAS_UPDATE;
3167 goto done;
40643d7c
MF		 3168 }
3169
dedc5eae 3170 do {
667b8e29 3171 tcg_gen_insn_start(dc.pc);
959082fc 3172 ++insn_count;
dedc5eae 3173
b933066a
RH		 3174 if (unlikely(cpu_breakpoint_test(cs, dc.pc, BP_ANY))) {
3175 tcg_gen_movi_i32(cpu_pc, dc.pc);
3176 gen_exception(&dc, EXCP_DEBUG);
3177 dc.is_jmp = DISAS_UPDATE;
522a0d4e
RH		 3178 /* The address covered by the breakpoint must be included in
3179 [tb->pc, tb->pc + tb->size) in order to for it to be
3180 properly cleared -- thus we increment the PC here so that
3181 the logic setting tb->size below does the right thing. */
3182 dc.pc += 2;
b933066a
RH		 3183 break;
3184 }
3185
959082fc 3186 if (insn_count == max_insns && (tb->cflags & CF_LAST_IO)) {
b994e91b
MF		 3187 gen_io_start();
3188 }
3189
35b5c044 3190 if (dc.icount) {
42a268c2 3191 TCGLabel *label = gen_new_label();
35b5c044
MF		 3192
3193 tcg_gen_addi_i32(dc.next_icount, cpu_SR[ICOUNT], 1);
3194 tcg_gen_brcondi_i32(TCG_COND_NE, dc.next_icount, 0, label);
3195 tcg_gen_mov_i32(dc.next_icount, cpu_SR[ICOUNT]);
3196 if (dc.debug) {
3197 gen_debug_exception(&dc, DEBUGCAUSE_IC);
3198 }
3199 gen_set_label(label);
3200 }
3201
e61dc8f7
MF		 3202 if (dc.debug) {
3203 gen_ibreak_check(env, &dc);
3204 }
3205
0c4fabea 3206 disas_xtensa_insn(env, &dc);
35b5c044
MF		 3207 if (dc.icount) {
3208 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount);
3209 }
ed2803da 3210 if (cs->singlestep_enabled) {
dedc5eae 3211 tcg_gen_movi_i32(cpu_pc, dc.pc);
b994e91b 3212 gen_exception(&dc, EXCP_DEBUG);
dedc5eae
MF		 3213 break;
3214 }
3215 } while (dc.is_jmp == DISAS_NEXT &&
3216 insn_count < max_insns &&
3217 dc.pc < next_page_start &&
01673a34 3218 dc.pc + xtensa_insn_len(env, &dc) <= next_page_start &&
fe700adb 3219 !tcg_op_buf_full());
d2132510 3220done:
6ad6dbf7 3221 reset_litbase(&dc);
3580ecad 3222 reset_sar_tracker(&dc);
35b5c044
MF		 3223 if (dc.icount) {
3224 tcg_temp_free(dc.next_icount);
3225 }
3580ecad 3226
b994e91b
MF		 3227 if (tb->cflags & CF_LAST_IO) {
3228 gen_io_end();
3229 }
3230
dedc5eae
MF		 3231 if (dc.is_jmp == DISAS_NEXT) {
3232 gen_jumpi(&dc, dc.pc, 0);
3233 }
806f352d 3234 gen_tb_end(tb, insn_count);
dedc5eae 3235
ca529f8e 3236#ifdef DEBUG_DISAS
4910e6e4
RH		 3237 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
3238 && qemu_log_in_addr_range(pc_start)) {
1ee73216 3239 qemu_log_lock();
ca529f8e
MF		 3240 qemu_log("----------------\n");
3241 qemu_log("IN: %s\n", lookup_symbol(pc_start));
d49190c4 3242 log_target_disas(cs, pc_start, dc.pc - pc_start, 0);
ca529f8e 3243 qemu_log("\n");
1ee73216 3244 qemu_log_unlock();
ca529f8e
MF		 3245 }
3246#endif
4e5e1215
RH		 3247 tb->size = dc.pc - pc_start;
3248 tb->icount = insn_count;
2328826b
MF		 3249}
3250
878096ee
AF		 3251void xtensa_cpu_dump_state(CPUState *cs, FILE *f,
3252 fprintf_function cpu_fprintf, int flags)
2328826b 3253{
878096ee
AF		 3254 XtensaCPU *cpu = XTENSA_CPU(cs);
3255 CPUXtensaState *env = &cpu->env;
2af3da91
MF		 3256 int i, j;
3257
3258 cpu_fprintf(f, "PC=%08x\n\n", env->pc);
3259
3260 for (i = j = 0; i < 256; ++i) {
fe0bd475
MF		 3261 if (xtensa_option_bits_enabled(env->config, sregnames[i].opt_bits)) {
3262 cpu_fprintf(f, "%12s=%08x%c", sregnames[i].name, env->sregs[i],
2af3da91
MF		 3263 (j++ % 4) == 3 ? '\n' : ' ');
3264 }
3265 }
3266
3267 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
3268
3269 for (i = j = 0; i < 256; ++i) {
fe0bd475
MF		 3270 if (xtensa_option_bits_enabled(env->config, uregnames[i].opt_bits)) {
3271 cpu_fprintf(f, "%s=%08x%c", uregnames[i].name, env->uregs[i],
2af3da91
MF		 3272 (j++ % 4) == 3 ? '\n' : ' ');
3273 }
3274 }
2328826b 3275
2af3da91 3276 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
2328826b
MF		 3277
3278 for (i = 0; i < 16; ++i) {
fe0bd475 3279 cpu_fprintf(f, " A%02d=%08x%c", i, env->regs[i],
2328826b
MF		 3280 (i % 4) == 3 ? '\n' : ' ');
3281 }
553e44f9
MF		 3282
3283 cpu_fprintf(f, "\n");
3284
3285 for (i = 0; i < env->config->nareg; ++i) {
3286 cpu_fprintf(f, "AR%02d=%08x%c", i, env->phys_regs[i],
3287 (i % 4) == 3 ? '\n' : ' ');
3288 }
dd519cbe
MF		 3289
3290 if (xtensa_option_enabled(env->config, XTENSA_OPTION_FP_COPROCESSOR)) {
3291 cpu_fprintf(f, "\n");
3292
3293 for (i = 0; i < 16; ++i) {
3294 cpu_fprintf(f, "F%02d=%08x (%+10.8e)%c", i,
ddd44279
MF		 3295 float32_val(env->fregs[i].f32[FP_F32_LOW]),
3296 *(float *)(env->fregs[i].f32 + FP_F32_LOW),
3297 (i % 2) == 1 ? '\n' : ' ');
dd519cbe
MF		 3298 }
3299 }
2328826b
MF		 3300}
3301
bad729e2
RH		 3302void restore_state_to_opc(CPUXtensaState *env, TranslationBlock *tb,
3303 target_ulong *data)
2328826b 3304{
bad729e2 3305 env->pc = data[0];
2328826b 3306}
QEMU mirror