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Commit | Line | Data |
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4c9649a9 JM |
1 | /* |
2 | * Alpha emulation cpu translation for qemu. | |
5fafdf24 | 3 | * |
4c9649a9 JM |
4 | * Copyright (c) 2007 Jocelyn Mayer |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
4c9649a9 JM |
18 | */ |
19 | ||
20 | #include <stdint.h> | |
21 | #include <stdlib.h> | |
22 | #include <stdio.h> | |
23 | ||
24 | #include "cpu.h" | |
25 | #include "exec-all.h" | |
26 | #include "disas.h" | |
ae8ecd42 | 27 | #include "host-utils.h" |
57fec1fe | 28 | #include "tcg-op.h" |
ca10f867 | 29 | #include "qemu-common.h" |
4c9649a9 | 30 | |
a7812ae4 PB |
31 | #include "helper.h" |
32 | #define GEN_HELPER 1 | |
33 | #include "helper.h" | |
34 | ||
55489a17 | 35 | /* #define DO_SINGLE_STEP */ |
4c9649a9 | 36 | #define ALPHA_DEBUG_DISAS |
55489a17 | 37 | /* #define DO_TB_FLUSH */ |
4c9649a9 | 38 | |
d12d51d5 AL |
39 | |
40 | #ifdef ALPHA_DEBUG_DISAS | |
93fcfe39 | 41 | # define LOG_DISAS(...) qemu_log(__VA_ARGS__) |
d12d51d5 AL |
42 | #else |
43 | # define LOG_DISAS(...) do { } while (0) | |
44 | #endif | |
45 | ||
4c9649a9 JM |
46 | typedef struct DisasContext DisasContext; |
47 | struct DisasContext { | |
48 | uint64_t pc; | |
49 | int mem_idx; | |
50 | #if !defined (CONFIG_USER_ONLY) | |
51 | int pal_mode; | |
52 | #endif | |
8579095b | 53 | CPUAlphaState *env; |
4c9649a9 JM |
54 | uint32_t amask; |
55 | }; | |
56 | ||
3761035f | 57 | /* global register indexes */ |
a7812ae4 | 58 | static TCGv_ptr cpu_env; |
496cb5b9 | 59 | static TCGv cpu_ir[31]; |
f18cd223 | 60 | static TCGv cpu_fir[31]; |
496cb5b9 | 61 | static TCGv cpu_pc; |
f4ed8679 | 62 | static TCGv cpu_lock; |
496cb5b9 | 63 | |
3761035f | 64 | /* register names */ |
f18cd223 | 65 | static char cpu_reg_names[10*4+21*5 + 10*5+21*6]; |
2e70f6ef PB |
66 | |
67 | #include "gen-icount.h" | |
68 | ||
a5f1b965 | 69 | static void alpha_translate_init(void) |
2e70f6ef | 70 | { |
496cb5b9 AJ |
71 | int i; |
72 | char *p; | |
2e70f6ef | 73 | static int done_init = 0; |
496cb5b9 | 74 | |
2e70f6ef PB |
75 | if (done_init) |
76 | return; | |
496cb5b9 | 77 | |
a7812ae4 | 78 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); |
496cb5b9 AJ |
79 | |
80 | p = cpu_reg_names; | |
81 | for (i = 0; i < 31; i++) { | |
82 | sprintf(p, "ir%d", i); | |
a7812ae4 PB |
83 | cpu_ir[i] = tcg_global_mem_new_i64(TCG_AREG0, |
84 | offsetof(CPUState, ir[i]), p); | |
6ba8dcd7 | 85 | p += (i < 10) ? 4 : 5; |
f18cd223 AJ |
86 | |
87 | sprintf(p, "fir%d", i); | |
a7812ae4 PB |
88 | cpu_fir[i] = tcg_global_mem_new_i64(TCG_AREG0, |
89 | offsetof(CPUState, fir[i]), p); | |
f18cd223 | 90 | p += (i < 10) ? 5 : 6; |
496cb5b9 AJ |
91 | } |
92 | ||
a7812ae4 PB |
93 | cpu_pc = tcg_global_mem_new_i64(TCG_AREG0, |
94 | offsetof(CPUState, pc), "pc"); | |
496cb5b9 | 95 | |
a7812ae4 PB |
96 | cpu_lock = tcg_global_mem_new_i64(TCG_AREG0, |
97 | offsetof(CPUState, lock), "lock"); | |
f4ed8679 | 98 | |
496cb5b9 | 99 | /* register helpers */ |
a7812ae4 | 100 | #define GEN_HELPER 2 |
496cb5b9 AJ |
101 | #include "helper.h" |
102 | ||
2e70f6ef PB |
103 | done_init = 1; |
104 | } | |
105 | ||
f071b4d3 JM |
106 | static always_inline void gen_excp (DisasContext *ctx, |
107 | int exception, int error_code) | |
4c9649a9 | 108 | { |
a7812ae4 | 109 | TCGv_i32 tmp1, tmp2; |
6ad02592 | 110 | |
496cb5b9 | 111 | tcg_gen_movi_i64(cpu_pc, ctx->pc); |
6ad02592 AJ |
112 | tmp1 = tcg_const_i32(exception); |
113 | tmp2 = tcg_const_i32(error_code); | |
a7812ae4 PB |
114 | gen_helper_excp(tmp1, tmp2); |
115 | tcg_temp_free_i32(tmp2); | |
116 | tcg_temp_free_i32(tmp1); | |
4c9649a9 JM |
117 | } |
118 | ||
f071b4d3 | 119 | static always_inline void gen_invalid (DisasContext *ctx) |
4c9649a9 JM |
120 | { |
121 | gen_excp(ctx, EXCP_OPCDEC, 0); | |
122 | } | |
123 | ||
f18cd223 AJ |
124 | static always_inline void gen_qemu_ldf (TCGv t0, TCGv t1, int flags) |
125 | { | |
a7812ae4 PB |
126 | TCGv tmp = tcg_temp_new(); |
127 | TCGv_i32 tmp32 = tcg_temp_new_i32(); | |
f18cd223 | 128 | tcg_gen_qemu_ld32u(tmp, t1, flags); |
a7812ae4 PB |
129 | tcg_gen_trunc_i64_i32(tmp32, tmp); |
130 | gen_helper_memory_to_f(t0, tmp32); | |
131 | tcg_temp_free_i32(tmp32); | |
f18cd223 AJ |
132 | tcg_temp_free(tmp); |
133 | } | |
134 | ||
135 | static always_inline void gen_qemu_ldg (TCGv t0, TCGv t1, int flags) | |
136 | { | |
a7812ae4 | 137 | TCGv tmp = tcg_temp_new(); |
f18cd223 | 138 | tcg_gen_qemu_ld64(tmp, t1, flags); |
a7812ae4 | 139 | gen_helper_memory_to_g(t0, tmp); |
f18cd223 AJ |
140 | tcg_temp_free(tmp); |
141 | } | |
142 | ||
143 | static always_inline void gen_qemu_lds (TCGv t0, TCGv t1, int flags) | |
144 | { | |
a7812ae4 PB |
145 | TCGv tmp = tcg_temp_new(); |
146 | TCGv_i32 tmp32 = tcg_temp_new_i32(); | |
f18cd223 | 147 | tcg_gen_qemu_ld32u(tmp, t1, flags); |
a7812ae4 PB |
148 | tcg_gen_trunc_i64_i32(tmp32, tmp); |
149 | gen_helper_memory_to_s(t0, tmp32); | |
150 | tcg_temp_free_i32(tmp32); | |
f18cd223 AJ |
151 | tcg_temp_free(tmp); |
152 | } | |
153 | ||
f4ed8679 AJ |
154 | static always_inline void gen_qemu_ldl_l (TCGv t0, TCGv t1, int flags) |
155 | { | |
156 | tcg_gen_mov_i64(cpu_lock, t1); | |
157 | tcg_gen_qemu_ld32s(t0, t1, flags); | |
158 | } | |
159 | ||
160 | static always_inline void gen_qemu_ldq_l (TCGv t0, TCGv t1, int flags) | |
161 | { | |
162 | tcg_gen_mov_i64(cpu_lock, t1); | |
163 | tcg_gen_qemu_ld64(t0, t1, flags); | |
164 | } | |
165 | ||
023d8ca2 AJ |
166 | static always_inline void gen_load_mem (DisasContext *ctx, |
167 | void (*tcg_gen_qemu_load)(TCGv t0, TCGv t1, int flags), | |
168 | int ra, int rb, int32_t disp16, | |
f18cd223 | 169 | int fp, int clear) |
023d8ca2 AJ |
170 | { |
171 | TCGv addr; | |
172 | ||
173 | if (unlikely(ra == 31)) | |
174 | return; | |
175 | ||
a7812ae4 | 176 | addr = tcg_temp_new(); |
023d8ca2 AJ |
177 | if (rb != 31) { |
178 | tcg_gen_addi_i64(addr, cpu_ir[rb], disp16); | |
179 | if (clear) | |
180 | tcg_gen_andi_i64(addr, addr, ~0x7); | |
181 | } else { | |
182 | if (clear) | |
183 | disp16 &= ~0x7; | |
184 | tcg_gen_movi_i64(addr, disp16); | |
185 | } | |
f18cd223 AJ |
186 | if (fp) |
187 | tcg_gen_qemu_load(cpu_fir[ra], addr, ctx->mem_idx); | |
188 | else | |
189 | tcg_gen_qemu_load(cpu_ir[ra], addr, ctx->mem_idx); | |
023d8ca2 AJ |
190 | tcg_temp_free(addr); |
191 | } | |
192 | ||
f18cd223 AJ |
193 | static always_inline void gen_qemu_stf (TCGv t0, TCGv t1, int flags) |
194 | { | |
a7812ae4 PB |
195 | TCGv_i32 tmp32 = tcg_temp_new_i32(); |
196 | TCGv tmp = tcg_temp_new(); | |
197 | gen_helper_f_to_memory(tmp32, t0); | |
198 | tcg_gen_extu_i32_i64(tmp, tmp32); | |
f18cd223 AJ |
199 | tcg_gen_qemu_st32(tmp, t1, flags); |
200 | tcg_temp_free(tmp); | |
a7812ae4 | 201 | tcg_temp_free_i32(tmp32); |
f18cd223 AJ |
202 | } |
203 | ||
204 | static always_inline void gen_qemu_stg (TCGv t0, TCGv t1, int flags) | |
205 | { | |
a7812ae4 PB |
206 | TCGv tmp = tcg_temp_new(); |
207 | gen_helper_g_to_memory(tmp, t0); | |
f18cd223 AJ |
208 | tcg_gen_qemu_st64(tmp, t1, flags); |
209 | tcg_temp_free(tmp); | |
210 | } | |
211 | ||
212 | static always_inline void gen_qemu_sts (TCGv t0, TCGv t1, int flags) | |
213 | { | |
a7812ae4 PB |
214 | TCGv_i32 tmp32 = tcg_temp_new_i32(); |
215 | TCGv tmp = tcg_temp_new(); | |
216 | gen_helper_s_to_memory(tmp32, t0); | |
217 | tcg_gen_extu_i32_i64(tmp, tmp32); | |
f18cd223 AJ |
218 | tcg_gen_qemu_st32(tmp, t1, flags); |
219 | tcg_temp_free(tmp); | |
a7812ae4 | 220 | tcg_temp_free_i32(tmp32); |
f18cd223 AJ |
221 | } |
222 | ||
f4ed8679 AJ |
223 | static always_inline void gen_qemu_stl_c (TCGv t0, TCGv t1, int flags) |
224 | { | |
225 | int l1, l2; | |
226 | ||
227 | l1 = gen_new_label(); | |
228 | l2 = gen_new_label(); | |
229 | tcg_gen_brcond_i64(TCG_COND_NE, cpu_lock, t1, l1); | |
230 | tcg_gen_qemu_st32(t0, t1, flags); | |
6223246a | 231 | tcg_gen_movi_i64(t0, 1); |
f4ed8679 AJ |
232 | tcg_gen_br(l2); |
233 | gen_set_label(l1); | |
6223246a | 234 | tcg_gen_movi_i64(t0, 0); |
f4ed8679 AJ |
235 | gen_set_label(l2); |
236 | tcg_gen_movi_i64(cpu_lock, -1); | |
237 | } | |
238 | ||
239 | static always_inline void gen_qemu_stq_c (TCGv t0, TCGv t1, int flags) | |
240 | { | |
241 | int l1, l2; | |
242 | ||
243 | l1 = gen_new_label(); | |
244 | l2 = gen_new_label(); | |
245 | tcg_gen_brcond_i64(TCG_COND_NE, cpu_lock, t1, l1); | |
246 | tcg_gen_qemu_st64(t0, t1, flags); | |
6223246a | 247 | tcg_gen_movi_i64(t0, 1); |
f4ed8679 AJ |
248 | tcg_gen_br(l2); |
249 | gen_set_label(l1); | |
6223246a | 250 | tcg_gen_movi_i64(t0, 0); |
f4ed8679 AJ |
251 | gen_set_label(l2); |
252 | tcg_gen_movi_i64(cpu_lock, -1); | |
253 | } | |
254 | ||
023d8ca2 AJ |
255 | static always_inline void gen_store_mem (DisasContext *ctx, |
256 | void (*tcg_gen_qemu_store)(TCGv t0, TCGv t1, int flags), | |
257 | int ra, int rb, int32_t disp16, | |
57a92c8e | 258 | int fp, int clear, int local) |
023d8ca2 | 259 | { |
9cd38c23 | 260 | TCGv addr; |
57a92c8e | 261 | if (local) |
a7812ae4 | 262 | addr = tcg_temp_local_new(); |
57a92c8e | 263 | else |
a7812ae4 | 264 | addr = tcg_temp_new(); |
023d8ca2 AJ |
265 | if (rb != 31) { |
266 | tcg_gen_addi_i64(addr, cpu_ir[rb], disp16); | |
267 | if (clear) | |
268 | tcg_gen_andi_i64(addr, addr, ~0x7); | |
269 | } else { | |
270 | if (clear) | |
271 | disp16 &= ~0x7; | |
272 | tcg_gen_movi_i64(addr, disp16); | |
273 | } | |
f18cd223 AJ |
274 | if (ra != 31) { |
275 | if (fp) | |
276 | tcg_gen_qemu_store(cpu_fir[ra], addr, ctx->mem_idx); | |
277 | else | |
278 | tcg_gen_qemu_store(cpu_ir[ra], addr, ctx->mem_idx); | |
279 | } else { | |
57a92c8e AJ |
280 | TCGv zero; |
281 | if (local) | |
282 | zero = tcg_const_local_i64(0); | |
283 | else | |
284 | zero = tcg_const_i64(0); | |
023d8ca2 AJ |
285 | tcg_gen_qemu_store(zero, addr, ctx->mem_idx); |
286 | tcg_temp_free(zero); | |
287 | } | |
288 | tcg_temp_free(addr); | |
289 | } | |
290 | ||
f071b4d3 | 291 | static always_inline void gen_bcond (DisasContext *ctx, |
9c29504e | 292 | TCGCond cond, |
a1516744 | 293 | int ra, int32_t disp, int mask) |
4c9649a9 | 294 | { |
9c29504e AJ |
295 | int l1, l2; |
296 | ||
297 | l1 = gen_new_label(); | |
298 | l2 = gen_new_label(); | |
299 | if (likely(ra != 31)) { | |
300 | if (mask) { | |
a7812ae4 | 301 | TCGv tmp = tcg_temp_new(); |
9c29504e AJ |
302 | tcg_gen_andi_i64(tmp, cpu_ir[ra], 1); |
303 | tcg_gen_brcondi_i64(cond, tmp, 0, l1); | |
304 | tcg_temp_free(tmp); | |
305 | } else | |
306 | tcg_gen_brcondi_i64(cond, cpu_ir[ra], 0, l1); | |
307 | } else { | |
308 | /* Very uncommon case - Do not bother to optimize. */ | |
309 | TCGv tmp = tcg_const_i64(0); | |
310 | tcg_gen_brcondi_i64(cond, tmp, 0, l1); | |
311 | tcg_temp_free(tmp); | |
312 | } | |
313 | tcg_gen_movi_i64(cpu_pc, ctx->pc); | |
314 | tcg_gen_br(l2); | |
315 | gen_set_label(l1); | |
a1516744 | 316 | tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp << 2)); |
9c29504e | 317 | gen_set_label(l2); |
4c9649a9 JM |
318 | } |
319 | ||
a7812ae4 | 320 | static always_inline void gen_fbcond (DisasContext *ctx, int opc, |
f071b4d3 | 321 | int ra, int32_t disp16) |
4c9649a9 | 322 | { |
f18cd223 AJ |
323 | int l1, l2; |
324 | TCGv tmp; | |
a7812ae4 | 325 | TCGv src; |
f18cd223 AJ |
326 | |
327 | l1 = gen_new_label(); | |
328 | l2 = gen_new_label(); | |
329 | if (ra != 31) { | |
a7812ae4 PB |
330 | tmp = tcg_temp_new(); |
331 | src = cpu_fir[ra]; | |
f18cd223 AJ |
332 | } else { |
333 | tmp = tcg_const_i64(0); | |
a7812ae4 PB |
334 | src = tmp; |
335 | } | |
336 | switch (opc) { | |
337 | case 0x31: /* FBEQ */ | |
338 | gen_helper_cmpfeq(tmp, src); | |
339 | break; | |
340 | case 0x32: /* FBLT */ | |
341 | gen_helper_cmpflt(tmp, src); | |
342 | break; | |
343 | case 0x33: /* FBLE */ | |
344 | gen_helper_cmpfle(tmp, src); | |
345 | break; | |
346 | case 0x35: /* FBNE */ | |
347 | gen_helper_cmpfne(tmp, src); | |
348 | break; | |
349 | case 0x36: /* FBGE */ | |
350 | gen_helper_cmpfge(tmp, src); | |
351 | break; | |
352 | case 0x37: /* FBGT */ | |
353 | gen_helper_cmpfgt(tmp, src); | |
354 | break; | |
355 | default: | |
356 | abort(); | |
f18cd223 AJ |
357 | } |
358 | tcg_gen_brcondi_i64(TCG_COND_NE, tmp, 0, l1); | |
359 | tcg_gen_movi_i64(cpu_pc, ctx->pc); | |
360 | tcg_gen_br(l2); | |
361 | gen_set_label(l1); | |
362 | tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp16 << 2)); | |
363 | gen_set_label(l2); | |
4c9649a9 JM |
364 | } |
365 | ||
fe2b269a | 366 | static always_inline void gen_cmov (TCGCond inv_cond, |
f071b4d3 | 367 | int ra, int rb, int rc, |
adf3c8b6 | 368 | int islit, uint8_t lit, int mask) |
4c9649a9 | 369 | { |
9c29504e AJ |
370 | int l1; |
371 | ||
372 | if (unlikely(rc == 31)) | |
373 | return; | |
374 | ||
375 | l1 = gen_new_label(); | |
376 | ||
377 | if (ra != 31) { | |
378 | if (mask) { | |
a7812ae4 | 379 | TCGv tmp = tcg_temp_new(); |
9c29504e AJ |
380 | tcg_gen_andi_i64(tmp, cpu_ir[ra], 1); |
381 | tcg_gen_brcondi_i64(inv_cond, tmp, 0, l1); | |
382 | tcg_temp_free(tmp); | |
383 | } else | |
384 | tcg_gen_brcondi_i64(inv_cond, cpu_ir[ra], 0, l1); | |
385 | } else { | |
386 | /* Very uncommon case - Do not bother to optimize. */ | |
387 | TCGv tmp = tcg_const_i64(0); | |
388 | tcg_gen_brcondi_i64(inv_cond, tmp, 0, l1); | |
389 | tcg_temp_free(tmp); | |
390 | } | |
391 | ||
4c9649a9 | 392 | if (islit) |
9c29504e | 393 | tcg_gen_movi_i64(cpu_ir[rc], lit); |
4c9649a9 | 394 | else |
dfaa8583 | 395 | tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]); |
9c29504e | 396 | gen_set_label(l1); |
4c9649a9 JM |
397 | } |
398 | ||
a7812ae4 PB |
399 | #define FARITH2(name) \ |
400 | static always_inline void glue(gen_f, name)(int rb, int rc) \ | |
401 | { \ | |
402 | if (unlikely(rc == 31)) \ | |
403 | return; \ | |
404 | \ | |
405 | if (rb != 31) \ | |
406 | gen_helper_ ## name (cpu_fir[rc], cpu_fir[rb]); \ | |
407 | else { \ | |
408 | TCGv tmp = tcg_const_i64(0); \ | |
409 | gen_helper_ ## name (cpu_fir[rc], tmp); \ | |
410 | tcg_temp_free(tmp); \ | |
411 | } \ | |
4c9649a9 | 412 | } |
a7812ae4 PB |
413 | FARITH2(sqrts) |
414 | FARITH2(sqrtf) | |
415 | FARITH2(sqrtg) | |
416 | FARITH2(sqrtt) | |
417 | FARITH2(cvtgf) | |
418 | FARITH2(cvtgq) | |
419 | FARITH2(cvtqf) | |
420 | FARITH2(cvtqg) | |
421 | FARITH2(cvtst) | |
422 | FARITH2(cvtts) | |
423 | FARITH2(cvttq) | |
424 | FARITH2(cvtqs) | |
425 | FARITH2(cvtqt) | |
426 | FARITH2(cvtlq) | |
427 | FARITH2(cvtql) | |
428 | FARITH2(cvtqlv) | |
429 | FARITH2(cvtqlsv) | |
430 | ||
431 | #define FARITH3(name) \ | |
432 | static always_inline void glue(gen_f, name) (int ra, int rb, int rc) \ | |
433 | { \ | |
434 | if (unlikely(rc == 31)) \ | |
435 | return; \ | |
436 | \ | |
437 | if (ra != 31) { \ | |
438 | if (rb != 31) \ | |
439 | gen_helper_ ## name (cpu_fir[rc], cpu_fir[ra], cpu_fir[rb]); \ | |
440 | else { \ | |
441 | TCGv tmp = tcg_const_i64(0); \ | |
442 | gen_helper_ ## name (cpu_fir[rc], cpu_fir[ra], tmp); \ | |
443 | tcg_temp_free(tmp); \ | |
444 | } \ | |
445 | } else { \ | |
446 | TCGv tmp = tcg_const_i64(0); \ | |
447 | if (rb != 31) \ | |
448 | gen_helper_ ## name (cpu_fir[rc], tmp, cpu_fir[rb]); \ | |
449 | else \ | |
450 | gen_helper_ ## name (cpu_fir[rc], tmp, tmp); \ | |
451 | tcg_temp_free(tmp); \ | |
452 | } \ | |
4c9649a9 JM |
453 | } |
454 | ||
a7812ae4 PB |
455 | FARITH3(addf) |
456 | FARITH3(subf) | |
457 | FARITH3(mulf) | |
458 | FARITH3(divf) | |
459 | FARITH3(addg) | |
460 | FARITH3(subg) | |
461 | FARITH3(mulg) | |
462 | FARITH3(divg) | |
463 | FARITH3(cmpgeq) | |
464 | FARITH3(cmpglt) | |
465 | FARITH3(cmpgle) | |
466 | FARITH3(adds) | |
467 | FARITH3(subs) | |
468 | FARITH3(muls) | |
469 | FARITH3(divs) | |
470 | FARITH3(addt) | |
471 | FARITH3(subt) | |
472 | FARITH3(mult) | |
473 | FARITH3(divt) | |
474 | FARITH3(cmptun) | |
475 | FARITH3(cmpteq) | |
476 | FARITH3(cmptlt) | |
477 | FARITH3(cmptle) | |
478 | FARITH3(cpys) | |
479 | FARITH3(cpysn) | |
480 | FARITH3(cpyse) | |
481 | ||
482 | #define FCMOV(name) \ | |
483 | static always_inline void glue(gen_f, name) (int ra, int rb, int rc) \ | |
484 | { \ | |
485 | int l1; \ | |
486 | TCGv tmp; \ | |
487 | \ | |
488 | if (unlikely(rc == 31)) \ | |
489 | return; \ | |
490 | \ | |
491 | l1 = gen_new_label(); \ | |
492 | tmp = tcg_temp_new(); \ | |
493 | if (ra != 31) { \ | |
494 | tmp = tcg_temp_new(); \ | |
495 | gen_helper_ ## name (tmp, cpu_fir[ra]); \ | |
496 | } else { \ | |
497 | tmp = tcg_const_i64(0); \ | |
498 | gen_helper_ ## name (tmp, tmp); \ | |
499 | } \ | |
500 | tcg_gen_brcondi_i64(TCG_COND_EQ, tmp, 0, l1); \ | |
501 | if (rb != 31) \ | |
502 | tcg_gen_mov_i64(cpu_fir[rc], cpu_fir[ra]); \ | |
503 | else \ | |
504 | tcg_gen_movi_i64(cpu_fir[rc], 0); \ | |
505 | gen_set_label(l1); \ | |
4c9649a9 | 506 | } |
a7812ae4 PB |
507 | FCMOV(cmpfeq) |
508 | FCMOV(cmpfne) | |
509 | FCMOV(cmpflt) | |
510 | FCMOV(cmpfge) | |
511 | FCMOV(cmpfle) | |
512 | FCMOV(cmpfgt) | |
4c9649a9 | 513 | |
b3249f63 AJ |
514 | /* EXTWH, EXTWH, EXTLH, EXTQH */ |
515 | static always_inline void gen_ext_h(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1), | |
516 | int ra, int rb, int rc, | |
adf3c8b6 | 517 | int islit, uint8_t lit) |
b3249f63 AJ |
518 | { |
519 | if (unlikely(rc == 31)) | |
520 | return; | |
521 | ||
522 | if (ra != 31) { | |
dfaa8583 AJ |
523 | if (islit) { |
524 | if (lit != 0) | |
525 | tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], 64 - ((lit & 7) * 8)); | |
526 | else | |
527 | tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[ra]); | |
fe2b269a | 528 | } else { |
b3249f63 | 529 | TCGv tmp1, tmp2; |
a7812ae4 | 530 | tmp1 = tcg_temp_new(); |
b3249f63 AJ |
531 | tcg_gen_andi_i64(tmp1, cpu_ir[rb], 7); |
532 | tcg_gen_shli_i64(tmp1, tmp1, 3); | |
533 | tmp2 = tcg_const_i64(64); | |
534 | tcg_gen_sub_i64(tmp1, tmp2, tmp1); | |
535 | tcg_temp_free(tmp2); | |
dfaa8583 | 536 | tcg_gen_shl_i64(cpu_ir[rc], cpu_ir[ra], tmp1); |
b3249f63 | 537 | tcg_temp_free(tmp1); |
dfaa8583 AJ |
538 | } |
539 | if (tcg_gen_ext_i64) | |
540 | tcg_gen_ext_i64(cpu_ir[rc], cpu_ir[rc]); | |
b3249f63 AJ |
541 | } else |
542 | tcg_gen_movi_i64(cpu_ir[rc], 0); | |
543 | } | |
544 | ||
545 | /* EXTBL, EXTWL, EXTWL, EXTLL, EXTQL */ | |
546 | static always_inline void gen_ext_l(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1), | |
547 | int ra, int rb, int rc, | |
adf3c8b6 | 548 | int islit, uint8_t lit) |
b3249f63 AJ |
549 | { |
550 | if (unlikely(rc == 31)) | |
551 | return; | |
552 | ||
553 | if (ra != 31) { | |
dfaa8583 AJ |
554 | if (islit) { |
555 | tcg_gen_shri_i64(cpu_ir[rc], cpu_ir[ra], (lit & 7) * 8); | |
556 | } else { | |
a7812ae4 | 557 | TCGv tmp = tcg_temp_new(); |
b3249f63 AJ |
558 | tcg_gen_andi_i64(tmp, cpu_ir[rb], 7); |
559 | tcg_gen_shli_i64(tmp, tmp, 3); | |
dfaa8583 | 560 | tcg_gen_shr_i64(cpu_ir[rc], cpu_ir[ra], tmp); |
b3249f63 | 561 | tcg_temp_free(tmp); |
fe2b269a | 562 | } |
dfaa8583 AJ |
563 | if (tcg_gen_ext_i64) |
564 | tcg_gen_ext_i64(cpu_ir[rc], cpu_ir[rc]); | |
b3249f63 AJ |
565 | } else |
566 | tcg_gen_movi_i64(cpu_ir[rc], 0); | |
567 | } | |
568 | ||
04acd307 | 569 | /* Code to call arith3 helpers */ |
a7812ae4 PB |
570 | #define ARITH3(name) \ |
571 | static always_inline void glue(gen_, name) (int ra, int rb, int rc, \ | |
572 | int islit, uint8_t lit) \ | |
573 | { \ | |
574 | if (unlikely(rc == 31)) \ | |
575 | return; \ | |
576 | \ | |
577 | if (ra != 31) { \ | |
578 | if (islit) { \ | |
579 | TCGv tmp = tcg_const_i64(lit); \ | |
580 | gen_helper_ ## name(cpu_ir[rc], cpu_ir[ra], tmp); \ | |
581 | tcg_temp_free(tmp); \ | |
582 | } else \ | |
583 | gen_helper_ ## name (cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); \ | |
584 | } else { \ | |
585 | TCGv tmp1 = tcg_const_i64(0); \ | |
586 | if (islit) { \ | |
587 | TCGv tmp2 = tcg_const_i64(lit); \ | |
588 | gen_helper_ ## name (cpu_ir[rc], tmp1, tmp2); \ | |
589 | tcg_temp_free(tmp2); \ | |
590 | } else \ | |
591 | gen_helper_ ## name (cpu_ir[rc], tmp1, cpu_ir[rb]); \ | |
592 | tcg_temp_free(tmp1); \ | |
593 | } \ | |
b3249f63 | 594 | } |
a7812ae4 PB |
595 | ARITH3(cmpbge) |
596 | ARITH3(addlv) | |
597 | ARITH3(sublv) | |
598 | ARITH3(addqv) | |
599 | ARITH3(subqv) | |
600 | ARITH3(mskbl) | |
601 | ARITH3(insbl) | |
602 | ARITH3(mskwl) | |
603 | ARITH3(inswl) | |
604 | ARITH3(mskll) | |
605 | ARITH3(insll) | |
606 | ARITH3(zap) | |
607 | ARITH3(zapnot) | |
608 | ARITH3(mskql) | |
609 | ARITH3(insql) | |
610 | ARITH3(mskwh) | |
611 | ARITH3(inswh) | |
612 | ARITH3(msklh) | |
613 | ARITH3(inslh) | |
614 | ARITH3(mskqh) | |
615 | ARITH3(insqh) | |
616 | ARITH3(umulh) | |
617 | ARITH3(mullv) | |
618 | ARITH3(mulqv) | |
b3249f63 | 619 | |
01ff9cc8 AJ |
620 | static always_inline void gen_cmp(TCGCond cond, |
621 | int ra, int rb, int rc, | |
a1cf28f4 | 622 | int islit, uint8_t lit) |
01ff9cc8 AJ |
623 | { |
624 | int l1, l2; | |
625 | TCGv tmp; | |
626 | ||
627 | if (unlikely(rc == 31)) | |
628 | return; | |
629 | ||
630 | l1 = gen_new_label(); | |
631 | l2 = gen_new_label(); | |
632 | ||
633 | if (ra != 31) { | |
a7812ae4 | 634 | tmp = tcg_temp_new(); |
01ff9cc8 AJ |
635 | tcg_gen_mov_i64(tmp, cpu_ir[ra]); |
636 | } else | |
637 | tmp = tcg_const_i64(0); | |
638 | if (islit) | |
639 | tcg_gen_brcondi_i64(cond, tmp, lit, l1); | |
01ff9cc8 | 640 | else |
dfaa8583 | 641 | tcg_gen_brcond_i64(cond, tmp, cpu_ir[rb], l1); |
01ff9cc8 AJ |
642 | |
643 | tcg_gen_movi_i64(cpu_ir[rc], 0); | |
644 | tcg_gen_br(l2); | |
645 | gen_set_label(l1); | |
646 | tcg_gen_movi_i64(cpu_ir[rc], 1); | |
647 | gen_set_label(l2); | |
648 | } | |
649 | ||
f071b4d3 | 650 | static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
4c9649a9 JM |
651 | { |
652 | uint32_t palcode; | |
653 | int32_t disp21, disp16, disp12; | |
654 | uint16_t fn11, fn16; | |
655 | uint8_t opc, ra, rb, rc, sbz, fpfn, fn7, fn2, islit; | |
adf3c8b6 | 656 | uint8_t lit; |
4c9649a9 JM |
657 | int ret; |
658 | ||
659 | /* Decode all instruction fields */ | |
660 | opc = insn >> 26; | |
661 | ra = (insn >> 21) & 0x1F; | |
662 | rb = (insn >> 16) & 0x1F; | |
663 | rc = insn & 0x1F; | |
664 | sbz = (insn >> 13) & 0x07; | |
665 | islit = (insn >> 12) & 1; | |
dfaa8583 AJ |
666 | if (rb == 31 && !islit) { |
667 | islit = 1; | |
668 | lit = 0; | |
669 | } else | |
670 | lit = (insn >> 13) & 0xFF; | |
4c9649a9 JM |
671 | palcode = insn & 0x03FFFFFF; |
672 | disp21 = ((int32_t)((insn & 0x001FFFFF) << 11)) >> 11; | |
673 | disp16 = (int16_t)(insn & 0x0000FFFF); | |
674 | disp12 = (int32_t)((insn & 0x00000FFF) << 20) >> 20; | |
675 | fn16 = insn & 0x0000FFFF; | |
676 | fn11 = (insn >> 5) & 0x000007FF; | |
677 | fpfn = fn11 & 0x3F; | |
678 | fn7 = (insn >> 5) & 0x0000007F; | |
679 | fn2 = (insn >> 5) & 0x00000003; | |
680 | ret = 0; | |
d12d51d5 AL |
681 | LOG_DISAS("opc %02x ra %d rb %d rc %d disp16 %04x\n", |
682 | opc, ra, rb, rc, disp16); | |
4c9649a9 JM |
683 | switch (opc) { |
684 | case 0x00: | |
685 | /* CALL_PAL */ | |
686 | if (palcode >= 0x80 && palcode < 0xC0) { | |
687 | /* Unprivileged PAL call */ | |
31a877f2 | 688 | gen_excp(ctx, EXCP_CALL_PAL + ((palcode & 0x3F) << 6), 0); |
4c9649a9 JM |
689 | #if !defined (CONFIG_USER_ONLY) |
690 | } else if (palcode < 0x40) { | |
691 | /* Privileged PAL code */ | |
692 | if (ctx->mem_idx & 1) | |
693 | goto invalid_opc; | |
694 | else | |
e79ab941 | 695 | gen_excp(ctx, EXCP_CALL_PALP + ((palcode & 0x3F) << 6), 0); |
4c9649a9 JM |
696 | #endif |
697 | } else { | |
698 | /* Invalid PAL call */ | |
699 | goto invalid_opc; | |
700 | } | |
701 | ret = 3; | |
702 | break; | |
703 | case 0x01: | |
704 | /* OPC01 */ | |
705 | goto invalid_opc; | |
706 | case 0x02: | |
707 | /* OPC02 */ | |
708 | goto invalid_opc; | |
709 | case 0x03: | |
710 | /* OPC03 */ | |
711 | goto invalid_opc; | |
712 | case 0x04: | |
713 | /* OPC04 */ | |
714 | goto invalid_opc; | |
715 | case 0x05: | |
716 | /* OPC05 */ | |
717 | goto invalid_opc; | |
718 | case 0x06: | |
719 | /* OPC06 */ | |
720 | goto invalid_opc; | |
721 | case 0x07: | |
722 | /* OPC07 */ | |
723 | goto invalid_opc; | |
724 | case 0x08: | |
725 | /* LDA */ | |
1ef4ef4e | 726 | if (likely(ra != 31)) { |
496cb5b9 | 727 | if (rb != 31) |
3761035f AJ |
728 | tcg_gen_addi_i64(cpu_ir[ra], cpu_ir[rb], disp16); |
729 | else | |
730 | tcg_gen_movi_i64(cpu_ir[ra], disp16); | |
496cb5b9 | 731 | } |
4c9649a9 JM |
732 | break; |
733 | case 0x09: | |
734 | /* LDAH */ | |
1ef4ef4e | 735 | if (likely(ra != 31)) { |
496cb5b9 | 736 | if (rb != 31) |
3761035f AJ |
737 | tcg_gen_addi_i64(cpu_ir[ra], cpu_ir[rb], disp16 << 16); |
738 | else | |
739 | tcg_gen_movi_i64(cpu_ir[ra], disp16 << 16); | |
496cb5b9 | 740 | } |
4c9649a9 JM |
741 | break; |
742 | case 0x0A: | |
743 | /* LDBU */ | |
744 | if (!(ctx->amask & AMASK_BWX)) | |
745 | goto invalid_opc; | |
f18cd223 | 746 | gen_load_mem(ctx, &tcg_gen_qemu_ld8u, ra, rb, disp16, 0, 0); |
4c9649a9 JM |
747 | break; |
748 | case 0x0B: | |
749 | /* LDQ_U */ | |
f18cd223 | 750 | gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 0, 1); |
4c9649a9 JM |
751 | break; |
752 | case 0x0C: | |
753 | /* LDWU */ | |
754 | if (!(ctx->amask & AMASK_BWX)) | |
755 | goto invalid_opc; | |
577d5e7f | 756 | gen_load_mem(ctx, &tcg_gen_qemu_ld16u, ra, rb, disp16, 0, 0); |
4c9649a9 JM |
757 | break; |
758 | case 0x0D: | |
759 | /* STW */ | |
57a92c8e | 760 | gen_store_mem(ctx, &tcg_gen_qemu_st16, ra, rb, disp16, 0, 0, 0); |
4c9649a9 JM |
761 | break; |
762 | case 0x0E: | |
763 | /* STB */ | |
57a92c8e | 764 | gen_store_mem(ctx, &tcg_gen_qemu_st8, ra, rb, disp16, 0, 0, 0); |
4c9649a9 JM |
765 | break; |
766 | case 0x0F: | |
767 | /* STQ_U */ | |
57a92c8e | 768 | gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0, 1, 0); |
4c9649a9 JM |
769 | break; |
770 | case 0x10: | |
771 | switch (fn7) { | |
772 | case 0x00: | |
773 | /* ADDL */ | |
30c7183b AJ |
774 | if (likely(rc != 31)) { |
775 | if (ra != 31) { | |
776 | if (islit) { | |
777 | tcg_gen_addi_i64(cpu_ir[rc], cpu_ir[ra], lit); | |
778 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]); | |
dfaa8583 | 779 | } else { |
30c7183b AJ |
780 | tcg_gen_add_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
781 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]); | |
dfaa8583 | 782 | } |
30c7183b AJ |
783 | } else { |
784 | if (islit) | |
dfaa8583 | 785 | tcg_gen_movi_i64(cpu_ir[rc], lit); |
30c7183b | 786 | else |
dfaa8583 | 787 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rb]); |
30c7183b AJ |
788 | } |
789 | } | |
4c9649a9 JM |
790 | break; |
791 | case 0x02: | |
792 | /* S4ADDL */ | |
30c7183b AJ |
793 | if (likely(rc != 31)) { |
794 | if (ra != 31) { | |
a7812ae4 | 795 | TCGv tmp = tcg_temp_new(); |
dfaa8583 AJ |
796 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 2); |
797 | if (islit) | |
798 | tcg_gen_addi_i64(tmp, tmp, lit); | |
799 | else | |
800 | tcg_gen_add_i64(tmp, tmp, cpu_ir[rb]); | |
801 | tcg_gen_ext32s_i64(cpu_ir[rc], tmp); | |
802 | tcg_temp_free(tmp); | |
30c7183b AJ |
803 | } else { |
804 | if (islit) | |
805 | tcg_gen_movi_i64(cpu_ir[rc], lit); | |
30c7183b | 806 | else |
dfaa8583 | 807 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rb]); |
30c7183b AJ |
808 | } |
809 | } | |
4c9649a9 JM |
810 | break; |
811 | case 0x09: | |
812 | /* SUBL */ | |
30c7183b AJ |
813 | if (likely(rc != 31)) { |
814 | if (ra != 31) { | |
dfaa8583 | 815 | if (islit) |
30c7183b | 816 | tcg_gen_subi_i64(cpu_ir[rc], cpu_ir[ra], lit); |
dfaa8583 | 817 | else |
30c7183b | 818 | tcg_gen_sub_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
dfaa8583 | 819 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]); |
30c7183b AJ |
820 | } else { |
821 | if (islit) | |
822 | tcg_gen_movi_i64(cpu_ir[rc], -lit); | |
dfaa8583 | 823 | else { |
30c7183b AJ |
824 | tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]); |
825 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]); | |
30c7183b AJ |
826 | } |
827 | } | |
4c9649a9 JM |
828 | break; |
829 | case 0x0B: | |
830 | /* S4SUBL */ | |
30c7183b AJ |
831 | if (likely(rc != 31)) { |
832 | if (ra != 31) { | |
a7812ae4 | 833 | TCGv tmp = tcg_temp_new(); |
dfaa8583 AJ |
834 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 2); |
835 | if (islit) | |
836 | tcg_gen_subi_i64(tmp, tmp, lit); | |
837 | else | |
838 | tcg_gen_sub_i64(tmp, tmp, cpu_ir[rb]); | |
839 | tcg_gen_ext32s_i64(cpu_ir[rc], tmp); | |
840 | tcg_temp_free(tmp); | |
30c7183b AJ |
841 | } else { |
842 | if (islit) | |
843 | tcg_gen_movi_i64(cpu_ir[rc], -lit); | |
dfaa8583 | 844 | else { |
30c7183b AJ |
845 | tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]); |
846 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]); | |
dfaa8583 | 847 | } |
30c7183b AJ |
848 | } |
849 | } | |
4c9649a9 JM |
850 | break; |
851 | case 0x0F: | |
852 | /* CMPBGE */ | |
a7812ae4 | 853 | gen_cmpbge(ra, rb, rc, islit, lit); |
4c9649a9 JM |
854 | break; |
855 | case 0x12: | |
856 | /* S8ADDL */ | |
30c7183b AJ |
857 | if (likely(rc != 31)) { |
858 | if (ra != 31) { | |
a7812ae4 | 859 | TCGv tmp = tcg_temp_new(); |
dfaa8583 AJ |
860 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 3); |
861 | if (islit) | |
862 | tcg_gen_addi_i64(tmp, tmp, lit); | |
863 | else | |
864 | tcg_gen_add_i64(tmp, tmp, cpu_ir[rb]); | |
865 | tcg_gen_ext32s_i64(cpu_ir[rc], tmp); | |
866 | tcg_temp_free(tmp); | |
30c7183b AJ |
867 | } else { |
868 | if (islit) | |
869 | tcg_gen_movi_i64(cpu_ir[rc], lit); | |
30c7183b | 870 | else |
dfaa8583 | 871 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rb]); |
30c7183b AJ |
872 | } |
873 | } | |
4c9649a9 JM |
874 | break; |
875 | case 0x1B: | |
876 | /* S8SUBL */ | |
30c7183b AJ |
877 | if (likely(rc != 31)) { |
878 | if (ra != 31) { | |
a7812ae4 | 879 | TCGv tmp = tcg_temp_new(); |
dfaa8583 AJ |
880 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 3); |
881 | if (islit) | |
882 | tcg_gen_subi_i64(tmp, tmp, lit); | |
883 | else | |
884 | tcg_gen_sub_i64(tmp, tmp, cpu_ir[rb]); | |
885 | tcg_gen_ext32s_i64(cpu_ir[rc], tmp); | |
886 | tcg_temp_free(tmp); | |
30c7183b AJ |
887 | } else { |
888 | if (islit) | |
889 | tcg_gen_movi_i64(cpu_ir[rc], -lit); | |
dfaa8583 | 890 | else |
30c7183b AJ |
891 | tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]); |
892 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]); | |
dfaa8583 | 893 | } |
30c7183b AJ |
894 | } |
895 | } | |
4c9649a9 JM |
896 | break; |
897 | case 0x1D: | |
898 | /* CMPULT */ | |
01ff9cc8 | 899 | gen_cmp(TCG_COND_LTU, ra, rb, rc, islit, lit); |
4c9649a9 JM |
900 | break; |
901 | case 0x20: | |
902 | /* ADDQ */ | |
30c7183b AJ |
903 | if (likely(rc != 31)) { |
904 | if (ra != 31) { | |
905 | if (islit) | |
906 | tcg_gen_addi_i64(cpu_ir[rc], cpu_ir[ra], lit); | |
30c7183b | 907 | else |
dfaa8583 | 908 | tcg_gen_add_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
30c7183b AJ |
909 | } else { |
910 | if (islit) | |
911 | tcg_gen_movi_i64(cpu_ir[rc], lit); | |
30c7183b | 912 | else |
dfaa8583 | 913 | tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]); |
30c7183b AJ |
914 | } |
915 | } | |
4c9649a9 JM |
916 | break; |
917 | case 0x22: | |
918 | /* S4ADDQ */ | |
30c7183b AJ |
919 | if (likely(rc != 31)) { |
920 | if (ra != 31) { | |
a7812ae4 | 921 | TCGv tmp = tcg_temp_new(); |
dfaa8583 AJ |
922 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 2); |
923 | if (islit) | |
924 | tcg_gen_addi_i64(cpu_ir[rc], tmp, lit); | |
925 | else | |
926 | tcg_gen_add_i64(cpu_ir[rc], tmp, cpu_ir[rb]); | |
927 | tcg_temp_free(tmp); | |
30c7183b AJ |
928 | } else { |
929 | if (islit) | |
930 | tcg_gen_movi_i64(cpu_ir[rc], lit); | |
30c7183b | 931 | else |
dfaa8583 | 932 | tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]); |
30c7183b AJ |
933 | } |
934 | } | |
4c9649a9 JM |
935 | break; |
936 | case 0x29: | |
937 | /* SUBQ */ | |
30c7183b AJ |
938 | if (likely(rc != 31)) { |
939 | if (ra != 31) { | |
940 | if (islit) | |
941 | tcg_gen_subi_i64(cpu_ir[rc], cpu_ir[ra], lit); | |
30c7183b | 942 | else |
dfaa8583 | 943 | tcg_gen_sub_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
30c7183b AJ |
944 | } else { |
945 | if (islit) | |
946 | tcg_gen_movi_i64(cpu_ir[rc], -lit); | |
30c7183b | 947 | else |
dfaa8583 | 948 | tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]); |
30c7183b AJ |
949 | } |
950 | } | |
4c9649a9 JM |
951 | break; |
952 | case 0x2B: | |
953 | /* S4SUBQ */ | |
30c7183b AJ |
954 | if (likely(rc != 31)) { |
955 | if (ra != 31) { | |
a7812ae4 | 956 | TCGv tmp = tcg_temp_new(); |
dfaa8583 AJ |
957 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 2); |
958 | if (islit) | |
959 | tcg_gen_subi_i64(cpu_ir[rc], tmp, lit); | |
960 | else | |
961 | tcg_gen_sub_i64(cpu_ir[rc], tmp, cpu_ir[rb]); | |
962 | tcg_temp_free(tmp); | |
30c7183b AJ |
963 | } else { |
964 | if (islit) | |
965 | tcg_gen_movi_i64(cpu_ir[rc], -lit); | |
30c7183b | 966 | else |
dfaa8583 | 967 | tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]); |
30c7183b AJ |
968 | } |
969 | } | |
4c9649a9 JM |
970 | break; |
971 | case 0x2D: | |
972 | /* CMPEQ */ | |
01ff9cc8 | 973 | gen_cmp(TCG_COND_EQ, ra, rb, rc, islit, lit); |
4c9649a9 JM |
974 | break; |
975 | case 0x32: | |
976 | /* S8ADDQ */ | |
30c7183b AJ |
977 | if (likely(rc != 31)) { |
978 | if (ra != 31) { | |
a7812ae4 | 979 | TCGv tmp = tcg_temp_new(); |
dfaa8583 AJ |
980 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 3); |
981 | if (islit) | |
982 | tcg_gen_addi_i64(cpu_ir[rc], tmp, lit); | |
983 | else | |
984 | tcg_gen_add_i64(cpu_ir[rc], tmp, cpu_ir[rb]); | |
985 | tcg_temp_free(tmp); | |
30c7183b AJ |
986 | } else { |
987 | if (islit) | |
988 | tcg_gen_movi_i64(cpu_ir[rc], lit); | |
30c7183b | 989 | else |
dfaa8583 | 990 | tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]); |
30c7183b AJ |
991 | } |
992 | } | |
4c9649a9 JM |
993 | break; |
994 | case 0x3B: | |
995 | /* S8SUBQ */ | |
30c7183b AJ |
996 | if (likely(rc != 31)) { |
997 | if (ra != 31) { | |
a7812ae4 | 998 | TCGv tmp = tcg_temp_new(); |
dfaa8583 AJ |
999 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 3); |
1000 | if (islit) | |
1001 | tcg_gen_subi_i64(cpu_ir[rc], tmp, lit); | |
1002 | else | |
1003 | tcg_gen_sub_i64(cpu_ir[rc], tmp, cpu_ir[rb]); | |
1004 | tcg_temp_free(tmp); | |
30c7183b AJ |
1005 | } else { |
1006 | if (islit) | |
1007 | tcg_gen_movi_i64(cpu_ir[rc], -lit); | |
30c7183b | 1008 | else |
dfaa8583 | 1009 | tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]); |
30c7183b AJ |
1010 | } |
1011 | } | |
4c9649a9 JM |
1012 | break; |
1013 | case 0x3D: | |
1014 | /* CMPULE */ | |
01ff9cc8 | 1015 | gen_cmp(TCG_COND_LEU, ra, rb, rc, islit, lit); |
4c9649a9 JM |
1016 | break; |
1017 | case 0x40: | |
1018 | /* ADDL/V */ | |
a7812ae4 | 1019 | gen_addlv(ra, rb, rc, islit, lit); |
4c9649a9 JM |
1020 | break; |
1021 | case 0x49: | |
1022 | /* SUBL/V */ | |
a7812ae4 | 1023 | gen_sublv(ra, rb, rc, islit, lit); |
4c9649a9 JM |
1024 | break; |
1025 | case 0x4D: | |
1026 | /* CMPLT */ | |
01ff9cc8 | 1027 | gen_cmp(TCG_COND_LT, ra, rb, rc, islit, lit); |
4c9649a9 JM |
1028 | break; |
1029 | case 0x60: | |
1030 | /* ADDQ/V */ | |
a7812ae4 | 1031 | gen_addqv(ra, rb, rc, islit, lit); |
4c9649a9 JM |
1032 | break; |
1033 | case 0x69: | |
1034 | /* SUBQ/V */ | |
a7812ae4 | 1035 | gen_subqv(ra, rb, rc, islit, lit); |
4c9649a9 JM |
1036 | break; |
1037 | case 0x6D: | |
1038 | /* CMPLE */ | |
01ff9cc8 | 1039 | gen_cmp(TCG_COND_LE, ra, rb, rc, islit, lit); |
4c9649a9 JM |
1040 | break; |
1041 | default: | |
1042 | goto invalid_opc; | |
1043 | } | |
1044 | break; | |
1045 | case 0x11: | |
1046 | switch (fn7) { | |
1047 | case 0x00: | |
1048 | /* AND */ | |
30c7183b | 1049 | if (likely(rc != 31)) { |
dfaa8583 | 1050 | if (ra == 31) |
30c7183b AJ |
1051 | tcg_gen_movi_i64(cpu_ir[rc], 0); |
1052 | else if (islit) | |
1053 | tcg_gen_andi_i64(cpu_ir[rc], cpu_ir[ra], lit); | |
1054 | else | |
1055 | tcg_gen_and_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); | |
1056 | } | |
4c9649a9 JM |
1057 | break; |
1058 | case 0x08: | |
1059 | /* BIC */ | |
30c7183b AJ |
1060 | if (likely(rc != 31)) { |
1061 | if (ra != 31) { | |
1062 | if (islit) | |
1063 | tcg_gen_andi_i64(cpu_ir[rc], cpu_ir[ra], ~lit); | |
1b581c44 AJ |
1064 | else |
1065 | tcg_gen_andc_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); | |
30c7183b AJ |
1066 | } else |
1067 | tcg_gen_movi_i64(cpu_ir[rc], 0); | |
1068 | } | |
4c9649a9 JM |
1069 | break; |
1070 | case 0x14: | |
1071 | /* CMOVLBS */ | |
fe2b269a | 1072 | gen_cmov(TCG_COND_EQ, ra, rb, rc, islit, lit, 1); |
4c9649a9 JM |
1073 | break; |
1074 | case 0x16: | |
1075 | /* CMOVLBC */ | |
fe2b269a | 1076 | gen_cmov(TCG_COND_NE, ra, rb, rc, islit, lit, 1); |
4c9649a9 JM |
1077 | break; |
1078 | case 0x20: | |
1079 | /* BIS */ | |
30c7183b AJ |
1080 | if (likely(rc != 31)) { |
1081 | if (ra != 31) { | |
1082 | if (islit) | |
1083 | tcg_gen_ori_i64(cpu_ir[rc], cpu_ir[ra], lit); | |
8bb6e981 | 1084 | else |
30c7183b | 1085 | tcg_gen_or_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
4c9649a9 | 1086 | } else { |
30c7183b AJ |
1087 | if (islit) |
1088 | tcg_gen_movi_i64(cpu_ir[rc], lit); | |
30c7183b | 1089 | else |
dfaa8583 | 1090 | tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]); |
4c9649a9 | 1091 | } |
4c9649a9 JM |
1092 | } |
1093 | break; | |
1094 | case 0x24: | |
1095 | /* CMOVEQ */ | |
fe2b269a | 1096 | gen_cmov(TCG_COND_NE, ra, rb, rc, islit, lit, 0); |
4c9649a9 JM |
1097 | break; |
1098 | case 0x26: | |
1099 | /* CMOVNE */ | |
fe2b269a | 1100 | gen_cmov(TCG_COND_EQ, ra, rb, rc, islit, lit, 0); |
4c9649a9 JM |
1101 | break; |
1102 | case 0x28: | |
1103 | /* ORNOT */ | |
30c7183b | 1104 | if (likely(rc != 31)) { |
dfaa8583 | 1105 | if (ra != 31) { |
30c7183b AJ |
1106 | if (islit) |
1107 | tcg_gen_ori_i64(cpu_ir[rc], cpu_ir[ra], ~lit); | |
1b581c44 AJ |
1108 | else |
1109 | tcg_gen_orc_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); | |
30c7183b AJ |
1110 | } else { |
1111 | if (islit) | |
1112 | tcg_gen_movi_i64(cpu_ir[rc], ~lit); | |
1113 | else | |
1114 | tcg_gen_not_i64(cpu_ir[rc], cpu_ir[rb]); | |
1115 | } | |
1116 | } | |
4c9649a9 JM |
1117 | break; |
1118 | case 0x40: | |
1119 | /* XOR */ | |
30c7183b AJ |
1120 | if (likely(rc != 31)) { |
1121 | if (ra != 31) { | |
1122 | if (islit) | |
1123 | tcg_gen_xori_i64(cpu_ir[rc], cpu_ir[ra], lit); | |
30c7183b | 1124 | else |
dfaa8583 | 1125 | tcg_gen_xor_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
30c7183b AJ |
1126 | } else { |
1127 | if (islit) | |
1128 | tcg_gen_movi_i64(cpu_ir[rc], lit); | |
30c7183b | 1129 | else |
dfaa8583 | 1130 | tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]); |
30c7183b AJ |
1131 | } |
1132 | } | |
4c9649a9 JM |
1133 | break; |
1134 | case 0x44: | |
1135 | /* CMOVLT */ | |
fe2b269a | 1136 | gen_cmov(TCG_COND_GE, ra, rb, rc, islit, lit, 0); |
4c9649a9 JM |
1137 | break; |
1138 | case 0x46: | |
1139 | /* CMOVGE */ | |
fe2b269a | 1140 | gen_cmov(TCG_COND_LT, ra, rb, rc, islit, lit, 0); |
4c9649a9 JM |
1141 | break; |
1142 | case 0x48: | |
1143 | /* EQV */ | |
30c7183b AJ |
1144 | if (likely(rc != 31)) { |
1145 | if (ra != 31) { | |
1146 | if (islit) | |
1147 | tcg_gen_xori_i64(cpu_ir[rc], cpu_ir[ra], ~lit); | |
1b581c44 AJ |
1148 | else |
1149 | tcg_gen_eqv_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); | |
30c7183b AJ |
1150 | } else { |
1151 | if (islit) | |
1152 | tcg_gen_movi_i64(cpu_ir[rc], ~lit); | |
30c7183b | 1153 | else |
dfaa8583 | 1154 | tcg_gen_not_i64(cpu_ir[rc], cpu_ir[rb]); |
30c7183b AJ |
1155 | } |
1156 | } | |
4c9649a9 JM |
1157 | break; |
1158 | case 0x61: | |
1159 | /* AMASK */ | |
ae8ecd42 AJ |
1160 | if (likely(rc != 31)) { |
1161 | if (islit) | |
1a1f7dbc | 1162 | tcg_gen_movi_i64(cpu_ir[rc], lit); |
ae8ecd42 | 1163 | else |
1a1f7dbc AJ |
1164 | tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]); |
1165 | switch (ctx->env->implver) { | |
1166 | case IMPLVER_2106x: | |
1167 | /* EV4, EV45, LCA, LCA45 & EV5 */ | |
1168 | break; | |
1169 | case IMPLVER_21164: | |
1170 | case IMPLVER_21264: | |
1171 | case IMPLVER_21364: | |
1172 | tcg_gen_andi_i64(cpu_ir[rc], cpu_ir[rc], | |
1173 | ~(uint64_t)ctx->amask); | |
1174 | break; | |
1175 | } | |
ae8ecd42 | 1176 | } |
4c9649a9 JM |
1177 | break; |
1178 | case 0x64: | |
1179 | /* CMOVLE */ | |
fe2b269a | 1180 | gen_cmov(TCG_COND_GT, ra, rb, rc, islit, lit, 0); |
4c9649a9 JM |
1181 | break; |
1182 | case 0x66: | |
1183 | /* CMOVGT */ | |
fe2b269a | 1184 | gen_cmov(TCG_COND_LE, ra, rb, rc, islit, lit, 0); |
4c9649a9 JM |
1185 | break; |
1186 | case 0x6C: | |
1187 | /* IMPLVER */ | |
3761035f | 1188 | if (rc != 31) |
8579095b | 1189 | tcg_gen_movi_i64(cpu_ir[rc], ctx->env->implver); |
4c9649a9 JM |
1190 | break; |
1191 | default: | |
1192 | goto invalid_opc; | |
1193 | } | |
1194 | break; | |
1195 | case 0x12: | |
1196 | switch (fn7) { | |
1197 | case 0x02: | |
1198 | /* MSKBL */ | |
a7812ae4 | 1199 | gen_mskbl(ra, rb, rc, islit, lit); |
4c9649a9 JM |
1200 | break; |
1201 | case 0x06: | |
1202 | /* EXTBL */ | |
b3249f63 | 1203 | gen_ext_l(&tcg_gen_ext8u_i64, ra, rb, rc, islit, lit); |
4c9649a9 JM |
1204 | break; |
1205 | case 0x0B: | |
1206 | /* INSBL */ | |
a7812ae4 | 1207 | gen_insbl(ra, rb, rc, islit, lit); |
4c9649a9 JM |
1208 | break; |
1209 | case 0x12: | |
1210 | /* MSKWL */ | |
a7812ae4 | 1211 | gen_mskwl(ra, rb, rc, islit, lit); |
4c9649a9 JM |
1212 | break; |
1213 | case 0x16: | |
1214 | /* EXTWL */ | |
b3249f63 | 1215 | gen_ext_l(&tcg_gen_ext16u_i64, ra, rb, rc, islit, lit); |
4c9649a9 JM |
1216 | break; |
1217 | case 0x1B: | |
1218 | /* INSWL */ | |
a7812ae4 | 1219 | gen_inswl(ra, rb, rc, islit, lit); |
4c9649a9 JM |
1220 | break; |
1221 | case 0x22: | |
1222 | /* MSKLL */ | |
a7812ae4 | 1223 | gen_mskll(ra, rb, rc, islit, lit); |
4c9649a9 JM |
1224 | break; |
1225 | case 0x26: | |
1226 | /* EXTLL */ | |
b3249f63 | 1227 | gen_ext_l(&tcg_gen_ext32u_i64, ra, rb, rc, islit, lit); |
4c9649a9 JM |
1228 | break; |
1229 | case 0x2B: | |
1230 | /* INSLL */ | |
a7812ae4 | 1231 | gen_insll(ra, rb, rc, islit, lit); |
4c9649a9 JM |
1232 | break; |
1233 | case 0x30: | |
1234 | /* ZAP */ | |
a7812ae4 | 1235 | gen_zap(ra, rb, rc, islit, lit); |
4c9649a9 JM |
1236 | break; |
1237 | case 0x31: | |
1238 | /* ZAPNOT */ | |
a7812ae4 | 1239 | gen_zapnot(ra, rb, rc, islit, lit); |
4c9649a9 JM |
1240 | break; |
1241 | case 0x32: | |
1242 | /* MSKQL */ | |
a7812ae4 | 1243 | gen_mskql(ra, rb, rc, islit, lit); |
4c9649a9 JM |
1244 | break; |
1245 | case 0x34: | |
1246 | /* SRL */ | |
30c7183b AJ |
1247 | if (likely(rc != 31)) { |
1248 | if (ra != 31) { | |
1249 | if (islit) | |
1250 | tcg_gen_shri_i64(cpu_ir[rc], cpu_ir[ra], lit & 0x3f); | |
dfaa8583 | 1251 | else { |
a7812ae4 | 1252 | TCGv shift = tcg_temp_new(); |
30c7183b AJ |
1253 | tcg_gen_andi_i64(shift, cpu_ir[rb], 0x3f); |
1254 | tcg_gen_shr_i64(cpu_ir[rc], cpu_ir[ra], shift); | |
1255 | tcg_temp_free(shift); | |
dfaa8583 | 1256 | } |
30c7183b AJ |
1257 | } else |
1258 | tcg_gen_movi_i64(cpu_ir[rc], 0); | |
1259 | } | |
4c9649a9 JM |
1260 | break; |
1261 | case 0x36: | |
1262 | /* EXTQL */ | |
b3249f63 | 1263 | gen_ext_l(NULL, ra, rb, rc, islit, lit); |
4c9649a9 JM |
1264 | break; |
1265 | case 0x39: | |
1266 | /* SLL */ | |
30c7183b AJ |
1267 | if (likely(rc != 31)) { |
1268 | if (ra != 31) { | |
1269 | if (islit) | |
1270 | tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], lit & 0x3f); | |
dfaa8583 | 1271 | else { |
a7812ae4 | 1272 | TCGv shift = tcg_temp_new(); |
30c7183b AJ |
1273 | tcg_gen_andi_i64(shift, cpu_ir[rb], 0x3f); |
1274 | tcg_gen_shl_i64(cpu_ir[rc], cpu_ir[ra], shift); | |
1275 | tcg_temp_free(shift); | |
dfaa8583 | 1276 | } |
30c7183b AJ |
1277 | } else |
1278 | tcg_gen_movi_i64(cpu_ir[rc], 0); | |
1279 | } | |
4c9649a9 JM |
1280 | break; |
1281 | case 0x3B: | |
1282 | /* INSQL */ | |
a7812ae4 | 1283 | gen_insql(ra, rb, rc, islit, lit); |
4c9649a9 JM |
1284 | break; |
1285 | case 0x3C: | |
1286 | /* SRA */ | |
30c7183b AJ |
1287 | if (likely(rc != 31)) { |
1288 | if (ra != 31) { | |
1289 | if (islit) | |
1290 | tcg_gen_sari_i64(cpu_ir[rc], cpu_ir[ra], lit & 0x3f); | |
dfaa8583 | 1291 | else { |
a7812ae4 | 1292 | TCGv shift = tcg_temp_new(); |
30c7183b AJ |
1293 | tcg_gen_andi_i64(shift, cpu_ir[rb], 0x3f); |
1294 | tcg_gen_sar_i64(cpu_ir[rc], cpu_ir[ra], shift); | |
1295 | tcg_temp_free(shift); | |
dfaa8583 | 1296 | } |
30c7183b AJ |
1297 | } else |
1298 | tcg_gen_movi_i64(cpu_ir[rc], 0); | |
1299 | } | |
4c9649a9 JM |
1300 | break; |
1301 | case 0x52: | |
1302 | /* MSKWH */ | |
a7812ae4 | 1303 | gen_mskwh(ra, rb, rc, islit, lit); |
4c9649a9 JM |
1304 | break; |
1305 | case 0x57: | |
1306 | /* INSWH */ | |
a7812ae4 | 1307 | gen_inswh(ra, rb, rc, islit, lit); |
4c9649a9 JM |
1308 | break; |
1309 | case 0x5A: | |
1310 | /* EXTWH */ | |
b3249f63 | 1311 | gen_ext_h(&tcg_gen_ext16u_i64, ra, rb, rc, islit, lit); |
4c9649a9 JM |
1312 | break; |
1313 | case 0x62: | |
1314 | /* MSKLH */ | |
a7812ae4 | 1315 | gen_msklh(ra, rb, rc, islit, lit); |
4c9649a9 JM |
1316 | break; |
1317 | case 0x67: | |
1318 | /* INSLH */ | |
a7812ae4 | 1319 | gen_inslh(ra, rb, rc, islit, lit); |
4c9649a9 JM |
1320 | break; |
1321 | case 0x6A: | |
1322 | /* EXTLH */ | |
b3249f63 | 1323 | gen_ext_h(&tcg_gen_ext16u_i64, ra, rb, rc, islit, lit); |
4c9649a9 JM |
1324 | break; |
1325 | case 0x72: | |
1326 | /* MSKQH */ | |
a7812ae4 | 1327 | gen_mskqh(ra, rb, rc, islit, lit); |
4c9649a9 JM |
1328 | break; |
1329 | case 0x77: | |
1330 | /* INSQH */ | |
a7812ae4 | 1331 | gen_insqh(ra, rb, rc, islit, lit); |
4c9649a9 JM |
1332 | break; |
1333 | case 0x7A: | |
1334 | /* EXTQH */ | |
b3249f63 | 1335 | gen_ext_h(NULL, ra, rb, rc, islit, lit); |
4c9649a9 JM |
1336 | break; |
1337 | default: | |
1338 | goto invalid_opc; | |
1339 | } | |
1340 | break; | |
1341 | case 0x13: | |
1342 | switch (fn7) { | |
1343 | case 0x00: | |
1344 | /* MULL */ | |
30c7183b | 1345 | if (likely(rc != 31)) { |
dfaa8583 | 1346 | if (ra == 31) |
30c7183b AJ |
1347 | tcg_gen_movi_i64(cpu_ir[rc], 0); |
1348 | else { | |
1349 | if (islit) | |
1350 | tcg_gen_muli_i64(cpu_ir[rc], cpu_ir[ra], lit); | |
1351 | else | |
1352 | tcg_gen_mul_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); | |
1353 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]); | |
1354 | } | |
1355 | } | |
4c9649a9 JM |
1356 | break; |
1357 | case 0x20: | |
1358 | /* MULQ */ | |
30c7183b | 1359 | if (likely(rc != 31)) { |
dfaa8583 | 1360 | if (ra == 31) |
30c7183b AJ |
1361 | tcg_gen_movi_i64(cpu_ir[rc], 0); |
1362 | else if (islit) | |
1363 | tcg_gen_muli_i64(cpu_ir[rc], cpu_ir[ra], lit); | |
1364 | else | |
1365 | tcg_gen_mul_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); | |
1366 | } | |
4c9649a9 JM |
1367 | break; |
1368 | case 0x30: | |
1369 | /* UMULH */ | |
a7812ae4 | 1370 | gen_umulh(ra, rb, rc, islit, lit); |
4c9649a9 JM |
1371 | break; |
1372 | case 0x40: | |
1373 | /* MULL/V */ | |
a7812ae4 | 1374 | gen_mullv(ra, rb, rc, islit, lit); |
4c9649a9 JM |
1375 | break; |
1376 | case 0x60: | |
1377 | /* MULQ/V */ | |
a7812ae4 | 1378 | gen_mulqv(ra, rb, rc, islit, lit); |
4c9649a9 JM |
1379 | break; |
1380 | default: | |
1381 | goto invalid_opc; | |
1382 | } | |
1383 | break; | |
1384 | case 0x14: | |
1385 | switch (fpfn) { /* f11 & 0x3F */ | |
1386 | case 0x04: | |
1387 | /* ITOFS */ | |
1388 | if (!(ctx->amask & AMASK_FIX)) | |
1389 | goto invalid_opc; | |
f18cd223 AJ |
1390 | if (likely(rc != 31)) { |
1391 | if (ra != 31) { | |
a7812ae4 | 1392 | TCGv_i32 tmp = tcg_temp_new_i32(); |
f18cd223 | 1393 | tcg_gen_trunc_i64_i32(tmp, cpu_ir[ra]); |
a7812ae4 PB |
1394 | gen_helper_memory_to_s(cpu_fir[rc], tmp); |
1395 | tcg_temp_free_i32(tmp); | |
f18cd223 AJ |
1396 | } else |
1397 | tcg_gen_movi_i64(cpu_fir[rc], 0); | |
1398 | } | |
4c9649a9 JM |
1399 | break; |
1400 | case 0x0A: | |
1401 | /* SQRTF */ | |
1402 | if (!(ctx->amask & AMASK_FIX)) | |
1403 | goto invalid_opc; | |
a7812ae4 | 1404 | gen_fsqrtf(rb, rc); |
4c9649a9 JM |
1405 | break; |
1406 | case 0x0B: | |
1407 | /* SQRTS */ | |
1408 | if (!(ctx->amask & AMASK_FIX)) | |
1409 | goto invalid_opc; | |
a7812ae4 | 1410 | gen_fsqrts(rb, rc); |
4c9649a9 JM |
1411 | break; |
1412 | case 0x14: | |
1413 | /* ITOFF */ | |
1414 | if (!(ctx->amask & AMASK_FIX)) | |
1415 | goto invalid_opc; | |
f18cd223 AJ |
1416 | if (likely(rc != 31)) { |
1417 | if (ra != 31) { | |
a7812ae4 | 1418 | TCGv_i32 tmp = tcg_temp_new_i32(); |
f18cd223 | 1419 | tcg_gen_trunc_i64_i32(tmp, cpu_ir[ra]); |
a7812ae4 PB |
1420 | gen_helper_memory_to_f(cpu_fir[rc], tmp); |
1421 | tcg_temp_free_i32(tmp); | |
f18cd223 AJ |
1422 | } else |
1423 | tcg_gen_movi_i64(cpu_fir[rc], 0); | |
1424 | } | |
4c9649a9 JM |
1425 | break; |
1426 | case 0x24: | |
1427 | /* ITOFT */ | |
1428 | if (!(ctx->amask & AMASK_FIX)) | |
1429 | goto invalid_opc; | |
f18cd223 AJ |
1430 | if (likely(rc != 31)) { |
1431 | if (ra != 31) | |
1432 | tcg_gen_mov_i64(cpu_fir[rc], cpu_ir[ra]); | |
1433 | else | |
1434 | tcg_gen_movi_i64(cpu_fir[rc], 0); | |
1435 | } | |
4c9649a9 JM |
1436 | break; |
1437 | case 0x2A: | |
1438 | /* SQRTG */ | |
1439 | if (!(ctx->amask & AMASK_FIX)) | |
1440 | goto invalid_opc; | |
a7812ae4 | 1441 | gen_fsqrtg(rb, rc); |
4c9649a9 JM |
1442 | break; |
1443 | case 0x02B: | |
1444 | /* SQRTT */ | |
1445 | if (!(ctx->amask & AMASK_FIX)) | |
1446 | goto invalid_opc; | |
a7812ae4 | 1447 | gen_fsqrtt(rb, rc); |
4c9649a9 JM |
1448 | break; |
1449 | default: | |
1450 | goto invalid_opc; | |
1451 | } | |
1452 | break; | |
1453 | case 0x15: | |
1454 | /* VAX floating point */ | |
1455 | /* XXX: rounding mode and trap are ignored (!) */ | |
1456 | switch (fpfn) { /* f11 & 0x3F */ | |
1457 | case 0x00: | |
1458 | /* ADDF */ | |
a7812ae4 | 1459 | gen_faddf(ra, rb, rc); |
4c9649a9 JM |
1460 | break; |
1461 | case 0x01: | |
1462 | /* SUBF */ | |
a7812ae4 | 1463 | gen_fsubf(ra, rb, rc); |
4c9649a9 JM |
1464 | break; |
1465 | case 0x02: | |
1466 | /* MULF */ | |
a7812ae4 | 1467 | gen_fmulf(ra, rb, rc); |
4c9649a9 JM |
1468 | break; |
1469 | case 0x03: | |
1470 | /* DIVF */ | |
a7812ae4 | 1471 | gen_fdivf(ra, rb, rc); |
4c9649a9 JM |
1472 | break; |
1473 | case 0x1E: | |
1474 | /* CVTDG */ | |
1475 | #if 0 // TODO | |
a7812ae4 | 1476 | gen_fcvtdg(rb, rc); |
4c9649a9 JM |
1477 | #else |
1478 | goto invalid_opc; | |
1479 | #endif | |
1480 | break; | |
1481 | case 0x20: | |
1482 | /* ADDG */ | |
a7812ae4 | 1483 | gen_faddg(ra, rb, rc); |
4c9649a9 JM |
1484 | break; |
1485 | case 0x21: | |
1486 | /* SUBG */ | |
a7812ae4 | 1487 | gen_fsubg(ra, rb, rc); |
4c9649a9 JM |
1488 | break; |
1489 | case 0x22: | |
1490 | /* MULG */ | |
a7812ae4 | 1491 | gen_fmulg(ra, rb, rc); |
4c9649a9 JM |
1492 | break; |
1493 | case 0x23: | |
1494 | /* DIVG */ | |
a7812ae4 | 1495 | gen_fdivg(ra, rb, rc); |
4c9649a9 JM |
1496 | break; |
1497 | case 0x25: | |
1498 | /* CMPGEQ */ | |
a7812ae4 | 1499 | gen_fcmpgeq(ra, rb, rc); |
4c9649a9 JM |
1500 | break; |
1501 | case 0x26: | |
1502 | /* CMPGLT */ | |
a7812ae4 | 1503 | gen_fcmpglt(ra, rb, rc); |
4c9649a9 JM |
1504 | break; |
1505 | case 0x27: | |
1506 | /* CMPGLE */ | |
a7812ae4 | 1507 | gen_fcmpgle(ra, rb, rc); |
4c9649a9 JM |
1508 | break; |
1509 | case 0x2C: | |
1510 | /* CVTGF */ | |
a7812ae4 | 1511 | gen_fcvtgf(rb, rc); |
4c9649a9 JM |
1512 | break; |
1513 | case 0x2D: | |
1514 | /* CVTGD */ | |
1515 | #if 0 // TODO | |
a7812ae4 | 1516 | gen_fcvtgd(rb, rc); |
4c9649a9 JM |
1517 | #else |
1518 | goto invalid_opc; | |
1519 | #endif | |
1520 | break; | |
1521 | case 0x2F: | |
1522 | /* CVTGQ */ | |
a7812ae4 | 1523 | gen_fcvtgq(rb, rc); |
4c9649a9 JM |
1524 | break; |
1525 | case 0x3C: | |
1526 | /* CVTQF */ | |
a7812ae4 | 1527 | gen_fcvtqf(rb, rc); |
4c9649a9 JM |
1528 | break; |
1529 | case 0x3E: | |
1530 | /* CVTQG */ | |
a7812ae4 | 1531 | gen_fcvtqg(rb, rc); |
4c9649a9 JM |
1532 | break; |
1533 | default: | |
1534 | goto invalid_opc; | |
1535 | } | |
1536 | break; | |
1537 | case 0x16: | |
1538 | /* IEEE floating-point */ | |
1539 | /* XXX: rounding mode and traps are ignored (!) */ | |
1540 | switch (fpfn) { /* f11 & 0x3F */ | |
1541 | case 0x00: | |
1542 | /* ADDS */ | |
a7812ae4 | 1543 | gen_fadds(ra, rb, rc); |
4c9649a9 JM |
1544 | break; |
1545 | case 0x01: | |
1546 | /* SUBS */ | |
a7812ae4 | 1547 | gen_fsubs(ra, rb, rc); |
4c9649a9 JM |
1548 | break; |
1549 | case 0x02: | |
1550 | /* MULS */ | |
a7812ae4 | 1551 | gen_fmuls(ra, rb, rc); |
4c9649a9 JM |
1552 | break; |
1553 | case 0x03: | |
1554 | /* DIVS */ | |
a7812ae4 | 1555 | gen_fdivs(ra, rb, rc); |
4c9649a9 JM |
1556 | break; |
1557 | case 0x20: | |
1558 | /* ADDT */ | |
a7812ae4 | 1559 | gen_faddt(ra, rb, rc); |
4c9649a9 JM |
1560 | break; |
1561 | case 0x21: | |
1562 | /* SUBT */ | |
a7812ae4 | 1563 | gen_fsubt(ra, rb, rc); |
4c9649a9 JM |
1564 | break; |
1565 | case 0x22: | |
1566 | /* MULT */ | |
a7812ae4 | 1567 | gen_fmult(ra, rb, rc); |
4c9649a9 JM |
1568 | break; |
1569 | case 0x23: | |
1570 | /* DIVT */ | |
a7812ae4 | 1571 | gen_fdivt(ra, rb, rc); |
4c9649a9 JM |
1572 | break; |
1573 | case 0x24: | |
1574 | /* CMPTUN */ | |
a7812ae4 | 1575 | gen_fcmptun(ra, rb, rc); |
4c9649a9 JM |
1576 | break; |
1577 | case 0x25: | |
1578 | /* CMPTEQ */ | |
a7812ae4 | 1579 | gen_fcmpteq(ra, rb, rc); |
4c9649a9 JM |
1580 | break; |
1581 | case 0x26: | |
1582 | /* CMPTLT */ | |
a7812ae4 | 1583 | gen_fcmptlt(ra, rb, rc); |
4c9649a9 JM |
1584 | break; |
1585 | case 0x27: | |
1586 | /* CMPTLE */ | |
a7812ae4 | 1587 | gen_fcmptle(ra, rb, rc); |
4c9649a9 JM |
1588 | break; |
1589 | case 0x2C: | |
1590 | /* XXX: incorrect */ | |
a74b4d2c | 1591 | if (fn11 == 0x2AC || fn11 == 0x6AC) { |
4c9649a9 | 1592 | /* CVTST */ |
a7812ae4 | 1593 | gen_fcvtst(rb, rc); |
4c9649a9 JM |
1594 | } else { |
1595 | /* CVTTS */ | |
a7812ae4 | 1596 | gen_fcvtts(rb, rc); |
4c9649a9 JM |
1597 | } |
1598 | break; | |
1599 | case 0x2F: | |
1600 | /* CVTTQ */ | |
a7812ae4 | 1601 | gen_fcvttq(rb, rc); |
4c9649a9 JM |
1602 | break; |
1603 | case 0x3C: | |
1604 | /* CVTQS */ | |
a7812ae4 | 1605 | gen_fcvtqs(rb, rc); |
4c9649a9 JM |
1606 | break; |
1607 | case 0x3E: | |
1608 | /* CVTQT */ | |
a7812ae4 | 1609 | gen_fcvtqt(rb, rc); |
4c9649a9 JM |
1610 | break; |
1611 | default: | |
1612 | goto invalid_opc; | |
1613 | } | |
1614 | break; | |
1615 | case 0x17: | |
1616 | switch (fn11) { | |
1617 | case 0x010: | |
1618 | /* CVTLQ */ | |
a7812ae4 | 1619 | gen_fcvtlq(rb, rc); |
4c9649a9 JM |
1620 | break; |
1621 | case 0x020: | |
f18cd223 AJ |
1622 | if (likely(rc != 31)) { |
1623 | if (ra == rb) | |
4c9649a9 | 1624 | /* FMOV */ |
f18cd223 AJ |
1625 | tcg_gen_mov_i64(cpu_fir[rc], cpu_fir[ra]); |
1626 | else | |
1627 | /* CPYS */ | |
a7812ae4 | 1628 | gen_fcpys(ra, rb, rc); |
4c9649a9 JM |
1629 | } |
1630 | break; | |
1631 | case 0x021: | |
1632 | /* CPYSN */ | |
a7812ae4 | 1633 | gen_fcpysn(ra, rb, rc); |
4c9649a9 JM |
1634 | break; |
1635 | case 0x022: | |
1636 | /* CPYSE */ | |
a7812ae4 | 1637 | gen_fcpyse(ra, rb, rc); |
4c9649a9 JM |
1638 | break; |
1639 | case 0x024: | |
1640 | /* MT_FPCR */ | |
f18cd223 | 1641 | if (likely(ra != 31)) |
a7812ae4 | 1642 | gen_helper_store_fpcr(cpu_fir[ra]); |
f18cd223 AJ |
1643 | else { |
1644 | TCGv tmp = tcg_const_i64(0); | |
a7812ae4 | 1645 | gen_helper_store_fpcr(tmp); |
f18cd223 AJ |
1646 | tcg_temp_free(tmp); |
1647 | } | |
4c9649a9 JM |
1648 | break; |
1649 | case 0x025: | |
1650 | /* MF_FPCR */ | |
f18cd223 | 1651 | if (likely(ra != 31)) |
a7812ae4 | 1652 | gen_helper_load_fpcr(cpu_fir[ra]); |
4c9649a9 JM |
1653 | break; |
1654 | case 0x02A: | |
1655 | /* FCMOVEQ */ | |
a7812ae4 | 1656 | gen_fcmpfeq(ra, rb, rc); |
4c9649a9 JM |
1657 | break; |
1658 | case 0x02B: | |
1659 | /* FCMOVNE */ | |
a7812ae4 | 1660 | gen_fcmpfne(ra, rb, rc); |
4c9649a9 JM |
1661 | break; |
1662 | case 0x02C: | |
1663 | /* FCMOVLT */ | |
a7812ae4 | 1664 | gen_fcmpflt(ra, rb, rc); |
4c9649a9 JM |
1665 | break; |
1666 | case 0x02D: | |
1667 | /* FCMOVGE */ | |
a7812ae4 | 1668 | gen_fcmpfge(ra, rb, rc); |
4c9649a9 JM |
1669 | break; |
1670 | case 0x02E: | |
1671 | /* FCMOVLE */ | |
a7812ae4 | 1672 | gen_fcmpfle(ra, rb, rc); |
4c9649a9 JM |
1673 | break; |
1674 | case 0x02F: | |
1675 | /* FCMOVGT */ | |
a7812ae4 | 1676 | gen_fcmpfgt(ra, rb, rc); |
4c9649a9 JM |
1677 | break; |
1678 | case 0x030: | |
1679 | /* CVTQL */ | |
a7812ae4 | 1680 | gen_fcvtql(rb, rc); |
4c9649a9 JM |
1681 | break; |
1682 | case 0x130: | |
1683 | /* CVTQL/V */ | |
a7812ae4 | 1684 | gen_fcvtqlv(rb, rc); |
4c9649a9 JM |
1685 | break; |
1686 | case 0x530: | |
1687 | /* CVTQL/SV */ | |
a7812ae4 | 1688 | gen_fcvtqlsv(rb, rc); |
4c9649a9 JM |
1689 | break; |
1690 | default: | |
1691 | goto invalid_opc; | |
1692 | } | |
1693 | break; | |
1694 | case 0x18: | |
1695 | switch ((uint16_t)disp16) { | |
1696 | case 0x0000: | |
1697 | /* TRAPB */ | |
1698 | /* No-op. Just exit from the current tb */ | |
1699 | ret = 2; | |
1700 | break; | |
1701 | case 0x0400: | |
1702 | /* EXCB */ | |
1703 | /* No-op. Just exit from the current tb */ | |
1704 | ret = 2; | |
1705 | break; | |
1706 | case 0x4000: | |
1707 | /* MB */ | |
1708 | /* No-op */ | |
1709 | break; | |
1710 | case 0x4400: | |
1711 | /* WMB */ | |
1712 | /* No-op */ | |
1713 | break; | |
1714 | case 0x8000: | |
1715 | /* FETCH */ | |
1716 | /* No-op */ | |
1717 | break; | |
1718 | case 0xA000: | |
1719 | /* FETCH_M */ | |
1720 | /* No-op */ | |
1721 | break; | |
1722 | case 0xC000: | |
1723 | /* RPCC */ | |
3761035f | 1724 | if (ra != 31) |
a7812ae4 | 1725 | gen_helper_load_pcc(cpu_ir[ra]); |
4c9649a9 JM |
1726 | break; |
1727 | case 0xE000: | |
1728 | /* RC */ | |
3761035f | 1729 | if (ra != 31) |
a7812ae4 | 1730 | gen_helper_rc(cpu_ir[ra]); |
4c9649a9 JM |
1731 | break; |
1732 | case 0xE800: | |
1733 | /* ECB */ | |
4c9649a9 JM |
1734 | break; |
1735 | case 0xF000: | |
1736 | /* RS */ | |
3761035f | 1737 | if (ra != 31) |
a7812ae4 | 1738 | gen_helper_rs(cpu_ir[ra]); |
4c9649a9 JM |
1739 | break; |
1740 | case 0xF800: | |
1741 | /* WH64 */ | |
1742 | /* No-op */ | |
1743 | break; | |
1744 | default: | |
1745 | goto invalid_opc; | |
1746 | } | |
1747 | break; | |
1748 | case 0x19: | |
1749 | /* HW_MFPR (PALcode) */ | |
1750 | #if defined (CONFIG_USER_ONLY) | |
1751 | goto invalid_opc; | |
1752 | #else | |
1753 | if (!ctx->pal_mode) | |
1754 | goto invalid_opc; | |
8bb6e981 AJ |
1755 | if (ra != 31) { |
1756 | TCGv tmp = tcg_const_i32(insn & 0xFF); | |
a7812ae4 | 1757 | gen_helper_mfpr(cpu_ir[ra], tmp, cpu_ir[ra]); |
8bb6e981 AJ |
1758 | tcg_temp_free(tmp); |
1759 | } | |
4c9649a9 JM |
1760 | break; |
1761 | #endif | |
1762 | case 0x1A: | |
3761035f AJ |
1763 | if (rb != 31) |
1764 | tcg_gen_andi_i64(cpu_pc, cpu_ir[rb], ~3); | |
1765 | else | |
1766 | tcg_gen_movi_i64(cpu_pc, 0); | |
1304ca87 AJ |
1767 | if (ra != 31) |
1768 | tcg_gen_movi_i64(cpu_ir[ra], ctx->pc); | |
4c9649a9 JM |
1769 | /* Those four jumps only differ by the branch prediction hint */ |
1770 | switch (fn2) { | |
1771 | case 0x0: | |
1772 | /* JMP */ | |
1773 | break; | |
1774 | case 0x1: | |
1775 | /* JSR */ | |
1776 | break; | |
1777 | case 0x2: | |
1778 | /* RET */ | |
1779 | break; | |
1780 | case 0x3: | |
1781 | /* JSR_COROUTINE */ | |
1782 | break; | |
1783 | } | |
1784 | ret = 1; | |
1785 | break; | |
1786 | case 0x1B: | |
1787 | /* HW_LD (PALcode) */ | |
1788 | #if defined (CONFIG_USER_ONLY) | |
1789 | goto invalid_opc; | |
1790 | #else | |
1791 | if (!ctx->pal_mode) | |
1792 | goto invalid_opc; | |
8bb6e981 | 1793 | if (ra != 31) { |
a7812ae4 | 1794 | TCGv addr = tcg_temp_new(); |
8bb6e981 AJ |
1795 | if (rb != 31) |
1796 | tcg_gen_addi_i64(addr, cpu_ir[rb], disp12); | |
1797 | else | |
1798 | tcg_gen_movi_i64(addr, disp12); | |
1799 | switch ((insn >> 12) & 0xF) { | |
1800 | case 0x0: | |
b5d51029 | 1801 | /* Longword physical access (hw_ldl/p) */ |
a7812ae4 | 1802 | gen_helper_ldl_raw(cpu_ir[ra], addr); |
8bb6e981 AJ |
1803 | break; |
1804 | case 0x1: | |
b5d51029 | 1805 | /* Quadword physical access (hw_ldq/p) */ |
a7812ae4 | 1806 | gen_helper_ldq_raw(cpu_ir[ra], addr); |
8bb6e981 AJ |
1807 | break; |
1808 | case 0x2: | |
b5d51029 | 1809 | /* Longword physical access with lock (hw_ldl_l/p) */ |
a7812ae4 | 1810 | gen_helper_ldl_l_raw(cpu_ir[ra], addr); |
8bb6e981 AJ |
1811 | break; |
1812 | case 0x3: | |
b5d51029 | 1813 | /* Quadword physical access with lock (hw_ldq_l/p) */ |
a7812ae4 | 1814 | gen_helper_ldq_l_raw(cpu_ir[ra], addr); |
8bb6e981 AJ |
1815 | break; |
1816 | case 0x4: | |
b5d51029 AJ |
1817 | /* Longword virtual PTE fetch (hw_ldl/v) */ |
1818 | tcg_gen_qemu_ld32s(cpu_ir[ra], addr, 0); | |
8bb6e981 AJ |
1819 | break; |
1820 | case 0x5: | |
b5d51029 AJ |
1821 | /* Quadword virtual PTE fetch (hw_ldq/v) */ |
1822 | tcg_gen_qemu_ld64(cpu_ir[ra], addr, 0); | |
8bb6e981 AJ |
1823 | break; |
1824 | case 0x6: | |
1825 | /* Incpu_ir[ra]id */ | |
b5d51029 | 1826 | goto invalid_opc; |
8bb6e981 AJ |
1827 | case 0x7: |
1828 | /* Incpu_ir[ra]id */ | |
b5d51029 | 1829 | goto invalid_opc; |
8bb6e981 | 1830 | case 0x8: |
b5d51029 | 1831 | /* Longword virtual access (hw_ldl) */ |
a7812ae4 PB |
1832 | gen_helper_st_virt_to_phys(addr, addr); |
1833 | gen_helper_ldl_raw(cpu_ir[ra], addr); | |
8bb6e981 AJ |
1834 | break; |
1835 | case 0x9: | |
b5d51029 | 1836 | /* Quadword virtual access (hw_ldq) */ |
a7812ae4 PB |
1837 | gen_helper_st_virt_to_phys(addr, addr); |
1838 | gen_helper_ldq_raw(cpu_ir[ra], addr); | |
8bb6e981 AJ |
1839 | break; |
1840 | case 0xA: | |
b5d51029 AJ |
1841 | /* Longword virtual access with protection check (hw_ldl/w) */ |
1842 | tcg_gen_qemu_ld32s(cpu_ir[ra], addr, 0); | |
8bb6e981 AJ |
1843 | break; |
1844 | case 0xB: | |
b5d51029 AJ |
1845 | /* Quadword virtual access with protection check (hw_ldq/w) */ |
1846 | tcg_gen_qemu_ld64(cpu_ir[ra], addr, 0); | |
8bb6e981 AJ |
1847 | break; |
1848 | case 0xC: | |
b5d51029 | 1849 | /* Longword virtual access with alt access mode (hw_ldl/a)*/ |
a7812ae4 PB |
1850 | gen_helper_set_alt_mode(); |
1851 | gen_helper_st_virt_to_phys(addr, addr); | |
1852 | gen_helper_ldl_raw(cpu_ir[ra], addr); | |
1853 | gen_helper_restore_mode(); | |
8bb6e981 AJ |
1854 | break; |
1855 | case 0xD: | |
b5d51029 | 1856 | /* Quadword virtual access with alt access mode (hw_ldq/a) */ |
a7812ae4 PB |
1857 | gen_helper_set_alt_mode(); |
1858 | gen_helper_st_virt_to_phys(addr, addr); | |
1859 | gen_helper_ldq_raw(cpu_ir[ra], addr); | |
1860 | gen_helper_restore_mode(); | |
8bb6e981 AJ |
1861 | break; |
1862 | case 0xE: | |
1863 | /* Longword virtual access with alternate access mode and | |
b5d51029 | 1864 | * protection checks (hw_ldl/wa) |
8bb6e981 | 1865 | */ |
a7812ae4 PB |
1866 | gen_helper_set_alt_mode(); |
1867 | gen_helper_ldl_data(cpu_ir[ra], addr); | |
1868 | gen_helper_restore_mode(); | |
8bb6e981 AJ |
1869 | break; |
1870 | case 0xF: | |
1871 | /* Quadword virtual access with alternate access mode and | |
b5d51029 | 1872 | * protection checks (hw_ldq/wa) |
8bb6e981 | 1873 | */ |
a7812ae4 PB |
1874 | gen_helper_set_alt_mode(); |
1875 | gen_helper_ldq_data(cpu_ir[ra], addr); | |
1876 | gen_helper_restore_mode(); | |
8bb6e981 AJ |
1877 | break; |
1878 | } | |
1879 | tcg_temp_free(addr); | |
4c9649a9 | 1880 | } |
4c9649a9 JM |
1881 | break; |
1882 | #endif | |
1883 | case 0x1C: | |
1884 | switch (fn7) { | |
1885 | case 0x00: | |
1886 | /* SEXTB */ | |
1887 | if (!(ctx->amask & AMASK_BWX)) | |
1888 | goto invalid_opc; | |
ae8ecd42 AJ |
1889 | if (likely(rc != 31)) { |
1890 | if (islit) | |
1891 | tcg_gen_movi_i64(cpu_ir[rc], (int64_t)((int8_t)lit)); | |
ae8ecd42 | 1892 | else |
dfaa8583 | 1893 | tcg_gen_ext8s_i64(cpu_ir[rc], cpu_ir[rb]); |
ae8ecd42 | 1894 | } |
4c9649a9 JM |
1895 | break; |
1896 | case 0x01: | |
1897 | /* SEXTW */ | |
1898 | if (!(ctx->amask & AMASK_BWX)) | |
1899 | goto invalid_opc; | |
ae8ecd42 AJ |
1900 | if (likely(rc != 31)) { |
1901 | if (islit) | |
1902 | tcg_gen_movi_i64(cpu_ir[rc], (int64_t)((int16_t)lit)); | |
ae8ecd42 | 1903 | else |
dfaa8583 | 1904 | tcg_gen_ext16s_i64(cpu_ir[rc], cpu_ir[rb]); |
ae8ecd42 | 1905 | } |
4c9649a9 JM |
1906 | break; |
1907 | case 0x30: | |
1908 | /* CTPOP */ | |
1909 | if (!(ctx->amask & AMASK_CIX)) | |
1910 | goto invalid_opc; | |
ae8ecd42 AJ |
1911 | if (likely(rc != 31)) { |
1912 | if (islit) | |
1913 | tcg_gen_movi_i64(cpu_ir[rc], ctpop64(lit)); | |
ae8ecd42 | 1914 | else |
a7812ae4 | 1915 | gen_helper_ctpop(cpu_ir[rc], cpu_ir[rb]); |
ae8ecd42 | 1916 | } |
4c9649a9 JM |
1917 | break; |
1918 | case 0x31: | |
1919 | /* PERR */ | |
1920 | if (!(ctx->amask & AMASK_MVI)) | |
1921 | goto invalid_opc; | |
1922 | /* XXX: TODO */ | |
1923 | goto invalid_opc; | |
1924 | break; | |
1925 | case 0x32: | |
1926 | /* CTLZ */ | |
1927 | if (!(ctx->amask & AMASK_CIX)) | |
1928 | goto invalid_opc; | |
ae8ecd42 AJ |
1929 | if (likely(rc != 31)) { |
1930 | if (islit) | |
1931 | tcg_gen_movi_i64(cpu_ir[rc], clz64(lit)); | |
ae8ecd42 | 1932 | else |
a7812ae4 | 1933 | gen_helper_ctlz(cpu_ir[rc], cpu_ir[rb]); |
ae8ecd42 | 1934 | } |
4c9649a9 JM |
1935 | break; |
1936 | case 0x33: | |
1937 | /* CTTZ */ | |
1938 | if (!(ctx->amask & AMASK_CIX)) | |
1939 | goto invalid_opc; | |
ae8ecd42 AJ |
1940 | if (likely(rc != 31)) { |
1941 | if (islit) | |
1942 | tcg_gen_movi_i64(cpu_ir[rc], ctz64(lit)); | |
ae8ecd42 | 1943 | else |
a7812ae4 | 1944 | gen_helper_cttz(cpu_ir[rc], cpu_ir[rb]); |
ae8ecd42 | 1945 | } |
4c9649a9 JM |
1946 | break; |
1947 | case 0x34: | |
1948 | /* UNPKBW */ | |
1949 | if (!(ctx->amask & AMASK_MVI)) | |
1950 | goto invalid_opc; | |
1951 | /* XXX: TODO */ | |
1952 | goto invalid_opc; | |
1953 | break; | |
1954 | case 0x35: | |
1955 | /* UNPKWL */ | |
1956 | if (!(ctx->amask & AMASK_MVI)) | |
1957 | goto invalid_opc; | |
1958 | /* XXX: TODO */ | |
1959 | goto invalid_opc; | |
1960 | break; | |
1961 | case 0x36: | |
1962 | /* PKWB */ | |
1963 | if (!(ctx->amask & AMASK_MVI)) | |
1964 | goto invalid_opc; | |
1965 | /* XXX: TODO */ | |
1966 | goto invalid_opc; | |
1967 | break; | |
1968 | case 0x37: | |
1969 | /* PKLB */ | |
1970 | if (!(ctx->amask & AMASK_MVI)) | |
1971 | goto invalid_opc; | |
1972 | /* XXX: TODO */ | |
1973 | goto invalid_opc; | |
1974 | break; | |
1975 | case 0x38: | |
1976 | /* MINSB8 */ | |
1977 | if (!(ctx->amask & AMASK_MVI)) | |
1978 | goto invalid_opc; | |
1979 | /* XXX: TODO */ | |
1980 | goto invalid_opc; | |
1981 | break; | |
1982 | case 0x39: | |
1983 | /* MINSW4 */ | |
1984 | if (!(ctx->amask & AMASK_MVI)) | |
1985 | goto invalid_opc; | |
1986 | /* XXX: TODO */ | |
1987 | goto invalid_opc; | |
1988 | break; | |
1989 | case 0x3A: | |
1990 | /* MINUB8 */ | |
1991 | if (!(ctx->amask & AMASK_MVI)) | |
1992 | goto invalid_opc; | |
1993 | /* XXX: TODO */ | |
1994 | goto invalid_opc; | |
1995 | break; | |
1996 | case 0x3B: | |
1997 | /* MINUW4 */ | |
1998 | if (!(ctx->amask & AMASK_MVI)) | |
1999 | goto invalid_opc; | |
2000 | /* XXX: TODO */ | |
2001 | goto invalid_opc; | |
2002 | break; | |
2003 | case 0x3C: | |
2004 | /* MAXUB8 */ | |
2005 | if (!(ctx->amask & AMASK_MVI)) | |
2006 | goto invalid_opc; | |
2007 | /* XXX: TODO */ | |
2008 | goto invalid_opc; | |
2009 | break; | |
2010 | case 0x3D: | |
2011 | /* MAXUW4 */ | |
2012 | if (!(ctx->amask & AMASK_MVI)) | |
2013 | goto invalid_opc; | |
2014 | /* XXX: TODO */ | |
2015 | goto invalid_opc; | |
2016 | break; | |
2017 | case 0x3E: | |
2018 | /* MAXSB8 */ | |
2019 | if (!(ctx->amask & AMASK_MVI)) | |
2020 | goto invalid_opc; | |
2021 | /* XXX: TODO */ | |
2022 | goto invalid_opc; | |
2023 | break; | |
2024 | case 0x3F: | |
2025 | /* MAXSW4 */ | |
2026 | if (!(ctx->amask & AMASK_MVI)) | |
2027 | goto invalid_opc; | |
2028 | /* XXX: TODO */ | |
2029 | goto invalid_opc; | |
2030 | break; | |
2031 | case 0x70: | |
2032 | /* FTOIT */ | |
2033 | if (!(ctx->amask & AMASK_FIX)) | |
2034 | goto invalid_opc; | |
f18cd223 AJ |
2035 | if (likely(rc != 31)) { |
2036 | if (ra != 31) | |
2037 | tcg_gen_mov_i64(cpu_ir[rc], cpu_fir[ra]); | |
2038 | else | |
2039 | tcg_gen_movi_i64(cpu_ir[rc], 0); | |
2040 | } | |
4c9649a9 JM |
2041 | break; |
2042 | case 0x78: | |
2043 | /* FTOIS */ | |
2044 | if (!(ctx->amask & AMASK_FIX)) | |
2045 | goto invalid_opc; | |
f18cd223 | 2046 | if (rc != 31) { |
a7812ae4 | 2047 | TCGv_i32 tmp1 = tcg_temp_new_i32(); |
f18cd223 | 2048 | if (ra != 31) |
a7812ae4 | 2049 | gen_helper_s_to_memory(tmp1, cpu_fir[ra]); |
f18cd223 AJ |
2050 | else { |
2051 | TCGv tmp2 = tcg_const_i64(0); | |
a7812ae4 | 2052 | gen_helper_s_to_memory(tmp1, tmp2); |
f18cd223 AJ |
2053 | tcg_temp_free(tmp2); |
2054 | } | |
2055 | tcg_gen_ext_i32_i64(cpu_ir[rc], tmp1); | |
a7812ae4 | 2056 | tcg_temp_free_i32(tmp1); |
f18cd223 | 2057 | } |
4c9649a9 JM |
2058 | break; |
2059 | default: | |
2060 | goto invalid_opc; | |
2061 | } | |
2062 | break; | |
2063 | case 0x1D: | |
2064 | /* HW_MTPR (PALcode) */ | |
2065 | #if defined (CONFIG_USER_ONLY) | |
2066 | goto invalid_opc; | |
2067 | #else | |
2068 | if (!ctx->pal_mode) | |
2069 | goto invalid_opc; | |
8bb6e981 AJ |
2070 | else { |
2071 | TCGv tmp1 = tcg_const_i32(insn & 0xFF); | |
2072 | if (ra != 31) | |
a7812ae4 | 2073 | gen_helper_mtpr(tmp1, cpu_ir[ra]); |
8bb6e981 AJ |
2074 | else { |
2075 | TCGv tmp2 = tcg_const_i64(0); | |
a7812ae4 | 2076 | gen_helper_mtpr(tmp1, tmp2); |
8bb6e981 AJ |
2077 | tcg_temp_free(tmp2); |
2078 | } | |
2079 | tcg_temp_free(tmp1); | |
2080 | ret = 2; | |
2081 | } | |
4c9649a9 JM |
2082 | break; |
2083 | #endif | |
2084 | case 0x1E: | |
2085 | /* HW_REI (PALcode) */ | |
2086 | #if defined (CONFIG_USER_ONLY) | |
2087 | goto invalid_opc; | |
2088 | #else | |
2089 | if (!ctx->pal_mode) | |
2090 | goto invalid_opc; | |
2091 | if (rb == 31) { | |
2092 | /* "Old" alpha */ | |
a7812ae4 | 2093 | gen_helper_hw_rei(); |
4c9649a9 | 2094 | } else { |
8bb6e981 AJ |
2095 | TCGv tmp; |
2096 | ||
2097 | if (ra != 31) { | |
a7812ae4 | 2098 | tmp = tcg_temp_new(); |
8bb6e981 AJ |
2099 | tcg_gen_addi_i64(tmp, cpu_ir[rb], (((int64_t)insn << 51) >> 51)); |
2100 | } else | |
2101 | tmp = tcg_const_i64(((int64_t)insn << 51) >> 51); | |
a7812ae4 | 2102 | gen_helper_hw_ret(tmp); |
8bb6e981 | 2103 | tcg_temp_free(tmp); |
4c9649a9 JM |
2104 | } |
2105 | ret = 2; | |
2106 | break; | |
2107 | #endif | |
2108 | case 0x1F: | |
2109 | /* HW_ST (PALcode) */ | |
2110 | #if defined (CONFIG_USER_ONLY) | |
2111 | goto invalid_opc; | |
2112 | #else | |
2113 | if (!ctx->pal_mode) | |
2114 | goto invalid_opc; | |
8bb6e981 AJ |
2115 | else { |
2116 | TCGv addr, val; | |
a7812ae4 | 2117 | addr = tcg_temp_new(); |
8bb6e981 AJ |
2118 | if (rb != 31) |
2119 | tcg_gen_addi_i64(addr, cpu_ir[rb], disp12); | |
2120 | else | |
2121 | tcg_gen_movi_i64(addr, disp12); | |
2122 | if (ra != 31) | |
2123 | val = cpu_ir[ra]; | |
2124 | else { | |
a7812ae4 | 2125 | val = tcg_temp_new(); |
8bb6e981 AJ |
2126 | tcg_gen_movi_i64(val, 0); |
2127 | } | |
2128 | switch ((insn >> 12) & 0xF) { | |
2129 | case 0x0: | |
2130 | /* Longword physical access */ | |
a7812ae4 | 2131 | gen_helper_stl_raw(val, addr); |
8bb6e981 AJ |
2132 | break; |
2133 | case 0x1: | |
2134 | /* Quadword physical access */ | |
a7812ae4 | 2135 | gen_helper_stq_raw(val, addr); |
8bb6e981 AJ |
2136 | break; |
2137 | case 0x2: | |
2138 | /* Longword physical access with lock */ | |
a7812ae4 | 2139 | gen_helper_stl_c_raw(val, val, addr); |
8bb6e981 AJ |
2140 | break; |
2141 | case 0x3: | |
2142 | /* Quadword physical access with lock */ | |
a7812ae4 | 2143 | gen_helper_stq_c_raw(val, val, addr); |
8bb6e981 AJ |
2144 | break; |
2145 | case 0x4: | |
2146 | /* Longword virtual access */ | |
a7812ae4 PB |
2147 | gen_helper_st_virt_to_phys(addr, addr); |
2148 | gen_helper_stl_raw(val, addr); | |
8bb6e981 AJ |
2149 | break; |
2150 | case 0x5: | |
2151 | /* Quadword virtual access */ | |
a7812ae4 PB |
2152 | gen_helper_st_virt_to_phys(addr, addr); |
2153 | gen_helper_stq_raw(val, addr); | |
8bb6e981 AJ |
2154 | break; |
2155 | case 0x6: | |
2156 | /* Invalid */ | |
2157 | goto invalid_opc; | |
2158 | case 0x7: | |
2159 | /* Invalid */ | |
2160 | goto invalid_opc; | |
2161 | case 0x8: | |
2162 | /* Invalid */ | |
2163 | goto invalid_opc; | |
2164 | case 0x9: | |
2165 | /* Invalid */ | |
2166 | goto invalid_opc; | |
2167 | case 0xA: | |
2168 | /* Invalid */ | |
2169 | goto invalid_opc; | |
2170 | case 0xB: | |
2171 | /* Invalid */ | |
2172 | goto invalid_opc; | |
2173 | case 0xC: | |
2174 | /* Longword virtual access with alternate access mode */ | |
a7812ae4 PB |
2175 | gen_helper_set_alt_mode(); |
2176 | gen_helper_st_virt_to_phys(addr, addr); | |
2177 | gen_helper_stl_raw(val, addr); | |
2178 | gen_helper_restore_mode(); | |
8bb6e981 AJ |
2179 | break; |
2180 | case 0xD: | |
2181 | /* Quadword virtual access with alternate access mode */ | |
a7812ae4 PB |
2182 | gen_helper_set_alt_mode(); |
2183 | gen_helper_st_virt_to_phys(addr, addr); | |
2184 | gen_helper_stl_raw(val, addr); | |
2185 | gen_helper_restore_mode(); | |
8bb6e981 AJ |
2186 | break; |
2187 | case 0xE: | |
2188 | /* Invalid */ | |
2189 | goto invalid_opc; | |
2190 | case 0xF: | |
2191 | /* Invalid */ | |
2192 | goto invalid_opc; | |
2193 | } | |
45d46ce8 | 2194 | if (ra == 31) |
8bb6e981 AJ |
2195 | tcg_temp_free(val); |
2196 | tcg_temp_free(addr); | |
4c9649a9 | 2197 | } |
4c9649a9 JM |
2198 | break; |
2199 | #endif | |
2200 | case 0x20: | |
2201 | /* LDF */ | |
f18cd223 | 2202 | gen_load_mem(ctx, &gen_qemu_ldf, ra, rb, disp16, 1, 0); |
4c9649a9 JM |
2203 | break; |
2204 | case 0x21: | |
2205 | /* LDG */ | |
f18cd223 | 2206 | gen_load_mem(ctx, &gen_qemu_ldg, ra, rb, disp16, 1, 0); |
4c9649a9 JM |
2207 | break; |
2208 | case 0x22: | |
2209 | /* LDS */ | |
f18cd223 | 2210 | gen_load_mem(ctx, &gen_qemu_lds, ra, rb, disp16, 1, 0); |
4c9649a9 JM |
2211 | break; |
2212 | case 0x23: | |
2213 | /* LDT */ | |
f18cd223 | 2214 | gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 1, 0); |
4c9649a9 JM |
2215 | break; |
2216 | case 0x24: | |
2217 | /* STF */ | |
57a92c8e | 2218 | gen_store_mem(ctx, &gen_qemu_stf, ra, rb, disp16, 1, 0, 0); |
4c9649a9 JM |
2219 | break; |
2220 | case 0x25: | |
2221 | /* STG */ | |
57a92c8e | 2222 | gen_store_mem(ctx, &gen_qemu_stg, ra, rb, disp16, 1, 0, 0); |
4c9649a9 JM |
2223 | break; |
2224 | case 0x26: | |
2225 | /* STS */ | |
57a92c8e | 2226 | gen_store_mem(ctx, &gen_qemu_sts, ra, rb, disp16, 1, 0, 0); |
4c9649a9 JM |
2227 | break; |
2228 | case 0x27: | |
2229 | /* STT */ | |
57a92c8e | 2230 | gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 1, 0, 0); |
4c9649a9 JM |
2231 | break; |
2232 | case 0x28: | |
2233 | /* LDL */ | |
f18cd223 | 2234 | gen_load_mem(ctx, &tcg_gen_qemu_ld32s, ra, rb, disp16, 0, 0); |
4c9649a9 JM |
2235 | break; |
2236 | case 0x29: | |
2237 | /* LDQ */ | |
f18cd223 | 2238 | gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 0, 0); |
4c9649a9 JM |
2239 | break; |
2240 | case 0x2A: | |
2241 | /* LDL_L */ | |
f4ed8679 | 2242 | gen_load_mem(ctx, &gen_qemu_ldl_l, ra, rb, disp16, 0, 0); |
4c9649a9 JM |
2243 | break; |
2244 | case 0x2B: | |
2245 | /* LDQ_L */ | |
f4ed8679 | 2246 | gen_load_mem(ctx, &gen_qemu_ldq_l, ra, rb, disp16, 0, 0); |
4c9649a9 JM |
2247 | break; |
2248 | case 0x2C: | |
2249 | /* STL */ | |
57a92c8e | 2250 | gen_store_mem(ctx, &tcg_gen_qemu_st32, ra, rb, disp16, 0, 0, 0); |
4c9649a9 JM |
2251 | break; |
2252 | case 0x2D: | |
2253 | /* STQ */ | |
57a92c8e | 2254 | gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0, 0, 0); |
4c9649a9 JM |
2255 | break; |
2256 | case 0x2E: | |
2257 | /* STL_C */ | |
57a92c8e | 2258 | gen_store_mem(ctx, &gen_qemu_stl_c, ra, rb, disp16, 0, 0, 1); |
4c9649a9 JM |
2259 | break; |
2260 | case 0x2F: | |
2261 | /* STQ_C */ | |
57a92c8e | 2262 | gen_store_mem(ctx, &gen_qemu_stq_c, ra, rb, disp16, 0, 0, 1); |
4c9649a9 JM |
2263 | break; |
2264 | case 0x30: | |
2265 | /* BR */ | |
3761035f AJ |
2266 | if (ra != 31) |
2267 | tcg_gen_movi_i64(cpu_ir[ra], ctx->pc); | |
2268 | tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp21 << 2)); | |
4c9649a9 JM |
2269 | ret = 1; |
2270 | break; | |
a7812ae4 PB |
2271 | case 0x31: /* FBEQ */ |
2272 | case 0x32: /* FBLT */ | |
2273 | case 0x33: /* FBLE */ | |
2274 | gen_fbcond(ctx, opc, ra, disp16); | |
4c9649a9 JM |
2275 | ret = 1; |
2276 | break; | |
2277 | case 0x34: | |
2278 | /* BSR */ | |
3761035f AJ |
2279 | if (ra != 31) |
2280 | tcg_gen_movi_i64(cpu_ir[ra], ctx->pc); | |
2281 | tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp21 << 2)); | |
4c9649a9 JM |
2282 | ret = 1; |
2283 | break; | |
a7812ae4 PB |
2284 | case 0x35: /* FBNE */ |
2285 | case 0x36: /* FBGE */ | |
2286 | case 0x37: /* FBGT */ | |
2287 | gen_fbcond(ctx, opc, ra, disp16); | |
4c9649a9 JM |
2288 | ret = 1; |
2289 | break; | |
2290 | case 0x38: | |
2291 | /* BLBC */ | |
a1516744 | 2292 | gen_bcond(ctx, TCG_COND_EQ, ra, disp21, 1); |
4c9649a9 JM |
2293 | ret = 1; |
2294 | break; | |
2295 | case 0x39: | |
2296 | /* BEQ */ | |
a1516744 | 2297 | gen_bcond(ctx, TCG_COND_EQ, ra, disp21, 0); |
4c9649a9 JM |
2298 | ret = 1; |
2299 | break; | |
2300 | case 0x3A: | |
2301 | /* BLT */ | |
a1516744 | 2302 | gen_bcond(ctx, TCG_COND_LT, ra, disp21, 0); |
4c9649a9 JM |
2303 | ret = 1; |
2304 | break; | |
2305 | case 0x3B: | |
2306 | /* BLE */ | |
a1516744 | 2307 | gen_bcond(ctx, TCG_COND_LE, ra, disp21, 0); |
4c9649a9 JM |
2308 | ret = 1; |
2309 | break; | |
2310 | case 0x3C: | |
2311 | /* BLBS */ | |
a1516744 | 2312 | gen_bcond(ctx, TCG_COND_NE, ra, disp21, 1); |
4c9649a9 JM |
2313 | ret = 1; |
2314 | break; | |
2315 | case 0x3D: | |
2316 | /* BNE */ | |
a1516744 | 2317 | gen_bcond(ctx, TCG_COND_NE, ra, disp21, 0); |
4c9649a9 JM |
2318 | ret = 1; |
2319 | break; | |
2320 | case 0x3E: | |
2321 | /* BGE */ | |
a1516744 | 2322 | gen_bcond(ctx, TCG_COND_GE, ra, disp21, 0); |
4c9649a9 JM |
2323 | ret = 1; |
2324 | break; | |
2325 | case 0x3F: | |
2326 | /* BGT */ | |
a1516744 | 2327 | gen_bcond(ctx, TCG_COND_GT, ra, disp21, 0); |
4c9649a9 JM |
2328 | ret = 1; |
2329 | break; | |
2330 | invalid_opc: | |
2331 | gen_invalid(ctx); | |
2332 | ret = 3; | |
2333 | break; | |
2334 | } | |
2335 | ||
2336 | return ret; | |
2337 | } | |
2338 | ||
2cfc5f17 TS |
2339 | static always_inline void gen_intermediate_code_internal (CPUState *env, |
2340 | TranslationBlock *tb, | |
2341 | int search_pc) | |
4c9649a9 JM |
2342 | { |
2343 | #if defined ALPHA_DEBUG_DISAS | |
2344 | static int insn_count; | |
2345 | #endif | |
2346 | DisasContext ctx, *ctxp = &ctx; | |
2347 | target_ulong pc_start; | |
2348 | uint32_t insn; | |
2349 | uint16_t *gen_opc_end; | |
a1d1bb31 | 2350 | CPUBreakpoint *bp; |
4c9649a9 JM |
2351 | int j, lj = -1; |
2352 | int ret; | |
2e70f6ef PB |
2353 | int num_insns; |
2354 | int max_insns; | |
4c9649a9 JM |
2355 | |
2356 | pc_start = tb->pc; | |
4c9649a9 | 2357 | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
4c9649a9 JM |
2358 | ctx.pc = pc_start; |
2359 | ctx.amask = env->amask; | |
8579095b | 2360 | ctx.env = env; |
4c9649a9 JM |
2361 | #if defined (CONFIG_USER_ONLY) |
2362 | ctx.mem_idx = 0; | |
2363 | #else | |
2364 | ctx.mem_idx = ((env->ps >> 3) & 3); | |
2365 | ctx.pal_mode = env->ipr[IPR_EXC_ADDR] & 1; | |
2366 | #endif | |
2e70f6ef PB |
2367 | num_insns = 0; |
2368 | max_insns = tb->cflags & CF_COUNT_MASK; | |
2369 | if (max_insns == 0) | |
2370 | max_insns = CF_COUNT_MASK; | |
2371 | ||
2372 | gen_icount_start(); | |
4c9649a9 | 2373 | for (ret = 0; ret == 0;) { |
c0ce998e AL |
2374 | if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) { |
2375 | TAILQ_FOREACH(bp, &env->breakpoints, entry) { | |
a1d1bb31 | 2376 | if (bp->pc == ctx.pc) { |
4c9649a9 JM |
2377 | gen_excp(&ctx, EXCP_DEBUG, 0); |
2378 | break; | |
2379 | } | |
2380 | } | |
2381 | } | |
2382 | if (search_pc) { | |
2383 | j = gen_opc_ptr - gen_opc_buf; | |
2384 | if (lj < j) { | |
2385 | lj++; | |
2386 | while (lj < j) | |
2387 | gen_opc_instr_start[lj++] = 0; | |
4c9649a9 | 2388 | } |
ed1dda53 AJ |
2389 | gen_opc_pc[lj] = ctx.pc; |
2390 | gen_opc_instr_start[lj] = 1; | |
2391 | gen_opc_icount[lj] = num_insns; | |
4c9649a9 | 2392 | } |
2e70f6ef PB |
2393 | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
2394 | gen_io_start(); | |
4c9649a9 JM |
2395 | #if defined ALPHA_DEBUG_DISAS |
2396 | insn_count++; | |
d12d51d5 AL |
2397 | LOG_DISAS("pc " TARGET_FMT_lx " mem_idx %d\n", |
2398 | ctx.pc, ctx.mem_idx); | |
4c9649a9 JM |
2399 | #endif |
2400 | insn = ldl_code(ctx.pc); | |
2401 | #if defined ALPHA_DEBUG_DISAS | |
2402 | insn_count++; | |
d12d51d5 | 2403 | LOG_DISAS("opcode %08x %d\n", insn, insn_count); |
4c9649a9 | 2404 | #endif |
2e70f6ef | 2405 | num_insns++; |
4c9649a9 JM |
2406 | ctx.pc += 4; |
2407 | ret = translate_one(ctxp, insn); | |
2408 | if (ret != 0) | |
2409 | break; | |
2410 | /* if we reach a page boundary or are single stepping, stop | |
2411 | * generation | |
2412 | */ | |
19bf517b AJ |
2413 | if (env->singlestep_enabled) { |
2414 | gen_excp(&ctx, EXCP_DEBUG, 0); | |
2415 | break; | |
1b530a6d | 2416 | } |
19bf517b | 2417 | |
8fcc55f9 AJ |
2418 | if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) |
2419 | break; | |
2420 | ||
2421 | if (gen_opc_ptr >= gen_opc_end) | |
2422 | break; | |
2423 | ||
2424 | if (num_insns >= max_insns) | |
2425 | break; | |
2426 | ||
1b530a6d AJ |
2427 | if (singlestep) { |
2428 | break; | |
2429 | } | |
4c9649a9 JM |
2430 | } |
2431 | if (ret != 1 && ret != 3) { | |
496cb5b9 | 2432 | tcg_gen_movi_i64(cpu_pc, ctx.pc); |
4c9649a9 | 2433 | } |
4c9649a9 | 2434 | #if defined (DO_TB_FLUSH) |
a7812ae4 | 2435 | gen_helper_tb_flush(); |
4c9649a9 | 2436 | #endif |
2e70f6ef PB |
2437 | if (tb->cflags & CF_LAST_IO) |
2438 | gen_io_end(); | |
4c9649a9 | 2439 | /* Generate the return instruction */ |
57fec1fe | 2440 | tcg_gen_exit_tb(0); |
2e70f6ef | 2441 | gen_icount_end(tb, num_insns); |
4c9649a9 JM |
2442 | *gen_opc_ptr = INDEX_op_end; |
2443 | if (search_pc) { | |
2444 | j = gen_opc_ptr - gen_opc_buf; | |
2445 | lj++; | |
2446 | while (lj <= j) | |
2447 | gen_opc_instr_start[lj++] = 0; | |
4c9649a9 JM |
2448 | } else { |
2449 | tb->size = ctx.pc - pc_start; | |
2e70f6ef | 2450 | tb->icount = num_insns; |
4c9649a9 JM |
2451 | } |
2452 | #if defined ALPHA_DEBUG_DISAS | |
93fcfe39 | 2453 | log_cpu_state_mask(CPU_LOG_TB_CPU, env, 0); |
8fec2b8c | 2454 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { |
93fcfe39 AL |
2455 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); |
2456 | log_target_disas(pc_start, ctx.pc - pc_start, 1); | |
2457 | qemu_log("\n"); | |
4c9649a9 | 2458 | } |
4c9649a9 | 2459 | #endif |
4c9649a9 JM |
2460 | } |
2461 | ||
2cfc5f17 | 2462 | void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb) |
4c9649a9 | 2463 | { |
2cfc5f17 | 2464 | gen_intermediate_code_internal(env, tb, 0); |
4c9649a9 JM |
2465 | } |
2466 | ||
2cfc5f17 | 2467 | void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb) |
4c9649a9 | 2468 | { |
2cfc5f17 | 2469 | gen_intermediate_code_internal(env, tb, 1); |
4c9649a9 JM |
2470 | } |
2471 | ||
aaed909a | 2472 | CPUAlphaState * cpu_alpha_init (const char *cpu_model) |
4c9649a9 JM |
2473 | { |
2474 | CPUAlphaState *env; | |
2475 | uint64_t hwpcb; | |
2476 | ||
2477 | env = qemu_mallocz(sizeof(CPUAlphaState)); | |
4c9649a9 | 2478 | cpu_exec_init(env); |
2e70f6ef | 2479 | alpha_translate_init(); |
4c9649a9 JM |
2480 | tlb_flush(env, 1); |
2481 | /* XXX: should not be hardcoded */ | |
2482 | env->implver = IMPLVER_2106x; | |
2483 | env->ps = 0x1F00; | |
2484 | #if defined (CONFIG_USER_ONLY) | |
2485 | env->ps |= 1 << 3; | |
2486 | #endif | |
2487 | pal_init(env); | |
2488 | /* Initialize IPR */ | |
2489 | hwpcb = env->ipr[IPR_PCBB]; | |
2490 | env->ipr[IPR_ASN] = 0; | |
2491 | env->ipr[IPR_ASTEN] = 0; | |
2492 | env->ipr[IPR_ASTSR] = 0; | |
2493 | env->ipr[IPR_DATFX] = 0; | |
2494 | /* XXX: fix this */ | |
2495 | // env->ipr[IPR_ESP] = ldq_raw(hwpcb + 8); | |
2496 | // env->ipr[IPR_KSP] = ldq_raw(hwpcb + 0); | |
2497 | // env->ipr[IPR_SSP] = ldq_raw(hwpcb + 16); | |
2498 | // env->ipr[IPR_USP] = ldq_raw(hwpcb + 24); | |
2499 | env->ipr[IPR_FEN] = 0; | |
2500 | env->ipr[IPR_IPL] = 31; | |
2501 | env->ipr[IPR_MCES] = 0; | |
2502 | env->ipr[IPR_PERFMON] = 0; /* Implementation specific */ | |
2503 | // env->ipr[IPR_PTBR] = ldq_raw(hwpcb + 32); | |
2504 | env->ipr[IPR_SISR] = 0; | |
2505 | env->ipr[IPR_VIRBND] = -1ULL; | |
2506 | ||
0bf46a40 | 2507 | qemu_init_vcpu(env); |
4c9649a9 JM |
2508 | return env; |
2509 | } | |
aaed909a | 2510 | |
d2856f1a AJ |
2511 | void gen_pc_load(CPUState *env, TranslationBlock *tb, |
2512 | unsigned long searched_pc, int pc_pos, void *puc) | |
2513 | { | |
2514 | env->pc = gen_opc_pc[pc_pos]; | |
2515 | } |