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dec9c2d4 AF |
1 | /* |
2 | * QEMU ARM CPU | |
3 | * | |
4 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | */ | |
20 | ||
778c3a06 | 21 | #include "cpu.h" |
ccd38087 | 22 | #include "internals.h" |
dec9c2d4 | 23 | #include "qemu-common.h" |
5de16430 | 24 | #include "hw/qdev-properties.h" |
07a5b0d2 | 25 | #include "qapi/qmp/qerror.h" |
3c30dd5a PM |
26 | #if !defined(CONFIG_USER_ONLY) |
27 | #include "hw/loader.h" | |
28 | #endif | |
7c1840b6 | 29 | #include "hw/arm/arm.h" |
9c17d615 | 30 | #include "sysemu/sysemu.h" |
7c1840b6 | 31 | #include "sysemu/kvm.h" |
50a2c6e5 | 32 | #include "kvm_arm.h" |
dec9c2d4 | 33 | |
f45748f1 AF |
34 | static void arm_cpu_set_pc(CPUState *cs, vaddr value) |
35 | { | |
36 | ARMCPU *cpu = ARM_CPU(cs); | |
37 | ||
38 | cpu->env.regs[15] = value; | |
39 | } | |
40 | ||
8c2e1b00 AF |
41 | static bool arm_cpu_has_work(CPUState *cs) |
42 | { | |
43 | return cs->interrupt_request & | |
44 | (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB); | |
45 | } | |
46 | ||
4b6a83fb PM |
47 | static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) |
48 | { | |
49 | /* Reset a single ARMCPRegInfo register */ | |
50 | ARMCPRegInfo *ri = value; | |
51 | ARMCPU *cpu = opaque; | |
52 | ||
53 | if (ri->type & ARM_CP_SPECIAL) { | |
54 | return; | |
55 | } | |
56 | ||
57 | if (ri->resetfn) { | |
58 | ri->resetfn(&cpu->env, ri); | |
59 | return; | |
60 | } | |
61 | ||
62 | /* A zero offset is never possible as it would be regs[0] | |
63 | * so we use it to indicate that reset is being handled elsewhere. | |
64 | * This is basically only used for fields in non-core coprocessors | |
65 | * (like the pxa2xx ones). | |
66 | */ | |
67 | if (!ri->fieldoffset) { | |
68 | return; | |
69 | } | |
70 | ||
67ed771d | 71 | if (cpreg_field_is_64bit(ri)) { |
4b6a83fb PM |
72 | CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; |
73 | } else { | |
74 | CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; | |
75 | } | |
76 | } | |
77 | ||
dec9c2d4 AF |
78 | /* CPUClass::reset() */ |
79 | static void arm_cpu_reset(CPUState *s) | |
80 | { | |
81 | ARMCPU *cpu = ARM_CPU(s); | |
82 | ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); | |
3c30dd5a | 83 | CPUARMState *env = &cpu->env; |
3c30dd5a | 84 | |
dec9c2d4 AF |
85 | acc->parent_reset(s); |
86 | ||
f0c3c505 | 87 | memset(env, 0, offsetof(CPUARMState, features)); |
4b6a83fb | 88 | g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); |
3c30dd5a PM |
89 | env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; |
90 | env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; | |
91 | env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; | |
a50c0f51 | 92 | env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2; |
3c30dd5a PM |
93 | |
94 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { | |
95 | env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; | |
96 | } | |
97 | ||
3926cc84 AG |
98 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { |
99 | /* 64 bit CPUs always start in 64 bit mode */ | |
100 | env->aarch64 = 1; | |
d356312f PM |
101 | #if defined(CONFIG_USER_ONLY) |
102 | env->pstate = PSTATE_MODE_EL0t; | |
8af35c37 PM |
103 | /* Userspace expects access to CTL_EL0 and the cache ops */ |
104 | env->cp15.c1_sys |= SCTLR_UCT | SCTLR_UCI; | |
8c6afa6a PM |
105 | /* and to the FP/Neon instructions */ |
106 | env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 2, 3); | |
d356312f | 107 | #else |
4cc35614 | 108 | env->pstate = PSTATE_MODE_EL1h; |
3933443e | 109 | env->pc = cpu->rvbar; |
8c6afa6a PM |
110 | #endif |
111 | } else { | |
112 | #if defined(CONFIG_USER_ONLY) | |
113 | /* Userspace expects access to cp10 and cp11 for FP/Neon */ | |
114 | env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 4, 0xf); | |
d356312f | 115 | #endif |
3926cc84 AG |
116 | } |
117 | ||
3c30dd5a PM |
118 | #if defined(CONFIG_USER_ONLY) |
119 | env->uncached_cpsr = ARM_CPU_MODE_USR; | |
120 | /* For user mode we must enable access to coprocessors */ | |
121 | env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; | |
122 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { | |
123 | env->cp15.c15_cpar = 3; | |
124 | } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
125 | env->cp15.c15_cpar = 1; | |
126 | } | |
127 | #else | |
128 | /* SVC mode with interrupts disabled. */ | |
4cc35614 PM |
129 | env->uncached_cpsr = ARM_CPU_MODE_SVC; |
130 | env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; | |
3c30dd5a PM |
131 | /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is |
132 | clear at reset. Initial SP and PC are loaded from ROM. */ | |
133 | if (IS_M(env)) { | |
134 | uint32_t pc; | |
135 | uint8_t *rom; | |
4cc35614 | 136 | env->daif &= ~PSTATE_I; |
3c30dd5a PM |
137 | rom = rom_ptr(0); |
138 | if (rom) { | |
139 | /* We should really use ldl_phys here, in case the guest | |
140 | modified flash and reset itself. However images | |
141 | loaded via -kernel have not been copied yet, so load the | |
142 | values directly from there. */ | |
f62cafd4 | 143 | env->regs[13] = ldl_p(rom) & 0xFFFFFFFC; |
3c30dd5a PM |
144 | pc = ldl_p(rom + 4); |
145 | env->thumb = pc & 1; | |
146 | env->regs[15] = pc & ~1; | |
147 | } | |
148 | } | |
387f9806 | 149 | |
76e3e1bc | 150 | if (env->cp15.c1_sys & SCTLR_V) { |
387f9806 AP |
151 | env->regs[15] = 0xFFFF0000; |
152 | } | |
153 | ||
3c30dd5a | 154 | env->vfp.xregs[ARM_VFP_FPEXC] = 0; |
3c30dd5a PM |
155 | #endif |
156 | set_flush_to_zero(1, &env->vfp.standard_fp_status); | |
157 | set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); | |
158 | set_default_nan_mode(1, &env->vfp.standard_fp_status); | |
159 | set_float_detect_tininess(float_tininess_before_rounding, | |
160 | &env->vfp.fp_status); | |
161 | set_float_detect_tininess(float_tininess_before_rounding, | |
162 | &env->vfp.standard_fp_status); | |
00c8cb0a | 163 | tlb_flush(s, 1); |
3c30dd5a PM |
164 | /* Reset is a state change for some CPUARMState fields which we |
165 | * bake assumptions about into translated code, so we need to | |
166 | * tb_flush(). | |
167 | */ | |
168 | tb_flush(env); | |
50a2c6e5 PB |
169 | |
170 | #ifndef CONFIG_USER_ONLY | |
171 | if (kvm_enabled()) { | |
172 | kvm_arm_reset_vcpu(cpu); | |
173 | } | |
174 | #endif | |
dec9c2d4 AF |
175 | } |
176 | ||
7c1840b6 PM |
177 | #ifndef CONFIG_USER_ONLY |
178 | static void arm_cpu_set_irq(void *opaque, int irq, int level) | |
179 | { | |
180 | ARMCPU *cpu = opaque; | |
181 | CPUState *cs = CPU(cpu); | |
182 | ||
183 | switch (irq) { | |
184 | case ARM_CPU_IRQ: | |
185 | if (level) { | |
186 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); | |
187 | } else { | |
188 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); | |
189 | } | |
190 | break; | |
191 | case ARM_CPU_FIQ: | |
192 | if (level) { | |
193 | cpu_interrupt(cs, CPU_INTERRUPT_FIQ); | |
194 | } else { | |
195 | cpu_reset_interrupt(cs, CPU_INTERRUPT_FIQ); | |
196 | } | |
197 | break; | |
198 | default: | |
199 | hw_error("arm_cpu_set_irq: Bad interrupt line %d\n", irq); | |
200 | } | |
201 | } | |
202 | ||
203 | static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) | |
204 | { | |
205 | #ifdef CONFIG_KVM | |
206 | ARMCPU *cpu = opaque; | |
207 | CPUState *cs = CPU(cpu); | |
208 | int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT; | |
209 | ||
210 | switch (irq) { | |
211 | case ARM_CPU_IRQ: | |
212 | kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; | |
213 | break; | |
214 | case ARM_CPU_FIQ: | |
215 | kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; | |
216 | break; | |
217 | default: | |
218 | hw_error("arm_cpu_kvm_set_irq: Bad interrupt line %d\n", irq); | |
219 | } | |
220 | kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; | |
221 | kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); | |
222 | #endif | |
223 | } | |
224 | #endif | |
225 | ||
581be094 PM |
226 | static inline void set_feature(CPUARMState *env, int feature) |
227 | { | |
918f5dca | 228 | env->features |= 1ULL << feature; |
581be094 PM |
229 | } |
230 | ||
777dc784 PM |
231 | static void arm_cpu_initfn(Object *obj) |
232 | { | |
c05efcb1 | 233 | CPUState *cs = CPU(obj); |
777dc784 | 234 | ARMCPU *cpu = ARM_CPU(obj); |
79614b78 | 235 | static bool inited; |
777dc784 | 236 | |
c05efcb1 | 237 | cs->env_ptr = &cpu->env; |
777dc784 | 238 | cpu_exec_init(&cpu->env); |
4b6a83fb PM |
239 | cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, |
240 | g_free, g_free); | |
79614b78 | 241 | |
7c1840b6 PM |
242 | #ifndef CONFIG_USER_ONLY |
243 | /* Our inbound IRQ and FIQ lines */ | |
244 | if (kvm_enabled()) { | |
245 | qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 2); | |
246 | } else { | |
247 | qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 2); | |
248 | } | |
55d284af | 249 | |
bc72ad67 | 250 | cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, |
55d284af | 251 | arm_gt_ptimer_cb, cpu); |
bc72ad67 | 252 | cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, |
55d284af PM |
253 | arm_gt_vtimer_cb, cpu); |
254 | qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, | |
255 | ARRAY_SIZE(cpu->gt_timer_outputs)); | |
7c1840b6 PM |
256 | #endif |
257 | ||
54d3e3f5 PM |
258 | /* DTB consumers generally don't in fact care what the 'compatible' |
259 | * string is, so always provide some string and trust that a hypothetical | |
260 | * picky DTB consumer will also provide a helpful error message. | |
261 | */ | |
262 | cpu->dtb_compatible = "qemu,unknown"; | |
dd032e34 | 263 | cpu->psci_version = 1; /* By default assume PSCI v0.1 */ |
3541addc | 264 | cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; |
54d3e3f5 | 265 | |
79614b78 AF |
266 | if (tcg_enabled() && !inited) { |
267 | inited = true; | |
268 | arm_translate_init(); | |
269 | } | |
4b6a83fb PM |
270 | } |
271 | ||
07a5b0d2 | 272 | static Property arm_cpu_reset_cbar_property = |
f318cec6 | 273 | DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); |
07a5b0d2 | 274 | |
68e0a40a AP |
275 | static Property arm_cpu_reset_hivecs_property = |
276 | DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); | |
277 | ||
3933443e PM |
278 | static Property arm_cpu_rvbar_property = |
279 | DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); | |
280 | ||
07a5b0d2 PC |
281 | static void arm_cpu_post_init(Object *obj) |
282 | { | |
283 | ARMCPU *cpu = ARM_CPU(obj); | |
07a5b0d2 | 284 | |
f318cec6 PM |
285 | if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || |
286 | arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { | |
07a5b0d2 | 287 | qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, |
5433a0a8 | 288 | &error_abort); |
07a5b0d2 | 289 | } |
68e0a40a AP |
290 | |
291 | if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { | |
292 | qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property, | |
5433a0a8 | 293 | &error_abort); |
68e0a40a | 294 | } |
3933443e PM |
295 | |
296 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | |
297 | qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property, | |
298 | &error_abort); | |
299 | } | |
07a5b0d2 PC |
300 | } |
301 | ||
4b6a83fb PM |
302 | static void arm_cpu_finalizefn(Object *obj) |
303 | { | |
304 | ARMCPU *cpu = ARM_CPU(obj); | |
305 | g_hash_table_destroy(cpu->cp_regs); | |
777dc784 PM |
306 | } |
307 | ||
14969266 | 308 | static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
581be094 | 309 | { |
14a10fc3 | 310 | CPUState *cs = CPU(dev); |
14969266 AF |
311 | ARMCPU *cpu = ARM_CPU(dev); |
312 | ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); | |
581be094 | 313 | CPUARMState *env = &cpu->env; |
14969266 | 314 | |
581be094 | 315 | /* Some features automatically imply others: */ |
81e69fb0 MR |
316 | if (arm_feature(env, ARM_FEATURE_V8)) { |
317 | set_feature(env, ARM_FEATURE_V7); | |
318 | set_feature(env, ARM_FEATURE_ARM_DIV); | |
319 | set_feature(env, ARM_FEATURE_LPAE); | |
320 | } | |
581be094 PM |
321 | if (arm_feature(env, ARM_FEATURE_V7)) { |
322 | set_feature(env, ARM_FEATURE_VAPA); | |
323 | set_feature(env, ARM_FEATURE_THUMB2); | |
81bdde9d | 324 | set_feature(env, ARM_FEATURE_MPIDR); |
581be094 PM |
325 | if (!arm_feature(env, ARM_FEATURE_M)) { |
326 | set_feature(env, ARM_FEATURE_V6K); | |
327 | } else { | |
328 | set_feature(env, ARM_FEATURE_V6); | |
329 | } | |
330 | } | |
331 | if (arm_feature(env, ARM_FEATURE_V6K)) { | |
332 | set_feature(env, ARM_FEATURE_V6); | |
333 | set_feature(env, ARM_FEATURE_MVFR); | |
334 | } | |
335 | if (arm_feature(env, ARM_FEATURE_V6)) { | |
336 | set_feature(env, ARM_FEATURE_V5); | |
337 | if (!arm_feature(env, ARM_FEATURE_M)) { | |
338 | set_feature(env, ARM_FEATURE_AUXCR); | |
339 | } | |
340 | } | |
341 | if (arm_feature(env, ARM_FEATURE_V5)) { | |
342 | set_feature(env, ARM_FEATURE_V4T); | |
343 | } | |
344 | if (arm_feature(env, ARM_FEATURE_M)) { | |
345 | set_feature(env, ARM_FEATURE_THUMB_DIV); | |
346 | } | |
347 | if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { | |
348 | set_feature(env, ARM_FEATURE_THUMB_DIV); | |
349 | } | |
350 | if (arm_feature(env, ARM_FEATURE_VFP4)) { | |
351 | set_feature(env, ARM_FEATURE_VFP3); | |
da5141fc | 352 | set_feature(env, ARM_FEATURE_VFP_FP16); |
581be094 PM |
353 | } |
354 | if (arm_feature(env, ARM_FEATURE_VFP3)) { | |
355 | set_feature(env, ARM_FEATURE_VFP); | |
356 | } | |
de9b05b8 | 357 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
bdcc150d | 358 | set_feature(env, ARM_FEATURE_V7MP); |
de9b05b8 PM |
359 | set_feature(env, ARM_FEATURE_PXN); |
360 | } | |
f318cec6 PM |
361 | if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { |
362 | set_feature(env, ARM_FEATURE_CBAR); | |
363 | } | |
2ceb98c0 | 364 | |
68e0a40a AP |
365 | if (cpu->reset_hivecs) { |
366 | cpu->reset_sctlr |= (1 << 13); | |
367 | } | |
368 | ||
2ceb98c0 | 369 | register_cp_regs_for_features(cpu); |
14969266 AF |
370 | arm_cpu_register_gdb_regs_for_features(cpu); |
371 | ||
721fae12 PM |
372 | init_cpreg_list(cpu); |
373 | ||
14a10fc3 | 374 | qemu_init_vcpu(cs); |
00d0f7cb | 375 | cpu_reset(cs); |
14969266 AF |
376 | |
377 | acc->parent_realize(dev, errp); | |
581be094 PM |
378 | } |
379 | ||
5900d6b2 AF |
380 | static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) |
381 | { | |
382 | ObjectClass *oc; | |
51492fd1 | 383 | char *typename; |
5900d6b2 AF |
384 | |
385 | if (!cpu_model) { | |
386 | return NULL; | |
387 | } | |
388 | ||
51492fd1 AF |
389 | typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpu_model); |
390 | oc = object_class_by_name(typename); | |
391 | g_free(typename); | |
245fb54d AF |
392 | if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || |
393 | object_class_is_abstract(oc)) { | |
5900d6b2 AF |
394 | return NULL; |
395 | } | |
396 | return oc; | |
397 | } | |
398 | ||
15ee776b PM |
399 | /* CPU models. These are not needed for the AArch64 linux-user build. */ |
400 | #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) | |
401 | ||
777dc784 PM |
402 | static void arm926_initfn(Object *obj) |
403 | { | |
404 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
405 | |
406 | cpu->dtb_compatible = "arm,arm926"; | |
581be094 PM |
407 | set_feature(&cpu->env, ARM_FEATURE_V5); |
408 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
c4804214 PM |
409 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
410 | set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); | |
b2d06f96 | 411 | cpu->midr = 0x41069265; |
325b3cef | 412 | cpu->reset_fpsid = 0x41011090; |
64e1671f | 413 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 414 | cpu->reset_sctlr = 0x00090078; |
777dc784 PM |
415 | } |
416 | ||
417 | static void arm946_initfn(Object *obj) | |
418 | { | |
419 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
420 | |
421 | cpu->dtb_compatible = "arm,arm946"; | |
581be094 PM |
422 | set_feature(&cpu->env, ARM_FEATURE_V5); |
423 | set_feature(&cpu->env, ARM_FEATURE_MPU); | |
c4804214 | 424 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 425 | cpu->midr = 0x41059461; |
64e1671f | 426 | cpu->ctr = 0x0f004006; |
0ca7e01c | 427 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
428 | } |
429 | ||
430 | static void arm1026_initfn(Object *obj) | |
431 | { | |
432 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
433 | |
434 | cpu->dtb_compatible = "arm,arm1026"; | |
581be094 PM |
435 | set_feature(&cpu->env, ARM_FEATURE_V5); |
436 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
437 | set_feature(&cpu->env, ARM_FEATURE_AUXCR); | |
c4804214 PM |
438 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
439 | set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); | |
b2d06f96 | 440 | cpu->midr = 0x4106a262; |
325b3cef | 441 | cpu->reset_fpsid = 0x410110a0; |
64e1671f | 442 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 443 | cpu->reset_sctlr = 0x00090078; |
2771db27 | 444 | cpu->reset_auxcr = 1; |
06d76f31 PM |
445 | { |
446 | /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ | |
447 | ARMCPRegInfo ifar = { | |
448 | .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, | |
449 | .access = PL1_RW, | |
6cd8a264 | 450 | .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el1), |
06d76f31 PM |
451 | .resetvalue = 0 |
452 | }; | |
453 | define_one_arm_cp_reg(cpu, &ifar); | |
454 | } | |
777dc784 PM |
455 | } |
456 | ||
457 | static void arm1136_r2_initfn(Object *obj) | |
458 | { | |
459 | ARMCPU *cpu = ARM_CPU(obj); | |
2e4d7e3e PM |
460 | /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an |
461 | * older core than plain "arm1136". In particular this does not | |
462 | * have the v6K features. | |
463 | * These ID register values are correct for 1136 but may be wrong | |
464 | * for 1136_r2 (in particular r0p2 does not actually implement most | |
465 | * of the ID registers). | |
466 | */ | |
54d3e3f5 PM |
467 | |
468 | cpu->dtb_compatible = "arm,arm1136"; | |
581be094 PM |
469 | set_feature(&cpu->env, ARM_FEATURE_V6); |
470 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
c4804214 PM |
471 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
472 | set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); | |
473 | set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); | |
b2d06f96 | 474 | cpu->midr = 0x4107b362; |
325b3cef | 475 | cpu->reset_fpsid = 0x410120b4; |
bd35c355 PM |
476 | cpu->mvfr0 = 0x11111111; |
477 | cpu->mvfr1 = 0x00000000; | |
64e1671f | 478 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 479 | cpu->reset_sctlr = 0x00050078; |
2e4d7e3e PM |
480 | cpu->id_pfr0 = 0x111; |
481 | cpu->id_pfr1 = 0x1; | |
482 | cpu->id_dfr0 = 0x2; | |
483 | cpu->id_afr0 = 0x3; | |
484 | cpu->id_mmfr0 = 0x01130003; | |
485 | cpu->id_mmfr1 = 0x10030302; | |
486 | cpu->id_mmfr2 = 0x01222110; | |
487 | cpu->id_isar0 = 0x00140011; | |
488 | cpu->id_isar1 = 0x12002111; | |
489 | cpu->id_isar2 = 0x11231111; | |
490 | cpu->id_isar3 = 0x01102131; | |
491 | cpu->id_isar4 = 0x141; | |
2771db27 | 492 | cpu->reset_auxcr = 7; |
777dc784 PM |
493 | } |
494 | ||
495 | static void arm1136_initfn(Object *obj) | |
496 | { | |
497 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
498 | |
499 | cpu->dtb_compatible = "arm,arm1136"; | |
581be094 PM |
500 | set_feature(&cpu->env, ARM_FEATURE_V6K); |
501 | set_feature(&cpu->env, ARM_FEATURE_V6); | |
502 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
c4804214 PM |
503 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
504 | set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); | |
505 | set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); | |
b2d06f96 | 506 | cpu->midr = 0x4117b363; |
325b3cef | 507 | cpu->reset_fpsid = 0x410120b4; |
bd35c355 PM |
508 | cpu->mvfr0 = 0x11111111; |
509 | cpu->mvfr1 = 0x00000000; | |
64e1671f | 510 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 511 | cpu->reset_sctlr = 0x00050078; |
2e4d7e3e PM |
512 | cpu->id_pfr0 = 0x111; |
513 | cpu->id_pfr1 = 0x1; | |
514 | cpu->id_dfr0 = 0x2; | |
515 | cpu->id_afr0 = 0x3; | |
516 | cpu->id_mmfr0 = 0x01130003; | |
517 | cpu->id_mmfr1 = 0x10030302; | |
518 | cpu->id_mmfr2 = 0x01222110; | |
519 | cpu->id_isar0 = 0x00140011; | |
520 | cpu->id_isar1 = 0x12002111; | |
521 | cpu->id_isar2 = 0x11231111; | |
522 | cpu->id_isar3 = 0x01102131; | |
523 | cpu->id_isar4 = 0x141; | |
2771db27 | 524 | cpu->reset_auxcr = 7; |
777dc784 PM |
525 | } |
526 | ||
527 | static void arm1176_initfn(Object *obj) | |
528 | { | |
529 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
530 | |
531 | cpu->dtb_compatible = "arm,arm1176"; | |
581be094 PM |
532 | set_feature(&cpu->env, ARM_FEATURE_V6K); |
533 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
534 | set_feature(&cpu->env, ARM_FEATURE_VAPA); | |
c4804214 PM |
535 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
536 | set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); | |
537 | set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); | |
b2d06f96 | 538 | cpu->midr = 0x410fb767; |
325b3cef | 539 | cpu->reset_fpsid = 0x410120b5; |
bd35c355 PM |
540 | cpu->mvfr0 = 0x11111111; |
541 | cpu->mvfr1 = 0x00000000; | |
64e1671f | 542 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 543 | cpu->reset_sctlr = 0x00050078; |
2e4d7e3e PM |
544 | cpu->id_pfr0 = 0x111; |
545 | cpu->id_pfr1 = 0x11; | |
546 | cpu->id_dfr0 = 0x33; | |
547 | cpu->id_afr0 = 0; | |
548 | cpu->id_mmfr0 = 0x01130003; | |
549 | cpu->id_mmfr1 = 0x10030302; | |
550 | cpu->id_mmfr2 = 0x01222100; | |
551 | cpu->id_isar0 = 0x0140011; | |
552 | cpu->id_isar1 = 0x12002111; | |
553 | cpu->id_isar2 = 0x11231121; | |
554 | cpu->id_isar3 = 0x01102131; | |
555 | cpu->id_isar4 = 0x01141; | |
2771db27 | 556 | cpu->reset_auxcr = 7; |
777dc784 PM |
557 | } |
558 | ||
559 | static void arm11mpcore_initfn(Object *obj) | |
560 | { | |
561 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
562 | |
563 | cpu->dtb_compatible = "arm,arm11mpcore"; | |
581be094 PM |
564 | set_feature(&cpu->env, ARM_FEATURE_V6K); |
565 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
566 | set_feature(&cpu->env, ARM_FEATURE_VAPA); | |
81bdde9d | 567 | set_feature(&cpu->env, ARM_FEATURE_MPIDR); |
c4804214 | 568 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 569 | cpu->midr = 0x410fb022; |
325b3cef | 570 | cpu->reset_fpsid = 0x410120b4; |
bd35c355 PM |
571 | cpu->mvfr0 = 0x11111111; |
572 | cpu->mvfr1 = 0x00000000; | |
200bf596 | 573 | cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ |
2e4d7e3e PM |
574 | cpu->id_pfr0 = 0x111; |
575 | cpu->id_pfr1 = 0x1; | |
576 | cpu->id_dfr0 = 0; | |
577 | cpu->id_afr0 = 0x2; | |
578 | cpu->id_mmfr0 = 0x01100103; | |
579 | cpu->id_mmfr1 = 0x10020302; | |
580 | cpu->id_mmfr2 = 0x01222000; | |
581 | cpu->id_isar0 = 0x00100011; | |
582 | cpu->id_isar1 = 0x12002111; | |
583 | cpu->id_isar2 = 0x11221011; | |
584 | cpu->id_isar3 = 0x01102131; | |
585 | cpu->id_isar4 = 0x141; | |
2771db27 | 586 | cpu->reset_auxcr = 1; |
777dc784 PM |
587 | } |
588 | ||
589 | static void cortex_m3_initfn(Object *obj) | |
590 | { | |
591 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
592 | set_feature(&cpu->env, ARM_FEATURE_V7); |
593 | set_feature(&cpu->env, ARM_FEATURE_M); | |
b2d06f96 | 594 | cpu->midr = 0x410fc231; |
777dc784 PM |
595 | } |
596 | ||
e6f010cc AF |
597 | static void arm_v7m_class_init(ObjectClass *oc, void *data) |
598 | { | |
599 | #ifndef CONFIG_USER_ONLY | |
600 | CPUClass *cc = CPU_CLASS(oc); | |
601 | ||
602 | cc->do_interrupt = arm_v7m_cpu_do_interrupt; | |
603 | #endif | |
604 | } | |
605 | ||
34f90529 PM |
606 | static const ARMCPRegInfo cortexa8_cp_reginfo[] = { |
607 | { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, | |
608 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
609 | { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, | |
610 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
611 | REGINFO_SENTINEL | |
612 | }; | |
613 | ||
777dc784 PM |
614 | static void cortex_a8_initfn(Object *obj) |
615 | { | |
616 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
617 | |
618 | cpu->dtb_compatible = "arm,cortex-a8"; | |
581be094 PM |
619 | set_feature(&cpu->env, ARM_FEATURE_V7); |
620 | set_feature(&cpu->env, ARM_FEATURE_VFP3); | |
621 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
622 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
c4804214 | 623 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 624 | cpu->midr = 0x410fc080; |
325b3cef | 625 | cpu->reset_fpsid = 0x410330c0; |
bd35c355 PM |
626 | cpu->mvfr0 = 0x11110222; |
627 | cpu->mvfr1 = 0x00011100; | |
64e1671f | 628 | cpu->ctr = 0x82048004; |
0ca7e01c | 629 | cpu->reset_sctlr = 0x00c50078; |
2e4d7e3e PM |
630 | cpu->id_pfr0 = 0x1031; |
631 | cpu->id_pfr1 = 0x11; | |
632 | cpu->id_dfr0 = 0x400; | |
633 | cpu->id_afr0 = 0; | |
634 | cpu->id_mmfr0 = 0x31100003; | |
635 | cpu->id_mmfr1 = 0x20000000; | |
636 | cpu->id_mmfr2 = 0x01202000; | |
637 | cpu->id_mmfr3 = 0x11; | |
638 | cpu->id_isar0 = 0x00101111; | |
639 | cpu->id_isar1 = 0x12112111; | |
640 | cpu->id_isar2 = 0x21232031; | |
641 | cpu->id_isar3 = 0x11112131; | |
642 | cpu->id_isar4 = 0x00111142; | |
85df3786 PM |
643 | cpu->clidr = (1 << 27) | (2 << 24) | 3; |
644 | cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ | |
645 | cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ | |
646 | cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ | |
2771db27 | 647 | cpu->reset_auxcr = 2; |
34f90529 | 648 | define_arm_cp_regs(cpu, cortexa8_cp_reginfo); |
777dc784 PM |
649 | } |
650 | ||
1047b9d7 PM |
651 | static const ARMCPRegInfo cortexa9_cp_reginfo[] = { |
652 | /* power_control should be set to maximum latency. Again, | |
653 | * default to 0 and set by private hook | |
654 | */ | |
655 | { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, | |
656 | .access = PL1_RW, .resetvalue = 0, | |
657 | .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, | |
658 | { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, | |
659 | .access = PL1_RW, .resetvalue = 0, | |
660 | .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, | |
661 | { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, | |
662 | .access = PL1_RW, .resetvalue = 0, | |
663 | .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, | |
664 | { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, | |
665 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
666 | /* TLB lockdown control */ | |
667 | { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, | |
668 | .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, | |
669 | { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, | |
670 | .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, | |
671 | { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, | |
672 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
673 | { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, | |
674 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
675 | { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, | |
676 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
677 | REGINFO_SENTINEL | |
678 | }; | |
679 | ||
777dc784 PM |
680 | static void cortex_a9_initfn(Object *obj) |
681 | { | |
682 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
683 | |
684 | cpu->dtb_compatible = "arm,cortex-a9"; | |
581be094 PM |
685 | set_feature(&cpu->env, ARM_FEATURE_V7); |
686 | set_feature(&cpu->env, ARM_FEATURE_VFP3); | |
687 | set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); | |
688 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
689 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
690 | /* Note that A9 supports the MP extensions even for | |
691 | * A9UP and single-core A9MP (which are both different | |
692 | * and valid configurations; we don't model A9UP). | |
693 | */ | |
694 | set_feature(&cpu->env, ARM_FEATURE_V7MP); | |
d8ba780b | 695 | set_feature(&cpu->env, ARM_FEATURE_CBAR); |
b2d06f96 | 696 | cpu->midr = 0x410fc090; |
325b3cef | 697 | cpu->reset_fpsid = 0x41033090; |
bd35c355 PM |
698 | cpu->mvfr0 = 0x11110222; |
699 | cpu->mvfr1 = 0x01111111; | |
64e1671f | 700 | cpu->ctr = 0x80038003; |
0ca7e01c | 701 | cpu->reset_sctlr = 0x00c50078; |
2e4d7e3e PM |
702 | cpu->id_pfr0 = 0x1031; |
703 | cpu->id_pfr1 = 0x11; | |
704 | cpu->id_dfr0 = 0x000; | |
705 | cpu->id_afr0 = 0; | |
706 | cpu->id_mmfr0 = 0x00100103; | |
707 | cpu->id_mmfr1 = 0x20000000; | |
708 | cpu->id_mmfr2 = 0x01230000; | |
709 | cpu->id_mmfr3 = 0x00002111; | |
710 | cpu->id_isar0 = 0x00101111; | |
711 | cpu->id_isar1 = 0x13112111; | |
712 | cpu->id_isar2 = 0x21232041; | |
713 | cpu->id_isar3 = 0x11112131; | |
714 | cpu->id_isar4 = 0x00111142; | |
85df3786 PM |
715 | cpu->clidr = (1 << 27) | (1 << 24) | 3; |
716 | cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */ | |
717 | cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */ | |
d8ba780b | 718 | define_arm_cp_regs(cpu, cortexa9_cp_reginfo); |
777dc784 PM |
719 | } |
720 | ||
34f90529 | 721 | #ifndef CONFIG_USER_ONLY |
c4241c7d | 722 | static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
34f90529 PM |
723 | { |
724 | /* Linux wants the number of processors from here. | |
725 | * Might as well set the interrupt-controller bit too. | |
726 | */ | |
c4241c7d | 727 | return ((smp_cpus - 1) << 24) | (1 << 23); |
34f90529 PM |
728 | } |
729 | #endif | |
730 | ||
731 | static const ARMCPRegInfo cortexa15_cp_reginfo[] = { | |
732 | #ifndef CONFIG_USER_ONLY | |
733 | { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, | |
734 | .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, | |
735 | .writefn = arm_cp_write_ignore, }, | |
736 | #endif | |
737 | { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, | |
738 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
739 | REGINFO_SENTINEL | |
740 | }; | |
741 | ||
777dc784 PM |
742 | static void cortex_a15_initfn(Object *obj) |
743 | { | |
744 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
745 | |
746 | cpu->dtb_compatible = "arm,cortex-a15"; | |
581be094 PM |
747 | set_feature(&cpu->env, ARM_FEATURE_V7); |
748 | set_feature(&cpu->env, ARM_FEATURE_VFP4); | |
581be094 PM |
749 | set_feature(&cpu->env, ARM_FEATURE_NEON); |
750 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
751 | set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); | |
581be094 | 752 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); |
c4804214 | 753 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
c29f9a0a | 754 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); |
de9b05b8 | 755 | set_feature(&cpu->env, ARM_FEATURE_LPAE); |
3541addc | 756 | cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; |
b2d06f96 | 757 | cpu->midr = 0x412fc0f1; |
325b3cef | 758 | cpu->reset_fpsid = 0x410430f0; |
bd35c355 PM |
759 | cpu->mvfr0 = 0x10110222; |
760 | cpu->mvfr1 = 0x11111111; | |
64e1671f | 761 | cpu->ctr = 0x8444c004; |
0ca7e01c | 762 | cpu->reset_sctlr = 0x00c50078; |
2e4d7e3e PM |
763 | cpu->id_pfr0 = 0x00001131; |
764 | cpu->id_pfr1 = 0x00011011; | |
765 | cpu->id_dfr0 = 0x02010555; | |
766 | cpu->id_afr0 = 0x00000000; | |
767 | cpu->id_mmfr0 = 0x10201105; | |
768 | cpu->id_mmfr1 = 0x20000000; | |
769 | cpu->id_mmfr2 = 0x01240000; | |
770 | cpu->id_mmfr3 = 0x02102211; | |
771 | cpu->id_isar0 = 0x02101110; | |
772 | cpu->id_isar1 = 0x13112111; | |
773 | cpu->id_isar2 = 0x21232041; | |
774 | cpu->id_isar3 = 0x11112131; | |
775 | cpu->id_isar4 = 0x10011142; | |
85df3786 PM |
776 | cpu->clidr = 0x0a200023; |
777 | cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ | |
778 | cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ | |
779 | cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ | |
34f90529 | 780 | define_arm_cp_regs(cpu, cortexa15_cp_reginfo); |
777dc784 PM |
781 | } |
782 | ||
783 | static void ti925t_initfn(Object *obj) | |
784 | { | |
785 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
786 | set_feature(&cpu->env, ARM_FEATURE_V4T); |
787 | set_feature(&cpu->env, ARM_FEATURE_OMAPCP); | |
777dc784 | 788 | cpu->midr = ARM_CPUID_TI925T; |
64e1671f | 789 | cpu->ctr = 0x5109149; |
0ca7e01c | 790 | cpu->reset_sctlr = 0x00000070; |
777dc784 PM |
791 | } |
792 | ||
793 | static void sa1100_initfn(Object *obj) | |
794 | { | |
795 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
796 | |
797 | cpu->dtb_compatible = "intel,sa1100"; | |
581be094 | 798 | set_feature(&cpu->env, ARM_FEATURE_STRONGARM); |
c4804214 | 799 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 800 | cpu->midr = 0x4401A11B; |
0ca7e01c | 801 | cpu->reset_sctlr = 0x00000070; |
777dc784 PM |
802 | } |
803 | ||
804 | static void sa1110_initfn(Object *obj) | |
805 | { | |
806 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 | 807 | set_feature(&cpu->env, ARM_FEATURE_STRONGARM); |
c4804214 | 808 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 809 | cpu->midr = 0x6901B119; |
0ca7e01c | 810 | cpu->reset_sctlr = 0x00000070; |
777dc784 PM |
811 | } |
812 | ||
813 | static void pxa250_initfn(Object *obj) | |
814 | { | |
815 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
816 | |
817 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
818 | set_feature(&cpu->env, ARM_FEATURE_V5); |
819 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 820 | cpu->midr = 0x69052100; |
64e1671f | 821 | cpu->ctr = 0xd172172; |
0ca7e01c | 822 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
823 | } |
824 | ||
825 | static void pxa255_initfn(Object *obj) | |
826 | { | |
827 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
828 | |
829 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
830 | set_feature(&cpu->env, ARM_FEATURE_V5); |
831 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 832 | cpu->midr = 0x69052d00; |
64e1671f | 833 | cpu->ctr = 0xd172172; |
0ca7e01c | 834 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
835 | } |
836 | ||
837 | static void pxa260_initfn(Object *obj) | |
838 | { | |
839 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
840 | |
841 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
842 | set_feature(&cpu->env, ARM_FEATURE_V5); |
843 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 844 | cpu->midr = 0x69052903; |
64e1671f | 845 | cpu->ctr = 0xd172172; |
0ca7e01c | 846 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
847 | } |
848 | ||
849 | static void pxa261_initfn(Object *obj) | |
850 | { | |
851 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
852 | |
853 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
854 | set_feature(&cpu->env, ARM_FEATURE_V5); |
855 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 856 | cpu->midr = 0x69052d05; |
64e1671f | 857 | cpu->ctr = 0xd172172; |
0ca7e01c | 858 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
859 | } |
860 | ||
861 | static void pxa262_initfn(Object *obj) | |
862 | { | |
863 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
864 | |
865 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
866 | set_feature(&cpu->env, ARM_FEATURE_V5); |
867 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 868 | cpu->midr = 0x69052d06; |
64e1671f | 869 | cpu->ctr = 0xd172172; |
0ca7e01c | 870 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
871 | } |
872 | ||
873 | static void pxa270a0_initfn(Object *obj) | |
874 | { | |
875 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
876 | |
877 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
878 | set_feature(&cpu->env, ARM_FEATURE_V5); |
879 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
880 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 881 | cpu->midr = 0x69054110; |
64e1671f | 882 | cpu->ctr = 0xd172172; |
0ca7e01c | 883 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
884 | } |
885 | ||
886 | static void pxa270a1_initfn(Object *obj) | |
887 | { | |
888 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
889 | |
890 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
891 | set_feature(&cpu->env, ARM_FEATURE_V5); |
892 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
893 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 894 | cpu->midr = 0x69054111; |
64e1671f | 895 | cpu->ctr = 0xd172172; |
0ca7e01c | 896 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
897 | } |
898 | ||
899 | static void pxa270b0_initfn(Object *obj) | |
900 | { | |
901 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
902 | |
903 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
904 | set_feature(&cpu->env, ARM_FEATURE_V5); |
905 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
906 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 907 | cpu->midr = 0x69054112; |
64e1671f | 908 | cpu->ctr = 0xd172172; |
0ca7e01c | 909 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
910 | } |
911 | ||
912 | static void pxa270b1_initfn(Object *obj) | |
913 | { | |
914 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
915 | |
916 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
917 | set_feature(&cpu->env, ARM_FEATURE_V5); |
918 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
919 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 920 | cpu->midr = 0x69054113; |
64e1671f | 921 | cpu->ctr = 0xd172172; |
0ca7e01c | 922 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
923 | } |
924 | ||
925 | static void pxa270c0_initfn(Object *obj) | |
926 | { | |
927 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
928 | |
929 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
930 | set_feature(&cpu->env, ARM_FEATURE_V5); |
931 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
932 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 933 | cpu->midr = 0x69054114; |
64e1671f | 934 | cpu->ctr = 0xd172172; |
0ca7e01c | 935 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
936 | } |
937 | ||
938 | static void pxa270c5_initfn(Object *obj) | |
939 | { | |
940 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
941 | |
942 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
943 | set_feature(&cpu->env, ARM_FEATURE_V5); |
944 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
945 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 946 | cpu->midr = 0x69054117; |
64e1671f | 947 | cpu->ctr = 0xd172172; |
0ca7e01c | 948 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
949 | } |
950 | ||
f5f6d38b | 951 | #ifdef CONFIG_USER_ONLY |
777dc784 PM |
952 | static void arm_any_initfn(Object *obj) |
953 | { | |
954 | ARMCPU *cpu = ARM_CPU(obj); | |
81e69fb0 | 955 | set_feature(&cpu->env, ARM_FEATURE_V8); |
581be094 | 956 | set_feature(&cpu->env, ARM_FEATURE_VFP4); |
581be094 PM |
957 | set_feature(&cpu->env, ARM_FEATURE_NEON); |
958 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
25f748e3 PM |
959 | set_feature(&cpu->env, ARM_FEATURE_V8_AES); |
960 | set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); | |
961 | set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); | |
962 | set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); | |
eb0ecd5a | 963 | set_feature(&cpu->env, ARM_FEATURE_CRC); |
b2d06f96 | 964 | cpu->midr = 0xffffffff; |
777dc784 | 965 | } |
f5f6d38b | 966 | #endif |
777dc784 | 967 | |
15ee776b PM |
968 | #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ |
969 | ||
777dc784 PM |
970 | typedef struct ARMCPUInfo { |
971 | const char *name; | |
972 | void (*initfn)(Object *obj); | |
e6f010cc | 973 | void (*class_init)(ObjectClass *oc, void *data); |
777dc784 PM |
974 | } ARMCPUInfo; |
975 | ||
976 | static const ARMCPUInfo arm_cpus[] = { | |
15ee776b | 977 | #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) |
777dc784 PM |
978 | { .name = "arm926", .initfn = arm926_initfn }, |
979 | { .name = "arm946", .initfn = arm946_initfn }, | |
980 | { .name = "arm1026", .initfn = arm1026_initfn }, | |
981 | /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an | |
982 | * older core than plain "arm1136". In particular this does not | |
983 | * have the v6K features. | |
984 | */ | |
985 | { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, | |
986 | { .name = "arm1136", .initfn = arm1136_initfn }, | |
987 | { .name = "arm1176", .initfn = arm1176_initfn }, | |
988 | { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, | |
e6f010cc AF |
989 | { .name = "cortex-m3", .initfn = cortex_m3_initfn, |
990 | .class_init = arm_v7m_class_init }, | |
777dc784 PM |
991 | { .name = "cortex-a8", .initfn = cortex_a8_initfn }, |
992 | { .name = "cortex-a9", .initfn = cortex_a9_initfn }, | |
993 | { .name = "cortex-a15", .initfn = cortex_a15_initfn }, | |
994 | { .name = "ti925t", .initfn = ti925t_initfn }, | |
995 | { .name = "sa1100", .initfn = sa1100_initfn }, | |
996 | { .name = "sa1110", .initfn = sa1110_initfn }, | |
997 | { .name = "pxa250", .initfn = pxa250_initfn }, | |
998 | { .name = "pxa255", .initfn = pxa255_initfn }, | |
999 | { .name = "pxa260", .initfn = pxa260_initfn }, | |
1000 | { .name = "pxa261", .initfn = pxa261_initfn }, | |
1001 | { .name = "pxa262", .initfn = pxa262_initfn }, | |
1002 | /* "pxa270" is an alias for "pxa270-a0" */ | |
1003 | { .name = "pxa270", .initfn = pxa270a0_initfn }, | |
1004 | { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, | |
1005 | { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, | |
1006 | { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, | |
1007 | { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, | |
1008 | { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, | |
1009 | { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, | |
f5f6d38b | 1010 | #ifdef CONFIG_USER_ONLY |
777dc784 | 1011 | { .name = "any", .initfn = arm_any_initfn }, |
f5f6d38b | 1012 | #endif |
15ee776b | 1013 | #endif |
83e6813a | 1014 | { .name = NULL } |
777dc784 PM |
1015 | }; |
1016 | ||
5de16430 PM |
1017 | static Property arm_cpu_properties[] = { |
1018 | DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), | |
51a9b04b | 1019 | DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), |
5de16430 PM |
1020 | DEFINE_PROP_END_OF_LIST() |
1021 | }; | |
1022 | ||
dec9c2d4 AF |
1023 | static void arm_cpu_class_init(ObjectClass *oc, void *data) |
1024 | { | |
1025 | ARMCPUClass *acc = ARM_CPU_CLASS(oc); | |
1026 | CPUClass *cc = CPU_CLASS(acc); | |
14969266 AF |
1027 | DeviceClass *dc = DEVICE_CLASS(oc); |
1028 | ||
1029 | acc->parent_realize = dc->realize; | |
1030 | dc->realize = arm_cpu_realizefn; | |
5de16430 | 1031 | dc->props = arm_cpu_properties; |
dec9c2d4 AF |
1032 | |
1033 | acc->parent_reset = cc->reset; | |
1034 | cc->reset = arm_cpu_reset; | |
5900d6b2 AF |
1035 | |
1036 | cc->class_by_name = arm_cpu_class_by_name; | |
8c2e1b00 | 1037 | cc->has_work = arm_cpu_has_work; |
97a8ea5a | 1038 | cc->do_interrupt = arm_cpu_do_interrupt; |
878096ee | 1039 | cc->dump_state = arm_cpu_dump_state; |
f45748f1 | 1040 | cc->set_pc = arm_cpu_set_pc; |
5b50e790 AF |
1041 | cc->gdb_read_register = arm_cpu_gdb_read_register; |
1042 | cc->gdb_write_register = arm_cpu_gdb_write_register; | |
7510454e AF |
1043 | #ifdef CONFIG_USER_ONLY |
1044 | cc->handle_mmu_fault = arm_cpu_handle_mmu_fault; | |
1045 | #else | |
00b941e5 AF |
1046 | cc->get_phys_page_debug = arm_cpu_get_phys_page_debug; |
1047 | cc->vmsd = &vmstate_arm_cpu; | |
1048 | #endif | |
a0e372f0 | 1049 | cc->gdb_num_core_regs = 26; |
5b24c641 | 1050 | cc->gdb_core_xml_file = "arm-core.xml"; |
dec9c2d4 AF |
1051 | } |
1052 | ||
777dc784 PM |
1053 | static void cpu_register(const ARMCPUInfo *info) |
1054 | { | |
1055 | TypeInfo type_info = { | |
777dc784 PM |
1056 | .parent = TYPE_ARM_CPU, |
1057 | .instance_size = sizeof(ARMCPU), | |
1058 | .instance_init = info->initfn, | |
1059 | .class_size = sizeof(ARMCPUClass), | |
e6f010cc | 1060 | .class_init = info->class_init, |
777dc784 PM |
1061 | }; |
1062 | ||
51492fd1 | 1063 | type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); |
918fd083 | 1064 | type_register(&type_info); |
51492fd1 | 1065 | g_free((void *)type_info.name); |
777dc784 PM |
1066 | } |
1067 | ||
dec9c2d4 AF |
1068 | static const TypeInfo arm_cpu_type_info = { |
1069 | .name = TYPE_ARM_CPU, | |
1070 | .parent = TYPE_CPU, | |
1071 | .instance_size = sizeof(ARMCPU), | |
777dc784 | 1072 | .instance_init = arm_cpu_initfn, |
07a5b0d2 | 1073 | .instance_post_init = arm_cpu_post_init, |
4b6a83fb | 1074 | .instance_finalize = arm_cpu_finalizefn, |
777dc784 | 1075 | .abstract = true, |
dec9c2d4 AF |
1076 | .class_size = sizeof(ARMCPUClass), |
1077 | .class_init = arm_cpu_class_init, | |
1078 | }; | |
1079 | ||
1080 | static void arm_cpu_register_types(void) | |
1081 | { | |
83e6813a | 1082 | const ARMCPUInfo *info = arm_cpus; |
777dc784 | 1083 | |
dec9c2d4 | 1084 | type_register_static(&arm_cpu_type_info); |
83e6813a PM |
1085 | |
1086 | while (info->name) { | |
1087 | cpu_register(info); | |
1088 | info++; | |
777dc784 | 1089 | } |
dec9c2d4 AF |
1090 | } |
1091 | ||
1092 | type_init(arm_cpu_register_types) |