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dec9c2d4 AF |
1 | /* |
2 | * QEMU ARM CPU | |
3 | * | |
4 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | */ | |
20 | ||
778c3a06 | 21 | #include "cpu.h" |
ccd38087 | 22 | #include "internals.h" |
dec9c2d4 | 23 | #include "qemu-common.h" |
5de16430 | 24 | #include "hw/qdev-properties.h" |
07a5b0d2 | 25 | #include "qapi/qmp/qerror.h" |
3c30dd5a PM |
26 | #if !defined(CONFIG_USER_ONLY) |
27 | #include "hw/loader.h" | |
28 | #endif | |
7c1840b6 | 29 | #include "hw/arm/arm.h" |
9c17d615 | 30 | #include "sysemu/sysemu.h" |
7c1840b6 | 31 | #include "sysemu/kvm.h" |
50a2c6e5 | 32 | #include "kvm_arm.h" |
dec9c2d4 | 33 | |
f45748f1 AF |
34 | static void arm_cpu_set_pc(CPUState *cs, vaddr value) |
35 | { | |
36 | ARMCPU *cpu = ARM_CPU(cs); | |
37 | ||
38 | cpu->env.regs[15] = value; | |
39 | } | |
40 | ||
8c2e1b00 AF |
41 | static bool arm_cpu_has_work(CPUState *cs) |
42 | { | |
543486db RH |
43 | ARMCPU *cpu = ARM_CPU(cs); |
44 | ||
45 | return !cpu->powered_off | |
46 | && cs->interrupt_request & | |
136e67e9 EI |
47 | (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD |
48 | | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | |
49 | | CPU_INTERRUPT_EXITTB); | |
8c2e1b00 AF |
50 | } |
51 | ||
4b6a83fb PM |
52 | static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) |
53 | { | |
54 | /* Reset a single ARMCPRegInfo register */ | |
55 | ARMCPRegInfo *ri = value; | |
56 | ARMCPU *cpu = opaque; | |
57 | ||
58 | if (ri->type & ARM_CP_SPECIAL) { | |
59 | return; | |
60 | } | |
61 | ||
62 | if (ri->resetfn) { | |
63 | ri->resetfn(&cpu->env, ri); | |
64 | return; | |
65 | } | |
66 | ||
67 | /* A zero offset is never possible as it would be regs[0] | |
68 | * so we use it to indicate that reset is being handled elsewhere. | |
69 | * This is basically only used for fields in non-core coprocessors | |
70 | * (like the pxa2xx ones). | |
71 | */ | |
72 | if (!ri->fieldoffset) { | |
73 | return; | |
74 | } | |
75 | ||
67ed771d | 76 | if (cpreg_field_is_64bit(ri)) { |
4b6a83fb PM |
77 | CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; |
78 | } else { | |
79 | CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; | |
80 | } | |
81 | } | |
82 | ||
dec9c2d4 AF |
83 | /* CPUClass::reset() */ |
84 | static void arm_cpu_reset(CPUState *s) | |
85 | { | |
86 | ARMCPU *cpu = ARM_CPU(s); | |
87 | ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); | |
3c30dd5a | 88 | CPUARMState *env = &cpu->env; |
3c30dd5a | 89 | |
dec9c2d4 AF |
90 | acc->parent_reset(s); |
91 | ||
f0c3c505 | 92 | memset(env, 0, offsetof(CPUARMState, features)); |
4b6a83fb | 93 | g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); |
3c30dd5a PM |
94 | env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; |
95 | env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; | |
96 | env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; | |
a50c0f51 | 97 | env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2; |
3c30dd5a | 98 | |
543486db RH |
99 | cpu->powered_off = cpu->start_powered_off; |
100 | s->halted = cpu->start_powered_off; | |
101 | ||
3c30dd5a PM |
102 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { |
103 | env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; | |
104 | } | |
105 | ||
3926cc84 AG |
106 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { |
107 | /* 64 bit CPUs always start in 64 bit mode */ | |
108 | env->aarch64 = 1; | |
d356312f PM |
109 | #if defined(CONFIG_USER_ONLY) |
110 | env->pstate = PSTATE_MODE_EL0t; | |
14e5f106 | 111 | /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ |
137feaa9 | 112 | env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; |
8c6afa6a | 113 | /* and to the FP/Neon instructions */ |
7ebd5f2e | 114 | env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); |
d356312f | 115 | #else |
5097227c GB |
116 | /* Reset into the highest available EL */ |
117 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
118 | env->pstate = PSTATE_MODE_EL3h; | |
119 | } else if (arm_feature(env, ARM_FEATURE_EL2)) { | |
120 | env->pstate = PSTATE_MODE_EL2h; | |
121 | } else { | |
122 | env->pstate = PSTATE_MODE_EL1h; | |
123 | } | |
3933443e | 124 | env->pc = cpu->rvbar; |
8c6afa6a PM |
125 | #endif |
126 | } else { | |
127 | #if defined(CONFIG_USER_ONLY) | |
128 | /* Userspace expects access to cp10 and cp11 for FP/Neon */ | |
7ebd5f2e | 129 | env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); |
d356312f | 130 | #endif |
3926cc84 AG |
131 | } |
132 | ||
3c30dd5a PM |
133 | #if defined(CONFIG_USER_ONLY) |
134 | env->uncached_cpsr = ARM_CPU_MODE_USR; | |
135 | /* For user mode we must enable access to coprocessors */ | |
136 | env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; | |
137 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { | |
138 | env->cp15.c15_cpar = 3; | |
139 | } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
140 | env->cp15.c15_cpar = 1; | |
141 | } | |
142 | #else | |
143 | /* SVC mode with interrupts disabled. */ | |
4cc35614 PM |
144 | env->uncached_cpsr = ARM_CPU_MODE_SVC; |
145 | env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; | |
3c30dd5a | 146 | /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is |
6e3cf5df MG |
147 | * clear at reset. Initial SP and PC are loaded from ROM. |
148 | */ | |
3c30dd5a | 149 | if (IS_M(env)) { |
6e3cf5df MG |
150 | uint32_t initial_msp; /* Loaded from 0x0 */ |
151 | uint32_t initial_pc; /* Loaded from 0x4 */ | |
3c30dd5a | 152 | uint8_t *rom; |
6e3cf5df | 153 | |
4cc35614 | 154 | env->daif &= ~PSTATE_I; |
3c30dd5a PM |
155 | rom = rom_ptr(0); |
156 | if (rom) { | |
6e3cf5df MG |
157 | /* Address zero is covered by ROM which hasn't yet been |
158 | * copied into physical memory. | |
159 | */ | |
160 | initial_msp = ldl_p(rom); | |
161 | initial_pc = ldl_p(rom + 4); | |
162 | } else { | |
163 | /* Address zero not covered by a ROM blob, or the ROM blob | |
164 | * is in non-modifiable memory and this is a second reset after | |
165 | * it got copied into memory. In the latter case, rom_ptr | |
166 | * will return a NULL pointer and we should use ldl_phys instead. | |
167 | */ | |
168 | initial_msp = ldl_phys(s->as, 0); | |
169 | initial_pc = ldl_phys(s->as, 4); | |
3c30dd5a | 170 | } |
6e3cf5df MG |
171 | |
172 | env->regs[13] = initial_msp & 0xFFFFFFFC; | |
173 | env->regs[15] = initial_pc & ~1; | |
174 | env->thumb = initial_pc & 1; | |
3c30dd5a | 175 | } |
387f9806 | 176 | |
137feaa9 FA |
177 | /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently |
178 | * executing as AArch32 then check if highvecs are enabled and | |
179 | * adjust the PC accordingly. | |
180 | */ | |
181 | if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { | |
34bf7744 | 182 | env->regs[15] = 0xFFFF0000; |
387f9806 AP |
183 | } |
184 | ||
3c30dd5a | 185 | env->vfp.xregs[ARM_VFP_FPEXC] = 0; |
3c30dd5a PM |
186 | #endif |
187 | set_flush_to_zero(1, &env->vfp.standard_fp_status); | |
188 | set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); | |
189 | set_default_nan_mode(1, &env->vfp.standard_fp_status); | |
190 | set_float_detect_tininess(float_tininess_before_rounding, | |
191 | &env->vfp.fp_status); | |
192 | set_float_detect_tininess(float_tininess_before_rounding, | |
193 | &env->vfp.standard_fp_status); | |
00c8cb0a | 194 | tlb_flush(s, 1); |
50a2c6e5 PB |
195 | |
196 | #ifndef CONFIG_USER_ONLY | |
197 | if (kvm_enabled()) { | |
198 | kvm_arm_reset_vcpu(cpu); | |
199 | } | |
200 | #endif | |
9ee98ce8 | 201 | |
46747d15 | 202 | hw_breakpoint_update_all(cpu); |
9ee98ce8 | 203 | hw_watchpoint_update_all(cpu); |
dec9c2d4 AF |
204 | } |
205 | ||
e8925712 RH |
206 | bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) |
207 | { | |
208 | CPUClass *cc = CPU_GET_CLASS(cs); | |
012a906b GB |
209 | CPUARMState *env = cs->env_ptr; |
210 | uint32_t cur_el = arm_current_el(env); | |
211 | bool secure = arm_is_secure(env); | |
212 | uint32_t target_el; | |
213 | uint32_t excp_idx; | |
e8925712 RH |
214 | bool ret = false; |
215 | ||
012a906b GB |
216 | if (interrupt_request & CPU_INTERRUPT_FIQ) { |
217 | excp_idx = EXCP_FIQ; | |
218 | target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); | |
219 | if (arm_excp_unmasked(cs, excp_idx, target_el)) { | |
220 | cs->exception_index = excp_idx; | |
221 | env->exception.target_el = target_el; | |
222 | cc->do_interrupt(cs); | |
223 | ret = true; | |
224 | } | |
e8925712 | 225 | } |
012a906b GB |
226 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
227 | excp_idx = EXCP_IRQ; | |
228 | target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); | |
229 | if (arm_excp_unmasked(cs, excp_idx, target_el)) { | |
230 | cs->exception_index = excp_idx; | |
231 | env->exception.target_el = target_el; | |
232 | cc->do_interrupt(cs); | |
233 | ret = true; | |
234 | } | |
e8925712 | 235 | } |
012a906b GB |
236 | if (interrupt_request & CPU_INTERRUPT_VIRQ) { |
237 | excp_idx = EXCP_VIRQ; | |
238 | target_el = 1; | |
239 | if (arm_excp_unmasked(cs, excp_idx, target_el)) { | |
240 | cs->exception_index = excp_idx; | |
241 | env->exception.target_el = target_el; | |
242 | cc->do_interrupt(cs); | |
243 | ret = true; | |
244 | } | |
136e67e9 | 245 | } |
012a906b GB |
246 | if (interrupt_request & CPU_INTERRUPT_VFIQ) { |
247 | excp_idx = EXCP_VFIQ; | |
248 | target_el = 1; | |
249 | if (arm_excp_unmasked(cs, excp_idx, target_el)) { | |
250 | cs->exception_index = excp_idx; | |
251 | env->exception.target_el = target_el; | |
252 | cc->do_interrupt(cs); | |
253 | ret = true; | |
254 | } | |
136e67e9 | 255 | } |
e8925712 RH |
256 | |
257 | return ret; | |
258 | } | |
259 | ||
b5c633c5 PM |
260 | #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) |
261 | static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) | |
262 | { | |
263 | CPUClass *cc = CPU_GET_CLASS(cs); | |
264 | ARMCPU *cpu = ARM_CPU(cs); | |
265 | CPUARMState *env = &cpu->env; | |
266 | bool ret = false; | |
267 | ||
268 | ||
269 | if (interrupt_request & CPU_INTERRUPT_FIQ | |
270 | && !(env->daif & PSTATE_F)) { | |
271 | cs->exception_index = EXCP_FIQ; | |
272 | cc->do_interrupt(cs); | |
273 | ret = true; | |
274 | } | |
275 | /* ARMv7-M interrupt return works by loading a magic value | |
276 | * into the PC. On real hardware the load causes the | |
277 | * return to occur. The qemu implementation performs the | |
278 | * jump normally, then does the exception return when the | |
279 | * CPU tries to execute code at the magic address. | |
280 | * This will cause the magic PC value to be pushed to | |
281 | * the stack if an interrupt occurred at the wrong time. | |
282 | * We avoid this by disabling interrupts when | |
283 | * pc contains a magic address. | |
284 | */ | |
285 | if (interrupt_request & CPU_INTERRUPT_HARD | |
286 | && !(env->daif & PSTATE_I) | |
287 | && (env->regs[15] < 0xfffffff0)) { | |
288 | cs->exception_index = EXCP_IRQ; | |
289 | cc->do_interrupt(cs); | |
290 | ret = true; | |
291 | } | |
292 | return ret; | |
293 | } | |
294 | #endif | |
295 | ||
7c1840b6 PM |
296 | #ifndef CONFIG_USER_ONLY |
297 | static void arm_cpu_set_irq(void *opaque, int irq, int level) | |
298 | { | |
299 | ARMCPU *cpu = opaque; | |
136e67e9 | 300 | CPUARMState *env = &cpu->env; |
7c1840b6 | 301 | CPUState *cs = CPU(cpu); |
136e67e9 EI |
302 | static const int mask[] = { |
303 | [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, | |
304 | [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, | |
305 | [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, | |
306 | [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ | |
307 | }; | |
7c1840b6 PM |
308 | |
309 | switch (irq) { | |
136e67e9 EI |
310 | case ARM_CPU_VIRQ: |
311 | case ARM_CPU_VFIQ: | |
312 | if (!arm_feature(env, ARM_FEATURE_EL2)) { | |
313 | hw_error("%s: Virtual interrupt line %d with no EL2 support\n", | |
314 | __func__, irq); | |
7c1840b6 | 315 | } |
136e67e9 EI |
316 | /* fall through */ |
317 | case ARM_CPU_IRQ: | |
7c1840b6 PM |
318 | case ARM_CPU_FIQ: |
319 | if (level) { | |
136e67e9 | 320 | cpu_interrupt(cs, mask[irq]); |
7c1840b6 | 321 | } else { |
136e67e9 | 322 | cpu_reset_interrupt(cs, mask[irq]); |
7c1840b6 PM |
323 | } |
324 | break; | |
325 | default: | |
326 | hw_error("arm_cpu_set_irq: Bad interrupt line %d\n", irq); | |
327 | } | |
328 | } | |
329 | ||
330 | static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) | |
331 | { | |
332 | #ifdef CONFIG_KVM | |
333 | ARMCPU *cpu = opaque; | |
334 | CPUState *cs = CPU(cpu); | |
335 | int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT; | |
336 | ||
337 | switch (irq) { | |
338 | case ARM_CPU_IRQ: | |
339 | kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; | |
340 | break; | |
341 | case ARM_CPU_FIQ: | |
342 | kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; | |
343 | break; | |
344 | default: | |
345 | hw_error("arm_cpu_kvm_set_irq: Bad interrupt line %d\n", irq); | |
346 | } | |
347 | kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; | |
348 | kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); | |
349 | #endif | |
350 | } | |
84f2bed3 PS |
351 | |
352 | static bool arm_cpu_is_big_endian(CPUState *cs) | |
353 | { | |
354 | ARMCPU *cpu = ARM_CPU(cs); | |
355 | CPUARMState *env = &cpu->env; | |
356 | int cur_el; | |
357 | ||
358 | cpu_synchronize_state(cs); | |
359 | ||
360 | /* In 32bit guest endianness is determined by looking at CPSR's E bit */ | |
361 | if (!is_a64(env)) { | |
362 | return (env->uncached_cpsr & CPSR_E) ? 1 : 0; | |
363 | } | |
364 | ||
365 | cur_el = arm_current_el(env); | |
366 | ||
367 | if (cur_el == 0) { | |
368 | return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0; | |
369 | } | |
370 | ||
371 | return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0; | |
372 | } | |
373 | ||
7c1840b6 PM |
374 | #endif |
375 | ||
581be094 PM |
376 | static inline void set_feature(CPUARMState *env, int feature) |
377 | { | |
918f5dca | 378 | env->features |= 1ULL << feature; |
581be094 PM |
379 | } |
380 | ||
08828484 GB |
381 | static inline void unset_feature(CPUARMState *env, int feature) |
382 | { | |
383 | env->features &= ~(1ULL << feature); | |
384 | } | |
385 | ||
eb5e1d3c PF |
386 | #define ARM_CPUS_PER_CLUSTER 8 |
387 | ||
777dc784 PM |
388 | static void arm_cpu_initfn(Object *obj) |
389 | { | |
c05efcb1 | 390 | CPUState *cs = CPU(obj); |
777dc784 | 391 | ARMCPU *cpu = ARM_CPU(obj); |
79614b78 | 392 | static bool inited; |
eb5e1d3c | 393 | uint32_t Aff1, Aff0; |
777dc784 | 394 | |
c05efcb1 | 395 | cs->env_ptr = &cpu->env; |
777dc784 | 396 | cpu_exec_init(&cpu->env); |
4b6a83fb PM |
397 | cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, |
398 | g_free, g_free); | |
79614b78 | 399 | |
eb5e1d3c PF |
400 | /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. |
401 | * We don't support setting cluster ID ([16..23]) (known as Aff2 | |
402 | * in later ARM ARM versions), or any of the higher affinity level fields, | |
403 | * so these bits always RAZ. | |
404 | */ | |
405 | Aff1 = cs->cpu_index / ARM_CPUS_PER_CLUSTER; | |
406 | Aff0 = cs->cpu_index % ARM_CPUS_PER_CLUSTER; | |
407 | cpu->mp_affinity = (Aff1 << 8) | Aff0; | |
408 | ||
7c1840b6 PM |
409 | #ifndef CONFIG_USER_ONLY |
410 | /* Our inbound IRQ and FIQ lines */ | |
411 | if (kvm_enabled()) { | |
136e67e9 EI |
412 | /* VIRQ and VFIQ are unused with KVM but we add them to maintain |
413 | * the same interface as non-KVM CPUs. | |
414 | */ | |
415 | qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); | |
7c1840b6 | 416 | } else { |
136e67e9 | 417 | qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); |
7c1840b6 | 418 | } |
55d284af | 419 | |
bc72ad67 | 420 | cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, |
55d284af | 421 | arm_gt_ptimer_cb, cpu); |
bc72ad67 | 422 | cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, |
55d284af PM |
423 | arm_gt_vtimer_cb, cpu); |
424 | qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, | |
425 | ARRAY_SIZE(cpu->gt_timer_outputs)); | |
7c1840b6 PM |
426 | #endif |
427 | ||
54d3e3f5 PM |
428 | /* DTB consumers generally don't in fact care what the 'compatible' |
429 | * string is, so always provide some string and trust that a hypothetical | |
430 | * picky DTB consumer will also provide a helpful error message. | |
431 | */ | |
432 | cpu->dtb_compatible = "qemu,unknown"; | |
dd032e34 | 433 | cpu->psci_version = 1; /* By default assume PSCI v0.1 */ |
3541addc | 434 | cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; |
54d3e3f5 | 435 | |
98128601 RH |
436 | if (tcg_enabled()) { |
437 | cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ | |
438 | if (!inited) { | |
439 | inited = true; | |
440 | arm_translate_init(); | |
441 | } | |
79614b78 | 442 | } |
4b6a83fb PM |
443 | } |
444 | ||
07a5b0d2 | 445 | static Property arm_cpu_reset_cbar_property = |
f318cec6 | 446 | DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); |
07a5b0d2 | 447 | |
68e0a40a AP |
448 | static Property arm_cpu_reset_hivecs_property = |
449 | DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); | |
450 | ||
3933443e PM |
451 | static Property arm_cpu_rvbar_property = |
452 | DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); | |
453 | ||
51942aee GB |
454 | static Property arm_cpu_has_el3_property = |
455 | DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); | |
456 | ||
07a5b0d2 PC |
457 | static void arm_cpu_post_init(Object *obj) |
458 | { | |
459 | ARMCPU *cpu = ARM_CPU(obj); | |
07a5b0d2 | 460 | |
f318cec6 PM |
461 | if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || |
462 | arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { | |
07a5b0d2 | 463 | qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, |
5433a0a8 | 464 | &error_abort); |
07a5b0d2 | 465 | } |
68e0a40a AP |
466 | |
467 | if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { | |
468 | qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property, | |
5433a0a8 | 469 | &error_abort); |
68e0a40a | 470 | } |
3933443e PM |
471 | |
472 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | |
473 | qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property, | |
474 | &error_abort); | |
475 | } | |
51942aee GB |
476 | |
477 | if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { | |
478 | /* Add the has_el3 state CPU property only if EL3 is allowed. This will | |
479 | * prevent "has_el3" from existing on CPUs which cannot support EL3. | |
480 | */ | |
481 | qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property, | |
482 | &error_abort); | |
483 | } | |
07a5b0d2 PC |
484 | } |
485 | ||
4b6a83fb PM |
486 | static void arm_cpu_finalizefn(Object *obj) |
487 | { | |
488 | ARMCPU *cpu = ARM_CPU(obj); | |
489 | g_hash_table_destroy(cpu->cp_regs); | |
777dc784 PM |
490 | } |
491 | ||
14969266 | 492 | static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
581be094 | 493 | { |
14a10fc3 | 494 | CPUState *cs = CPU(dev); |
14969266 AF |
495 | ARMCPU *cpu = ARM_CPU(dev); |
496 | ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); | |
581be094 | 497 | CPUARMState *env = &cpu->env; |
14969266 | 498 | |
581be094 | 499 | /* Some features automatically imply others: */ |
81e69fb0 MR |
500 | if (arm_feature(env, ARM_FEATURE_V8)) { |
501 | set_feature(env, ARM_FEATURE_V7); | |
502 | set_feature(env, ARM_FEATURE_ARM_DIV); | |
503 | set_feature(env, ARM_FEATURE_LPAE); | |
504 | } | |
581be094 PM |
505 | if (arm_feature(env, ARM_FEATURE_V7)) { |
506 | set_feature(env, ARM_FEATURE_VAPA); | |
507 | set_feature(env, ARM_FEATURE_THUMB2); | |
81bdde9d | 508 | set_feature(env, ARM_FEATURE_MPIDR); |
581be094 PM |
509 | if (!arm_feature(env, ARM_FEATURE_M)) { |
510 | set_feature(env, ARM_FEATURE_V6K); | |
511 | } else { | |
512 | set_feature(env, ARM_FEATURE_V6); | |
513 | } | |
514 | } | |
515 | if (arm_feature(env, ARM_FEATURE_V6K)) { | |
516 | set_feature(env, ARM_FEATURE_V6); | |
517 | set_feature(env, ARM_FEATURE_MVFR); | |
518 | } | |
519 | if (arm_feature(env, ARM_FEATURE_V6)) { | |
520 | set_feature(env, ARM_FEATURE_V5); | |
521 | if (!arm_feature(env, ARM_FEATURE_M)) { | |
522 | set_feature(env, ARM_FEATURE_AUXCR); | |
523 | } | |
524 | } | |
525 | if (arm_feature(env, ARM_FEATURE_V5)) { | |
526 | set_feature(env, ARM_FEATURE_V4T); | |
527 | } | |
528 | if (arm_feature(env, ARM_FEATURE_M)) { | |
529 | set_feature(env, ARM_FEATURE_THUMB_DIV); | |
530 | } | |
531 | if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { | |
532 | set_feature(env, ARM_FEATURE_THUMB_DIV); | |
533 | } | |
534 | if (arm_feature(env, ARM_FEATURE_VFP4)) { | |
535 | set_feature(env, ARM_FEATURE_VFP3); | |
da5141fc | 536 | set_feature(env, ARM_FEATURE_VFP_FP16); |
581be094 PM |
537 | } |
538 | if (arm_feature(env, ARM_FEATURE_VFP3)) { | |
539 | set_feature(env, ARM_FEATURE_VFP); | |
540 | } | |
de9b05b8 | 541 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
bdcc150d | 542 | set_feature(env, ARM_FEATURE_V7MP); |
de9b05b8 PM |
543 | set_feature(env, ARM_FEATURE_PXN); |
544 | } | |
f318cec6 PM |
545 | if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { |
546 | set_feature(env, ARM_FEATURE_CBAR); | |
547 | } | |
2ceb98c0 | 548 | |
68e0a40a AP |
549 | if (cpu->reset_hivecs) { |
550 | cpu->reset_sctlr |= (1 << 13); | |
551 | } | |
552 | ||
51942aee GB |
553 | if (!cpu->has_el3) { |
554 | /* If the has_el3 CPU property is disabled then we need to disable the | |
555 | * feature. | |
556 | */ | |
557 | unset_feature(env, ARM_FEATURE_EL3); | |
558 | ||
559 | /* Disable the security extension feature bits in the processor feature | |
3d5c84ff | 560 | * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. |
51942aee GB |
561 | */ |
562 | cpu->id_pfr1 &= ~0xf0; | |
3d5c84ff | 563 | cpu->id_aa64pfr0 &= ~0xf000; |
51942aee GB |
564 | } |
565 | ||
2ceb98c0 | 566 | register_cp_regs_for_features(cpu); |
14969266 AF |
567 | arm_cpu_register_gdb_regs_for_features(cpu); |
568 | ||
721fae12 PM |
569 | init_cpreg_list(cpu); |
570 | ||
14a10fc3 | 571 | qemu_init_vcpu(cs); |
00d0f7cb | 572 | cpu_reset(cs); |
14969266 AF |
573 | |
574 | acc->parent_realize(dev, errp); | |
581be094 PM |
575 | } |
576 | ||
5900d6b2 AF |
577 | static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) |
578 | { | |
579 | ObjectClass *oc; | |
51492fd1 | 580 | char *typename; |
fb8d6c24 | 581 | char **cpuname; |
5900d6b2 AF |
582 | |
583 | if (!cpu_model) { | |
584 | return NULL; | |
585 | } | |
586 | ||
fb8d6c24 GB |
587 | cpuname = g_strsplit(cpu_model, ",", 1); |
588 | typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpuname[0]); | |
51492fd1 | 589 | oc = object_class_by_name(typename); |
fb8d6c24 | 590 | g_strfreev(cpuname); |
51492fd1 | 591 | g_free(typename); |
245fb54d AF |
592 | if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || |
593 | object_class_is_abstract(oc)) { | |
5900d6b2 AF |
594 | return NULL; |
595 | } | |
596 | return oc; | |
597 | } | |
598 | ||
15ee776b PM |
599 | /* CPU models. These are not needed for the AArch64 linux-user build. */ |
600 | #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) | |
601 | ||
777dc784 PM |
602 | static void arm926_initfn(Object *obj) |
603 | { | |
604 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
605 | |
606 | cpu->dtb_compatible = "arm,arm926"; | |
581be094 PM |
607 | set_feature(&cpu->env, ARM_FEATURE_V5); |
608 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
c4804214 PM |
609 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
610 | set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); | |
b2d06f96 | 611 | cpu->midr = 0x41069265; |
325b3cef | 612 | cpu->reset_fpsid = 0x41011090; |
64e1671f | 613 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 614 | cpu->reset_sctlr = 0x00090078; |
777dc784 PM |
615 | } |
616 | ||
617 | static void arm946_initfn(Object *obj) | |
618 | { | |
619 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
620 | |
621 | cpu->dtb_compatible = "arm,arm946"; | |
581be094 PM |
622 | set_feature(&cpu->env, ARM_FEATURE_V5); |
623 | set_feature(&cpu->env, ARM_FEATURE_MPU); | |
c4804214 | 624 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 625 | cpu->midr = 0x41059461; |
64e1671f | 626 | cpu->ctr = 0x0f004006; |
0ca7e01c | 627 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
628 | } |
629 | ||
630 | static void arm1026_initfn(Object *obj) | |
631 | { | |
632 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
633 | |
634 | cpu->dtb_compatible = "arm,arm1026"; | |
581be094 PM |
635 | set_feature(&cpu->env, ARM_FEATURE_V5); |
636 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
637 | set_feature(&cpu->env, ARM_FEATURE_AUXCR); | |
c4804214 PM |
638 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
639 | set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); | |
b2d06f96 | 640 | cpu->midr = 0x4106a262; |
325b3cef | 641 | cpu->reset_fpsid = 0x410110a0; |
64e1671f | 642 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 643 | cpu->reset_sctlr = 0x00090078; |
2771db27 | 644 | cpu->reset_auxcr = 1; |
06d76f31 PM |
645 | { |
646 | /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ | |
647 | ARMCPRegInfo ifar = { | |
648 | .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, | |
649 | .access = PL1_RW, | |
b848ce2b | 650 | .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), |
06d76f31 PM |
651 | .resetvalue = 0 |
652 | }; | |
653 | define_one_arm_cp_reg(cpu, &ifar); | |
654 | } | |
777dc784 PM |
655 | } |
656 | ||
657 | static void arm1136_r2_initfn(Object *obj) | |
658 | { | |
659 | ARMCPU *cpu = ARM_CPU(obj); | |
2e4d7e3e PM |
660 | /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an |
661 | * older core than plain "arm1136". In particular this does not | |
662 | * have the v6K features. | |
663 | * These ID register values are correct for 1136 but may be wrong | |
664 | * for 1136_r2 (in particular r0p2 does not actually implement most | |
665 | * of the ID registers). | |
666 | */ | |
54d3e3f5 PM |
667 | |
668 | cpu->dtb_compatible = "arm,arm1136"; | |
581be094 PM |
669 | set_feature(&cpu->env, ARM_FEATURE_V6); |
670 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
c4804214 PM |
671 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
672 | set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); | |
673 | set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); | |
b2d06f96 | 674 | cpu->midr = 0x4107b362; |
325b3cef | 675 | cpu->reset_fpsid = 0x410120b4; |
bd35c355 PM |
676 | cpu->mvfr0 = 0x11111111; |
677 | cpu->mvfr1 = 0x00000000; | |
64e1671f | 678 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 679 | cpu->reset_sctlr = 0x00050078; |
2e4d7e3e PM |
680 | cpu->id_pfr0 = 0x111; |
681 | cpu->id_pfr1 = 0x1; | |
682 | cpu->id_dfr0 = 0x2; | |
683 | cpu->id_afr0 = 0x3; | |
684 | cpu->id_mmfr0 = 0x01130003; | |
685 | cpu->id_mmfr1 = 0x10030302; | |
686 | cpu->id_mmfr2 = 0x01222110; | |
687 | cpu->id_isar0 = 0x00140011; | |
688 | cpu->id_isar1 = 0x12002111; | |
689 | cpu->id_isar2 = 0x11231111; | |
690 | cpu->id_isar3 = 0x01102131; | |
691 | cpu->id_isar4 = 0x141; | |
2771db27 | 692 | cpu->reset_auxcr = 7; |
777dc784 PM |
693 | } |
694 | ||
695 | static void arm1136_initfn(Object *obj) | |
696 | { | |
697 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
698 | |
699 | cpu->dtb_compatible = "arm,arm1136"; | |
581be094 PM |
700 | set_feature(&cpu->env, ARM_FEATURE_V6K); |
701 | set_feature(&cpu->env, ARM_FEATURE_V6); | |
702 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
c4804214 PM |
703 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
704 | set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); | |
705 | set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); | |
b2d06f96 | 706 | cpu->midr = 0x4117b363; |
325b3cef | 707 | cpu->reset_fpsid = 0x410120b4; |
bd35c355 PM |
708 | cpu->mvfr0 = 0x11111111; |
709 | cpu->mvfr1 = 0x00000000; | |
64e1671f | 710 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 711 | cpu->reset_sctlr = 0x00050078; |
2e4d7e3e PM |
712 | cpu->id_pfr0 = 0x111; |
713 | cpu->id_pfr1 = 0x1; | |
714 | cpu->id_dfr0 = 0x2; | |
715 | cpu->id_afr0 = 0x3; | |
716 | cpu->id_mmfr0 = 0x01130003; | |
717 | cpu->id_mmfr1 = 0x10030302; | |
718 | cpu->id_mmfr2 = 0x01222110; | |
719 | cpu->id_isar0 = 0x00140011; | |
720 | cpu->id_isar1 = 0x12002111; | |
721 | cpu->id_isar2 = 0x11231111; | |
722 | cpu->id_isar3 = 0x01102131; | |
723 | cpu->id_isar4 = 0x141; | |
2771db27 | 724 | cpu->reset_auxcr = 7; |
777dc784 PM |
725 | } |
726 | ||
727 | static void arm1176_initfn(Object *obj) | |
728 | { | |
729 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
730 | |
731 | cpu->dtb_compatible = "arm,arm1176"; | |
581be094 PM |
732 | set_feature(&cpu->env, ARM_FEATURE_V6K); |
733 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
734 | set_feature(&cpu->env, ARM_FEATURE_VAPA); | |
c4804214 PM |
735 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
736 | set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); | |
737 | set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); | |
c0ccb02d | 738 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
b2d06f96 | 739 | cpu->midr = 0x410fb767; |
325b3cef | 740 | cpu->reset_fpsid = 0x410120b5; |
bd35c355 PM |
741 | cpu->mvfr0 = 0x11111111; |
742 | cpu->mvfr1 = 0x00000000; | |
64e1671f | 743 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 744 | cpu->reset_sctlr = 0x00050078; |
2e4d7e3e PM |
745 | cpu->id_pfr0 = 0x111; |
746 | cpu->id_pfr1 = 0x11; | |
747 | cpu->id_dfr0 = 0x33; | |
748 | cpu->id_afr0 = 0; | |
749 | cpu->id_mmfr0 = 0x01130003; | |
750 | cpu->id_mmfr1 = 0x10030302; | |
751 | cpu->id_mmfr2 = 0x01222100; | |
752 | cpu->id_isar0 = 0x0140011; | |
753 | cpu->id_isar1 = 0x12002111; | |
754 | cpu->id_isar2 = 0x11231121; | |
755 | cpu->id_isar3 = 0x01102131; | |
756 | cpu->id_isar4 = 0x01141; | |
2771db27 | 757 | cpu->reset_auxcr = 7; |
777dc784 PM |
758 | } |
759 | ||
760 | static void arm11mpcore_initfn(Object *obj) | |
761 | { | |
762 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
763 | |
764 | cpu->dtb_compatible = "arm,arm11mpcore"; | |
581be094 PM |
765 | set_feature(&cpu->env, ARM_FEATURE_V6K); |
766 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
767 | set_feature(&cpu->env, ARM_FEATURE_VAPA); | |
81bdde9d | 768 | set_feature(&cpu->env, ARM_FEATURE_MPIDR); |
c4804214 | 769 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 770 | cpu->midr = 0x410fb022; |
325b3cef | 771 | cpu->reset_fpsid = 0x410120b4; |
bd35c355 PM |
772 | cpu->mvfr0 = 0x11111111; |
773 | cpu->mvfr1 = 0x00000000; | |
200bf596 | 774 | cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ |
2e4d7e3e PM |
775 | cpu->id_pfr0 = 0x111; |
776 | cpu->id_pfr1 = 0x1; | |
777 | cpu->id_dfr0 = 0; | |
778 | cpu->id_afr0 = 0x2; | |
779 | cpu->id_mmfr0 = 0x01100103; | |
780 | cpu->id_mmfr1 = 0x10020302; | |
781 | cpu->id_mmfr2 = 0x01222000; | |
782 | cpu->id_isar0 = 0x00100011; | |
783 | cpu->id_isar1 = 0x12002111; | |
784 | cpu->id_isar2 = 0x11221011; | |
785 | cpu->id_isar3 = 0x01102131; | |
786 | cpu->id_isar4 = 0x141; | |
2771db27 | 787 | cpu->reset_auxcr = 1; |
777dc784 PM |
788 | } |
789 | ||
790 | static void cortex_m3_initfn(Object *obj) | |
791 | { | |
792 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
793 | set_feature(&cpu->env, ARM_FEATURE_V7); |
794 | set_feature(&cpu->env, ARM_FEATURE_M); | |
b2d06f96 | 795 | cpu->midr = 0x410fc231; |
777dc784 PM |
796 | } |
797 | ||
e6f010cc AF |
798 | static void arm_v7m_class_init(ObjectClass *oc, void *data) |
799 | { | |
e6f010cc AF |
800 | CPUClass *cc = CPU_CLASS(oc); |
801 | ||
b5c633c5 | 802 | #ifndef CONFIG_USER_ONLY |
e6f010cc AF |
803 | cc->do_interrupt = arm_v7m_cpu_do_interrupt; |
804 | #endif | |
b5c633c5 PM |
805 | |
806 | cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; | |
e6f010cc AF |
807 | } |
808 | ||
34f90529 PM |
809 | static const ARMCPRegInfo cortexa8_cp_reginfo[] = { |
810 | { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, | |
811 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
812 | { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, | |
813 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
814 | REGINFO_SENTINEL | |
815 | }; | |
816 | ||
777dc784 PM |
817 | static void cortex_a8_initfn(Object *obj) |
818 | { | |
819 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
820 | |
821 | cpu->dtb_compatible = "arm,cortex-a8"; | |
581be094 PM |
822 | set_feature(&cpu->env, ARM_FEATURE_V7); |
823 | set_feature(&cpu->env, ARM_FEATURE_VFP3); | |
824 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
825 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
c4804214 | 826 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
c0ccb02d | 827 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
b2d06f96 | 828 | cpu->midr = 0x410fc080; |
325b3cef | 829 | cpu->reset_fpsid = 0x410330c0; |
bd35c355 PM |
830 | cpu->mvfr0 = 0x11110222; |
831 | cpu->mvfr1 = 0x00011100; | |
64e1671f | 832 | cpu->ctr = 0x82048004; |
0ca7e01c | 833 | cpu->reset_sctlr = 0x00c50078; |
2e4d7e3e PM |
834 | cpu->id_pfr0 = 0x1031; |
835 | cpu->id_pfr1 = 0x11; | |
836 | cpu->id_dfr0 = 0x400; | |
837 | cpu->id_afr0 = 0; | |
838 | cpu->id_mmfr0 = 0x31100003; | |
839 | cpu->id_mmfr1 = 0x20000000; | |
840 | cpu->id_mmfr2 = 0x01202000; | |
841 | cpu->id_mmfr3 = 0x11; | |
842 | cpu->id_isar0 = 0x00101111; | |
843 | cpu->id_isar1 = 0x12112111; | |
844 | cpu->id_isar2 = 0x21232031; | |
845 | cpu->id_isar3 = 0x11112131; | |
846 | cpu->id_isar4 = 0x00111142; | |
48eb3ae6 | 847 | cpu->dbgdidr = 0x15141000; |
85df3786 PM |
848 | cpu->clidr = (1 << 27) | (2 << 24) | 3; |
849 | cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ | |
850 | cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ | |
851 | cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ | |
2771db27 | 852 | cpu->reset_auxcr = 2; |
34f90529 | 853 | define_arm_cp_regs(cpu, cortexa8_cp_reginfo); |
777dc784 PM |
854 | } |
855 | ||
1047b9d7 PM |
856 | static const ARMCPRegInfo cortexa9_cp_reginfo[] = { |
857 | /* power_control should be set to maximum latency. Again, | |
858 | * default to 0 and set by private hook | |
859 | */ | |
860 | { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, | |
861 | .access = PL1_RW, .resetvalue = 0, | |
862 | .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, | |
863 | { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, | |
864 | .access = PL1_RW, .resetvalue = 0, | |
865 | .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, | |
866 | { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, | |
867 | .access = PL1_RW, .resetvalue = 0, | |
868 | .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, | |
869 | { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, | |
870 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
871 | /* TLB lockdown control */ | |
872 | { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, | |
873 | .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, | |
874 | { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, | |
875 | .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, | |
876 | { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, | |
877 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
878 | { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, | |
879 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
880 | { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, | |
881 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
882 | REGINFO_SENTINEL | |
883 | }; | |
884 | ||
777dc784 PM |
885 | static void cortex_a9_initfn(Object *obj) |
886 | { | |
887 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
888 | |
889 | cpu->dtb_compatible = "arm,cortex-a9"; | |
581be094 PM |
890 | set_feature(&cpu->env, ARM_FEATURE_V7); |
891 | set_feature(&cpu->env, ARM_FEATURE_VFP3); | |
892 | set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); | |
893 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
894 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
c0ccb02d | 895 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
581be094 PM |
896 | /* Note that A9 supports the MP extensions even for |
897 | * A9UP and single-core A9MP (which are both different | |
898 | * and valid configurations; we don't model A9UP). | |
899 | */ | |
900 | set_feature(&cpu->env, ARM_FEATURE_V7MP); | |
d8ba780b | 901 | set_feature(&cpu->env, ARM_FEATURE_CBAR); |
b2d06f96 | 902 | cpu->midr = 0x410fc090; |
325b3cef | 903 | cpu->reset_fpsid = 0x41033090; |
bd35c355 PM |
904 | cpu->mvfr0 = 0x11110222; |
905 | cpu->mvfr1 = 0x01111111; | |
64e1671f | 906 | cpu->ctr = 0x80038003; |
0ca7e01c | 907 | cpu->reset_sctlr = 0x00c50078; |
2e4d7e3e PM |
908 | cpu->id_pfr0 = 0x1031; |
909 | cpu->id_pfr1 = 0x11; | |
910 | cpu->id_dfr0 = 0x000; | |
911 | cpu->id_afr0 = 0; | |
912 | cpu->id_mmfr0 = 0x00100103; | |
913 | cpu->id_mmfr1 = 0x20000000; | |
914 | cpu->id_mmfr2 = 0x01230000; | |
915 | cpu->id_mmfr3 = 0x00002111; | |
916 | cpu->id_isar0 = 0x00101111; | |
917 | cpu->id_isar1 = 0x13112111; | |
918 | cpu->id_isar2 = 0x21232041; | |
919 | cpu->id_isar3 = 0x11112131; | |
920 | cpu->id_isar4 = 0x00111142; | |
48eb3ae6 | 921 | cpu->dbgdidr = 0x35141000; |
85df3786 | 922 | cpu->clidr = (1 << 27) | (1 << 24) | 3; |
f7838b52 PC |
923 | cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ |
924 | cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ | |
d8ba780b | 925 | define_arm_cp_regs(cpu, cortexa9_cp_reginfo); |
777dc784 PM |
926 | } |
927 | ||
34f90529 | 928 | #ifndef CONFIG_USER_ONLY |
c4241c7d | 929 | static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
34f90529 PM |
930 | { |
931 | /* Linux wants the number of processors from here. | |
932 | * Might as well set the interrupt-controller bit too. | |
933 | */ | |
c4241c7d | 934 | return ((smp_cpus - 1) << 24) | (1 << 23); |
34f90529 PM |
935 | } |
936 | #endif | |
937 | ||
938 | static const ARMCPRegInfo cortexa15_cp_reginfo[] = { | |
939 | #ifndef CONFIG_USER_ONLY | |
940 | { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, | |
941 | .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, | |
942 | .writefn = arm_cp_write_ignore, }, | |
943 | #endif | |
944 | { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, | |
945 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
946 | REGINFO_SENTINEL | |
947 | }; | |
948 | ||
777dc784 PM |
949 | static void cortex_a15_initfn(Object *obj) |
950 | { | |
951 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
952 | |
953 | cpu->dtb_compatible = "arm,cortex-a15"; | |
581be094 PM |
954 | set_feature(&cpu->env, ARM_FEATURE_V7); |
955 | set_feature(&cpu->env, ARM_FEATURE_VFP4); | |
581be094 PM |
956 | set_feature(&cpu->env, ARM_FEATURE_NEON); |
957 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
958 | set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); | |
581be094 | 959 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); |
c4804214 | 960 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
c29f9a0a | 961 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); |
de9b05b8 | 962 | set_feature(&cpu->env, ARM_FEATURE_LPAE); |
c0ccb02d | 963 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
3541addc | 964 | cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; |
b2d06f96 | 965 | cpu->midr = 0x412fc0f1; |
325b3cef | 966 | cpu->reset_fpsid = 0x410430f0; |
bd35c355 PM |
967 | cpu->mvfr0 = 0x10110222; |
968 | cpu->mvfr1 = 0x11111111; | |
64e1671f | 969 | cpu->ctr = 0x8444c004; |
0ca7e01c | 970 | cpu->reset_sctlr = 0x00c50078; |
2e4d7e3e PM |
971 | cpu->id_pfr0 = 0x00001131; |
972 | cpu->id_pfr1 = 0x00011011; | |
973 | cpu->id_dfr0 = 0x02010555; | |
974 | cpu->id_afr0 = 0x00000000; | |
975 | cpu->id_mmfr0 = 0x10201105; | |
976 | cpu->id_mmfr1 = 0x20000000; | |
977 | cpu->id_mmfr2 = 0x01240000; | |
978 | cpu->id_mmfr3 = 0x02102211; | |
979 | cpu->id_isar0 = 0x02101110; | |
980 | cpu->id_isar1 = 0x13112111; | |
981 | cpu->id_isar2 = 0x21232041; | |
982 | cpu->id_isar3 = 0x11112131; | |
983 | cpu->id_isar4 = 0x10011142; | |
48eb3ae6 | 984 | cpu->dbgdidr = 0x3515f021; |
85df3786 PM |
985 | cpu->clidr = 0x0a200023; |
986 | cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ | |
987 | cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ | |
988 | cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ | |
34f90529 | 989 | define_arm_cp_regs(cpu, cortexa15_cp_reginfo); |
777dc784 PM |
990 | } |
991 | ||
992 | static void ti925t_initfn(Object *obj) | |
993 | { | |
994 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
995 | set_feature(&cpu->env, ARM_FEATURE_V4T); |
996 | set_feature(&cpu->env, ARM_FEATURE_OMAPCP); | |
777dc784 | 997 | cpu->midr = ARM_CPUID_TI925T; |
64e1671f | 998 | cpu->ctr = 0x5109149; |
0ca7e01c | 999 | cpu->reset_sctlr = 0x00000070; |
777dc784 PM |
1000 | } |
1001 | ||
1002 | static void sa1100_initfn(Object *obj) | |
1003 | { | |
1004 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1005 | |
1006 | cpu->dtb_compatible = "intel,sa1100"; | |
581be094 | 1007 | set_feature(&cpu->env, ARM_FEATURE_STRONGARM); |
c4804214 | 1008 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 1009 | cpu->midr = 0x4401A11B; |
0ca7e01c | 1010 | cpu->reset_sctlr = 0x00000070; |
777dc784 PM |
1011 | } |
1012 | ||
1013 | static void sa1110_initfn(Object *obj) | |
1014 | { | |
1015 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 | 1016 | set_feature(&cpu->env, ARM_FEATURE_STRONGARM); |
c4804214 | 1017 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 1018 | cpu->midr = 0x6901B119; |
0ca7e01c | 1019 | cpu->reset_sctlr = 0x00000070; |
777dc784 PM |
1020 | } |
1021 | ||
1022 | static void pxa250_initfn(Object *obj) | |
1023 | { | |
1024 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1025 | |
1026 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1027 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1028 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 1029 | cpu->midr = 0x69052100; |
64e1671f | 1030 | cpu->ctr = 0xd172172; |
0ca7e01c | 1031 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1032 | } |
1033 | ||
1034 | static void pxa255_initfn(Object *obj) | |
1035 | { | |
1036 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1037 | |
1038 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1039 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1040 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 1041 | cpu->midr = 0x69052d00; |
64e1671f | 1042 | cpu->ctr = 0xd172172; |
0ca7e01c | 1043 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1044 | } |
1045 | ||
1046 | static void pxa260_initfn(Object *obj) | |
1047 | { | |
1048 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1049 | |
1050 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1051 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1052 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 1053 | cpu->midr = 0x69052903; |
64e1671f | 1054 | cpu->ctr = 0xd172172; |
0ca7e01c | 1055 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1056 | } |
1057 | ||
1058 | static void pxa261_initfn(Object *obj) | |
1059 | { | |
1060 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1061 | |
1062 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1063 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1064 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 1065 | cpu->midr = 0x69052d05; |
64e1671f | 1066 | cpu->ctr = 0xd172172; |
0ca7e01c | 1067 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1068 | } |
1069 | ||
1070 | static void pxa262_initfn(Object *obj) | |
1071 | { | |
1072 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1073 | |
1074 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1075 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1076 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 1077 | cpu->midr = 0x69052d06; |
64e1671f | 1078 | cpu->ctr = 0xd172172; |
0ca7e01c | 1079 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1080 | } |
1081 | ||
1082 | static void pxa270a0_initfn(Object *obj) | |
1083 | { | |
1084 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1085 | |
1086 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1087 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1088 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
1089 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 1090 | cpu->midr = 0x69054110; |
64e1671f | 1091 | cpu->ctr = 0xd172172; |
0ca7e01c | 1092 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1093 | } |
1094 | ||
1095 | static void pxa270a1_initfn(Object *obj) | |
1096 | { | |
1097 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1098 | |
1099 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1100 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1101 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
1102 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 1103 | cpu->midr = 0x69054111; |
64e1671f | 1104 | cpu->ctr = 0xd172172; |
0ca7e01c | 1105 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1106 | } |
1107 | ||
1108 | static void pxa270b0_initfn(Object *obj) | |
1109 | { | |
1110 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1111 | |
1112 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1113 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1114 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
1115 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 1116 | cpu->midr = 0x69054112; |
64e1671f | 1117 | cpu->ctr = 0xd172172; |
0ca7e01c | 1118 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1119 | } |
1120 | ||
1121 | static void pxa270b1_initfn(Object *obj) | |
1122 | { | |
1123 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1124 | |
1125 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1126 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1127 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
1128 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 1129 | cpu->midr = 0x69054113; |
64e1671f | 1130 | cpu->ctr = 0xd172172; |
0ca7e01c | 1131 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1132 | } |
1133 | ||
1134 | static void pxa270c0_initfn(Object *obj) | |
1135 | { | |
1136 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1137 | |
1138 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1139 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1140 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
1141 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 1142 | cpu->midr = 0x69054114; |
64e1671f | 1143 | cpu->ctr = 0xd172172; |
0ca7e01c | 1144 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1145 | } |
1146 | ||
1147 | static void pxa270c5_initfn(Object *obj) | |
1148 | { | |
1149 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1150 | |
1151 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1152 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1153 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
1154 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 1155 | cpu->midr = 0x69054117; |
64e1671f | 1156 | cpu->ctr = 0xd172172; |
0ca7e01c | 1157 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1158 | } |
1159 | ||
f5f6d38b | 1160 | #ifdef CONFIG_USER_ONLY |
777dc784 PM |
1161 | static void arm_any_initfn(Object *obj) |
1162 | { | |
1163 | ARMCPU *cpu = ARM_CPU(obj); | |
81e69fb0 | 1164 | set_feature(&cpu->env, ARM_FEATURE_V8); |
581be094 | 1165 | set_feature(&cpu->env, ARM_FEATURE_VFP4); |
581be094 PM |
1166 | set_feature(&cpu->env, ARM_FEATURE_NEON); |
1167 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
25f748e3 PM |
1168 | set_feature(&cpu->env, ARM_FEATURE_V8_AES); |
1169 | set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); | |
1170 | set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); | |
1171 | set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); | |
eb0ecd5a | 1172 | set_feature(&cpu->env, ARM_FEATURE_CRC); |
b2d06f96 | 1173 | cpu->midr = 0xffffffff; |
777dc784 | 1174 | } |
f5f6d38b | 1175 | #endif |
777dc784 | 1176 | |
15ee776b PM |
1177 | #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ |
1178 | ||
777dc784 PM |
1179 | typedef struct ARMCPUInfo { |
1180 | const char *name; | |
1181 | void (*initfn)(Object *obj); | |
e6f010cc | 1182 | void (*class_init)(ObjectClass *oc, void *data); |
777dc784 PM |
1183 | } ARMCPUInfo; |
1184 | ||
1185 | static const ARMCPUInfo arm_cpus[] = { | |
15ee776b | 1186 | #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) |
777dc784 PM |
1187 | { .name = "arm926", .initfn = arm926_initfn }, |
1188 | { .name = "arm946", .initfn = arm946_initfn }, | |
1189 | { .name = "arm1026", .initfn = arm1026_initfn }, | |
1190 | /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an | |
1191 | * older core than plain "arm1136". In particular this does not | |
1192 | * have the v6K features. | |
1193 | */ | |
1194 | { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, | |
1195 | { .name = "arm1136", .initfn = arm1136_initfn }, | |
1196 | { .name = "arm1176", .initfn = arm1176_initfn }, | |
1197 | { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, | |
e6f010cc AF |
1198 | { .name = "cortex-m3", .initfn = cortex_m3_initfn, |
1199 | .class_init = arm_v7m_class_init }, | |
777dc784 PM |
1200 | { .name = "cortex-a8", .initfn = cortex_a8_initfn }, |
1201 | { .name = "cortex-a9", .initfn = cortex_a9_initfn }, | |
1202 | { .name = "cortex-a15", .initfn = cortex_a15_initfn }, | |
1203 | { .name = "ti925t", .initfn = ti925t_initfn }, | |
1204 | { .name = "sa1100", .initfn = sa1100_initfn }, | |
1205 | { .name = "sa1110", .initfn = sa1110_initfn }, | |
1206 | { .name = "pxa250", .initfn = pxa250_initfn }, | |
1207 | { .name = "pxa255", .initfn = pxa255_initfn }, | |
1208 | { .name = "pxa260", .initfn = pxa260_initfn }, | |
1209 | { .name = "pxa261", .initfn = pxa261_initfn }, | |
1210 | { .name = "pxa262", .initfn = pxa262_initfn }, | |
1211 | /* "pxa270" is an alias for "pxa270-a0" */ | |
1212 | { .name = "pxa270", .initfn = pxa270a0_initfn }, | |
1213 | { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, | |
1214 | { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, | |
1215 | { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, | |
1216 | { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, | |
1217 | { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, | |
1218 | { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, | |
f5f6d38b | 1219 | #ifdef CONFIG_USER_ONLY |
777dc784 | 1220 | { .name = "any", .initfn = arm_any_initfn }, |
f5f6d38b | 1221 | #endif |
15ee776b | 1222 | #endif |
83e6813a | 1223 | { .name = NULL } |
777dc784 PM |
1224 | }; |
1225 | ||
5de16430 PM |
1226 | static Property arm_cpu_properties[] = { |
1227 | DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), | |
98128601 | 1228 | DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), |
51a9b04b | 1229 | DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), |
5de16430 PM |
1230 | DEFINE_PROP_END_OF_LIST() |
1231 | }; | |
1232 | ||
8c6084bf PM |
1233 | #ifdef CONFIG_USER_ONLY |
1234 | static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, | |
1235 | int mmu_idx) | |
1236 | { | |
1237 | ARMCPU *cpu = ARM_CPU(cs); | |
1238 | CPUARMState *env = &cpu->env; | |
1239 | ||
1240 | env->exception.vaddress = address; | |
1241 | if (rw == 2) { | |
1242 | cs->exception_index = EXCP_PREFETCH_ABORT; | |
1243 | } else { | |
1244 | cs->exception_index = EXCP_DATA_ABORT; | |
1245 | } | |
1246 | return 1; | |
1247 | } | |
1248 | #endif | |
1249 | ||
dec9c2d4 AF |
1250 | static void arm_cpu_class_init(ObjectClass *oc, void *data) |
1251 | { | |
1252 | ARMCPUClass *acc = ARM_CPU_CLASS(oc); | |
1253 | CPUClass *cc = CPU_CLASS(acc); | |
14969266 AF |
1254 | DeviceClass *dc = DEVICE_CLASS(oc); |
1255 | ||
1256 | acc->parent_realize = dc->realize; | |
1257 | dc->realize = arm_cpu_realizefn; | |
5de16430 | 1258 | dc->props = arm_cpu_properties; |
dec9c2d4 AF |
1259 | |
1260 | acc->parent_reset = cc->reset; | |
1261 | cc->reset = arm_cpu_reset; | |
5900d6b2 AF |
1262 | |
1263 | cc->class_by_name = arm_cpu_class_by_name; | |
8c2e1b00 | 1264 | cc->has_work = arm_cpu_has_work; |
e8925712 | 1265 | cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; |
878096ee | 1266 | cc->dump_state = arm_cpu_dump_state; |
f45748f1 | 1267 | cc->set_pc = arm_cpu_set_pc; |
5b50e790 AF |
1268 | cc->gdb_read_register = arm_cpu_gdb_read_register; |
1269 | cc->gdb_write_register = arm_cpu_gdb_write_register; | |
7510454e AF |
1270 | #ifdef CONFIG_USER_ONLY |
1271 | cc->handle_mmu_fault = arm_cpu_handle_mmu_fault; | |
1272 | #else | |
0adf7d3c | 1273 | cc->do_interrupt = arm_cpu_do_interrupt; |
00b941e5 AF |
1274 | cc->get_phys_page_debug = arm_cpu_get_phys_page_debug; |
1275 | cc->vmsd = &vmstate_arm_cpu; | |
84f2bed3 | 1276 | cc->virtio_is_big_endian = arm_cpu_is_big_endian; |
00b941e5 | 1277 | #endif |
a0e372f0 | 1278 | cc->gdb_num_core_regs = 26; |
5b24c641 | 1279 | cc->gdb_core_xml_file = "arm-core.xml"; |
2472b6c0 | 1280 | cc->gdb_stop_before_watchpoint = true; |
3ff6fc91 | 1281 | cc->debug_excp_handler = arm_debug_excp_handler; |
dec9c2d4 AF |
1282 | } |
1283 | ||
777dc784 PM |
1284 | static void cpu_register(const ARMCPUInfo *info) |
1285 | { | |
1286 | TypeInfo type_info = { | |
777dc784 PM |
1287 | .parent = TYPE_ARM_CPU, |
1288 | .instance_size = sizeof(ARMCPU), | |
1289 | .instance_init = info->initfn, | |
1290 | .class_size = sizeof(ARMCPUClass), | |
e6f010cc | 1291 | .class_init = info->class_init, |
777dc784 PM |
1292 | }; |
1293 | ||
51492fd1 | 1294 | type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); |
918fd083 | 1295 | type_register(&type_info); |
51492fd1 | 1296 | g_free((void *)type_info.name); |
777dc784 PM |
1297 | } |
1298 | ||
dec9c2d4 AF |
1299 | static const TypeInfo arm_cpu_type_info = { |
1300 | .name = TYPE_ARM_CPU, | |
1301 | .parent = TYPE_CPU, | |
1302 | .instance_size = sizeof(ARMCPU), | |
777dc784 | 1303 | .instance_init = arm_cpu_initfn, |
07a5b0d2 | 1304 | .instance_post_init = arm_cpu_post_init, |
4b6a83fb | 1305 | .instance_finalize = arm_cpu_finalizefn, |
777dc784 | 1306 | .abstract = true, |
dec9c2d4 AF |
1307 | .class_size = sizeof(ARMCPUClass), |
1308 | .class_init = arm_cpu_class_init, | |
1309 | }; | |
1310 | ||
1311 | static void arm_cpu_register_types(void) | |
1312 | { | |
83e6813a | 1313 | const ARMCPUInfo *info = arm_cpus; |
777dc784 | 1314 | |
dec9c2d4 | 1315 | type_register_static(&arm_cpu_type_info); |
83e6813a PM |
1316 | |
1317 | while (info->name) { | |
1318 | cpu_register(info); | |
1319 | info++; | |
777dc784 | 1320 | } |
dec9c2d4 AF |
1321 | } |
1322 | ||
1323 | type_init(arm_cpu_register_types) |