[mirror_qemu.git] / target-arm / cpu.c

/*
 * QEMU ARM CPU
 *
 * Copyright (c) 2012 SUSE LINUX Products GmbH
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, see
 * <http://www.gnu.org/licenses/gpl-2.0.html>
 */

#include "cpu-qom.h"
#include "qemu-common.h"

/* CPUClass::reset() */
static void arm_cpu_reset(CPUState *s)
{
    ARMCPU *cpu = ARM_CPU(s);
    ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);

    acc->parent_reset(s);

    /* TODO Inline the current contents of cpu_state_reset(),
            once cpu_reset_model_id() is eliminated. */
    cpu_state_reset(&cpu->env);
}

static inline void set_feature(CPUARMState *env, int feature)
{
    env->features |= 1u << feature;
}

static void arm_cpu_initfn(Object *obj)
{
    ARMCPU *cpu = ARM_CPU(obj);

    cpu_exec_init(&cpu->env);
}

void arm_cpu_realize(ARMCPU *cpu)
{
    /* This function is called by cpu_arm_init() because it
     * needs to do common actions based on feature bits, etc
     * that have been set by the subclass init functions.
     * When we have QOM realize support it should become
     * a true realize function instead.
     */
    CPUARMState *env = &cpu->env;
    /* Some features automatically imply others: */
    if (arm_feature(env, ARM_FEATURE_V7)) {
        set_feature(env, ARM_FEATURE_VAPA);
        set_feature(env, ARM_FEATURE_THUMB2);
        if (!arm_feature(env, ARM_FEATURE_M)) {
            set_feature(env, ARM_FEATURE_V6K);
        } else {
            set_feature(env, ARM_FEATURE_V6);
        }
    }
    if (arm_feature(env, ARM_FEATURE_V6K)) {
        set_feature(env, ARM_FEATURE_V6);
        set_feature(env, ARM_FEATURE_MVFR);
    }
    if (arm_feature(env, ARM_FEATURE_V6)) {
        set_feature(env, ARM_FEATURE_V5);
        if (!arm_feature(env, ARM_FEATURE_M)) {
            set_feature(env, ARM_FEATURE_AUXCR);
        }
    }
    if (arm_feature(env, ARM_FEATURE_V5)) {
        set_feature(env, ARM_FEATURE_V4T);
    }
    if (arm_feature(env, ARM_FEATURE_M)) {
        set_feature(env, ARM_FEATURE_THUMB_DIV);
    }
    if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
        set_feature(env, ARM_FEATURE_THUMB_DIV);
    }
    if (arm_feature(env, ARM_FEATURE_VFP4)) {
        set_feature(env, ARM_FEATURE_VFP3);
    }
    if (arm_feature(env, ARM_FEATURE_VFP3)) {
        set_feature(env, ARM_FEATURE_VFP);
    }
}

/* CPU models */

static void arm926_initfn(Object *obj)
{
    ARMCPU *cpu = ARM_CPU(obj);
    set_feature(&cpu->env, ARM_FEATURE_V5);
    set_feature(&cpu->env, ARM_FEATURE_VFP);
    cpu->midr = ARM_CPUID_ARM926;
}

static void arm946_initfn(Object *obj)
{
    ARMCPU *cpu = ARM_CPU(obj);
    set_feature(&cpu->env, ARM_FEATURE_V5);
    set_feature(&cpu->env, ARM_FEATURE_MPU);
    cpu->midr = ARM_CPUID_ARM946;
}

static void arm1026_initfn(Object *obj)
{
    ARMCPU *cpu = ARM_CPU(obj);
    set_feature(&cpu->env, ARM_FEATURE_V5);
    set_feature(&cpu->env, ARM_FEATURE_VFP);
    set_feature(&cpu->env, ARM_FEATURE_AUXCR);
    cpu->midr = ARM_CPUID_ARM1026;
}

static void arm1136_r2_initfn(Object *obj)
{
    ARMCPU *cpu = ARM_CPU(obj);
    set_feature(&cpu->env, ARM_FEATURE_V6);
    set_feature(&cpu->env, ARM_FEATURE_VFP);
    cpu->midr = ARM_CPUID_ARM1136_R2;
}

static void arm1136_initfn(Object *obj)
{
    ARMCPU *cpu = ARM_CPU(obj);
    set_feature(&cpu->env, ARM_FEATURE_V6K);
    set_feature(&cpu->env, ARM_FEATURE_V6);
    set_feature(&cpu->env, ARM_FEATURE_VFP);
    cpu->midr = ARM_CPUID_ARM1136;
}

static void arm1176_initfn(Object *obj)
{
    ARMCPU *cpu = ARM_CPU(obj);
    set_feature(&cpu->env, ARM_FEATURE_V6K);
    set_feature(&cpu->env, ARM_FEATURE_VFP);
    set_feature(&cpu->env, ARM_FEATURE_VAPA);
    cpu->midr = ARM_CPUID_ARM1176;
}

static void arm11mpcore_initfn(Object *obj)
{
    ARMCPU *cpu = ARM_CPU(obj);
    set_feature(&cpu->env, ARM_FEATURE_V6K);
    set_feature(&cpu->env, ARM_FEATURE_VFP);
    set_feature(&cpu->env, ARM_FEATURE_VAPA);
    cpu->midr = ARM_CPUID_ARM11MPCORE;
}

static void cortex_m3_initfn(Object *obj)
{
    ARMCPU *cpu = ARM_CPU(obj);
    set_feature(&cpu->env, ARM_FEATURE_V7);
    set_feature(&cpu->env, ARM_FEATURE_M);
    cpu->midr = ARM_CPUID_CORTEXM3;
}

static void cortex_a8_initfn(Object *obj)
{
    ARMCPU *cpu = ARM_CPU(obj);
    set_feature(&cpu->env, ARM_FEATURE_V7);
    set_feature(&cpu->env, ARM_FEATURE_VFP3);
    set_feature(&cpu->env, ARM_FEATURE_NEON);
    set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
    cpu->midr = ARM_CPUID_CORTEXA8;
}

static void cortex_a9_initfn(Object *obj)
{
    ARMCPU *cpu = ARM_CPU(obj);
    set_feature(&cpu->env, ARM_FEATURE_V7);
    set_feature(&cpu->env, ARM_FEATURE_VFP3);
    set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
    set_feature(&cpu->env, ARM_FEATURE_NEON);
    set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
    /* Note that A9 supports the MP extensions even for
     * A9UP and single-core A9MP (which are both different
     * and valid configurations; we don't model A9UP).
     */
    set_feature(&cpu->env, ARM_FEATURE_V7MP);
    cpu->midr = ARM_CPUID_CORTEXA9;
}

static void cortex_a15_initfn(Object *obj)
{
    ARMCPU *cpu = ARM_CPU(obj);
    set_feature(&cpu->env, ARM_FEATURE_V7);
    set_feature(&cpu->env, ARM_FEATURE_VFP4);
    set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
    set_feature(&cpu->env, ARM_FEATURE_NEON);
    set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
    set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
    set_feature(&cpu->env, ARM_FEATURE_V7MP);
    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
    cpu->midr = ARM_CPUID_CORTEXA15;
}

static void ti925t_initfn(Object *obj)
{
    ARMCPU *cpu = ARM_CPU(obj);
    set_feature(&cpu->env, ARM_FEATURE_V4T);
    set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
    cpu->midr = ARM_CPUID_TI925T;
}

static void sa1100_initfn(Object *obj)
{
    ARMCPU *cpu = ARM_CPU(obj);
    set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
    cpu->midr = ARM_CPUID_SA1100;
}

static void sa1110_initfn(Object *obj)
{
    ARMCPU *cpu = ARM_CPU(obj);
    set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
    cpu->midr = ARM_CPUID_SA1110;
}

static void pxa250_initfn(Object *obj)
{
    ARMCPU *cpu = ARM_CPU(obj);
    set_feature(&cpu->env, ARM_FEATURE_V5);
    set_feature(&cpu->env, ARM_FEATURE_XSCALE);
    cpu->midr = ARM_CPUID_PXA250;
}

static void pxa255_initfn(Object *obj)
{
    ARMCPU *cpu = ARM_CPU(obj);
    set_feature(&cpu->env, ARM_FEATURE_V5);
    set_feature(&cpu->env, ARM_FEATURE_XSCALE);
    cpu->midr = ARM_CPUID_PXA255;
}

static void pxa260_initfn(Object *obj)
{
    ARMCPU *cpu = ARM_CPU(obj);
    set_feature(&cpu->env, ARM_FEATURE_V5);
    set_feature(&cpu->env, ARM_FEATURE_XSCALE);
    cpu->midr = ARM_CPUID_PXA260;
}

static void pxa261_initfn(Object *obj)
{
    ARMCPU *cpu = ARM_CPU(obj);
    set_feature(&cpu->env, ARM_FEATURE_V5);
    set_feature(&cpu->env, ARM_FEATURE_XSCALE);
    cpu->midr = ARM_CPUID_PXA261;
}

static void pxa262_initfn(Object *obj)
{
    ARMCPU *cpu = ARM_CPU(obj);
    set_feature(&cpu->env, ARM_FEATURE_V5);
    set_feature(&cpu->env, ARM_FEATURE_XSCALE);
    cpu->midr = ARM_CPUID_PXA262;
}

static void pxa270a0_initfn(Object *obj)
{
    ARMCPU *cpu = ARM_CPU(obj);
    set_feature(&cpu->env, ARM_FEATURE_V5);
    set_feature(&cpu->env, ARM_FEATURE_XSCALE);
    set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
    cpu->midr = ARM_CPUID_PXA270_A0;
}

static void pxa270a1_initfn(Object *obj)
{
    ARMCPU *cpu = ARM_CPU(obj);
    set_feature(&cpu->env, ARM_FEATURE_V5);
    set_feature(&cpu->env, ARM_FEATURE_XSCALE);
    set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
    cpu->midr = ARM_CPUID_PXA270_A1;
}

static void pxa270b0_initfn(Object *obj)
{
    ARMCPU *cpu = ARM_CPU(obj);
    set_feature(&cpu->env, ARM_FEATURE_V5);
    set_feature(&cpu->env, ARM_FEATURE_XSCALE);
    set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
    cpu->midr = ARM_CPUID_PXA270_B0;
}

static void pxa270b1_initfn(Object *obj)
{
    ARMCPU *cpu = ARM_CPU(obj);
    set_feature(&cpu->env, ARM_FEATURE_V5);
    set_feature(&cpu->env, ARM_FEATURE_XSCALE);
    set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
    cpu->midr = ARM_CPUID_PXA270_B1;
}

static void pxa270c0_initfn(Object *obj)
{
    ARMCPU *cpu = ARM_CPU(obj);
    set_feature(&cpu->env, ARM_FEATURE_V5);
    set_feature(&cpu->env, ARM_FEATURE_XSCALE);
    set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
    cpu->midr = ARM_CPUID_PXA270_C0;
}

static void pxa270c5_initfn(Object *obj)
{
    ARMCPU *cpu = ARM_CPU(obj);
    set_feature(&cpu->env, ARM_FEATURE_V5);
    set_feature(&cpu->env, ARM_FEATURE_XSCALE);
    set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
    cpu->midr = ARM_CPUID_PXA270_C5;
}

static void arm_any_initfn(Object *obj)
{
    ARMCPU *cpu = ARM_CPU(obj);
    set_feature(&cpu->env, ARM_FEATURE_V7);
    set_feature(&cpu->env, ARM_FEATURE_VFP4);
    set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
    set_feature(&cpu->env, ARM_FEATURE_NEON);
    set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
    set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
    set_feature(&cpu->env, ARM_FEATURE_V7MP);
    cpu->midr = ARM_CPUID_ANY;
}

typedef struct ARMCPUInfo {
    const char *name;
    void (*initfn)(Object *obj);
} ARMCPUInfo;

static const ARMCPUInfo arm_cpus[] = {
    { .name = "arm926",      .initfn = arm926_initfn },
    { .name = "arm946",      .initfn = arm946_initfn },
    { .name = "arm1026",     .initfn = arm1026_initfn },
    /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
     * older core than plain "arm1136". In particular this does not
     * have the v6K features.
     */
    { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
    { .name = "arm1136",     .initfn = arm1136_initfn },
    { .name = "arm1176",     .initfn = arm1176_initfn },
    { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
    { .name = "cortex-m3",   .initfn = cortex_m3_initfn },
    { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
    { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
    { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
    { .name = "ti925t",      .initfn = ti925t_initfn },
    { .name = "sa1100",      .initfn = sa1100_initfn },
    { .name = "sa1110",      .initfn = sa1110_initfn },
    { .name = "pxa250",      .initfn = pxa250_initfn },
    { .name = "pxa255",      .initfn = pxa255_initfn },
    { .name = "pxa260",      .initfn = pxa260_initfn },
    { .name = "pxa261",      .initfn = pxa261_initfn },
    { .name = "pxa262",      .initfn = pxa262_initfn },
    /* "pxa270" is an alias for "pxa270-a0" */
    { .name = "pxa270",      .initfn = pxa270a0_initfn },
    { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
    { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
    { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
    { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
    { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
    { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
    { .name = "any",         .initfn = arm_any_initfn },
};

static void arm_cpu_class_init(ObjectClass *oc, void *data)
{
    ARMCPUClass *acc = ARM_CPU_CLASS(oc);
    CPUClass *cc = CPU_CLASS(acc);

    acc->parent_reset = cc->reset;
    cc->reset = arm_cpu_reset;
}

static void cpu_register(const ARMCPUInfo *info)
{
    TypeInfo type_info = {
        .name = info->name,
        .parent = TYPE_ARM_CPU,
        .instance_size = sizeof(ARMCPU),
        .instance_init = info->initfn,
        .class_size = sizeof(ARMCPUClass),
    };

    type_register_static(&type_info);
}

static const TypeInfo arm_cpu_type_info = {
    .name = TYPE_ARM_CPU,
    .parent = TYPE_CPU,
    .instance_size = sizeof(ARMCPU),
    .instance_init = arm_cpu_initfn,
    .abstract = true,
    .class_size = sizeof(ARMCPUClass),
    .class_init = arm_cpu_class_init,
};

static void arm_cpu_register_types(void)
{
    int i;

    type_register_static(&arm_cpu_type_info);
    for (i = 0; i < ARRAY_SIZE(arm_cpus); i++) {
        cpu_register(&arm_cpus[i]);
    }
}

type_init(arm_cpu_register_types)
Commit	Line	Data
dec9c2d4 AF	1	/*
	2	* QEMU ARM CPU
	3	*
	4	* Copyright (c) 2012 SUSE LINUX Products GmbH
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version 2
	9	* of the License, or (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, see
	18	* <http://www.gnu.org/licenses/gpl-2.0.html>
	19	*/
	20
	21	#include "cpu-qom.h"
	22	#include "qemu-common.h"
	23
	24	/* CPUClass::reset() */
	25	static void arm_cpu_reset(CPUState *s)
	26	{
	27	ARMCPU *cpu = ARM_CPU(s);
	28	ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
	29
	30	acc->parent_reset(s);
	31
	32	/* TODO Inline the current contents of cpu_state_reset(),
	33	once cpu_reset_model_id() is eliminated. */
	34	cpu_state_reset(&cpu->env);
	35	}
	36
581be094 PM	37	static inline void set_feature(CPUARMState *env, int feature)
	38	{
	39	env->features \|= 1u << feature;
	40	}
	41
777dc784 PM	42	static void arm_cpu_initfn(Object *obj)
	43	{
	44	ARMCPU *cpu = ARM_CPU(obj);
	45
	46	cpu_exec_init(&cpu->env);
	47	}
	48
581be094 PM	49	void arm_cpu_realize(ARMCPU *cpu)
	50	{
	51	/* This function is called by cpu_arm_init() because it
	52	* needs to do common actions based on feature bits, etc
	53	* that have been set by the subclass init functions.
	54	* When we have QOM realize support it should become
	55	* a true realize function instead.
	56	*/
	57	CPUARMState *env = &cpu->env;
	58	/* Some features automatically imply others: */
	59	if (arm_feature(env, ARM_FEATURE_V7)) {
	60	set_feature(env, ARM_FEATURE_VAPA);
	61	set_feature(env, ARM_FEATURE_THUMB2);
	62	if (!arm_feature(env, ARM_FEATURE_M)) {
	63	set_feature(env, ARM_FEATURE_V6K);
	64	} else {
	65	set_feature(env, ARM_FEATURE_V6);
	66	}
	67	}
	68	if (arm_feature(env, ARM_FEATURE_V6K)) {
	69	set_feature(env, ARM_FEATURE_V6);
	70	set_feature(env, ARM_FEATURE_MVFR);
	71	}
	72	if (arm_feature(env, ARM_FEATURE_V6)) {
	73	set_feature(env, ARM_FEATURE_V5);
	74	if (!arm_feature(env, ARM_FEATURE_M)) {
	75	set_feature(env, ARM_FEATURE_AUXCR);
	76	}
	77	}
	78	if (arm_feature(env, ARM_FEATURE_V5)) {
	79	set_feature(env, ARM_FEATURE_V4T);
	80	}
	81	if (arm_feature(env, ARM_FEATURE_M)) {
	82	set_feature(env, ARM_FEATURE_THUMB_DIV);
	83	}
	84	if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
	85	set_feature(env, ARM_FEATURE_THUMB_DIV);
	86	}
	87	if (arm_feature(env, ARM_FEATURE_VFP4)) {
	88	set_feature(env, ARM_FEATURE_VFP3);
	89	}
	90	if (arm_feature(env, ARM_FEATURE_VFP3)) {
	91	set_feature(env, ARM_FEATURE_VFP);
	92	}
	93	}
	94
777dc784 PM	95	/* CPU models */
	96
	97	static void arm926_initfn(Object *obj)
	98	{
	99	ARMCPU *cpu = ARM_CPU(obj);
581be094 PM	100	set_feature(&cpu->env, ARM_FEATURE_V5);
581be094 PM	101	set_feature(&cpu->env, ARM_FEATURE_VFP);
777dc784 PM	102	cpu->midr = ARM_CPUID_ARM926;
	103	}
	104
	105	static void arm946_initfn(Object *obj)
	106	{
	107	ARMCPU *cpu = ARM_CPU(obj);
581be094 PM	108	set_feature(&cpu->env, ARM_FEATURE_V5);
581be094 PM	109	set_feature(&cpu->env, ARM_FEATURE_MPU);
777dc784 PM	110	cpu->midr = ARM_CPUID_ARM946;
	111	}
	112
	113	static void arm1026_initfn(Object *obj)
	114	{
	115	ARMCPU *cpu = ARM_CPU(obj);
581be094 PM	116	set_feature(&cpu->env, ARM_FEATURE_V5);
	117	set_feature(&cpu->env, ARM_FEATURE_VFP);
	118	set_feature(&cpu->env, ARM_FEATURE_AUXCR);
777dc784 PM	119	cpu->midr = ARM_CPUID_ARM1026;
	120	}
	121
	122	static void arm1136_r2_initfn(Object *obj)
	123	{
	124	ARMCPU *cpu = ARM_CPU(obj);
581be094 PM	125	set_feature(&cpu->env, ARM_FEATURE_V6);
581be094 PM	126	set_feature(&cpu->env, ARM_FEATURE_VFP);
777dc784 PM	127	cpu->midr = ARM_CPUID_ARM1136_R2;
	128	}
	129
	130	static void arm1136_initfn(Object *obj)
	131	{
	132	ARMCPU *cpu = ARM_CPU(obj);
581be094 PM	133	set_feature(&cpu->env, ARM_FEATURE_V6K);
	134	set_feature(&cpu->env, ARM_FEATURE_V6);
	135	set_feature(&cpu->env, ARM_FEATURE_VFP);
777dc784 PM	136	cpu->midr = ARM_CPUID_ARM1136;
	137	}
	138
	139	static void arm1176_initfn(Object *obj)
	140	{
	141	ARMCPU *cpu = ARM_CPU(obj);
581be094 PM	142	set_feature(&cpu->env, ARM_FEATURE_V6K);
	143	set_feature(&cpu->env, ARM_FEATURE_VFP);
	144	set_feature(&cpu->env, ARM_FEATURE_VAPA);
777dc784 PM	145	cpu->midr = ARM_CPUID_ARM1176;
	146	}
	147
	148	static void arm11mpcore_initfn(Object *obj)
	149	{
	150	ARMCPU *cpu = ARM_CPU(obj);
581be094 PM	151	set_feature(&cpu->env, ARM_FEATURE_V6K);
	152	set_feature(&cpu->env, ARM_FEATURE_VFP);
	153	set_feature(&cpu->env, ARM_FEATURE_VAPA);
777dc784 PM	154	cpu->midr = ARM_CPUID_ARM11MPCORE;
	155	}
	156
	157	static void cortex_m3_initfn(Object *obj)
	158	{
	159	ARMCPU *cpu = ARM_CPU(obj);
581be094 PM	160	set_feature(&cpu->env, ARM_FEATURE_V7);
581be094 PM	161	set_feature(&cpu->env, ARM_FEATURE_M);
777dc784 PM	162	cpu->midr = ARM_CPUID_CORTEXM3;
	163	}
	164
	165	static void cortex_a8_initfn(Object *obj)
	166	{
	167	ARMCPU *cpu = ARM_CPU(obj);
581be094 PM	168	set_feature(&cpu->env, ARM_FEATURE_V7);
	169	set_feature(&cpu->env, ARM_FEATURE_VFP3);
	170	set_feature(&cpu->env, ARM_FEATURE_NEON);
	171	set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
777dc784 PM	172	cpu->midr = ARM_CPUID_CORTEXA8;
	173	}
	174
	175	static void cortex_a9_initfn(Object *obj)
	176	{
	177	ARMCPU *cpu = ARM_CPU(obj);
581be094 PM	178	set_feature(&cpu->env, ARM_FEATURE_V7);
	179	set_feature(&cpu->env, ARM_FEATURE_VFP3);
	180	set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
	181	set_feature(&cpu->env, ARM_FEATURE_NEON);
	182	set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
	183	/* Note that A9 supports the MP extensions even for
	184	* A9UP and single-core A9MP (which are both different
	185	* and valid configurations; we don't model A9UP).
	186	*/
	187	set_feature(&cpu->env, ARM_FEATURE_V7MP);
777dc784 PM	188	cpu->midr = ARM_CPUID_CORTEXA9;
	189	}
	190
	191	static void cortex_a15_initfn(Object *obj)
	192	{
	193	ARMCPU *cpu = ARM_CPU(obj);
581be094 PM	194	set_feature(&cpu->env, ARM_FEATURE_V7);
	195	set_feature(&cpu->env, ARM_FEATURE_VFP4);
	196	set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
	197	set_feature(&cpu->env, ARM_FEATURE_NEON);
	198	set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
	199	set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
	200	set_feature(&cpu->env, ARM_FEATURE_V7MP);
	201	set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
777dc784 PM	202	cpu->midr = ARM_CPUID_CORTEXA15;
	203	}
	204
	205	static void ti925t_initfn(Object *obj)
	206	{
	207	ARMCPU *cpu = ARM_CPU(obj);
581be094 PM	208	set_feature(&cpu->env, ARM_FEATURE_V4T);
581be094 PM	209	set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
777dc784 PM	210	cpu->midr = ARM_CPUID_TI925T;
	211	}
	212
	213	static void sa1100_initfn(Object *obj)
	214	{
	215	ARMCPU *cpu = ARM_CPU(obj);
581be094	216	set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
777dc784 PM	217	cpu->midr = ARM_CPUID_SA1100;
	218	}
	219
	220	static void sa1110_initfn(Object *obj)
	221	{
	222	ARMCPU *cpu = ARM_CPU(obj);
581be094	223	set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
777dc784 PM	224	cpu->midr = ARM_CPUID_SA1110;
	225	}
	226
	227	static void pxa250_initfn(Object *obj)
	228	{
	229	ARMCPU *cpu = ARM_CPU(obj);
581be094 PM	230	set_feature(&cpu->env, ARM_FEATURE_V5);
581be094 PM	231	set_feature(&cpu->env, ARM_FEATURE_XSCALE);
777dc784 PM	232	cpu->midr = ARM_CPUID_PXA250;
	233	}
	234
	235	static void pxa255_initfn(Object *obj)
	236	{
	237	ARMCPU *cpu = ARM_CPU(obj);
581be094 PM	238	set_feature(&cpu->env, ARM_FEATURE_V5);
581be094 PM	239	set_feature(&cpu->env, ARM_FEATURE_XSCALE);
777dc784 PM	240	cpu->midr = ARM_CPUID_PXA255;
	241	}
	242
	243	static void pxa260_initfn(Object *obj)
	244	{
	245	ARMCPU *cpu = ARM_CPU(obj);
581be094 PM	246	set_feature(&cpu->env, ARM_FEATURE_V5);
581be094 PM	247	set_feature(&cpu->env, ARM_FEATURE_XSCALE);
777dc784 PM	248	cpu->midr = ARM_CPUID_PXA260;
	249	}
	250
	251	static void pxa261_initfn(Object *obj)
	252	{
	253	ARMCPU *cpu = ARM_CPU(obj);
581be094 PM	254	set_feature(&cpu->env, ARM_FEATURE_V5);
581be094 PM	255	set_feature(&cpu->env, ARM_FEATURE_XSCALE);
777dc784 PM	256	cpu->midr = ARM_CPUID_PXA261;
	257	}
	258
	259	static void pxa262_initfn(Object *obj)
	260	{
	261	ARMCPU *cpu = ARM_CPU(obj);
581be094 PM	262	set_feature(&cpu->env, ARM_FEATURE_V5);
581be094 PM	263	set_feature(&cpu->env, ARM_FEATURE_XSCALE);
777dc784 PM	264	cpu->midr = ARM_CPUID_PXA262;
	265	}
	266
	267	static void pxa270a0_initfn(Object *obj)
	268	{
	269	ARMCPU *cpu = ARM_CPU(obj);
581be094 PM	270	set_feature(&cpu->env, ARM_FEATURE_V5);
	271	set_feature(&cpu->env, ARM_FEATURE_XSCALE);
	272	set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
777dc784 PM	273	cpu->midr = ARM_CPUID_PXA270_A0;
	274	}
	275
	276	static void pxa270a1_initfn(Object *obj)
	277	{
	278	ARMCPU *cpu = ARM_CPU(obj);
581be094 PM	279	set_feature(&cpu->env, ARM_FEATURE_V5);
	280	set_feature(&cpu->env, ARM_FEATURE_XSCALE);
	281	set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
777dc784 PM	282	cpu->midr = ARM_CPUID_PXA270_A1;
	283	}
	284
	285	static void pxa270b0_initfn(Object *obj)
	286	{
	287	ARMCPU *cpu = ARM_CPU(obj);
581be094 PM	288	set_feature(&cpu->env, ARM_FEATURE_V5);
	289	set_feature(&cpu->env, ARM_FEATURE_XSCALE);
	290	set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
777dc784 PM	291	cpu->midr = ARM_CPUID_PXA270_B0;
	292	}
	293
	294	static void pxa270b1_initfn(Object *obj)
	295	{
	296	ARMCPU *cpu = ARM_CPU(obj);
581be094 PM	297	set_feature(&cpu->env, ARM_FEATURE_V5);
	298	set_feature(&cpu->env, ARM_FEATURE_XSCALE);
	299	set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
777dc784 PM	300	cpu->midr = ARM_CPUID_PXA270_B1;
	301	}
	302
	303	static void pxa270c0_initfn(Object *obj)
	304	{
	305	ARMCPU *cpu = ARM_CPU(obj);
581be094 PM	306	set_feature(&cpu->env, ARM_FEATURE_V5);
	307	set_feature(&cpu->env, ARM_FEATURE_XSCALE);
	308	set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
777dc784 PM	309	cpu->midr = ARM_CPUID_PXA270_C0;
	310	}
	311
	312	static void pxa270c5_initfn(Object *obj)
	313	{
	314	ARMCPU *cpu = ARM_CPU(obj);
581be094 PM	315	set_feature(&cpu->env, ARM_FEATURE_V5);
	316	set_feature(&cpu->env, ARM_FEATURE_XSCALE);
	317	set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
777dc784 PM	318	cpu->midr = ARM_CPUID_PXA270_C5;
	319	}
	320
	321	static void arm_any_initfn(Object *obj)
	322	{
	323	ARMCPU *cpu = ARM_CPU(obj);
581be094 PM	324	set_feature(&cpu->env, ARM_FEATURE_V7);
	325	set_feature(&cpu->env, ARM_FEATURE_VFP4);
	326	set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
	327	set_feature(&cpu->env, ARM_FEATURE_NEON);
	328	set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
	329	set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
	330	set_feature(&cpu->env, ARM_FEATURE_V7MP);
777dc784 PM	331	cpu->midr = ARM_CPUID_ANY;
	332	}
	333
	334	typedef struct ARMCPUInfo {
	335	const char *name;
	336	void (initfn)(Object obj);
	337	} ARMCPUInfo;
	338
	339	static const ARMCPUInfo arm_cpus[] = {
	340	{ .name = "arm926", .initfn = arm926_initfn },
	341	{ .name = "arm946", .initfn = arm946_initfn },
	342	{ .name = "arm1026", .initfn = arm1026_initfn },
	343	/* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
	344	* older core than plain "arm1136". In particular this does not
	345	* have the v6K features.
	346	*/
	347	{ .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
	348	{ .name = "arm1136", .initfn = arm1136_initfn },
	349	{ .name = "arm1176", .initfn = arm1176_initfn },
	350	{ .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
	351	{ .name = "cortex-m3", .initfn = cortex_m3_initfn },
	352	{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
	353	{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
	354	{ .name = "cortex-a15", .initfn = cortex_a15_initfn },
	355	{ .name = "ti925t", .initfn = ti925t_initfn },
	356	{ .name = "sa1100", .initfn = sa1100_initfn },
	357	{ .name = "sa1110", .initfn = sa1110_initfn },
	358	{ .name = "pxa250", .initfn = pxa250_initfn },
	359	{ .name = "pxa255", .initfn = pxa255_initfn },
	360	{ .name = "pxa260", .initfn = pxa260_initfn },
	361	{ .name = "pxa261", .initfn = pxa261_initfn },
	362	{ .name = "pxa262", .initfn = pxa262_initfn },
	363	/* "pxa270" is an alias for "pxa270-a0" */
	364	{ .name = "pxa270", .initfn = pxa270a0_initfn },
	365	{ .name = "pxa270-a0", .initfn = pxa270a0_initfn },
	366	{ .name = "pxa270-a1", .initfn = pxa270a1_initfn },
	367	{ .name = "pxa270-b0", .initfn = pxa270b0_initfn },
	368	{ .name = "pxa270-b1", .initfn = pxa270b1_initfn },
	369	{ .name = "pxa270-c0", .initfn = pxa270c0_initfn },
	370	{ .name = "pxa270-c5", .initfn = pxa270c5_initfn },
	371	{ .name = "any", .initfn = arm_any_initfn },
	372	};
	373
dec9c2d4 AF	374	static void arm_cpu_class_init(ObjectClass oc, void data)
	375	{
	376	ARMCPUClass *acc = ARM_CPU_CLASS(oc);
	377	CPUClass *cc = CPU_CLASS(acc);
	378
	379	acc->parent_reset = cc->reset;
	380	cc->reset = arm_cpu_reset;
	381	}
	382
777dc784 PM	383	static void cpu_register(const ARMCPUInfo *info)
	384	{
	385	TypeInfo type_info = {
	386	.name = info->name,
	387	.parent = TYPE_ARM_CPU,
	388	.instance_size = sizeof(ARMCPU),
	389	.instance_init = info->initfn,
	390	.class_size = sizeof(ARMCPUClass),
	391	};
	392
	393	type_register_static(&type_info);
	394	}
	395
dec9c2d4 AF	396	static const TypeInfo arm_cpu_type_info = {
	397	.name = TYPE_ARM_CPU,
	398	.parent = TYPE_CPU,
	399	.instance_size = sizeof(ARMCPU),
777dc784 PM	400	.instance_init = arm_cpu_initfn,
777dc784 PM	401	.abstract = true,
dec9c2d4 AF	402	.class_size = sizeof(ARMCPUClass),
	403	.class_init = arm_cpu_class_init,
	404	};
	405
	406	static void arm_cpu_register_types(void)
	407	{
777dc784 PM	408	int i;
777dc784 PM	409
dec9c2d4	410	type_register_static(&arm_cpu_type_info);
777dc784 PM	411	for (i = 0; i < ARRAY_SIZE(arm_cpus); i++) {
	412	cpu_register(&arm_cpus[i]);
	413	}
dec9c2d4 AF	414	}
	415
	416	type_init(arm_cpu_register_types)