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dec9c2d4 AF |
1 | /* |
2 | * QEMU ARM CPU | |
3 | * | |
4 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | */ | |
20 | ||
778c3a06 | 21 | #include "cpu.h" |
dec9c2d4 | 22 | #include "qemu-common.h" |
5de16430 | 23 | #include "hw/qdev-properties.h" |
07a5b0d2 | 24 | #include "qapi/qmp/qerror.h" |
3c30dd5a PM |
25 | #if !defined(CONFIG_USER_ONLY) |
26 | #include "hw/loader.h" | |
27 | #endif | |
7c1840b6 | 28 | #include "hw/arm/arm.h" |
9c17d615 | 29 | #include "sysemu/sysemu.h" |
7c1840b6 | 30 | #include "sysemu/kvm.h" |
dec9c2d4 | 31 | |
f45748f1 AF |
32 | static void arm_cpu_set_pc(CPUState *cs, vaddr value) |
33 | { | |
34 | ARMCPU *cpu = ARM_CPU(cs); | |
35 | ||
36 | cpu->env.regs[15] = value; | |
37 | } | |
38 | ||
4b6a83fb PM |
39 | static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) |
40 | { | |
41 | /* Reset a single ARMCPRegInfo register */ | |
42 | ARMCPRegInfo *ri = value; | |
43 | ARMCPU *cpu = opaque; | |
44 | ||
45 | if (ri->type & ARM_CP_SPECIAL) { | |
46 | return; | |
47 | } | |
48 | ||
49 | if (ri->resetfn) { | |
50 | ri->resetfn(&cpu->env, ri); | |
51 | return; | |
52 | } | |
53 | ||
54 | /* A zero offset is never possible as it would be regs[0] | |
55 | * so we use it to indicate that reset is being handled elsewhere. | |
56 | * This is basically only used for fields in non-core coprocessors | |
57 | * (like the pxa2xx ones). | |
58 | */ | |
59 | if (!ri->fieldoffset) { | |
60 | return; | |
61 | } | |
62 | ||
63 | if (ri->type & ARM_CP_64BIT) { | |
64 | CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; | |
65 | } else { | |
66 | CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; | |
67 | } | |
68 | } | |
69 | ||
dec9c2d4 AF |
70 | /* CPUClass::reset() */ |
71 | static void arm_cpu_reset(CPUState *s) | |
72 | { | |
73 | ARMCPU *cpu = ARM_CPU(s); | |
74 | ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); | |
3c30dd5a | 75 | CPUARMState *env = &cpu->env; |
3c30dd5a | 76 | |
dec9c2d4 AF |
77 | acc->parent_reset(s); |
78 | ||
3c30dd5a | 79 | memset(env, 0, offsetof(CPUARMState, breakpoints)); |
4b6a83fb | 80 | g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); |
3c30dd5a PM |
81 | env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; |
82 | env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; | |
83 | env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; | |
3c30dd5a PM |
84 | |
85 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { | |
86 | env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; | |
87 | } | |
88 | ||
3926cc84 AG |
89 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { |
90 | /* 64 bit CPUs always start in 64 bit mode */ | |
91 | env->aarch64 = 1; | |
92 | } | |
93 | ||
3c30dd5a PM |
94 | #if defined(CONFIG_USER_ONLY) |
95 | env->uncached_cpsr = ARM_CPU_MODE_USR; | |
96 | /* For user mode we must enable access to coprocessors */ | |
97 | env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; | |
98 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { | |
99 | env->cp15.c15_cpar = 3; | |
100 | } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
101 | env->cp15.c15_cpar = 1; | |
102 | } | |
103 | #else | |
104 | /* SVC mode with interrupts disabled. */ | |
105 | env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I; | |
106 | /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is | |
107 | clear at reset. Initial SP and PC are loaded from ROM. */ | |
108 | if (IS_M(env)) { | |
109 | uint32_t pc; | |
110 | uint8_t *rom; | |
111 | env->uncached_cpsr &= ~CPSR_I; | |
112 | rom = rom_ptr(0); | |
113 | if (rom) { | |
114 | /* We should really use ldl_phys here, in case the guest | |
115 | modified flash and reset itself. However images | |
116 | loaded via -kernel have not been copied yet, so load the | |
117 | values directly from there. */ | |
f62cafd4 | 118 | env->regs[13] = ldl_p(rom) & 0xFFFFFFFC; |
3c30dd5a PM |
119 | pc = ldl_p(rom + 4); |
120 | env->thumb = pc & 1; | |
121 | env->regs[15] = pc & ~1; | |
122 | } | |
123 | } | |
387f9806 AP |
124 | |
125 | if (env->cp15.c1_sys & (1 << 13)) { | |
126 | env->regs[15] = 0xFFFF0000; | |
127 | } | |
128 | ||
3c30dd5a | 129 | env->vfp.xregs[ARM_VFP_FPEXC] = 0; |
3c30dd5a PM |
130 | #endif |
131 | set_flush_to_zero(1, &env->vfp.standard_fp_status); | |
132 | set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); | |
133 | set_default_nan_mode(1, &env->vfp.standard_fp_status); | |
134 | set_float_detect_tininess(float_tininess_before_rounding, | |
135 | &env->vfp.fp_status); | |
136 | set_float_detect_tininess(float_tininess_before_rounding, | |
137 | &env->vfp.standard_fp_status); | |
138 | tlb_flush(env, 1); | |
139 | /* Reset is a state change for some CPUARMState fields which we | |
140 | * bake assumptions about into translated code, so we need to | |
141 | * tb_flush(). | |
142 | */ | |
143 | tb_flush(env); | |
dec9c2d4 AF |
144 | } |
145 | ||
7c1840b6 PM |
146 | #ifndef CONFIG_USER_ONLY |
147 | static void arm_cpu_set_irq(void *opaque, int irq, int level) | |
148 | { | |
149 | ARMCPU *cpu = opaque; | |
150 | CPUState *cs = CPU(cpu); | |
151 | ||
152 | switch (irq) { | |
153 | case ARM_CPU_IRQ: | |
154 | if (level) { | |
155 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); | |
156 | } else { | |
157 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); | |
158 | } | |
159 | break; | |
160 | case ARM_CPU_FIQ: | |
161 | if (level) { | |
162 | cpu_interrupt(cs, CPU_INTERRUPT_FIQ); | |
163 | } else { | |
164 | cpu_reset_interrupt(cs, CPU_INTERRUPT_FIQ); | |
165 | } | |
166 | break; | |
167 | default: | |
168 | hw_error("arm_cpu_set_irq: Bad interrupt line %d\n", irq); | |
169 | } | |
170 | } | |
171 | ||
172 | static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) | |
173 | { | |
174 | #ifdef CONFIG_KVM | |
175 | ARMCPU *cpu = opaque; | |
176 | CPUState *cs = CPU(cpu); | |
177 | int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT; | |
178 | ||
179 | switch (irq) { | |
180 | case ARM_CPU_IRQ: | |
181 | kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; | |
182 | break; | |
183 | case ARM_CPU_FIQ: | |
184 | kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; | |
185 | break; | |
186 | default: | |
187 | hw_error("arm_cpu_kvm_set_irq: Bad interrupt line %d\n", irq); | |
188 | } | |
189 | kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; | |
190 | kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); | |
191 | #endif | |
192 | } | |
193 | #endif | |
194 | ||
581be094 PM |
195 | static inline void set_feature(CPUARMState *env, int feature) |
196 | { | |
918f5dca | 197 | env->features |= 1ULL << feature; |
581be094 PM |
198 | } |
199 | ||
777dc784 PM |
200 | static void arm_cpu_initfn(Object *obj) |
201 | { | |
c05efcb1 | 202 | CPUState *cs = CPU(obj); |
777dc784 | 203 | ARMCPU *cpu = ARM_CPU(obj); |
79614b78 | 204 | static bool inited; |
777dc784 | 205 | |
c05efcb1 | 206 | cs->env_ptr = &cpu->env; |
777dc784 | 207 | cpu_exec_init(&cpu->env); |
4b6a83fb PM |
208 | cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, |
209 | g_free, g_free); | |
79614b78 | 210 | |
7c1840b6 PM |
211 | #ifndef CONFIG_USER_ONLY |
212 | /* Our inbound IRQ and FIQ lines */ | |
213 | if (kvm_enabled()) { | |
214 | qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 2); | |
215 | } else { | |
216 | qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 2); | |
217 | } | |
55d284af | 218 | |
bc72ad67 | 219 | cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, |
55d284af | 220 | arm_gt_ptimer_cb, cpu); |
bc72ad67 | 221 | cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, |
55d284af PM |
222 | arm_gt_vtimer_cb, cpu); |
223 | qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, | |
224 | ARRAY_SIZE(cpu->gt_timer_outputs)); | |
7c1840b6 PM |
225 | #endif |
226 | ||
54d3e3f5 PM |
227 | /* DTB consumers generally don't in fact care what the 'compatible' |
228 | * string is, so always provide some string and trust that a hypothetical | |
229 | * picky DTB consumer will also provide a helpful error message. | |
230 | */ | |
231 | cpu->dtb_compatible = "qemu,unknown"; | |
3541addc | 232 | cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; |
54d3e3f5 | 233 | |
79614b78 AF |
234 | if (tcg_enabled() && !inited) { |
235 | inited = true; | |
236 | arm_translate_init(); | |
237 | } | |
4b6a83fb PM |
238 | } |
239 | ||
07a5b0d2 PC |
240 | static Property arm_cpu_reset_cbar_property = |
241 | DEFINE_PROP_UINT32("reset-cbar", ARMCPU, reset_cbar, 0); | |
242 | ||
68e0a40a AP |
243 | static Property arm_cpu_reset_hivecs_property = |
244 | DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); | |
245 | ||
07a5b0d2 PC |
246 | static void arm_cpu_post_init(Object *obj) |
247 | { | |
248 | ARMCPU *cpu = ARM_CPU(obj); | |
249 | Error *err = NULL; | |
250 | ||
251 | if (arm_feature(&cpu->env, ARM_FEATURE_CBAR)) { | |
252 | qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, | |
253 | &err); | |
254 | assert_no_error(err); | |
255 | } | |
68e0a40a AP |
256 | |
257 | if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { | |
258 | qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property, | |
259 | &err); | |
260 | assert_no_error(err); | |
261 | } | |
07a5b0d2 PC |
262 | } |
263 | ||
4b6a83fb PM |
264 | static void arm_cpu_finalizefn(Object *obj) |
265 | { | |
266 | ARMCPU *cpu = ARM_CPU(obj); | |
267 | g_hash_table_destroy(cpu->cp_regs); | |
777dc784 PM |
268 | } |
269 | ||
14969266 | 270 | static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
581be094 | 271 | { |
14a10fc3 | 272 | CPUState *cs = CPU(dev); |
14969266 AF |
273 | ARMCPU *cpu = ARM_CPU(dev); |
274 | ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); | |
581be094 | 275 | CPUARMState *env = &cpu->env; |
14969266 | 276 | |
581be094 | 277 | /* Some features automatically imply others: */ |
81e69fb0 MR |
278 | if (arm_feature(env, ARM_FEATURE_V8)) { |
279 | set_feature(env, ARM_FEATURE_V7); | |
280 | set_feature(env, ARM_FEATURE_ARM_DIV); | |
281 | set_feature(env, ARM_FEATURE_LPAE); | |
9d935509 | 282 | set_feature(env, ARM_FEATURE_V8_AES); |
81e69fb0 | 283 | } |
581be094 PM |
284 | if (arm_feature(env, ARM_FEATURE_V7)) { |
285 | set_feature(env, ARM_FEATURE_VAPA); | |
286 | set_feature(env, ARM_FEATURE_THUMB2); | |
81bdde9d | 287 | set_feature(env, ARM_FEATURE_MPIDR); |
581be094 PM |
288 | if (!arm_feature(env, ARM_FEATURE_M)) { |
289 | set_feature(env, ARM_FEATURE_V6K); | |
290 | } else { | |
291 | set_feature(env, ARM_FEATURE_V6); | |
292 | } | |
293 | } | |
294 | if (arm_feature(env, ARM_FEATURE_V6K)) { | |
295 | set_feature(env, ARM_FEATURE_V6); | |
296 | set_feature(env, ARM_FEATURE_MVFR); | |
297 | } | |
298 | if (arm_feature(env, ARM_FEATURE_V6)) { | |
299 | set_feature(env, ARM_FEATURE_V5); | |
300 | if (!arm_feature(env, ARM_FEATURE_M)) { | |
301 | set_feature(env, ARM_FEATURE_AUXCR); | |
302 | } | |
303 | } | |
304 | if (arm_feature(env, ARM_FEATURE_V5)) { | |
305 | set_feature(env, ARM_FEATURE_V4T); | |
306 | } | |
307 | if (arm_feature(env, ARM_FEATURE_M)) { | |
308 | set_feature(env, ARM_FEATURE_THUMB_DIV); | |
309 | } | |
310 | if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { | |
311 | set_feature(env, ARM_FEATURE_THUMB_DIV); | |
312 | } | |
313 | if (arm_feature(env, ARM_FEATURE_VFP4)) { | |
314 | set_feature(env, ARM_FEATURE_VFP3); | |
315 | } | |
316 | if (arm_feature(env, ARM_FEATURE_VFP3)) { | |
317 | set_feature(env, ARM_FEATURE_VFP); | |
318 | } | |
de9b05b8 | 319 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
bdcc150d | 320 | set_feature(env, ARM_FEATURE_V7MP); |
de9b05b8 PM |
321 | set_feature(env, ARM_FEATURE_PXN); |
322 | } | |
2ceb98c0 | 323 | |
68e0a40a AP |
324 | if (cpu->reset_hivecs) { |
325 | cpu->reset_sctlr |= (1 << 13); | |
326 | } | |
327 | ||
2ceb98c0 | 328 | register_cp_regs_for_features(cpu); |
14969266 AF |
329 | arm_cpu_register_gdb_regs_for_features(cpu); |
330 | ||
721fae12 PM |
331 | init_cpreg_list(cpu); |
332 | ||
14a10fc3 AF |
333 | cpu_reset(cs); |
334 | qemu_init_vcpu(cs); | |
14969266 AF |
335 | |
336 | acc->parent_realize(dev, errp); | |
581be094 PM |
337 | } |
338 | ||
5900d6b2 AF |
339 | static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) |
340 | { | |
341 | ObjectClass *oc; | |
51492fd1 | 342 | char *typename; |
5900d6b2 AF |
343 | |
344 | if (!cpu_model) { | |
345 | return NULL; | |
346 | } | |
347 | ||
51492fd1 AF |
348 | typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpu_model); |
349 | oc = object_class_by_name(typename); | |
350 | g_free(typename); | |
245fb54d AF |
351 | if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || |
352 | object_class_is_abstract(oc)) { | |
5900d6b2 AF |
353 | return NULL; |
354 | } | |
355 | return oc; | |
356 | } | |
357 | ||
15ee776b PM |
358 | /* CPU models. These are not needed for the AArch64 linux-user build. */ |
359 | #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) | |
360 | ||
777dc784 PM |
361 | static void arm926_initfn(Object *obj) |
362 | { | |
363 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
364 | |
365 | cpu->dtb_compatible = "arm,arm926"; | |
581be094 PM |
366 | set_feature(&cpu->env, ARM_FEATURE_V5); |
367 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
c4804214 PM |
368 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
369 | set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); | |
b2d06f96 | 370 | cpu->midr = 0x41069265; |
325b3cef | 371 | cpu->reset_fpsid = 0x41011090; |
64e1671f | 372 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 373 | cpu->reset_sctlr = 0x00090078; |
777dc784 PM |
374 | } |
375 | ||
376 | static void arm946_initfn(Object *obj) | |
377 | { | |
378 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
379 | |
380 | cpu->dtb_compatible = "arm,arm946"; | |
581be094 PM |
381 | set_feature(&cpu->env, ARM_FEATURE_V5); |
382 | set_feature(&cpu->env, ARM_FEATURE_MPU); | |
c4804214 | 383 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 384 | cpu->midr = 0x41059461; |
64e1671f | 385 | cpu->ctr = 0x0f004006; |
0ca7e01c | 386 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
387 | } |
388 | ||
389 | static void arm1026_initfn(Object *obj) | |
390 | { | |
391 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
392 | |
393 | cpu->dtb_compatible = "arm,arm1026"; | |
581be094 PM |
394 | set_feature(&cpu->env, ARM_FEATURE_V5); |
395 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
396 | set_feature(&cpu->env, ARM_FEATURE_AUXCR); | |
c4804214 PM |
397 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
398 | set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); | |
b2d06f96 | 399 | cpu->midr = 0x4106a262; |
325b3cef | 400 | cpu->reset_fpsid = 0x410110a0; |
64e1671f | 401 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 402 | cpu->reset_sctlr = 0x00090078; |
2771db27 | 403 | cpu->reset_auxcr = 1; |
06d76f31 PM |
404 | { |
405 | /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ | |
406 | ARMCPRegInfo ifar = { | |
407 | .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, | |
408 | .access = PL1_RW, | |
409 | .fieldoffset = offsetof(CPUARMState, cp15.c6_insn), | |
410 | .resetvalue = 0 | |
411 | }; | |
412 | define_one_arm_cp_reg(cpu, &ifar); | |
413 | } | |
777dc784 PM |
414 | } |
415 | ||
416 | static void arm1136_r2_initfn(Object *obj) | |
417 | { | |
418 | ARMCPU *cpu = ARM_CPU(obj); | |
2e4d7e3e PM |
419 | /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an |
420 | * older core than plain "arm1136". In particular this does not | |
421 | * have the v6K features. | |
422 | * These ID register values are correct for 1136 but may be wrong | |
423 | * for 1136_r2 (in particular r0p2 does not actually implement most | |
424 | * of the ID registers). | |
425 | */ | |
54d3e3f5 PM |
426 | |
427 | cpu->dtb_compatible = "arm,arm1136"; | |
581be094 PM |
428 | set_feature(&cpu->env, ARM_FEATURE_V6); |
429 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
c4804214 PM |
430 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
431 | set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); | |
432 | set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); | |
b2d06f96 | 433 | cpu->midr = 0x4107b362; |
325b3cef | 434 | cpu->reset_fpsid = 0x410120b4; |
bd35c355 PM |
435 | cpu->mvfr0 = 0x11111111; |
436 | cpu->mvfr1 = 0x00000000; | |
64e1671f | 437 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 438 | cpu->reset_sctlr = 0x00050078; |
2e4d7e3e PM |
439 | cpu->id_pfr0 = 0x111; |
440 | cpu->id_pfr1 = 0x1; | |
441 | cpu->id_dfr0 = 0x2; | |
442 | cpu->id_afr0 = 0x3; | |
443 | cpu->id_mmfr0 = 0x01130003; | |
444 | cpu->id_mmfr1 = 0x10030302; | |
445 | cpu->id_mmfr2 = 0x01222110; | |
446 | cpu->id_isar0 = 0x00140011; | |
447 | cpu->id_isar1 = 0x12002111; | |
448 | cpu->id_isar2 = 0x11231111; | |
449 | cpu->id_isar3 = 0x01102131; | |
450 | cpu->id_isar4 = 0x141; | |
2771db27 | 451 | cpu->reset_auxcr = 7; |
777dc784 PM |
452 | } |
453 | ||
454 | static void arm1136_initfn(Object *obj) | |
455 | { | |
456 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
457 | |
458 | cpu->dtb_compatible = "arm,arm1136"; | |
581be094 PM |
459 | set_feature(&cpu->env, ARM_FEATURE_V6K); |
460 | set_feature(&cpu->env, ARM_FEATURE_V6); | |
461 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
c4804214 PM |
462 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
463 | set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); | |
464 | set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); | |
b2d06f96 | 465 | cpu->midr = 0x4117b363; |
325b3cef | 466 | cpu->reset_fpsid = 0x410120b4; |
bd35c355 PM |
467 | cpu->mvfr0 = 0x11111111; |
468 | cpu->mvfr1 = 0x00000000; | |
64e1671f | 469 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 470 | cpu->reset_sctlr = 0x00050078; |
2e4d7e3e PM |
471 | cpu->id_pfr0 = 0x111; |
472 | cpu->id_pfr1 = 0x1; | |
473 | cpu->id_dfr0 = 0x2; | |
474 | cpu->id_afr0 = 0x3; | |
475 | cpu->id_mmfr0 = 0x01130003; | |
476 | cpu->id_mmfr1 = 0x10030302; | |
477 | cpu->id_mmfr2 = 0x01222110; | |
478 | cpu->id_isar0 = 0x00140011; | |
479 | cpu->id_isar1 = 0x12002111; | |
480 | cpu->id_isar2 = 0x11231111; | |
481 | cpu->id_isar3 = 0x01102131; | |
482 | cpu->id_isar4 = 0x141; | |
2771db27 | 483 | cpu->reset_auxcr = 7; |
777dc784 PM |
484 | } |
485 | ||
486 | static void arm1176_initfn(Object *obj) | |
487 | { | |
488 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
489 | |
490 | cpu->dtb_compatible = "arm,arm1176"; | |
581be094 PM |
491 | set_feature(&cpu->env, ARM_FEATURE_V6K); |
492 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
493 | set_feature(&cpu->env, ARM_FEATURE_VAPA); | |
c4804214 PM |
494 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
495 | set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); | |
496 | set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); | |
b2d06f96 | 497 | cpu->midr = 0x410fb767; |
325b3cef | 498 | cpu->reset_fpsid = 0x410120b5; |
bd35c355 PM |
499 | cpu->mvfr0 = 0x11111111; |
500 | cpu->mvfr1 = 0x00000000; | |
64e1671f | 501 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 502 | cpu->reset_sctlr = 0x00050078; |
2e4d7e3e PM |
503 | cpu->id_pfr0 = 0x111; |
504 | cpu->id_pfr1 = 0x11; | |
505 | cpu->id_dfr0 = 0x33; | |
506 | cpu->id_afr0 = 0; | |
507 | cpu->id_mmfr0 = 0x01130003; | |
508 | cpu->id_mmfr1 = 0x10030302; | |
509 | cpu->id_mmfr2 = 0x01222100; | |
510 | cpu->id_isar0 = 0x0140011; | |
511 | cpu->id_isar1 = 0x12002111; | |
512 | cpu->id_isar2 = 0x11231121; | |
513 | cpu->id_isar3 = 0x01102131; | |
514 | cpu->id_isar4 = 0x01141; | |
2771db27 | 515 | cpu->reset_auxcr = 7; |
777dc784 PM |
516 | } |
517 | ||
518 | static void arm11mpcore_initfn(Object *obj) | |
519 | { | |
520 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
521 | |
522 | cpu->dtb_compatible = "arm,arm11mpcore"; | |
581be094 PM |
523 | set_feature(&cpu->env, ARM_FEATURE_V6K); |
524 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
525 | set_feature(&cpu->env, ARM_FEATURE_VAPA); | |
81bdde9d | 526 | set_feature(&cpu->env, ARM_FEATURE_MPIDR); |
c4804214 | 527 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 528 | cpu->midr = 0x410fb022; |
325b3cef | 529 | cpu->reset_fpsid = 0x410120b4; |
bd35c355 PM |
530 | cpu->mvfr0 = 0x11111111; |
531 | cpu->mvfr1 = 0x00000000; | |
200bf596 | 532 | cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ |
2e4d7e3e PM |
533 | cpu->id_pfr0 = 0x111; |
534 | cpu->id_pfr1 = 0x1; | |
535 | cpu->id_dfr0 = 0; | |
536 | cpu->id_afr0 = 0x2; | |
537 | cpu->id_mmfr0 = 0x01100103; | |
538 | cpu->id_mmfr1 = 0x10020302; | |
539 | cpu->id_mmfr2 = 0x01222000; | |
540 | cpu->id_isar0 = 0x00100011; | |
541 | cpu->id_isar1 = 0x12002111; | |
542 | cpu->id_isar2 = 0x11221011; | |
543 | cpu->id_isar3 = 0x01102131; | |
544 | cpu->id_isar4 = 0x141; | |
2771db27 | 545 | cpu->reset_auxcr = 1; |
777dc784 PM |
546 | } |
547 | ||
548 | static void cortex_m3_initfn(Object *obj) | |
549 | { | |
550 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
551 | set_feature(&cpu->env, ARM_FEATURE_V7); |
552 | set_feature(&cpu->env, ARM_FEATURE_M); | |
b2d06f96 | 553 | cpu->midr = 0x410fc231; |
777dc784 PM |
554 | } |
555 | ||
e6f010cc AF |
556 | static void arm_v7m_class_init(ObjectClass *oc, void *data) |
557 | { | |
558 | #ifndef CONFIG_USER_ONLY | |
559 | CPUClass *cc = CPU_CLASS(oc); | |
560 | ||
561 | cc->do_interrupt = arm_v7m_cpu_do_interrupt; | |
562 | #endif | |
563 | } | |
564 | ||
34f90529 PM |
565 | static const ARMCPRegInfo cortexa8_cp_reginfo[] = { |
566 | { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, | |
567 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
568 | { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, | |
569 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
570 | REGINFO_SENTINEL | |
571 | }; | |
572 | ||
777dc784 PM |
573 | static void cortex_a8_initfn(Object *obj) |
574 | { | |
575 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
576 | |
577 | cpu->dtb_compatible = "arm,cortex-a8"; | |
581be094 PM |
578 | set_feature(&cpu->env, ARM_FEATURE_V7); |
579 | set_feature(&cpu->env, ARM_FEATURE_VFP3); | |
580 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
581 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
c4804214 | 582 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 583 | cpu->midr = 0x410fc080; |
325b3cef | 584 | cpu->reset_fpsid = 0x410330c0; |
bd35c355 PM |
585 | cpu->mvfr0 = 0x11110222; |
586 | cpu->mvfr1 = 0x00011100; | |
64e1671f | 587 | cpu->ctr = 0x82048004; |
0ca7e01c | 588 | cpu->reset_sctlr = 0x00c50078; |
2e4d7e3e PM |
589 | cpu->id_pfr0 = 0x1031; |
590 | cpu->id_pfr1 = 0x11; | |
591 | cpu->id_dfr0 = 0x400; | |
592 | cpu->id_afr0 = 0; | |
593 | cpu->id_mmfr0 = 0x31100003; | |
594 | cpu->id_mmfr1 = 0x20000000; | |
595 | cpu->id_mmfr2 = 0x01202000; | |
596 | cpu->id_mmfr3 = 0x11; | |
597 | cpu->id_isar0 = 0x00101111; | |
598 | cpu->id_isar1 = 0x12112111; | |
599 | cpu->id_isar2 = 0x21232031; | |
600 | cpu->id_isar3 = 0x11112131; | |
601 | cpu->id_isar4 = 0x00111142; | |
85df3786 PM |
602 | cpu->clidr = (1 << 27) | (2 << 24) | 3; |
603 | cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ | |
604 | cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ | |
605 | cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ | |
2771db27 | 606 | cpu->reset_auxcr = 2; |
34f90529 | 607 | define_arm_cp_regs(cpu, cortexa8_cp_reginfo); |
777dc784 PM |
608 | } |
609 | ||
1047b9d7 PM |
610 | static const ARMCPRegInfo cortexa9_cp_reginfo[] = { |
611 | /* power_control should be set to maximum latency. Again, | |
612 | * default to 0 and set by private hook | |
613 | */ | |
614 | { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, | |
615 | .access = PL1_RW, .resetvalue = 0, | |
616 | .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, | |
617 | { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, | |
618 | .access = PL1_RW, .resetvalue = 0, | |
619 | .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, | |
620 | { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, | |
621 | .access = PL1_RW, .resetvalue = 0, | |
622 | .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, | |
623 | { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, | |
624 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
625 | /* TLB lockdown control */ | |
626 | { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, | |
627 | .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, | |
628 | { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, | |
629 | .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, | |
630 | { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, | |
631 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
632 | { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, | |
633 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
634 | { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, | |
635 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
636 | REGINFO_SENTINEL | |
637 | }; | |
638 | ||
777dc784 PM |
639 | static void cortex_a9_initfn(Object *obj) |
640 | { | |
641 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
642 | |
643 | cpu->dtb_compatible = "arm,cortex-a9"; | |
581be094 PM |
644 | set_feature(&cpu->env, ARM_FEATURE_V7); |
645 | set_feature(&cpu->env, ARM_FEATURE_VFP3); | |
646 | set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); | |
647 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
648 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
649 | /* Note that A9 supports the MP extensions even for | |
650 | * A9UP and single-core A9MP (which are both different | |
651 | * and valid configurations; we don't model A9UP). | |
652 | */ | |
653 | set_feature(&cpu->env, ARM_FEATURE_V7MP); | |
d8ba780b | 654 | set_feature(&cpu->env, ARM_FEATURE_CBAR); |
b2d06f96 | 655 | cpu->midr = 0x410fc090; |
325b3cef | 656 | cpu->reset_fpsid = 0x41033090; |
bd35c355 PM |
657 | cpu->mvfr0 = 0x11110222; |
658 | cpu->mvfr1 = 0x01111111; | |
64e1671f | 659 | cpu->ctr = 0x80038003; |
0ca7e01c | 660 | cpu->reset_sctlr = 0x00c50078; |
2e4d7e3e PM |
661 | cpu->id_pfr0 = 0x1031; |
662 | cpu->id_pfr1 = 0x11; | |
663 | cpu->id_dfr0 = 0x000; | |
664 | cpu->id_afr0 = 0; | |
665 | cpu->id_mmfr0 = 0x00100103; | |
666 | cpu->id_mmfr1 = 0x20000000; | |
667 | cpu->id_mmfr2 = 0x01230000; | |
668 | cpu->id_mmfr3 = 0x00002111; | |
669 | cpu->id_isar0 = 0x00101111; | |
670 | cpu->id_isar1 = 0x13112111; | |
671 | cpu->id_isar2 = 0x21232041; | |
672 | cpu->id_isar3 = 0x11112131; | |
673 | cpu->id_isar4 = 0x00111142; | |
85df3786 PM |
674 | cpu->clidr = (1 << 27) | (1 << 24) | 3; |
675 | cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */ | |
676 | cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */ | |
d8ba780b | 677 | define_arm_cp_regs(cpu, cortexa9_cp_reginfo); |
777dc784 PM |
678 | } |
679 | ||
34f90529 PM |
680 | #ifndef CONFIG_USER_ONLY |
681 | static int a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri, | |
682 | uint64_t *value) | |
683 | { | |
684 | /* Linux wants the number of processors from here. | |
685 | * Might as well set the interrupt-controller bit too. | |
686 | */ | |
687 | *value = ((smp_cpus - 1) << 24) | (1 << 23); | |
688 | return 0; | |
689 | } | |
690 | #endif | |
691 | ||
692 | static const ARMCPRegInfo cortexa15_cp_reginfo[] = { | |
693 | #ifndef CONFIG_USER_ONLY | |
694 | { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, | |
695 | .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, | |
696 | .writefn = arm_cp_write_ignore, }, | |
697 | #endif | |
698 | { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, | |
699 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
700 | REGINFO_SENTINEL | |
701 | }; | |
702 | ||
777dc784 PM |
703 | static void cortex_a15_initfn(Object *obj) |
704 | { | |
705 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
706 | |
707 | cpu->dtb_compatible = "arm,cortex-a15"; | |
581be094 PM |
708 | set_feature(&cpu->env, ARM_FEATURE_V7); |
709 | set_feature(&cpu->env, ARM_FEATURE_VFP4); | |
710 | set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); | |
711 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
712 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
713 | set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); | |
581be094 | 714 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); |
c4804214 | 715 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
d8ba780b | 716 | set_feature(&cpu->env, ARM_FEATURE_CBAR); |
de9b05b8 | 717 | set_feature(&cpu->env, ARM_FEATURE_LPAE); |
3541addc | 718 | cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; |
b2d06f96 | 719 | cpu->midr = 0x412fc0f1; |
325b3cef | 720 | cpu->reset_fpsid = 0x410430f0; |
bd35c355 PM |
721 | cpu->mvfr0 = 0x10110222; |
722 | cpu->mvfr1 = 0x11111111; | |
64e1671f | 723 | cpu->ctr = 0x8444c004; |
0ca7e01c | 724 | cpu->reset_sctlr = 0x00c50078; |
2e4d7e3e PM |
725 | cpu->id_pfr0 = 0x00001131; |
726 | cpu->id_pfr1 = 0x00011011; | |
727 | cpu->id_dfr0 = 0x02010555; | |
728 | cpu->id_afr0 = 0x00000000; | |
729 | cpu->id_mmfr0 = 0x10201105; | |
730 | cpu->id_mmfr1 = 0x20000000; | |
731 | cpu->id_mmfr2 = 0x01240000; | |
732 | cpu->id_mmfr3 = 0x02102211; | |
733 | cpu->id_isar0 = 0x02101110; | |
734 | cpu->id_isar1 = 0x13112111; | |
735 | cpu->id_isar2 = 0x21232041; | |
736 | cpu->id_isar3 = 0x11112131; | |
737 | cpu->id_isar4 = 0x10011142; | |
85df3786 PM |
738 | cpu->clidr = 0x0a200023; |
739 | cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ | |
740 | cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ | |
741 | cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ | |
34f90529 | 742 | define_arm_cp_regs(cpu, cortexa15_cp_reginfo); |
777dc784 PM |
743 | } |
744 | ||
745 | static void ti925t_initfn(Object *obj) | |
746 | { | |
747 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
748 | set_feature(&cpu->env, ARM_FEATURE_V4T); |
749 | set_feature(&cpu->env, ARM_FEATURE_OMAPCP); | |
777dc784 | 750 | cpu->midr = ARM_CPUID_TI925T; |
64e1671f | 751 | cpu->ctr = 0x5109149; |
0ca7e01c | 752 | cpu->reset_sctlr = 0x00000070; |
777dc784 PM |
753 | } |
754 | ||
755 | static void sa1100_initfn(Object *obj) | |
756 | { | |
757 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
758 | |
759 | cpu->dtb_compatible = "intel,sa1100"; | |
581be094 | 760 | set_feature(&cpu->env, ARM_FEATURE_STRONGARM); |
c4804214 | 761 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 762 | cpu->midr = 0x4401A11B; |
0ca7e01c | 763 | cpu->reset_sctlr = 0x00000070; |
777dc784 PM |
764 | } |
765 | ||
766 | static void sa1110_initfn(Object *obj) | |
767 | { | |
768 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 | 769 | set_feature(&cpu->env, ARM_FEATURE_STRONGARM); |
c4804214 | 770 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 771 | cpu->midr = 0x6901B119; |
0ca7e01c | 772 | cpu->reset_sctlr = 0x00000070; |
777dc784 PM |
773 | } |
774 | ||
775 | static void pxa250_initfn(Object *obj) | |
776 | { | |
777 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
778 | |
779 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
780 | set_feature(&cpu->env, ARM_FEATURE_V5); |
781 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 782 | cpu->midr = 0x69052100; |
64e1671f | 783 | cpu->ctr = 0xd172172; |
0ca7e01c | 784 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
785 | } |
786 | ||
787 | static void pxa255_initfn(Object *obj) | |
788 | { | |
789 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
790 | |
791 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
792 | set_feature(&cpu->env, ARM_FEATURE_V5); |
793 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 794 | cpu->midr = 0x69052d00; |
64e1671f | 795 | cpu->ctr = 0xd172172; |
0ca7e01c | 796 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
797 | } |
798 | ||
799 | static void pxa260_initfn(Object *obj) | |
800 | { | |
801 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
802 | |
803 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
804 | set_feature(&cpu->env, ARM_FEATURE_V5); |
805 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 806 | cpu->midr = 0x69052903; |
64e1671f | 807 | cpu->ctr = 0xd172172; |
0ca7e01c | 808 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
809 | } |
810 | ||
811 | static void pxa261_initfn(Object *obj) | |
812 | { | |
813 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
814 | |
815 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
816 | set_feature(&cpu->env, ARM_FEATURE_V5); |
817 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 818 | cpu->midr = 0x69052d05; |
64e1671f | 819 | cpu->ctr = 0xd172172; |
0ca7e01c | 820 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
821 | } |
822 | ||
823 | static void pxa262_initfn(Object *obj) | |
824 | { | |
825 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
826 | |
827 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
828 | set_feature(&cpu->env, ARM_FEATURE_V5); |
829 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 830 | cpu->midr = 0x69052d06; |
64e1671f | 831 | cpu->ctr = 0xd172172; |
0ca7e01c | 832 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
833 | } |
834 | ||
835 | static void pxa270a0_initfn(Object *obj) | |
836 | { | |
837 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
838 | |
839 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
840 | set_feature(&cpu->env, ARM_FEATURE_V5); |
841 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
842 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 843 | cpu->midr = 0x69054110; |
64e1671f | 844 | cpu->ctr = 0xd172172; |
0ca7e01c | 845 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
846 | } |
847 | ||
848 | static void pxa270a1_initfn(Object *obj) | |
849 | { | |
850 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
851 | |
852 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
853 | set_feature(&cpu->env, ARM_FEATURE_V5); |
854 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
855 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 856 | cpu->midr = 0x69054111; |
64e1671f | 857 | cpu->ctr = 0xd172172; |
0ca7e01c | 858 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
859 | } |
860 | ||
861 | static void pxa270b0_initfn(Object *obj) | |
862 | { | |
863 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
864 | |
865 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
866 | set_feature(&cpu->env, ARM_FEATURE_V5); |
867 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
868 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 869 | cpu->midr = 0x69054112; |
64e1671f | 870 | cpu->ctr = 0xd172172; |
0ca7e01c | 871 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
872 | } |
873 | ||
874 | static void pxa270b1_initfn(Object *obj) | |
875 | { | |
876 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
877 | |
878 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
879 | set_feature(&cpu->env, ARM_FEATURE_V5); |
880 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
881 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 882 | cpu->midr = 0x69054113; |
64e1671f | 883 | cpu->ctr = 0xd172172; |
0ca7e01c | 884 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
885 | } |
886 | ||
887 | static void pxa270c0_initfn(Object *obj) | |
888 | { | |
889 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
890 | |
891 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
892 | set_feature(&cpu->env, ARM_FEATURE_V5); |
893 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
894 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 895 | cpu->midr = 0x69054114; |
64e1671f | 896 | cpu->ctr = 0xd172172; |
0ca7e01c | 897 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
898 | } |
899 | ||
900 | static void pxa270c5_initfn(Object *obj) | |
901 | { | |
902 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
903 | |
904 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
905 | set_feature(&cpu->env, ARM_FEATURE_V5); |
906 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
907 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 908 | cpu->midr = 0x69054117; |
64e1671f | 909 | cpu->ctr = 0xd172172; |
0ca7e01c | 910 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
911 | } |
912 | ||
f5f6d38b | 913 | #ifdef CONFIG_USER_ONLY |
777dc784 PM |
914 | static void arm_any_initfn(Object *obj) |
915 | { | |
916 | ARMCPU *cpu = ARM_CPU(obj); | |
81e69fb0 | 917 | set_feature(&cpu->env, ARM_FEATURE_V8); |
581be094 PM |
918 | set_feature(&cpu->env, ARM_FEATURE_VFP4); |
919 | set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); | |
920 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
921 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
922 | set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); | |
923 | set_feature(&cpu->env, ARM_FEATURE_V7MP); | |
3926cc84 AG |
924 | #ifdef TARGET_AARCH64 |
925 | set_feature(&cpu->env, ARM_FEATURE_AARCH64); | |
926 | #endif | |
b2d06f96 | 927 | cpu->midr = 0xffffffff; |
777dc784 | 928 | } |
f5f6d38b | 929 | #endif |
777dc784 | 930 | |
15ee776b PM |
931 | #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ |
932 | ||
777dc784 PM |
933 | typedef struct ARMCPUInfo { |
934 | const char *name; | |
935 | void (*initfn)(Object *obj); | |
e6f010cc | 936 | void (*class_init)(ObjectClass *oc, void *data); |
777dc784 PM |
937 | } ARMCPUInfo; |
938 | ||
939 | static const ARMCPUInfo arm_cpus[] = { | |
15ee776b | 940 | #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) |
777dc784 PM |
941 | { .name = "arm926", .initfn = arm926_initfn }, |
942 | { .name = "arm946", .initfn = arm946_initfn }, | |
943 | { .name = "arm1026", .initfn = arm1026_initfn }, | |
944 | /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an | |
945 | * older core than plain "arm1136". In particular this does not | |
946 | * have the v6K features. | |
947 | */ | |
948 | { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, | |
949 | { .name = "arm1136", .initfn = arm1136_initfn }, | |
950 | { .name = "arm1176", .initfn = arm1176_initfn }, | |
951 | { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, | |
e6f010cc AF |
952 | { .name = "cortex-m3", .initfn = cortex_m3_initfn, |
953 | .class_init = arm_v7m_class_init }, | |
777dc784 PM |
954 | { .name = "cortex-a8", .initfn = cortex_a8_initfn }, |
955 | { .name = "cortex-a9", .initfn = cortex_a9_initfn }, | |
956 | { .name = "cortex-a15", .initfn = cortex_a15_initfn }, | |
957 | { .name = "ti925t", .initfn = ti925t_initfn }, | |
958 | { .name = "sa1100", .initfn = sa1100_initfn }, | |
959 | { .name = "sa1110", .initfn = sa1110_initfn }, | |
960 | { .name = "pxa250", .initfn = pxa250_initfn }, | |
961 | { .name = "pxa255", .initfn = pxa255_initfn }, | |
962 | { .name = "pxa260", .initfn = pxa260_initfn }, | |
963 | { .name = "pxa261", .initfn = pxa261_initfn }, | |
964 | { .name = "pxa262", .initfn = pxa262_initfn }, | |
965 | /* "pxa270" is an alias for "pxa270-a0" */ | |
966 | { .name = "pxa270", .initfn = pxa270a0_initfn }, | |
967 | { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, | |
968 | { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, | |
969 | { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, | |
970 | { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, | |
971 | { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, | |
972 | { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, | |
f5f6d38b | 973 | #ifdef CONFIG_USER_ONLY |
777dc784 | 974 | { .name = "any", .initfn = arm_any_initfn }, |
f5f6d38b | 975 | #endif |
15ee776b | 976 | #endif |
777dc784 PM |
977 | }; |
978 | ||
5de16430 PM |
979 | static Property arm_cpu_properties[] = { |
980 | DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), | |
981 | DEFINE_PROP_END_OF_LIST() | |
982 | }; | |
983 | ||
dec9c2d4 AF |
984 | static void arm_cpu_class_init(ObjectClass *oc, void *data) |
985 | { | |
986 | ARMCPUClass *acc = ARM_CPU_CLASS(oc); | |
987 | CPUClass *cc = CPU_CLASS(acc); | |
14969266 AF |
988 | DeviceClass *dc = DEVICE_CLASS(oc); |
989 | ||
990 | acc->parent_realize = dc->realize; | |
991 | dc->realize = arm_cpu_realizefn; | |
5de16430 | 992 | dc->props = arm_cpu_properties; |
dec9c2d4 AF |
993 | |
994 | acc->parent_reset = cc->reset; | |
995 | cc->reset = arm_cpu_reset; | |
5900d6b2 AF |
996 | |
997 | cc->class_by_name = arm_cpu_class_by_name; | |
97a8ea5a | 998 | cc->do_interrupt = arm_cpu_do_interrupt; |
878096ee | 999 | cc->dump_state = arm_cpu_dump_state; |
f45748f1 | 1000 | cc->set_pc = arm_cpu_set_pc; |
5b50e790 AF |
1001 | cc->gdb_read_register = arm_cpu_gdb_read_register; |
1002 | cc->gdb_write_register = arm_cpu_gdb_write_register; | |
00b941e5 AF |
1003 | #ifndef CONFIG_USER_ONLY |
1004 | cc->get_phys_page_debug = arm_cpu_get_phys_page_debug; | |
1005 | cc->vmsd = &vmstate_arm_cpu; | |
1006 | #endif | |
a0e372f0 | 1007 | cc->gdb_num_core_regs = 26; |
5b24c641 | 1008 | cc->gdb_core_xml_file = "arm-core.xml"; |
dec9c2d4 AF |
1009 | } |
1010 | ||
777dc784 PM |
1011 | static void cpu_register(const ARMCPUInfo *info) |
1012 | { | |
1013 | TypeInfo type_info = { | |
777dc784 PM |
1014 | .parent = TYPE_ARM_CPU, |
1015 | .instance_size = sizeof(ARMCPU), | |
1016 | .instance_init = info->initfn, | |
1017 | .class_size = sizeof(ARMCPUClass), | |
e6f010cc | 1018 | .class_init = info->class_init, |
777dc784 PM |
1019 | }; |
1020 | ||
51492fd1 | 1021 | type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); |
918fd083 | 1022 | type_register(&type_info); |
51492fd1 | 1023 | g_free((void *)type_info.name); |
777dc784 PM |
1024 | } |
1025 | ||
dec9c2d4 AF |
1026 | static const TypeInfo arm_cpu_type_info = { |
1027 | .name = TYPE_ARM_CPU, | |
1028 | .parent = TYPE_CPU, | |
1029 | .instance_size = sizeof(ARMCPU), | |
777dc784 | 1030 | .instance_init = arm_cpu_initfn, |
07a5b0d2 | 1031 | .instance_post_init = arm_cpu_post_init, |
4b6a83fb | 1032 | .instance_finalize = arm_cpu_finalizefn, |
777dc784 | 1033 | .abstract = true, |
dec9c2d4 AF |
1034 | .class_size = sizeof(ARMCPUClass), |
1035 | .class_init = arm_cpu_class_init, | |
1036 | }; | |
1037 | ||
1038 | static void arm_cpu_register_types(void) | |
1039 | { | |
777dc784 PM |
1040 | int i; |
1041 | ||
dec9c2d4 | 1042 | type_register_static(&arm_cpu_type_info); |
777dc784 PM |
1043 | for (i = 0; i < ARRAY_SIZE(arm_cpus); i++) { |
1044 | cpu_register(&arm_cpus[i]); | |
1045 | } | |
dec9c2d4 AF |
1046 | } |
1047 | ||
1048 | type_init(arm_cpu_register_types) |