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dec9c2d4 AF |
1 | /* |
2 | * QEMU ARM CPU | |
3 | * | |
4 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | */ | |
20 | ||
778c3a06 | 21 | #include "cpu.h" |
dec9c2d4 | 22 | #include "qemu-common.h" |
3c30dd5a PM |
23 | #if !defined(CONFIG_USER_ONLY) |
24 | #include "hw/loader.h" | |
25 | #endif | |
7c1840b6 | 26 | #include "hw/arm/arm.h" |
9c17d615 | 27 | #include "sysemu/sysemu.h" |
7c1840b6 | 28 | #include "sysemu/kvm.h" |
dec9c2d4 | 29 | |
f45748f1 AF |
30 | static void arm_cpu_set_pc(CPUState *cs, vaddr value) |
31 | { | |
32 | ARMCPU *cpu = ARM_CPU(cs); | |
33 | ||
34 | cpu->env.regs[15] = value; | |
35 | } | |
36 | ||
4b6a83fb PM |
37 | static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) |
38 | { | |
39 | /* Reset a single ARMCPRegInfo register */ | |
40 | ARMCPRegInfo *ri = value; | |
41 | ARMCPU *cpu = opaque; | |
42 | ||
43 | if (ri->type & ARM_CP_SPECIAL) { | |
44 | return; | |
45 | } | |
46 | ||
47 | if (ri->resetfn) { | |
48 | ri->resetfn(&cpu->env, ri); | |
49 | return; | |
50 | } | |
51 | ||
52 | /* A zero offset is never possible as it would be regs[0] | |
53 | * so we use it to indicate that reset is being handled elsewhere. | |
54 | * This is basically only used for fields in non-core coprocessors | |
55 | * (like the pxa2xx ones). | |
56 | */ | |
57 | if (!ri->fieldoffset) { | |
58 | return; | |
59 | } | |
60 | ||
61 | if (ri->type & ARM_CP_64BIT) { | |
62 | CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; | |
63 | } else { | |
64 | CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; | |
65 | } | |
66 | } | |
67 | ||
dec9c2d4 AF |
68 | /* CPUClass::reset() */ |
69 | static void arm_cpu_reset(CPUState *s) | |
70 | { | |
71 | ARMCPU *cpu = ARM_CPU(s); | |
72 | ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); | |
3c30dd5a | 73 | CPUARMState *env = &cpu->env; |
3c30dd5a | 74 | |
dec9c2d4 AF |
75 | acc->parent_reset(s); |
76 | ||
3c30dd5a | 77 | memset(env, 0, offsetof(CPUARMState, breakpoints)); |
4b6a83fb | 78 | g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); |
3c30dd5a PM |
79 | env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; |
80 | env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; | |
81 | env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; | |
3c30dd5a PM |
82 | |
83 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { | |
84 | env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; | |
85 | } | |
86 | ||
87 | #if defined(CONFIG_USER_ONLY) | |
88 | env->uncached_cpsr = ARM_CPU_MODE_USR; | |
89 | /* For user mode we must enable access to coprocessors */ | |
90 | env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; | |
91 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { | |
92 | env->cp15.c15_cpar = 3; | |
93 | } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
94 | env->cp15.c15_cpar = 1; | |
95 | } | |
96 | #else | |
97 | /* SVC mode with interrupts disabled. */ | |
98 | env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I; | |
99 | /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is | |
100 | clear at reset. Initial SP and PC are loaded from ROM. */ | |
101 | if (IS_M(env)) { | |
102 | uint32_t pc; | |
103 | uint8_t *rom; | |
104 | env->uncached_cpsr &= ~CPSR_I; | |
105 | rom = rom_ptr(0); | |
106 | if (rom) { | |
107 | /* We should really use ldl_phys here, in case the guest | |
108 | modified flash and reset itself. However images | |
109 | loaded via -kernel have not been copied yet, so load the | |
110 | values directly from there. */ | |
111 | env->regs[13] = ldl_p(rom); | |
112 | pc = ldl_p(rom + 4); | |
113 | env->thumb = pc & 1; | |
114 | env->regs[15] = pc & ~1; | |
115 | } | |
116 | } | |
117 | env->vfp.xregs[ARM_VFP_FPEXC] = 0; | |
3c30dd5a PM |
118 | #endif |
119 | set_flush_to_zero(1, &env->vfp.standard_fp_status); | |
120 | set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); | |
121 | set_default_nan_mode(1, &env->vfp.standard_fp_status); | |
122 | set_float_detect_tininess(float_tininess_before_rounding, | |
123 | &env->vfp.fp_status); | |
124 | set_float_detect_tininess(float_tininess_before_rounding, | |
125 | &env->vfp.standard_fp_status); | |
126 | tlb_flush(env, 1); | |
127 | /* Reset is a state change for some CPUARMState fields which we | |
128 | * bake assumptions about into translated code, so we need to | |
129 | * tb_flush(). | |
130 | */ | |
131 | tb_flush(env); | |
dec9c2d4 AF |
132 | } |
133 | ||
7c1840b6 PM |
134 | #ifndef CONFIG_USER_ONLY |
135 | static void arm_cpu_set_irq(void *opaque, int irq, int level) | |
136 | { | |
137 | ARMCPU *cpu = opaque; | |
138 | CPUState *cs = CPU(cpu); | |
139 | ||
140 | switch (irq) { | |
141 | case ARM_CPU_IRQ: | |
142 | if (level) { | |
143 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); | |
144 | } else { | |
145 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); | |
146 | } | |
147 | break; | |
148 | case ARM_CPU_FIQ: | |
149 | if (level) { | |
150 | cpu_interrupt(cs, CPU_INTERRUPT_FIQ); | |
151 | } else { | |
152 | cpu_reset_interrupt(cs, CPU_INTERRUPT_FIQ); | |
153 | } | |
154 | break; | |
155 | default: | |
156 | hw_error("arm_cpu_set_irq: Bad interrupt line %d\n", irq); | |
157 | } | |
158 | } | |
159 | ||
160 | static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) | |
161 | { | |
162 | #ifdef CONFIG_KVM | |
163 | ARMCPU *cpu = opaque; | |
164 | CPUState *cs = CPU(cpu); | |
165 | int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT; | |
166 | ||
167 | switch (irq) { | |
168 | case ARM_CPU_IRQ: | |
169 | kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; | |
170 | break; | |
171 | case ARM_CPU_FIQ: | |
172 | kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; | |
173 | break; | |
174 | default: | |
175 | hw_error("arm_cpu_kvm_set_irq: Bad interrupt line %d\n", irq); | |
176 | } | |
177 | kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; | |
178 | kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); | |
179 | #endif | |
180 | } | |
181 | #endif | |
182 | ||
581be094 PM |
183 | static inline void set_feature(CPUARMState *env, int feature) |
184 | { | |
918f5dca | 185 | env->features |= 1ULL << feature; |
581be094 PM |
186 | } |
187 | ||
777dc784 PM |
188 | static void arm_cpu_initfn(Object *obj) |
189 | { | |
c05efcb1 | 190 | CPUState *cs = CPU(obj); |
777dc784 | 191 | ARMCPU *cpu = ARM_CPU(obj); |
79614b78 | 192 | static bool inited; |
777dc784 | 193 | |
c05efcb1 | 194 | cs->env_ptr = &cpu->env; |
777dc784 | 195 | cpu_exec_init(&cpu->env); |
4b6a83fb PM |
196 | cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, |
197 | g_free, g_free); | |
79614b78 | 198 | |
7c1840b6 PM |
199 | #ifndef CONFIG_USER_ONLY |
200 | /* Our inbound IRQ and FIQ lines */ | |
201 | if (kvm_enabled()) { | |
202 | qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 2); | |
203 | } else { | |
204 | qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 2); | |
205 | } | |
55d284af | 206 | |
bc72ad67 | 207 | cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, |
55d284af | 208 | arm_gt_ptimer_cb, cpu); |
bc72ad67 | 209 | cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, |
55d284af PM |
210 | arm_gt_vtimer_cb, cpu); |
211 | qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, | |
212 | ARRAY_SIZE(cpu->gt_timer_outputs)); | |
7c1840b6 PM |
213 | #endif |
214 | ||
79614b78 AF |
215 | if (tcg_enabled() && !inited) { |
216 | inited = true; | |
217 | arm_translate_init(); | |
218 | } | |
4b6a83fb PM |
219 | } |
220 | ||
221 | static void arm_cpu_finalizefn(Object *obj) | |
222 | { | |
223 | ARMCPU *cpu = ARM_CPU(obj); | |
224 | g_hash_table_destroy(cpu->cp_regs); | |
777dc784 PM |
225 | } |
226 | ||
14969266 | 227 | static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
581be094 | 228 | { |
14a10fc3 | 229 | CPUState *cs = CPU(dev); |
14969266 AF |
230 | ARMCPU *cpu = ARM_CPU(dev); |
231 | ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); | |
581be094 | 232 | CPUARMState *env = &cpu->env; |
14969266 | 233 | |
581be094 | 234 | /* Some features automatically imply others: */ |
81e69fb0 MR |
235 | if (arm_feature(env, ARM_FEATURE_V8)) { |
236 | set_feature(env, ARM_FEATURE_V7); | |
237 | set_feature(env, ARM_FEATURE_ARM_DIV); | |
238 | set_feature(env, ARM_FEATURE_LPAE); | |
239 | } | |
581be094 PM |
240 | if (arm_feature(env, ARM_FEATURE_V7)) { |
241 | set_feature(env, ARM_FEATURE_VAPA); | |
242 | set_feature(env, ARM_FEATURE_THUMB2); | |
81bdde9d | 243 | set_feature(env, ARM_FEATURE_MPIDR); |
581be094 PM |
244 | if (!arm_feature(env, ARM_FEATURE_M)) { |
245 | set_feature(env, ARM_FEATURE_V6K); | |
246 | } else { | |
247 | set_feature(env, ARM_FEATURE_V6); | |
248 | } | |
249 | } | |
250 | if (arm_feature(env, ARM_FEATURE_V6K)) { | |
251 | set_feature(env, ARM_FEATURE_V6); | |
252 | set_feature(env, ARM_FEATURE_MVFR); | |
253 | } | |
254 | if (arm_feature(env, ARM_FEATURE_V6)) { | |
255 | set_feature(env, ARM_FEATURE_V5); | |
256 | if (!arm_feature(env, ARM_FEATURE_M)) { | |
257 | set_feature(env, ARM_FEATURE_AUXCR); | |
258 | } | |
259 | } | |
260 | if (arm_feature(env, ARM_FEATURE_V5)) { | |
261 | set_feature(env, ARM_FEATURE_V4T); | |
262 | } | |
263 | if (arm_feature(env, ARM_FEATURE_M)) { | |
264 | set_feature(env, ARM_FEATURE_THUMB_DIV); | |
265 | } | |
266 | if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { | |
267 | set_feature(env, ARM_FEATURE_THUMB_DIV); | |
268 | } | |
269 | if (arm_feature(env, ARM_FEATURE_VFP4)) { | |
270 | set_feature(env, ARM_FEATURE_VFP3); | |
271 | } | |
272 | if (arm_feature(env, ARM_FEATURE_VFP3)) { | |
273 | set_feature(env, ARM_FEATURE_VFP); | |
274 | } | |
de9b05b8 | 275 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
bdcc150d | 276 | set_feature(env, ARM_FEATURE_V7MP); |
de9b05b8 PM |
277 | set_feature(env, ARM_FEATURE_PXN); |
278 | } | |
2ceb98c0 PM |
279 | |
280 | register_cp_regs_for_features(cpu); | |
14969266 AF |
281 | arm_cpu_register_gdb_regs_for_features(cpu); |
282 | ||
721fae12 PM |
283 | init_cpreg_list(cpu); |
284 | ||
14a10fc3 AF |
285 | cpu_reset(cs); |
286 | qemu_init_vcpu(cs); | |
14969266 AF |
287 | |
288 | acc->parent_realize(dev, errp); | |
581be094 PM |
289 | } |
290 | ||
777dc784 PM |
291 | /* CPU models */ |
292 | ||
5900d6b2 AF |
293 | static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) |
294 | { | |
295 | ObjectClass *oc; | |
51492fd1 | 296 | char *typename; |
5900d6b2 AF |
297 | |
298 | if (!cpu_model) { | |
299 | return NULL; | |
300 | } | |
301 | ||
51492fd1 AF |
302 | typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpu_model); |
303 | oc = object_class_by_name(typename); | |
304 | g_free(typename); | |
245fb54d AF |
305 | if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || |
306 | object_class_is_abstract(oc)) { | |
5900d6b2 AF |
307 | return NULL; |
308 | } | |
309 | return oc; | |
310 | } | |
311 | ||
777dc784 PM |
312 | static void arm926_initfn(Object *obj) |
313 | { | |
314 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
315 | set_feature(&cpu->env, ARM_FEATURE_V5); |
316 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
c4804214 PM |
317 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
318 | set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); | |
b2d06f96 | 319 | cpu->midr = 0x41069265; |
325b3cef | 320 | cpu->reset_fpsid = 0x41011090; |
64e1671f | 321 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 322 | cpu->reset_sctlr = 0x00090078; |
777dc784 PM |
323 | } |
324 | ||
325 | static void arm946_initfn(Object *obj) | |
326 | { | |
327 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
328 | set_feature(&cpu->env, ARM_FEATURE_V5); |
329 | set_feature(&cpu->env, ARM_FEATURE_MPU); | |
c4804214 | 330 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 331 | cpu->midr = 0x41059461; |
64e1671f | 332 | cpu->ctr = 0x0f004006; |
0ca7e01c | 333 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
334 | } |
335 | ||
336 | static void arm1026_initfn(Object *obj) | |
337 | { | |
338 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
339 | set_feature(&cpu->env, ARM_FEATURE_V5); |
340 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
341 | set_feature(&cpu->env, ARM_FEATURE_AUXCR); | |
c4804214 PM |
342 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
343 | set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); | |
b2d06f96 | 344 | cpu->midr = 0x4106a262; |
325b3cef | 345 | cpu->reset_fpsid = 0x410110a0; |
64e1671f | 346 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 347 | cpu->reset_sctlr = 0x00090078; |
2771db27 | 348 | cpu->reset_auxcr = 1; |
06d76f31 PM |
349 | { |
350 | /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ | |
351 | ARMCPRegInfo ifar = { | |
352 | .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, | |
353 | .access = PL1_RW, | |
354 | .fieldoffset = offsetof(CPUARMState, cp15.c6_insn), | |
355 | .resetvalue = 0 | |
356 | }; | |
357 | define_one_arm_cp_reg(cpu, &ifar); | |
358 | } | |
777dc784 PM |
359 | } |
360 | ||
361 | static void arm1136_r2_initfn(Object *obj) | |
362 | { | |
363 | ARMCPU *cpu = ARM_CPU(obj); | |
2e4d7e3e PM |
364 | /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an |
365 | * older core than plain "arm1136". In particular this does not | |
366 | * have the v6K features. | |
367 | * These ID register values are correct for 1136 but may be wrong | |
368 | * for 1136_r2 (in particular r0p2 does not actually implement most | |
369 | * of the ID registers). | |
370 | */ | |
581be094 PM |
371 | set_feature(&cpu->env, ARM_FEATURE_V6); |
372 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
c4804214 PM |
373 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
374 | set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); | |
375 | set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); | |
b2d06f96 | 376 | cpu->midr = 0x4107b362; |
325b3cef | 377 | cpu->reset_fpsid = 0x410120b4; |
bd35c355 PM |
378 | cpu->mvfr0 = 0x11111111; |
379 | cpu->mvfr1 = 0x00000000; | |
64e1671f | 380 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 381 | cpu->reset_sctlr = 0x00050078; |
2e4d7e3e PM |
382 | cpu->id_pfr0 = 0x111; |
383 | cpu->id_pfr1 = 0x1; | |
384 | cpu->id_dfr0 = 0x2; | |
385 | cpu->id_afr0 = 0x3; | |
386 | cpu->id_mmfr0 = 0x01130003; | |
387 | cpu->id_mmfr1 = 0x10030302; | |
388 | cpu->id_mmfr2 = 0x01222110; | |
389 | cpu->id_isar0 = 0x00140011; | |
390 | cpu->id_isar1 = 0x12002111; | |
391 | cpu->id_isar2 = 0x11231111; | |
392 | cpu->id_isar3 = 0x01102131; | |
393 | cpu->id_isar4 = 0x141; | |
2771db27 | 394 | cpu->reset_auxcr = 7; |
777dc784 PM |
395 | } |
396 | ||
397 | static void arm1136_initfn(Object *obj) | |
398 | { | |
399 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
400 | set_feature(&cpu->env, ARM_FEATURE_V6K); |
401 | set_feature(&cpu->env, ARM_FEATURE_V6); | |
402 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
c4804214 PM |
403 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
404 | set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); | |
405 | set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); | |
b2d06f96 | 406 | cpu->midr = 0x4117b363; |
325b3cef | 407 | cpu->reset_fpsid = 0x410120b4; |
bd35c355 PM |
408 | cpu->mvfr0 = 0x11111111; |
409 | cpu->mvfr1 = 0x00000000; | |
64e1671f | 410 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 411 | cpu->reset_sctlr = 0x00050078; |
2e4d7e3e PM |
412 | cpu->id_pfr0 = 0x111; |
413 | cpu->id_pfr1 = 0x1; | |
414 | cpu->id_dfr0 = 0x2; | |
415 | cpu->id_afr0 = 0x3; | |
416 | cpu->id_mmfr0 = 0x01130003; | |
417 | cpu->id_mmfr1 = 0x10030302; | |
418 | cpu->id_mmfr2 = 0x01222110; | |
419 | cpu->id_isar0 = 0x00140011; | |
420 | cpu->id_isar1 = 0x12002111; | |
421 | cpu->id_isar2 = 0x11231111; | |
422 | cpu->id_isar3 = 0x01102131; | |
423 | cpu->id_isar4 = 0x141; | |
2771db27 | 424 | cpu->reset_auxcr = 7; |
777dc784 PM |
425 | } |
426 | ||
427 | static void arm1176_initfn(Object *obj) | |
428 | { | |
429 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
430 | set_feature(&cpu->env, ARM_FEATURE_V6K); |
431 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
432 | set_feature(&cpu->env, ARM_FEATURE_VAPA); | |
c4804214 PM |
433 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
434 | set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); | |
435 | set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); | |
b2d06f96 | 436 | cpu->midr = 0x410fb767; |
325b3cef | 437 | cpu->reset_fpsid = 0x410120b5; |
bd35c355 PM |
438 | cpu->mvfr0 = 0x11111111; |
439 | cpu->mvfr1 = 0x00000000; | |
64e1671f | 440 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 441 | cpu->reset_sctlr = 0x00050078; |
2e4d7e3e PM |
442 | cpu->id_pfr0 = 0x111; |
443 | cpu->id_pfr1 = 0x11; | |
444 | cpu->id_dfr0 = 0x33; | |
445 | cpu->id_afr0 = 0; | |
446 | cpu->id_mmfr0 = 0x01130003; | |
447 | cpu->id_mmfr1 = 0x10030302; | |
448 | cpu->id_mmfr2 = 0x01222100; | |
449 | cpu->id_isar0 = 0x0140011; | |
450 | cpu->id_isar1 = 0x12002111; | |
451 | cpu->id_isar2 = 0x11231121; | |
452 | cpu->id_isar3 = 0x01102131; | |
453 | cpu->id_isar4 = 0x01141; | |
2771db27 | 454 | cpu->reset_auxcr = 7; |
777dc784 PM |
455 | } |
456 | ||
457 | static void arm11mpcore_initfn(Object *obj) | |
458 | { | |
459 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
460 | set_feature(&cpu->env, ARM_FEATURE_V6K); |
461 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
462 | set_feature(&cpu->env, ARM_FEATURE_VAPA); | |
81bdde9d | 463 | set_feature(&cpu->env, ARM_FEATURE_MPIDR); |
c4804214 | 464 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 465 | cpu->midr = 0x410fb022; |
325b3cef | 466 | cpu->reset_fpsid = 0x410120b4; |
bd35c355 PM |
467 | cpu->mvfr0 = 0x11111111; |
468 | cpu->mvfr1 = 0x00000000; | |
200bf596 | 469 | cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ |
2e4d7e3e PM |
470 | cpu->id_pfr0 = 0x111; |
471 | cpu->id_pfr1 = 0x1; | |
472 | cpu->id_dfr0 = 0; | |
473 | cpu->id_afr0 = 0x2; | |
474 | cpu->id_mmfr0 = 0x01100103; | |
475 | cpu->id_mmfr1 = 0x10020302; | |
476 | cpu->id_mmfr2 = 0x01222000; | |
477 | cpu->id_isar0 = 0x00100011; | |
478 | cpu->id_isar1 = 0x12002111; | |
479 | cpu->id_isar2 = 0x11221011; | |
480 | cpu->id_isar3 = 0x01102131; | |
481 | cpu->id_isar4 = 0x141; | |
2771db27 | 482 | cpu->reset_auxcr = 1; |
777dc784 PM |
483 | } |
484 | ||
485 | static void cortex_m3_initfn(Object *obj) | |
486 | { | |
487 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
488 | set_feature(&cpu->env, ARM_FEATURE_V7); |
489 | set_feature(&cpu->env, ARM_FEATURE_M); | |
b2d06f96 | 490 | cpu->midr = 0x410fc231; |
777dc784 PM |
491 | } |
492 | ||
e6f010cc AF |
493 | static void arm_v7m_class_init(ObjectClass *oc, void *data) |
494 | { | |
495 | #ifndef CONFIG_USER_ONLY | |
496 | CPUClass *cc = CPU_CLASS(oc); | |
497 | ||
498 | cc->do_interrupt = arm_v7m_cpu_do_interrupt; | |
499 | #endif | |
500 | } | |
501 | ||
34f90529 PM |
502 | static const ARMCPRegInfo cortexa8_cp_reginfo[] = { |
503 | { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, | |
504 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
505 | { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, | |
506 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
507 | REGINFO_SENTINEL | |
508 | }; | |
509 | ||
777dc784 PM |
510 | static void cortex_a8_initfn(Object *obj) |
511 | { | |
512 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
513 | set_feature(&cpu->env, ARM_FEATURE_V7); |
514 | set_feature(&cpu->env, ARM_FEATURE_VFP3); | |
515 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
516 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
c4804214 | 517 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 518 | cpu->midr = 0x410fc080; |
325b3cef | 519 | cpu->reset_fpsid = 0x410330c0; |
bd35c355 PM |
520 | cpu->mvfr0 = 0x11110222; |
521 | cpu->mvfr1 = 0x00011100; | |
64e1671f | 522 | cpu->ctr = 0x82048004; |
0ca7e01c | 523 | cpu->reset_sctlr = 0x00c50078; |
2e4d7e3e PM |
524 | cpu->id_pfr0 = 0x1031; |
525 | cpu->id_pfr1 = 0x11; | |
526 | cpu->id_dfr0 = 0x400; | |
527 | cpu->id_afr0 = 0; | |
528 | cpu->id_mmfr0 = 0x31100003; | |
529 | cpu->id_mmfr1 = 0x20000000; | |
530 | cpu->id_mmfr2 = 0x01202000; | |
531 | cpu->id_mmfr3 = 0x11; | |
532 | cpu->id_isar0 = 0x00101111; | |
533 | cpu->id_isar1 = 0x12112111; | |
534 | cpu->id_isar2 = 0x21232031; | |
535 | cpu->id_isar3 = 0x11112131; | |
536 | cpu->id_isar4 = 0x00111142; | |
85df3786 PM |
537 | cpu->clidr = (1 << 27) | (2 << 24) | 3; |
538 | cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ | |
539 | cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ | |
540 | cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ | |
2771db27 | 541 | cpu->reset_auxcr = 2; |
34f90529 | 542 | define_arm_cp_regs(cpu, cortexa8_cp_reginfo); |
777dc784 PM |
543 | } |
544 | ||
1047b9d7 PM |
545 | static const ARMCPRegInfo cortexa9_cp_reginfo[] = { |
546 | /* power_control should be set to maximum latency. Again, | |
547 | * default to 0 and set by private hook | |
548 | */ | |
549 | { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, | |
550 | .access = PL1_RW, .resetvalue = 0, | |
551 | .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, | |
552 | { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, | |
553 | .access = PL1_RW, .resetvalue = 0, | |
554 | .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, | |
555 | { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, | |
556 | .access = PL1_RW, .resetvalue = 0, | |
557 | .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, | |
558 | { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, | |
559 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
560 | /* TLB lockdown control */ | |
561 | { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, | |
562 | .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, | |
563 | { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, | |
564 | .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, | |
565 | { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, | |
566 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
567 | { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, | |
568 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
569 | { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, | |
570 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
571 | REGINFO_SENTINEL | |
572 | }; | |
573 | ||
777dc784 PM |
574 | static void cortex_a9_initfn(Object *obj) |
575 | { | |
576 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
577 | set_feature(&cpu->env, ARM_FEATURE_V7); |
578 | set_feature(&cpu->env, ARM_FEATURE_VFP3); | |
579 | set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); | |
580 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
581 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
582 | /* Note that A9 supports the MP extensions even for | |
583 | * A9UP and single-core A9MP (which are both different | |
584 | * and valid configurations; we don't model A9UP). | |
585 | */ | |
586 | set_feature(&cpu->env, ARM_FEATURE_V7MP); | |
b2d06f96 | 587 | cpu->midr = 0x410fc090; |
325b3cef | 588 | cpu->reset_fpsid = 0x41033090; |
bd35c355 PM |
589 | cpu->mvfr0 = 0x11110222; |
590 | cpu->mvfr1 = 0x01111111; | |
64e1671f | 591 | cpu->ctr = 0x80038003; |
0ca7e01c | 592 | cpu->reset_sctlr = 0x00c50078; |
2e4d7e3e PM |
593 | cpu->id_pfr0 = 0x1031; |
594 | cpu->id_pfr1 = 0x11; | |
595 | cpu->id_dfr0 = 0x000; | |
596 | cpu->id_afr0 = 0; | |
597 | cpu->id_mmfr0 = 0x00100103; | |
598 | cpu->id_mmfr1 = 0x20000000; | |
599 | cpu->id_mmfr2 = 0x01230000; | |
600 | cpu->id_mmfr3 = 0x00002111; | |
601 | cpu->id_isar0 = 0x00101111; | |
602 | cpu->id_isar1 = 0x13112111; | |
603 | cpu->id_isar2 = 0x21232041; | |
604 | cpu->id_isar3 = 0x11112131; | |
605 | cpu->id_isar4 = 0x00111142; | |
85df3786 PM |
606 | cpu->clidr = (1 << 27) | (1 << 24) | 3; |
607 | cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */ | |
608 | cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */ | |
1047b9d7 PM |
609 | { |
610 | ARMCPRegInfo cbar = { | |
611 | .name = "CBAR", .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, | |
612 | .opc2 = 0, .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar, | |
613 | .fieldoffset = offsetof(CPUARMState, cp15.c15_config_base_address) | |
614 | }; | |
615 | define_one_arm_cp_reg(cpu, &cbar); | |
616 | define_arm_cp_regs(cpu, cortexa9_cp_reginfo); | |
617 | } | |
777dc784 PM |
618 | } |
619 | ||
34f90529 PM |
620 | #ifndef CONFIG_USER_ONLY |
621 | static int a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri, | |
622 | uint64_t *value) | |
623 | { | |
624 | /* Linux wants the number of processors from here. | |
625 | * Might as well set the interrupt-controller bit too. | |
626 | */ | |
627 | *value = ((smp_cpus - 1) << 24) | (1 << 23); | |
628 | return 0; | |
629 | } | |
630 | #endif | |
631 | ||
632 | static const ARMCPRegInfo cortexa15_cp_reginfo[] = { | |
633 | #ifndef CONFIG_USER_ONLY | |
634 | { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, | |
635 | .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, | |
636 | .writefn = arm_cp_write_ignore, }, | |
637 | #endif | |
638 | { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, | |
639 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
640 | REGINFO_SENTINEL | |
641 | }; | |
642 | ||
777dc784 PM |
643 | static void cortex_a15_initfn(Object *obj) |
644 | { | |
645 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
646 | set_feature(&cpu->env, ARM_FEATURE_V7); |
647 | set_feature(&cpu->env, ARM_FEATURE_VFP4); | |
648 | set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); | |
649 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
650 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
651 | set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); | |
581be094 | 652 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); |
c4804214 | 653 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
de9b05b8 | 654 | set_feature(&cpu->env, ARM_FEATURE_LPAE); |
b2d06f96 | 655 | cpu->midr = 0x412fc0f1; |
325b3cef | 656 | cpu->reset_fpsid = 0x410430f0; |
bd35c355 PM |
657 | cpu->mvfr0 = 0x10110222; |
658 | cpu->mvfr1 = 0x11111111; | |
64e1671f | 659 | cpu->ctr = 0x8444c004; |
0ca7e01c | 660 | cpu->reset_sctlr = 0x00c50078; |
2e4d7e3e PM |
661 | cpu->id_pfr0 = 0x00001131; |
662 | cpu->id_pfr1 = 0x00011011; | |
663 | cpu->id_dfr0 = 0x02010555; | |
664 | cpu->id_afr0 = 0x00000000; | |
665 | cpu->id_mmfr0 = 0x10201105; | |
666 | cpu->id_mmfr1 = 0x20000000; | |
667 | cpu->id_mmfr2 = 0x01240000; | |
668 | cpu->id_mmfr3 = 0x02102211; | |
669 | cpu->id_isar0 = 0x02101110; | |
670 | cpu->id_isar1 = 0x13112111; | |
671 | cpu->id_isar2 = 0x21232041; | |
672 | cpu->id_isar3 = 0x11112131; | |
673 | cpu->id_isar4 = 0x10011142; | |
85df3786 PM |
674 | cpu->clidr = 0x0a200023; |
675 | cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ | |
676 | cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ | |
677 | cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ | |
34f90529 | 678 | define_arm_cp_regs(cpu, cortexa15_cp_reginfo); |
777dc784 PM |
679 | } |
680 | ||
681 | static void ti925t_initfn(Object *obj) | |
682 | { | |
683 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
684 | set_feature(&cpu->env, ARM_FEATURE_V4T); |
685 | set_feature(&cpu->env, ARM_FEATURE_OMAPCP); | |
777dc784 | 686 | cpu->midr = ARM_CPUID_TI925T; |
64e1671f | 687 | cpu->ctr = 0x5109149; |
0ca7e01c | 688 | cpu->reset_sctlr = 0x00000070; |
777dc784 PM |
689 | } |
690 | ||
691 | static void sa1100_initfn(Object *obj) | |
692 | { | |
693 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 | 694 | set_feature(&cpu->env, ARM_FEATURE_STRONGARM); |
c4804214 | 695 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 696 | cpu->midr = 0x4401A11B; |
0ca7e01c | 697 | cpu->reset_sctlr = 0x00000070; |
777dc784 PM |
698 | } |
699 | ||
700 | static void sa1110_initfn(Object *obj) | |
701 | { | |
702 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 | 703 | set_feature(&cpu->env, ARM_FEATURE_STRONGARM); |
c4804214 | 704 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 705 | cpu->midr = 0x6901B119; |
0ca7e01c | 706 | cpu->reset_sctlr = 0x00000070; |
777dc784 PM |
707 | } |
708 | ||
709 | static void pxa250_initfn(Object *obj) | |
710 | { | |
711 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
712 | set_feature(&cpu->env, ARM_FEATURE_V5); |
713 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 714 | cpu->midr = 0x69052100; |
64e1671f | 715 | cpu->ctr = 0xd172172; |
0ca7e01c | 716 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
717 | } |
718 | ||
719 | static void pxa255_initfn(Object *obj) | |
720 | { | |
721 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
722 | set_feature(&cpu->env, ARM_FEATURE_V5); |
723 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 724 | cpu->midr = 0x69052d00; |
64e1671f | 725 | cpu->ctr = 0xd172172; |
0ca7e01c | 726 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
727 | } |
728 | ||
729 | static void pxa260_initfn(Object *obj) | |
730 | { | |
731 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
732 | set_feature(&cpu->env, ARM_FEATURE_V5); |
733 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 734 | cpu->midr = 0x69052903; |
64e1671f | 735 | cpu->ctr = 0xd172172; |
0ca7e01c | 736 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
737 | } |
738 | ||
739 | static void pxa261_initfn(Object *obj) | |
740 | { | |
741 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
742 | set_feature(&cpu->env, ARM_FEATURE_V5); |
743 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 744 | cpu->midr = 0x69052d05; |
64e1671f | 745 | cpu->ctr = 0xd172172; |
0ca7e01c | 746 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
747 | } |
748 | ||
749 | static void pxa262_initfn(Object *obj) | |
750 | { | |
751 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
752 | set_feature(&cpu->env, ARM_FEATURE_V5); |
753 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 754 | cpu->midr = 0x69052d06; |
64e1671f | 755 | cpu->ctr = 0xd172172; |
0ca7e01c | 756 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
757 | } |
758 | ||
759 | static void pxa270a0_initfn(Object *obj) | |
760 | { | |
761 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
762 | set_feature(&cpu->env, ARM_FEATURE_V5); |
763 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
764 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 765 | cpu->midr = 0x69054110; |
64e1671f | 766 | cpu->ctr = 0xd172172; |
0ca7e01c | 767 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
768 | } |
769 | ||
770 | static void pxa270a1_initfn(Object *obj) | |
771 | { | |
772 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
773 | set_feature(&cpu->env, ARM_FEATURE_V5); |
774 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
775 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 776 | cpu->midr = 0x69054111; |
64e1671f | 777 | cpu->ctr = 0xd172172; |
0ca7e01c | 778 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
779 | } |
780 | ||
781 | static void pxa270b0_initfn(Object *obj) | |
782 | { | |
783 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
784 | set_feature(&cpu->env, ARM_FEATURE_V5); |
785 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
786 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 787 | cpu->midr = 0x69054112; |
64e1671f | 788 | cpu->ctr = 0xd172172; |
0ca7e01c | 789 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
790 | } |
791 | ||
792 | static void pxa270b1_initfn(Object *obj) | |
793 | { | |
794 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
795 | set_feature(&cpu->env, ARM_FEATURE_V5); |
796 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
797 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 798 | cpu->midr = 0x69054113; |
64e1671f | 799 | cpu->ctr = 0xd172172; |
0ca7e01c | 800 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
801 | } |
802 | ||
803 | static void pxa270c0_initfn(Object *obj) | |
804 | { | |
805 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
806 | set_feature(&cpu->env, ARM_FEATURE_V5); |
807 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
808 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 809 | cpu->midr = 0x69054114; |
64e1671f | 810 | cpu->ctr = 0xd172172; |
0ca7e01c | 811 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
812 | } |
813 | ||
814 | static void pxa270c5_initfn(Object *obj) | |
815 | { | |
816 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
817 | set_feature(&cpu->env, ARM_FEATURE_V5); |
818 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
819 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 820 | cpu->midr = 0x69054117; |
64e1671f | 821 | cpu->ctr = 0xd172172; |
0ca7e01c | 822 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
823 | } |
824 | ||
825 | static void arm_any_initfn(Object *obj) | |
826 | { | |
827 | ARMCPU *cpu = ARM_CPU(obj); | |
81e69fb0 | 828 | set_feature(&cpu->env, ARM_FEATURE_V8); |
581be094 PM |
829 | set_feature(&cpu->env, ARM_FEATURE_VFP4); |
830 | set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); | |
831 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
832 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
833 | set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); | |
834 | set_feature(&cpu->env, ARM_FEATURE_V7MP); | |
b2d06f96 | 835 | cpu->midr = 0xffffffff; |
777dc784 PM |
836 | } |
837 | ||
838 | typedef struct ARMCPUInfo { | |
839 | const char *name; | |
840 | void (*initfn)(Object *obj); | |
e6f010cc | 841 | void (*class_init)(ObjectClass *oc, void *data); |
777dc784 PM |
842 | } ARMCPUInfo; |
843 | ||
844 | static const ARMCPUInfo arm_cpus[] = { | |
845 | { .name = "arm926", .initfn = arm926_initfn }, | |
846 | { .name = "arm946", .initfn = arm946_initfn }, | |
847 | { .name = "arm1026", .initfn = arm1026_initfn }, | |
848 | /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an | |
849 | * older core than plain "arm1136". In particular this does not | |
850 | * have the v6K features. | |
851 | */ | |
852 | { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, | |
853 | { .name = "arm1136", .initfn = arm1136_initfn }, | |
854 | { .name = "arm1176", .initfn = arm1176_initfn }, | |
855 | { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, | |
e6f010cc AF |
856 | { .name = "cortex-m3", .initfn = cortex_m3_initfn, |
857 | .class_init = arm_v7m_class_init }, | |
777dc784 PM |
858 | { .name = "cortex-a8", .initfn = cortex_a8_initfn }, |
859 | { .name = "cortex-a9", .initfn = cortex_a9_initfn }, | |
860 | { .name = "cortex-a15", .initfn = cortex_a15_initfn }, | |
861 | { .name = "ti925t", .initfn = ti925t_initfn }, | |
862 | { .name = "sa1100", .initfn = sa1100_initfn }, | |
863 | { .name = "sa1110", .initfn = sa1110_initfn }, | |
864 | { .name = "pxa250", .initfn = pxa250_initfn }, | |
865 | { .name = "pxa255", .initfn = pxa255_initfn }, | |
866 | { .name = "pxa260", .initfn = pxa260_initfn }, | |
867 | { .name = "pxa261", .initfn = pxa261_initfn }, | |
868 | { .name = "pxa262", .initfn = pxa262_initfn }, | |
869 | /* "pxa270" is an alias for "pxa270-a0" */ | |
870 | { .name = "pxa270", .initfn = pxa270a0_initfn }, | |
871 | { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, | |
872 | { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, | |
873 | { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, | |
874 | { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, | |
875 | { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, | |
876 | { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, | |
877 | { .name = "any", .initfn = arm_any_initfn }, | |
878 | }; | |
879 | ||
dec9c2d4 AF |
880 | static void arm_cpu_class_init(ObjectClass *oc, void *data) |
881 | { | |
882 | ARMCPUClass *acc = ARM_CPU_CLASS(oc); | |
883 | CPUClass *cc = CPU_CLASS(acc); | |
14969266 AF |
884 | DeviceClass *dc = DEVICE_CLASS(oc); |
885 | ||
886 | acc->parent_realize = dc->realize; | |
887 | dc->realize = arm_cpu_realizefn; | |
dec9c2d4 AF |
888 | |
889 | acc->parent_reset = cc->reset; | |
890 | cc->reset = arm_cpu_reset; | |
5900d6b2 AF |
891 | |
892 | cc->class_by_name = arm_cpu_class_by_name; | |
97a8ea5a | 893 | cc->do_interrupt = arm_cpu_do_interrupt; |
878096ee | 894 | cc->dump_state = arm_cpu_dump_state; |
f45748f1 | 895 | cc->set_pc = arm_cpu_set_pc; |
5b50e790 AF |
896 | cc->gdb_read_register = arm_cpu_gdb_read_register; |
897 | cc->gdb_write_register = arm_cpu_gdb_write_register; | |
00b941e5 AF |
898 | #ifndef CONFIG_USER_ONLY |
899 | cc->get_phys_page_debug = arm_cpu_get_phys_page_debug; | |
900 | cc->vmsd = &vmstate_arm_cpu; | |
901 | #endif | |
a0e372f0 | 902 | cc->gdb_num_core_regs = 26; |
5b24c641 | 903 | cc->gdb_core_xml_file = "arm-core.xml"; |
dec9c2d4 AF |
904 | } |
905 | ||
777dc784 PM |
906 | static void cpu_register(const ARMCPUInfo *info) |
907 | { | |
908 | TypeInfo type_info = { | |
777dc784 PM |
909 | .parent = TYPE_ARM_CPU, |
910 | .instance_size = sizeof(ARMCPU), | |
911 | .instance_init = info->initfn, | |
912 | .class_size = sizeof(ARMCPUClass), | |
e6f010cc | 913 | .class_init = info->class_init, |
777dc784 PM |
914 | }; |
915 | ||
51492fd1 | 916 | type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); |
918fd083 | 917 | type_register(&type_info); |
51492fd1 | 918 | g_free((void *)type_info.name); |
777dc784 PM |
919 | } |
920 | ||
dec9c2d4 AF |
921 | static const TypeInfo arm_cpu_type_info = { |
922 | .name = TYPE_ARM_CPU, | |
923 | .parent = TYPE_CPU, | |
924 | .instance_size = sizeof(ARMCPU), | |
777dc784 | 925 | .instance_init = arm_cpu_initfn, |
4b6a83fb | 926 | .instance_finalize = arm_cpu_finalizefn, |
777dc784 | 927 | .abstract = true, |
dec9c2d4 AF |
928 | .class_size = sizeof(ARMCPUClass), |
929 | .class_init = arm_cpu_class_init, | |
930 | }; | |
931 | ||
932 | static void arm_cpu_register_types(void) | |
933 | { | |
777dc784 PM |
934 | int i; |
935 | ||
dec9c2d4 | 936 | type_register_static(&arm_cpu_type_info); |
777dc784 PM |
937 | for (i = 0; i < ARRAY_SIZE(arm_cpus); i++) { |
938 | cpu_register(&arm_cpus[i]); | |
939 | } | |
dec9c2d4 AF |
940 | } |
941 | ||
942 | type_init(arm_cpu_register_types) |