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target-arm: convert cp15 crn=7 registers
[mirror_qemu.git] / target-arm / cpu.c
CommitLineData
dec9c2d4
AF		 1/*
2 * QEMU ARM CPU
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 */
20
778c3a06 21#include "cpu.h"
dec9c2d4 22#include "qemu-common.h"
3c30dd5a
PM		 23#if !defined(CONFIG_USER_ONLY)
24#include "hw/loader.h"
25#endif
dec9c2d4 26
4b6a83fb
PM		 27static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
28{
29 /* Reset a single ARMCPRegInfo register */
30 ARMCPRegInfo *ri = value;
31 ARMCPU *cpu = opaque;
32
33 if (ri->type & ARM_CP_SPECIAL) {
34 return;
35 }
36
37 if (ri->resetfn) {
38 ri->resetfn(&cpu->env, ri);
39 return;
40 }
41
42 /* A zero offset is never possible as it would be regs[0]
43 * so we use it to indicate that reset is being handled elsewhere.
44 * This is basically only used for fields in non-core coprocessors
45 * (like the pxa2xx ones).
46 */
47 if (!ri->fieldoffset) {
48 return;
49 }
50
51 if (ri->type & ARM_CP_64BIT) {
52 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
53 } else {
54 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
55 }
56}
57
dec9c2d4
AF		 58/* CPUClass::reset() */
59static void arm_cpu_reset(CPUState *s)
60{
61 ARMCPU *cpu = ARM_CPU(s);
62 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
3c30dd5a 63 CPUARMState *env = &cpu->env;
3c30dd5a
PM		 64
65 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
66 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
67 log_cpu_state(env, 0);
68 }
dec9c2d4
AF		 69
70 acc->parent_reset(s);
71
3c30dd5a 72 memset(env, 0, offsetof(CPUARMState, breakpoints));
4b6a83fb 73 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
3c30dd5a
PM		 74 env->cp15.c0_cpuid = cpu->midr;
75 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
76 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
77 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
78 env->cp15.c0_cachetype = cpu->ctr;
79 env->cp15.c1_sys = cpu->reset_sctlr;
80 env->cp15.c0_c1[0] = cpu->id_pfr0;
81 env->cp15.c0_c1[1] = cpu->id_pfr1;
82 env->cp15.c0_c1[2] = cpu->id_dfr0;
83 env->cp15.c0_c1[3] = cpu->id_afr0;
84 env->cp15.c0_c1[4] = cpu->id_mmfr0;
85 env->cp15.c0_c1[5] = cpu->id_mmfr1;
86 env->cp15.c0_c1[6] = cpu->id_mmfr2;
87 env->cp15.c0_c1[7] = cpu->id_mmfr3;
88 env->cp15.c0_c2[0] = cpu->id_isar0;
89 env->cp15.c0_c2[1] = cpu->id_isar1;
90 env->cp15.c0_c2[2] = cpu->id_isar2;
91 env->cp15.c0_c2[3] = cpu->id_isar3;
92 env->cp15.c0_c2[4] = cpu->id_isar4;
93 env->cp15.c0_c2[5] = cpu->id_isar5;
3c30dd5a
PM		 94 env->cp15.c0_clid = cpu->clidr;
95 memcpy(env->cp15.c0_ccsid, cpu->ccsidr, ARRAY_SIZE(cpu->ccsidr));
96
97 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
98 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
99 }
100
101#if defined(CONFIG_USER_ONLY)
102 env->uncached_cpsr = ARM_CPU_MODE_USR;
103 /* For user mode we must enable access to coprocessors */
104 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
105 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
106 env->cp15.c15_cpar = 3;
107 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
108 env->cp15.c15_cpar = 1;
109 }
110#else
111 /* SVC mode with interrupts disabled. */
112 env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
113 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
114 clear at reset. Initial SP and PC are loaded from ROM. */
115 if (IS_M(env)) {
116 uint32_t pc;
117 uint8_t *rom;
118 env->uncached_cpsr &= ~CPSR_I;
119 rom = rom_ptr(0);
120 if (rom) {
121 /* We should really use ldl_phys here, in case the guest
122 modified flash and reset itself. However images
123 loaded via -kernel have not been copied yet, so load the
124 values directly from there. */
125 env->regs[13] = ldl_p(rom);
126 pc = ldl_p(rom + 4);
127 env->thumb = pc & 1;
128 env->regs[15] = pc & ~1;
129 }
130 }
131 env->vfp.xregs[ARM_VFP_FPEXC] = 0;
3c30dd5a
PM		 132#endif
133 set_flush_to_zero(1, &env->vfp.standard_fp_status);
134 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
135 set_default_nan_mode(1, &env->vfp.standard_fp_status);
136 set_float_detect_tininess(float_tininess_before_rounding,
137 &env->vfp.fp_status);
138 set_float_detect_tininess(float_tininess_before_rounding,
139 &env->vfp.standard_fp_status);
140 tlb_flush(env, 1);
141 /* Reset is a state change for some CPUARMState fields which we
142 * bake assumptions about into translated code, so we need to
143 * tb_flush().
144 */
145 tb_flush(env);
dec9c2d4
AF		 146}
147
581be094
PM		 148static inline void set_feature(CPUARMState *env, int feature)
149{
150 env->features |= 1u << feature;
151}
152
777dc784
PM		 153static void arm_cpu_initfn(Object *obj)
154{
155 ARMCPU *cpu = ARM_CPU(obj);
156
157 cpu_exec_init(&cpu->env);
4b6a83fb
PM		 158 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
159 g_free, g_free);
160}
161
162static void arm_cpu_finalizefn(Object *obj)
163{
164 ARMCPU *cpu = ARM_CPU(obj);
165 g_hash_table_destroy(cpu->cp_regs);
777dc784
PM		 166}
167
581be094
PM		 168void arm_cpu_realize(ARMCPU *cpu)
169{
170 /* This function is called by cpu_arm_init() because it
171 * needs to do common actions based on feature bits, etc
172 * that have been set by the subclass init functions.
173 * When we have QOM realize support it should become
174 * a true realize function instead.
175 */
176 CPUARMState *env = &cpu->env;
177 /* Some features automatically imply others: */
178 if (arm_feature(env, ARM_FEATURE_V7)) {
179 set_feature(env, ARM_FEATURE_VAPA);
180 set_feature(env, ARM_FEATURE_THUMB2);
181 if (!arm_feature(env, ARM_FEATURE_M)) {
182 set_feature(env, ARM_FEATURE_V6K);
183 } else {
184 set_feature(env, ARM_FEATURE_V6);
185 }
186 }
187 if (arm_feature(env, ARM_FEATURE_V6K)) {
188 set_feature(env, ARM_FEATURE_V6);
189 set_feature(env, ARM_FEATURE_MVFR);
190 }
191 if (arm_feature(env, ARM_FEATURE_V6)) {
192 set_feature(env, ARM_FEATURE_V5);
193 if (!arm_feature(env, ARM_FEATURE_M)) {
194 set_feature(env, ARM_FEATURE_AUXCR);
195 }
196 }
197 if (arm_feature(env, ARM_FEATURE_V5)) {
198 set_feature(env, ARM_FEATURE_V4T);
199 }
200 if (arm_feature(env, ARM_FEATURE_M)) {
201 set_feature(env, ARM_FEATURE_THUMB_DIV);
202 }
203 if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
204 set_feature(env, ARM_FEATURE_THUMB_DIV);
205 }
206 if (arm_feature(env, ARM_FEATURE_VFP4)) {
207 set_feature(env, ARM_FEATURE_VFP3);
208 }
209 if (arm_feature(env, ARM_FEATURE_VFP3)) {
210 set_feature(env, ARM_FEATURE_VFP);
211 }
2ceb98c0
PM		 212
213 register_cp_regs_for_features(cpu);
581be094
PM		 214}
215
777dc784
PM		 216/* CPU models */
217
218static void arm926_initfn(Object *obj)
219{
220 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 221 set_feature(&cpu->env, ARM_FEATURE_V5);
222 set_feature(&cpu->env, ARM_FEATURE_VFP);
c4804214
PM		 223 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
224 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
777dc784 225 cpu->midr = ARM_CPUID_ARM926;
325b3cef 226 cpu->reset_fpsid = 0x41011090;
64e1671f 227 cpu->ctr = 0x1dd20d2;
0ca7e01c 228 cpu->reset_sctlr = 0x00090078;
777dc784
PM		 229}
230
231static void arm946_initfn(Object *obj)
232{
233 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 234 set_feature(&cpu->env, ARM_FEATURE_V5);
235 set_feature(&cpu->env, ARM_FEATURE_MPU);
c4804214 236 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
777dc784 237 cpu->midr = ARM_CPUID_ARM946;
64e1671f 238 cpu->ctr = 0x0f004006;
0ca7e01c 239 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 240}
241
242static void arm1026_initfn(Object *obj)
243{
244 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 245 set_feature(&cpu->env, ARM_FEATURE_V5);
246 set_feature(&cpu->env, ARM_FEATURE_VFP);
247 set_feature(&cpu->env, ARM_FEATURE_AUXCR);
c4804214
PM		 248 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
249 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
777dc784 250 cpu->midr = ARM_CPUID_ARM1026;
325b3cef 251 cpu->reset_fpsid = 0x410110a0;
64e1671f 252 cpu->ctr = 0x1dd20d2;
0ca7e01c 253 cpu->reset_sctlr = 0x00090078;
777dc784
PM		 254}
255
256static void arm1136_r2_initfn(Object *obj)
257{
258 ARMCPU *cpu = ARM_CPU(obj);
2e4d7e3e
PM		 259 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
260 * older core than plain "arm1136". In particular this does not
261 * have the v6K features.
262 * These ID register values are correct for 1136 but may be wrong
263 * for 1136_r2 (in particular r0p2 does not actually implement most
264 * of the ID registers).
265 */
581be094
PM		 266 set_feature(&cpu->env, ARM_FEATURE_V6);
267 set_feature(&cpu->env, ARM_FEATURE_VFP);
c4804214
PM		 268 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
269 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
270 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
777dc784 271 cpu->midr = ARM_CPUID_ARM1136_R2;
325b3cef 272 cpu->reset_fpsid = 0x410120b4;
bd35c355
PM		 273 cpu->mvfr0 = 0x11111111;
274 cpu->mvfr1 = 0x00000000;
64e1671f 275 cpu->ctr = 0x1dd20d2;
0ca7e01c 276 cpu->reset_sctlr = 0x00050078;
2e4d7e3e
PM		 277 cpu->id_pfr0 = 0x111;
278 cpu->id_pfr1 = 0x1;
279 cpu->id_dfr0 = 0x2;
280 cpu->id_afr0 = 0x3;
281 cpu->id_mmfr0 = 0x01130003;
282 cpu->id_mmfr1 = 0x10030302;
283 cpu->id_mmfr2 = 0x01222110;
284 cpu->id_isar0 = 0x00140011;
285 cpu->id_isar1 = 0x12002111;
286 cpu->id_isar2 = 0x11231111;
287 cpu->id_isar3 = 0x01102131;
288 cpu->id_isar4 = 0x141;
777dc784
PM		 289}
290
291static void arm1136_initfn(Object *obj)
292{
293 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 294 set_feature(&cpu->env, ARM_FEATURE_V6K);
295 set_feature(&cpu->env, ARM_FEATURE_V6);
296 set_feature(&cpu->env, ARM_FEATURE_VFP);
c4804214
PM		 297 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
298 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
299 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
777dc784 300 cpu->midr = ARM_CPUID_ARM1136;
325b3cef 301 cpu->reset_fpsid = 0x410120b4;
bd35c355
PM		 302 cpu->mvfr0 = 0x11111111;
303 cpu->mvfr1 = 0x00000000;
64e1671f 304 cpu->ctr = 0x1dd20d2;
0ca7e01c 305 cpu->reset_sctlr = 0x00050078;
2e4d7e3e
PM		 306 cpu->id_pfr0 = 0x111;
307 cpu->id_pfr1 = 0x1;
308 cpu->id_dfr0 = 0x2;
309 cpu->id_afr0 = 0x3;
310 cpu->id_mmfr0 = 0x01130003;
311 cpu->id_mmfr1 = 0x10030302;
312 cpu->id_mmfr2 = 0x01222110;
313 cpu->id_isar0 = 0x00140011;
314 cpu->id_isar1 = 0x12002111;
315 cpu->id_isar2 = 0x11231111;
316 cpu->id_isar3 = 0x01102131;
317 cpu->id_isar4 = 0x141;
777dc784
PM		 318}
319
320static void arm1176_initfn(Object *obj)
321{
322 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 323 set_feature(&cpu->env, ARM_FEATURE_V6K);
324 set_feature(&cpu->env, ARM_FEATURE_VFP);
325 set_feature(&cpu->env, ARM_FEATURE_VAPA);
c4804214
PM		 326 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
327 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
328 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
777dc784 329 cpu->midr = ARM_CPUID_ARM1176;
325b3cef 330 cpu->reset_fpsid = 0x410120b5;
bd35c355
PM		 331 cpu->mvfr0 = 0x11111111;
332 cpu->mvfr1 = 0x00000000;
64e1671f 333 cpu->ctr = 0x1dd20d2;
0ca7e01c 334 cpu->reset_sctlr = 0x00050078;
2e4d7e3e
PM		 335 cpu->id_pfr0 = 0x111;
336 cpu->id_pfr1 = 0x11;
337 cpu->id_dfr0 = 0x33;
338 cpu->id_afr0 = 0;
339 cpu->id_mmfr0 = 0x01130003;
340 cpu->id_mmfr1 = 0x10030302;
341 cpu->id_mmfr2 = 0x01222100;
342 cpu->id_isar0 = 0x0140011;
343 cpu->id_isar1 = 0x12002111;
344 cpu->id_isar2 = 0x11231121;
345 cpu->id_isar3 = 0x01102131;
346 cpu->id_isar4 = 0x01141;
777dc784
PM		 347}
348
349static void arm11mpcore_initfn(Object *obj)
350{
351 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 352 set_feature(&cpu->env, ARM_FEATURE_V6K);
353 set_feature(&cpu->env, ARM_FEATURE_VFP);
354 set_feature(&cpu->env, ARM_FEATURE_VAPA);
c4804214 355 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
777dc784 356 cpu->midr = ARM_CPUID_ARM11MPCORE;
325b3cef 357 cpu->reset_fpsid = 0x410120b4;
bd35c355
PM		 358 cpu->mvfr0 = 0x11111111;
359 cpu->mvfr1 = 0x00000000;
200bf596 360 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
2e4d7e3e
PM		 361 cpu->id_pfr0 = 0x111;
362 cpu->id_pfr1 = 0x1;
363 cpu->id_dfr0 = 0;
364 cpu->id_afr0 = 0x2;
365 cpu->id_mmfr0 = 0x01100103;
366 cpu->id_mmfr1 = 0x10020302;
367 cpu->id_mmfr2 = 0x01222000;
368 cpu->id_isar0 = 0x00100011;
369 cpu->id_isar1 = 0x12002111;
370 cpu->id_isar2 = 0x11221011;
371 cpu->id_isar3 = 0x01102131;
372 cpu->id_isar4 = 0x141;
777dc784
PM		 373}
374
375static void cortex_m3_initfn(Object *obj)
376{
377 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 378 set_feature(&cpu->env, ARM_FEATURE_V7);
379 set_feature(&cpu->env, ARM_FEATURE_M);
777dc784
PM		 380 cpu->midr = ARM_CPUID_CORTEXM3;
381}
382
383static void cortex_a8_initfn(Object *obj)
384{
385 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 386 set_feature(&cpu->env, ARM_FEATURE_V7);
387 set_feature(&cpu->env, ARM_FEATURE_VFP3);
388 set_feature(&cpu->env, ARM_FEATURE_NEON);
389 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
c4804214 390 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
777dc784 391 cpu->midr = ARM_CPUID_CORTEXA8;
325b3cef 392 cpu->reset_fpsid = 0x410330c0;
bd35c355
PM		 393 cpu->mvfr0 = 0x11110222;
394 cpu->mvfr1 = 0x00011100;
64e1671f 395 cpu->ctr = 0x82048004;
0ca7e01c 396 cpu->reset_sctlr = 0x00c50078;
2e4d7e3e
PM		 397 cpu->id_pfr0 = 0x1031;
398 cpu->id_pfr1 = 0x11;
399 cpu->id_dfr0 = 0x400;
400 cpu->id_afr0 = 0;
401 cpu->id_mmfr0 = 0x31100003;
402 cpu->id_mmfr1 = 0x20000000;
403 cpu->id_mmfr2 = 0x01202000;
404 cpu->id_mmfr3 = 0x11;
405 cpu->id_isar0 = 0x00101111;
406 cpu->id_isar1 = 0x12112111;
407 cpu->id_isar2 = 0x21232031;
408 cpu->id_isar3 = 0x11112131;
409 cpu->id_isar4 = 0x00111142;
85df3786
PM		 410 cpu->clidr = (1 << 27) | (2 << 24) | 3;
411 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
412 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
413 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
777dc784
PM		 414}
415
1047b9d7
PM		 416static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
417 /* power_control should be set to maximum latency. Again,
418 * default to 0 and set by private hook
419 */
420 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
421 .access = PL1_RW, .resetvalue = 0,
422 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
423 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
424 .access = PL1_RW, .resetvalue = 0,
425 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
426 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
427 .access = PL1_RW, .resetvalue = 0,
428 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
429 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
430 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
431 /* TLB lockdown control */
432 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
433 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
434 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
435 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
436 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
437 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
438 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
439 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
440 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
441 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
442 REGINFO_SENTINEL
443};
444
777dc784
PM		 445static void cortex_a9_initfn(Object *obj)
446{
447 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 448 set_feature(&cpu->env, ARM_FEATURE_V7);
449 set_feature(&cpu->env, ARM_FEATURE_VFP3);
450 set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
451 set_feature(&cpu->env, ARM_FEATURE_NEON);
452 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
453 /* Note that A9 supports the MP extensions even for
454 * A9UP and single-core A9MP (which are both different
455 * and valid configurations; we don't model A9UP).
456 */
457 set_feature(&cpu->env, ARM_FEATURE_V7MP);
777dc784 458 cpu->midr = ARM_CPUID_CORTEXA9;
325b3cef 459 cpu->reset_fpsid = 0x41033090;
bd35c355
PM		 460 cpu->mvfr0 = 0x11110222;
461 cpu->mvfr1 = 0x01111111;
64e1671f 462 cpu->ctr = 0x80038003;
0ca7e01c 463 cpu->reset_sctlr = 0x00c50078;
2e4d7e3e
PM		 464 cpu->id_pfr0 = 0x1031;
465 cpu->id_pfr1 = 0x11;
466 cpu->id_dfr0 = 0x000;
467 cpu->id_afr0 = 0;
468 cpu->id_mmfr0 = 0x00100103;
469 cpu->id_mmfr1 = 0x20000000;
470 cpu->id_mmfr2 = 0x01230000;
471 cpu->id_mmfr3 = 0x00002111;
472 cpu->id_isar0 = 0x00101111;
473 cpu->id_isar1 = 0x13112111;
474 cpu->id_isar2 = 0x21232041;
475 cpu->id_isar3 = 0x11112131;
476 cpu->id_isar4 = 0x00111142;
85df3786
PM		 477 cpu->clidr = (1 << 27) | (1 << 24) | 3;
478 cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */
479 cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */
1047b9d7
PM		 480 {
481 ARMCPRegInfo cbar = {
482 .name = "CBAR", .cp = 15, .crn = 15, .crm = 0, .opc1 = 4,
483 .opc2 = 0, .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
484 .fieldoffset = offsetof(CPUARMState, cp15.c15_config_base_address)
485 };
486 define_one_arm_cp_reg(cpu, &cbar);
487 define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
488 }
777dc784
PM		 489}
490
491static void cortex_a15_initfn(Object *obj)
492{
493 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 494 set_feature(&cpu->env, ARM_FEATURE_V7);
495 set_feature(&cpu->env, ARM_FEATURE_VFP4);
496 set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
497 set_feature(&cpu->env, ARM_FEATURE_NEON);
498 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
499 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
500 set_feature(&cpu->env, ARM_FEATURE_V7MP);
501 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
c4804214 502 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
777dc784 503 cpu->midr = ARM_CPUID_CORTEXA15;
325b3cef 504 cpu->reset_fpsid = 0x410430f0;
bd35c355
PM		 505 cpu->mvfr0 = 0x10110222;
506 cpu->mvfr1 = 0x11111111;
64e1671f 507 cpu->ctr = 0x8444c004;
0ca7e01c 508 cpu->reset_sctlr = 0x00c50078;
2e4d7e3e
PM		 509 cpu->id_pfr0 = 0x00001131;
510 cpu->id_pfr1 = 0x00011011;
511 cpu->id_dfr0 = 0x02010555;
512 cpu->id_afr0 = 0x00000000;
513 cpu->id_mmfr0 = 0x10201105;
514 cpu->id_mmfr1 = 0x20000000;
515 cpu->id_mmfr2 = 0x01240000;
516 cpu->id_mmfr3 = 0x02102211;
517 cpu->id_isar0 = 0x02101110;
518 cpu->id_isar1 = 0x13112111;
519 cpu->id_isar2 = 0x21232041;
520 cpu->id_isar3 = 0x11112131;
521 cpu->id_isar4 = 0x10011142;
85df3786
PM		 522 cpu->clidr = 0x0a200023;
523 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
524 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
525 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
777dc784
PM		 526}
527
528static void ti925t_initfn(Object *obj)
529{
530 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 531 set_feature(&cpu->env, ARM_FEATURE_V4T);
532 set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
777dc784 533 cpu->midr = ARM_CPUID_TI925T;
64e1671f 534 cpu->ctr = 0x5109149;
0ca7e01c 535 cpu->reset_sctlr = 0x00000070;
777dc784
PM		 536}
537
538static void sa1100_initfn(Object *obj)
539{
540 ARMCPU *cpu = ARM_CPU(obj);
581be094 541 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
c4804214 542 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
777dc784 543 cpu->midr = ARM_CPUID_SA1100;
0ca7e01c 544 cpu->reset_sctlr = 0x00000070;
777dc784
PM		 545}
546
547static void sa1110_initfn(Object *obj)
548{
549 ARMCPU *cpu = ARM_CPU(obj);
581be094 550 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
c4804214 551 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
777dc784 552 cpu->midr = ARM_CPUID_SA1110;
0ca7e01c 553 cpu->reset_sctlr = 0x00000070;
777dc784
PM		 554}
555
556static void pxa250_initfn(Object *obj)
557{
558 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 559 set_feature(&cpu->env, ARM_FEATURE_V5);
560 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
777dc784 561 cpu->midr = ARM_CPUID_PXA250;
64e1671f 562 cpu->ctr = 0xd172172;
0ca7e01c 563 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 564}
565
566static void pxa255_initfn(Object *obj)
567{
568 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 569 set_feature(&cpu->env, ARM_FEATURE_V5);
570 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
777dc784 571 cpu->midr = ARM_CPUID_PXA255;
64e1671f 572 cpu->ctr = 0xd172172;
0ca7e01c 573 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 574}
575
576static void pxa260_initfn(Object *obj)
577{
578 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 579 set_feature(&cpu->env, ARM_FEATURE_V5);
580 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
777dc784 581 cpu->midr = ARM_CPUID_PXA260;
64e1671f 582 cpu->ctr = 0xd172172;
0ca7e01c 583 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 584}
585
586static void pxa261_initfn(Object *obj)
587{
588 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 589 set_feature(&cpu->env, ARM_FEATURE_V5);
590 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
777dc784 591 cpu->midr = ARM_CPUID_PXA261;
64e1671f 592 cpu->ctr = 0xd172172;
0ca7e01c 593 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 594}
595
596static void pxa262_initfn(Object *obj)
597{
598 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 599 set_feature(&cpu->env, ARM_FEATURE_V5);
600 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
777dc784 601 cpu->midr = ARM_CPUID_PXA262;
64e1671f 602 cpu->ctr = 0xd172172;
0ca7e01c 603 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 604}
605
606static void pxa270a0_initfn(Object *obj)
607{
608 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 609 set_feature(&cpu->env, ARM_FEATURE_V5);
610 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
611 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
777dc784 612 cpu->midr = ARM_CPUID_PXA270_A0;
64e1671f 613 cpu->ctr = 0xd172172;
0ca7e01c 614 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 615}
616
617static void pxa270a1_initfn(Object *obj)
618{
619 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 620 set_feature(&cpu->env, ARM_FEATURE_V5);
621 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
622 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
777dc784 623 cpu->midr = ARM_CPUID_PXA270_A1;
64e1671f 624 cpu->ctr = 0xd172172;
0ca7e01c 625 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 626}
627
628static void pxa270b0_initfn(Object *obj)
629{
630 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 631 set_feature(&cpu->env, ARM_FEATURE_V5);
632 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
633 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
777dc784 634 cpu->midr = ARM_CPUID_PXA270_B0;
64e1671f 635 cpu->ctr = 0xd172172;
0ca7e01c 636 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 637}
638
639static void pxa270b1_initfn(Object *obj)
640{
641 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 642 set_feature(&cpu->env, ARM_FEATURE_V5);
643 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
644 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
777dc784 645 cpu->midr = ARM_CPUID_PXA270_B1;
64e1671f 646 cpu->ctr = 0xd172172;
0ca7e01c 647 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 648}
649
650static void pxa270c0_initfn(Object *obj)
651{
652 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 653 set_feature(&cpu->env, ARM_FEATURE_V5);
654 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
655 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
777dc784 656 cpu->midr = ARM_CPUID_PXA270_C0;
64e1671f 657 cpu->ctr = 0xd172172;
0ca7e01c 658 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 659}
660
661static void pxa270c5_initfn(Object *obj)
662{
663 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 664 set_feature(&cpu->env, ARM_FEATURE_V5);
665 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
666 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
777dc784 667 cpu->midr = ARM_CPUID_PXA270_C5;
64e1671f 668 cpu->ctr = 0xd172172;
0ca7e01c 669 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 670}
671
672static void arm_any_initfn(Object *obj)
673{
674 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 675 set_feature(&cpu->env, ARM_FEATURE_V7);
676 set_feature(&cpu->env, ARM_FEATURE_VFP4);
677 set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
678 set_feature(&cpu->env, ARM_FEATURE_NEON);
679 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
680 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
681 set_feature(&cpu->env, ARM_FEATURE_V7MP);
777dc784
PM		 682 cpu->midr = ARM_CPUID_ANY;
683}
684
685typedef struct ARMCPUInfo {
686 const char *name;
687 void (*initfn)(Object *obj);
688} ARMCPUInfo;
689
690static const ARMCPUInfo arm_cpus[] = {
691 { .name = "arm926", .initfn = arm926_initfn },
692 { .name = "arm946", .initfn = arm946_initfn },
693 { .name = "arm1026", .initfn = arm1026_initfn },
694 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
695 * older core than plain "arm1136". In particular this does not
696 * have the v6K features.
697 */
698 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
699 { .name = "arm1136", .initfn = arm1136_initfn },
700 { .name = "arm1176", .initfn = arm1176_initfn },
701 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
702 { .name = "cortex-m3", .initfn = cortex_m3_initfn },
703 { .name = "cortex-a8", .initfn = cortex_a8_initfn },
704 { .name = "cortex-a9", .initfn = cortex_a9_initfn },
705 { .name = "cortex-a15", .initfn = cortex_a15_initfn },
706 { .name = "ti925t", .initfn = ti925t_initfn },
707 { .name = "sa1100", .initfn = sa1100_initfn },
708 { .name = "sa1110", .initfn = sa1110_initfn },
709 { .name = "pxa250", .initfn = pxa250_initfn },
710 { .name = "pxa255", .initfn = pxa255_initfn },
711 { .name = "pxa260", .initfn = pxa260_initfn },
712 { .name = "pxa261", .initfn = pxa261_initfn },
713 { .name = "pxa262", .initfn = pxa262_initfn },
714 /* "pxa270" is an alias for "pxa270-a0" */
715 { .name = "pxa270", .initfn = pxa270a0_initfn },
716 { .name = "pxa270-a0", .initfn = pxa270a0_initfn },
717 { .name = "pxa270-a1", .initfn = pxa270a1_initfn },
718 { .name = "pxa270-b0", .initfn = pxa270b0_initfn },
719 { .name = "pxa270-b1", .initfn = pxa270b1_initfn },
720 { .name = "pxa270-c0", .initfn = pxa270c0_initfn },
721 { .name = "pxa270-c5", .initfn = pxa270c5_initfn },
722 { .name = "any", .initfn = arm_any_initfn },
723};
724
dec9c2d4
AF		 725static void arm_cpu_class_init(ObjectClass *oc, void *data)
726{
727 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
728 CPUClass *cc = CPU_CLASS(acc);
729
730 acc->parent_reset = cc->reset;
731 cc->reset = arm_cpu_reset;
732}
733
777dc784
PM		 734static void cpu_register(const ARMCPUInfo *info)
735{
736 TypeInfo type_info = {
737 .name = info->name,
738 .parent = TYPE_ARM_CPU,
739 .instance_size = sizeof(ARMCPU),
740 .instance_init = info->initfn,
741 .class_size = sizeof(ARMCPUClass),
742 };
743
744 type_register_static(&type_info);
745}
746
dec9c2d4
AF		 747static const TypeInfo arm_cpu_type_info = {
748 .name = TYPE_ARM_CPU,
749 .parent = TYPE_CPU,
750 .instance_size = sizeof(ARMCPU),
777dc784 751 .instance_init = arm_cpu_initfn,
4b6a83fb 752 .instance_finalize = arm_cpu_finalizefn,
777dc784 753 .abstract = true,
dec9c2d4
AF		 754 .class_size = sizeof(ARMCPUClass),
755 .class_init = arm_cpu_class_init,
756};
757
758static void arm_cpu_register_types(void)
759{
777dc784
PM		 760 int i;
761
dec9c2d4 762 type_register_static(&arm_cpu_type_info);
777dc784
PM		 763 for (i = 0; i < ARRAY_SIZE(arm_cpus); i++) {
764 cpu_register(&arm_cpus[i]);
765 }
dec9c2d4
AF		 766}
767
768type_init(arm_cpu_register_types)
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