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dec9c2d4 AF |
1 | /* |
2 | * QEMU ARM CPU | |
3 | * | |
4 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | */ | |
20 | ||
778c3a06 | 21 | #include "cpu.h" |
ccd38087 | 22 | #include "internals.h" |
dec9c2d4 | 23 | #include "qemu-common.h" |
5de16430 | 24 | #include "hw/qdev-properties.h" |
3c30dd5a PM |
25 | #if !defined(CONFIG_USER_ONLY) |
26 | #include "hw/loader.h" | |
27 | #endif | |
7c1840b6 | 28 | #include "hw/arm/arm.h" |
9c17d615 | 29 | #include "sysemu/sysemu.h" |
7c1840b6 | 30 | #include "sysemu/kvm.h" |
50a2c6e5 | 31 | #include "kvm_arm.h" |
dec9c2d4 | 32 | |
f45748f1 AF |
33 | static void arm_cpu_set_pc(CPUState *cs, vaddr value) |
34 | { | |
35 | ARMCPU *cpu = ARM_CPU(cs); | |
36 | ||
37 | cpu->env.regs[15] = value; | |
38 | } | |
39 | ||
8c2e1b00 AF |
40 | static bool arm_cpu_has_work(CPUState *cs) |
41 | { | |
543486db RH |
42 | ARMCPU *cpu = ARM_CPU(cs); |
43 | ||
44 | return !cpu->powered_off | |
45 | && cs->interrupt_request & | |
136e67e9 EI |
46 | (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD |
47 | | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | |
48 | | CPU_INTERRUPT_EXITTB); | |
8c2e1b00 AF |
49 | } |
50 | ||
4b6a83fb PM |
51 | static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) |
52 | { | |
53 | /* Reset a single ARMCPRegInfo register */ | |
54 | ARMCPRegInfo *ri = value; | |
55 | ARMCPU *cpu = opaque; | |
56 | ||
b061a82b | 57 | if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { |
4b6a83fb PM |
58 | return; |
59 | } | |
60 | ||
61 | if (ri->resetfn) { | |
62 | ri->resetfn(&cpu->env, ri); | |
63 | return; | |
64 | } | |
65 | ||
66 | /* A zero offset is never possible as it would be regs[0] | |
67 | * so we use it to indicate that reset is being handled elsewhere. | |
68 | * This is basically only used for fields in non-core coprocessors | |
69 | * (like the pxa2xx ones). | |
70 | */ | |
71 | if (!ri->fieldoffset) { | |
72 | return; | |
73 | } | |
74 | ||
67ed771d | 75 | if (cpreg_field_is_64bit(ri)) { |
4b6a83fb PM |
76 | CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; |
77 | } else { | |
78 | CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; | |
79 | } | |
80 | } | |
81 | ||
dec9c2d4 AF |
82 | /* CPUClass::reset() */ |
83 | static void arm_cpu_reset(CPUState *s) | |
84 | { | |
85 | ARMCPU *cpu = ARM_CPU(s); | |
86 | ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); | |
3c30dd5a | 87 | CPUARMState *env = &cpu->env; |
3c30dd5a | 88 | |
dec9c2d4 AF |
89 | acc->parent_reset(s); |
90 | ||
f0c3c505 | 91 | memset(env, 0, offsetof(CPUARMState, features)); |
4b6a83fb | 92 | g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); |
3c30dd5a PM |
93 | env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; |
94 | env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; | |
95 | env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; | |
a50c0f51 | 96 | env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2; |
3c30dd5a | 97 | |
543486db RH |
98 | cpu->powered_off = cpu->start_powered_off; |
99 | s->halted = cpu->start_powered_off; | |
100 | ||
3c30dd5a PM |
101 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { |
102 | env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; | |
103 | } | |
104 | ||
3926cc84 AG |
105 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { |
106 | /* 64 bit CPUs always start in 64 bit mode */ | |
107 | env->aarch64 = 1; | |
d356312f PM |
108 | #if defined(CONFIG_USER_ONLY) |
109 | env->pstate = PSTATE_MODE_EL0t; | |
14e5f106 | 110 | /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ |
137feaa9 | 111 | env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; |
8c6afa6a | 112 | /* and to the FP/Neon instructions */ |
7ebd5f2e | 113 | env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); |
d356312f | 114 | #else |
5097227c GB |
115 | /* Reset into the highest available EL */ |
116 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
117 | env->pstate = PSTATE_MODE_EL3h; | |
118 | } else if (arm_feature(env, ARM_FEATURE_EL2)) { | |
119 | env->pstate = PSTATE_MODE_EL2h; | |
120 | } else { | |
121 | env->pstate = PSTATE_MODE_EL1h; | |
122 | } | |
3933443e | 123 | env->pc = cpu->rvbar; |
8c6afa6a PM |
124 | #endif |
125 | } else { | |
126 | #if defined(CONFIG_USER_ONLY) | |
127 | /* Userspace expects access to cp10 and cp11 for FP/Neon */ | |
7ebd5f2e | 128 | env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); |
d356312f | 129 | #endif |
3926cc84 AG |
130 | } |
131 | ||
3c30dd5a PM |
132 | #if defined(CONFIG_USER_ONLY) |
133 | env->uncached_cpsr = ARM_CPU_MODE_USR; | |
134 | /* For user mode we must enable access to coprocessors */ | |
135 | env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; | |
136 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { | |
137 | env->cp15.c15_cpar = 3; | |
138 | } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
139 | env->cp15.c15_cpar = 1; | |
140 | } | |
141 | #else | |
142 | /* SVC mode with interrupts disabled. */ | |
4cc35614 PM |
143 | env->uncached_cpsr = ARM_CPU_MODE_SVC; |
144 | env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; | |
3c30dd5a | 145 | /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is |
6e3cf5df MG |
146 | * clear at reset. Initial SP and PC are loaded from ROM. |
147 | */ | |
3c30dd5a | 148 | if (IS_M(env)) { |
6e3cf5df MG |
149 | uint32_t initial_msp; /* Loaded from 0x0 */ |
150 | uint32_t initial_pc; /* Loaded from 0x4 */ | |
3c30dd5a | 151 | uint8_t *rom; |
6e3cf5df | 152 | |
4cc35614 | 153 | env->daif &= ~PSTATE_I; |
3c30dd5a PM |
154 | rom = rom_ptr(0); |
155 | if (rom) { | |
6e3cf5df MG |
156 | /* Address zero is covered by ROM which hasn't yet been |
157 | * copied into physical memory. | |
158 | */ | |
159 | initial_msp = ldl_p(rom); | |
160 | initial_pc = ldl_p(rom + 4); | |
161 | } else { | |
162 | /* Address zero not covered by a ROM blob, or the ROM blob | |
163 | * is in non-modifiable memory and this is a second reset after | |
164 | * it got copied into memory. In the latter case, rom_ptr | |
165 | * will return a NULL pointer and we should use ldl_phys instead. | |
166 | */ | |
167 | initial_msp = ldl_phys(s->as, 0); | |
168 | initial_pc = ldl_phys(s->as, 4); | |
3c30dd5a | 169 | } |
6e3cf5df MG |
170 | |
171 | env->regs[13] = initial_msp & 0xFFFFFFFC; | |
172 | env->regs[15] = initial_pc & ~1; | |
173 | env->thumb = initial_pc & 1; | |
3c30dd5a | 174 | } |
387f9806 | 175 | |
137feaa9 FA |
176 | /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently |
177 | * executing as AArch32 then check if highvecs are enabled and | |
178 | * adjust the PC accordingly. | |
179 | */ | |
180 | if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { | |
34bf7744 | 181 | env->regs[15] = 0xFFFF0000; |
387f9806 AP |
182 | } |
183 | ||
3c30dd5a | 184 | env->vfp.xregs[ARM_VFP_FPEXC] = 0; |
3c30dd5a PM |
185 | #endif |
186 | set_flush_to_zero(1, &env->vfp.standard_fp_status); | |
187 | set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); | |
188 | set_default_nan_mode(1, &env->vfp.standard_fp_status); | |
189 | set_float_detect_tininess(float_tininess_before_rounding, | |
190 | &env->vfp.fp_status); | |
191 | set_float_detect_tininess(float_tininess_before_rounding, | |
192 | &env->vfp.standard_fp_status); | |
00c8cb0a | 193 | tlb_flush(s, 1); |
50a2c6e5 PB |
194 | |
195 | #ifndef CONFIG_USER_ONLY | |
196 | if (kvm_enabled()) { | |
197 | kvm_arm_reset_vcpu(cpu); | |
198 | } | |
199 | #endif | |
9ee98ce8 | 200 | |
46747d15 | 201 | hw_breakpoint_update_all(cpu); |
9ee98ce8 | 202 | hw_watchpoint_update_all(cpu); |
dec9c2d4 AF |
203 | } |
204 | ||
e8925712 RH |
205 | bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) |
206 | { | |
207 | CPUClass *cc = CPU_GET_CLASS(cs); | |
012a906b GB |
208 | CPUARMState *env = cs->env_ptr; |
209 | uint32_t cur_el = arm_current_el(env); | |
210 | bool secure = arm_is_secure(env); | |
211 | uint32_t target_el; | |
212 | uint32_t excp_idx; | |
e8925712 RH |
213 | bool ret = false; |
214 | ||
012a906b GB |
215 | if (interrupt_request & CPU_INTERRUPT_FIQ) { |
216 | excp_idx = EXCP_FIQ; | |
217 | target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); | |
218 | if (arm_excp_unmasked(cs, excp_idx, target_el)) { | |
219 | cs->exception_index = excp_idx; | |
220 | env->exception.target_el = target_el; | |
221 | cc->do_interrupt(cs); | |
222 | ret = true; | |
223 | } | |
e8925712 | 224 | } |
012a906b GB |
225 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
226 | excp_idx = EXCP_IRQ; | |
227 | target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); | |
228 | if (arm_excp_unmasked(cs, excp_idx, target_el)) { | |
229 | cs->exception_index = excp_idx; | |
230 | env->exception.target_el = target_el; | |
231 | cc->do_interrupt(cs); | |
232 | ret = true; | |
233 | } | |
e8925712 | 234 | } |
012a906b GB |
235 | if (interrupt_request & CPU_INTERRUPT_VIRQ) { |
236 | excp_idx = EXCP_VIRQ; | |
237 | target_el = 1; | |
238 | if (arm_excp_unmasked(cs, excp_idx, target_el)) { | |
239 | cs->exception_index = excp_idx; | |
240 | env->exception.target_el = target_el; | |
241 | cc->do_interrupt(cs); | |
242 | ret = true; | |
243 | } | |
136e67e9 | 244 | } |
012a906b GB |
245 | if (interrupt_request & CPU_INTERRUPT_VFIQ) { |
246 | excp_idx = EXCP_VFIQ; | |
247 | target_el = 1; | |
248 | if (arm_excp_unmasked(cs, excp_idx, target_el)) { | |
249 | cs->exception_index = excp_idx; | |
250 | env->exception.target_el = target_el; | |
251 | cc->do_interrupt(cs); | |
252 | ret = true; | |
253 | } | |
136e67e9 | 254 | } |
e8925712 RH |
255 | |
256 | return ret; | |
257 | } | |
258 | ||
b5c633c5 PM |
259 | #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) |
260 | static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) | |
261 | { | |
262 | CPUClass *cc = CPU_GET_CLASS(cs); | |
263 | ARMCPU *cpu = ARM_CPU(cs); | |
264 | CPUARMState *env = &cpu->env; | |
265 | bool ret = false; | |
266 | ||
267 | ||
268 | if (interrupt_request & CPU_INTERRUPT_FIQ | |
269 | && !(env->daif & PSTATE_F)) { | |
270 | cs->exception_index = EXCP_FIQ; | |
271 | cc->do_interrupt(cs); | |
272 | ret = true; | |
273 | } | |
274 | /* ARMv7-M interrupt return works by loading a magic value | |
275 | * into the PC. On real hardware the load causes the | |
276 | * return to occur. The qemu implementation performs the | |
277 | * jump normally, then does the exception return when the | |
278 | * CPU tries to execute code at the magic address. | |
279 | * This will cause the magic PC value to be pushed to | |
280 | * the stack if an interrupt occurred at the wrong time. | |
281 | * We avoid this by disabling interrupts when | |
282 | * pc contains a magic address. | |
283 | */ | |
284 | if (interrupt_request & CPU_INTERRUPT_HARD | |
285 | && !(env->daif & PSTATE_I) | |
286 | && (env->regs[15] < 0xfffffff0)) { | |
287 | cs->exception_index = EXCP_IRQ; | |
288 | cc->do_interrupt(cs); | |
289 | ret = true; | |
290 | } | |
291 | return ret; | |
292 | } | |
293 | #endif | |
294 | ||
7c1840b6 PM |
295 | #ifndef CONFIG_USER_ONLY |
296 | static void arm_cpu_set_irq(void *opaque, int irq, int level) | |
297 | { | |
298 | ARMCPU *cpu = opaque; | |
136e67e9 | 299 | CPUARMState *env = &cpu->env; |
7c1840b6 | 300 | CPUState *cs = CPU(cpu); |
136e67e9 EI |
301 | static const int mask[] = { |
302 | [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, | |
303 | [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, | |
304 | [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, | |
305 | [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ | |
306 | }; | |
7c1840b6 PM |
307 | |
308 | switch (irq) { | |
136e67e9 EI |
309 | case ARM_CPU_VIRQ: |
310 | case ARM_CPU_VFIQ: | |
311 | if (!arm_feature(env, ARM_FEATURE_EL2)) { | |
312 | hw_error("%s: Virtual interrupt line %d with no EL2 support\n", | |
313 | __func__, irq); | |
7c1840b6 | 314 | } |
136e67e9 EI |
315 | /* fall through */ |
316 | case ARM_CPU_IRQ: | |
7c1840b6 PM |
317 | case ARM_CPU_FIQ: |
318 | if (level) { | |
136e67e9 | 319 | cpu_interrupt(cs, mask[irq]); |
7c1840b6 | 320 | } else { |
136e67e9 | 321 | cpu_reset_interrupt(cs, mask[irq]); |
7c1840b6 PM |
322 | } |
323 | break; | |
324 | default: | |
325 | hw_error("arm_cpu_set_irq: Bad interrupt line %d\n", irq); | |
326 | } | |
327 | } | |
328 | ||
329 | static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) | |
330 | { | |
331 | #ifdef CONFIG_KVM | |
332 | ARMCPU *cpu = opaque; | |
333 | CPUState *cs = CPU(cpu); | |
334 | int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT; | |
335 | ||
336 | switch (irq) { | |
337 | case ARM_CPU_IRQ: | |
338 | kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; | |
339 | break; | |
340 | case ARM_CPU_FIQ: | |
341 | kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; | |
342 | break; | |
343 | default: | |
344 | hw_error("arm_cpu_kvm_set_irq: Bad interrupt line %d\n", irq); | |
345 | } | |
346 | kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; | |
347 | kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); | |
348 | #endif | |
349 | } | |
84f2bed3 PS |
350 | |
351 | static bool arm_cpu_is_big_endian(CPUState *cs) | |
352 | { | |
353 | ARMCPU *cpu = ARM_CPU(cs); | |
354 | CPUARMState *env = &cpu->env; | |
355 | int cur_el; | |
356 | ||
357 | cpu_synchronize_state(cs); | |
358 | ||
359 | /* In 32bit guest endianness is determined by looking at CPSR's E bit */ | |
360 | if (!is_a64(env)) { | |
361 | return (env->uncached_cpsr & CPSR_E) ? 1 : 0; | |
362 | } | |
363 | ||
364 | cur_el = arm_current_el(env); | |
365 | ||
366 | if (cur_el == 0) { | |
367 | return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0; | |
368 | } | |
369 | ||
370 | return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0; | |
371 | } | |
372 | ||
7c1840b6 PM |
373 | #endif |
374 | ||
581be094 PM |
375 | static inline void set_feature(CPUARMState *env, int feature) |
376 | { | |
918f5dca | 377 | env->features |= 1ULL << feature; |
581be094 PM |
378 | } |
379 | ||
08828484 GB |
380 | static inline void unset_feature(CPUARMState *env, int feature) |
381 | { | |
382 | env->features &= ~(1ULL << feature); | |
383 | } | |
384 | ||
eb5e1d3c PF |
385 | #define ARM_CPUS_PER_CLUSTER 8 |
386 | ||
777dc784 PM |
387 | static void arm_cpu_initfn(Object *obj) |
388 | { | |
c05efcb1 | 389 | CPUState *cs = CPU(obj); |
777dc784 | 390 | ARMCPU *cpu = ARM_CPU(obj); |
79614b78 | 391 | static bool inited; |
eb5e1d3c | 392 | uint32_t Aff1, Aff0; |
777dc784 | 393 | |
c05efcb1 | 394 | cs->env_ptr = &cpu->env; |
777dc784 | 395 | cpu_exec_init(&cpu->env); |
4b6a83fb PM |
396 | cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, |
397 | g_free, g_free); | |
79614b78 | 398 | |
eb5e1d3c PF |
399 | /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. |
400 | * We don't support setting cluster ID ([16..23]) (known as Aff2 | |
401 | * in later ARM ARM versions), or any of the higher affinity level fields, | |
402 | * so these bits always RAZ. | |
403 | */ | |
404 | Aff1 = cs->cpu_index / ARM_CPUS_PER_CLUSTER; | |
405 | Aff0 = cs->cpu_index % ARM_CPUS_PER_CLUSTER; | |
406 | cpu->mp_affinity = (Aff1 << 8) | Aff0; | |
407 | ||
7c1840b6 PM |
408 | #ifndef CONFIG_USER_ONLY |
409 | /* Our inbound IRQ and FIQ lines */ | |
410 | if (kvm_enabled()) { | |
136e67e9 EI |
411 | /* VIRQ and VFIQ are unused with KVM but we add them to maintain |
412 | * the same interface as non-KVM CPUs. | |
413 | */ | |
414 | qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); | |
7c1840b6 | 415 | } else { |
136e67e9 | 416 | qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); |
7c1840b6 | 417 | } |
55d284af | 418 | |
bc72ad67 | 419 | cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, |
55d284af | 420 | arm_gt_ptimer_cb, cpu); |
bc72ad67 | 421 | cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, |
55d284af PM |
422 | arm_gt_vtimer_cb, cpu); |
423 | qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, | |
424 | ARRAY_SIZE(cpu->gt_timer_outputs)); | |
7c1840b6 PM |
425 | #endif |
426 | ||
54d3e3f5 PM |
427 | /* DTB consumers generally don't in fact care what the 'compatible' |
428 | * string is, so always provide some string and trust that a hypothetical | |
429 | * picky DTB consumer will also provide a helpful error message. | |
430 | */ | |
431 | cpu->dtb_compatible = "qemu,unknown"; | |
dd032e34 | 432 | cpu->psci_version = 1; /* By default assume PSCI v0.1 */ |
3541addc | 433 | cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; |
54d3e3f5 | 434 | |
98128601 RH |
435 | if (tcg_enabled()) { |
436 | cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ | |
437 | if (!inited) { | |
438 | inited = true; | |
439 | arm_translate_init(); | |
440 | } | |
79614b78 | 441 | } |
4b6a83fb PM |
442 | } |
443 | ||
07a5b0d2 | 444 | static Property arm_cpu_reset_cbar_property = |
f318cec6 | 445 | DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); |
07a5b0d2 | 446 | |
68e0a40a AP |
447 | static Property arm_cpu_reset_hivecs_property = |
448 | DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); | |
449 | ||
3933443e PM |
450 | static Property arm_cpu_rvbar_property = |
451 | DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); | |
452 | ||
51942aee GB |
453 | static Property arm_cpu_has_el3_property = |
454 | DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); | |
455 | ||
8f325f56 PC |
456 | static Property arm_cpu_has_mpu_property = |
457 | DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); | |
458 | ||
3281af81 PC |
459 | static Property arm_cpu_pmsav7_dregion_property = |
460 | DEFINE_PROP_UINT32("pmsav7-dregion", ARMCPU, pmsav7_dregion, 16); | |
461 | ||
07a5b0d2 PC |
462 | static void arm_cpu_post_init(Object *obj) |
463 | { | |
464 | ARMCPU *cpu = ARM_CPU(obj); | |
07a5b0d2 | 465 | |
f318cec6 PM |
466 | if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || |
467 | arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { | |
07a5b0d2 | 468 | qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, |
5433a0a8 | 469 | &error_abort); |
07a5b0d2 | 470 | } |
68e0a40a AP |
471 | |
472 | if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { | |
473 | qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property, | |
5433a0a8 | 474 | &error_abort); |
68e0a40a | 475 | } |
3933443e PM |
476 | |
477 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | |
478 | qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property, | |
479 | &error_abort); | |
480 | } | |
51942aee GB |
481 | |
482 | if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { | |
483 | /* Add the has_el3 state CPU property only if EL3 is allowed. This will | |
484 | * prevent "has_el3" from existing on CPUs which cannot support EL3. | |
485 | */ | |
486 | qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property, | |
487 | &error_abort); | |
488 | } | |
8f325f56 PC |
489 | |
490 | if (arm_feature(&cpu->env, ARM_FEATURE_MPU)) { | |
491 | qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, | |
492 | &error_abort); | |
3281af81 PC |
493 | if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { |
494 | qdev_property_add_static(DEVICE(obj), | |
495 | &arm_cpu_pmsav7_dregion_property, | |
496 | &error_abort); | |
497 | } | |
8f325f56 PC |
498 | } |
499 | ||
07a5b0d2 PC |
500 | } |
501 | ||
4b6a83fb PM |
502 | static void arm_cpu_finalizefn(Object *obj) |
503 | { | |
504 | ARMCPU *cpu = ARM_CPU(obj); | |
505 | g_hash_table_destroy(cpu->cp_regs); | |
777dc784 PM |
506 | } |
507 | ||
14969266 | 508 | static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
581be094 | 509 | { |
14a10fc3 | 510 | CPUState *cs = CPU(dev); |
14969266 AF |
511 | ARMCPU *cpu = ARM_CPU(dev); |
512 | ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); | |
581be094 | 513 | CPUARMState *env = &cpu->env; |
14969266 | 514 | |
581be094 | 515 | /* Some features automatically imply others: */ |
81e69fb0 MR |
516 | if (arm_feature(env, ARM_FEATURE_V8)) { |
517 | set_feature(env, ARM_FEATURE_V7); | |
518 | set_feature(env, ARM_FEATURE_ARM_DIV); | |
519 | set_feature(env, ARM_FEATURE_LPAE); | |
520 | } | |
581be094 PM |
521 | if (arm_feature(env, ARM_FEATURE_V7)) { |
522 | set_feature(env, ARM_FEATURE_VAPA); | |
523 | set_feature(env, ARM_FEATURE_THUMB2); | |
81bdde9d | 524 | set_feature(env, ARM_FEATURE_MPIDR); |
581be094 PM |
525 | if (!arm_feature(env, ARM_FEATURE_M)) { |
526 | set_feature(env, ARM_FEATURE_V6K); | |
527 | } else { | |
528 | set_feature(env, ARM_FEATURE_V6); | |
529 | } | |
530 | } | |
531 | if (arm_feature(env, ARM_FEATURE_V6K)) { | |
532 | set_feature(env, ARM_FEATURE_V6); | |
533 | set_feature(env, ARM_FEATURE_MVFR); | |
534 | } | |
535 | if (arm_feature(env, ARM_FEATURE_V6)) { | |
536 | set_feature(env, ARM_FEATURE_V5); | |
537 | if (!arm_feature(env, ARM_FEATURE_M)) { | |
538 | set_feature(env, ARM_FEATURE_AUXCR); | |
539 | } | |
540 | } | |
541 | if (arm_feature(env, ARM_FEATURE_V5)) { | |
542 | set_feature(env, ARM_FEATURE_V4T); | |
543 | } | |
544 | if (arm_feature(env, ARM_FEATURE_M)) { | |
545 | set_feature(env, ARM_FEATURE_THUMB_DIV); | |
546 | } | |
547 | if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { | |
548 | set_feature(env, ARM_FEATURE_THUMB_DIV); | |
549 | } | |
550 | if (arm_feature(env, ARM_FEATURE_VFP4)) { | |
551 | set_feature(env, ARM_FEATURE_VFP3); | |
da5141fc | 552 | set_feature(env, ARM_FEATURE_VFP_FP16); |
581be094 PM |
553 | } |
554 | if (arm_feature(env, ARM_FEATURE_VFP3)) { | |
555 | set_feature(env, ARM_FEATURE_VFP); | |
556 | } | |
de9b05b8 | 557 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
bdcc150d | 558 | set_feature(env, ARM_FEATURE_V7MP); |
de9b05b8 PM |
559 | set_feature(env, ARM_FEATURE_PXN); |
560 | } | |
f318cec6 PM |
561 | if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { |
562 | set_feature(env, ARM_FEATURE_CBAR); | |
563 | } | |
62b44f05 AR |
564 | if (arm_feature(env, ARM_FEATURE_THUMB2) && |
565 | !arm_feature(env, ARM_FEATURE_M)) { | |
566 | set_feature(env, ARM_FEATURE_THUMB_DSP); | |
567 | } | |
2ceb98c0 | 568 | |
68e0a40a AP |
569 | if (cpu->reset_hivecs) { |
570 | cpu->reset_sctlr |= (1 << 13); | |
571 | } | |
572 | ||
51942aee GB |
573 | if (!cpu->has_el3) { |
574 | /* If the has_el3 CPU property is disabled then we need to disable the | |
575 | * feature. | |
576 | */ | |
577 | unset_feature(env, ARM_FEATURE_EL3); | |
578 | ||
579 | /* Disable the security extension feature bits in the processor feature | |
3d5c84ff | 580 | * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. |
51942aee GB |
581 | */ |
582 | cpu->id_pfr1 &= ~0xf0; | |
3d5c84ff | 583 | cpu->id_aa64pfr0 &= ~0xf000; |
51942aee GB |
584 | } |
585 | ||
8f325f56 PC |
586 | if (!cpu->has_mpu) { |
587 | unset_feature(env, ARM_FEATURE_MPU); | |
588 | } | |
589 | ||
3281af81 PC |
590 | if (arm_feature(env, ARM_FEATURE_MPU) && |
591 | arm_feature(env, ARM_FEATURE_V7)) { | |
592 | uint32_t nr = cpu->pmsav7_dregion; | |
593 | ||
594 | if (nr > 0xff) { | |
595 | error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32 "\n", nr); | |
596 | return; | |
597 | } | |
6cb0b013 PC |
598 | |
599 | if (nr) { | |
600 | env->pmsav7.drbar = g_new0(uint32_t, nr); | |
601 | env->pmsav7.drsr = g_new0(uint32_t, nr); | |
602 | env->pmsav7.dracr = g_new0(uint32_t, nr); | |
603 | } | |
3281af81 PC |
604 | } |
605 | ||
2ceb98c0 | 606 | register_cp_regs_for_features(cpu); |
14969266 AF |
607 | arm_cpu_register_gdb_regs_for_features(cpu); |
608 | ||
721fae12 PM |
609 | init_cpreg_list(cpu); |
610 | ||
14a10fc3 | 611 | qemu_init_vcpu(cs); |
00d0f7cb | 612 | cpu_reset(cs); |
14969266 AF |
613 | |
614 | acc->parent_realize(dev, errp); | |
581be094 PM |
615 | } |
616 | ||
5900d6b2 AF |
617 | static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) |
618 | { | |
619 | ObjectClass *oc; | |
51492fd1 | 620 | char *typename; |
fb8d6c24 | 621 | char **cpuname; |
5900d6b2 AF |
622 | |
623 | if (!cpu_model) { | |
624 | return NULL; | |
625 | } | |
626 | ||
fb8d6c24 GB |
627 | cpuname = g_strsplit(cpu_model, ",", 1); |
628 | typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpuname[0]); | |
51492fd1 | 629 | oc = object_class_by_name(typename); |
fb8d6c24 | 630 | g_strfreev(cpuname); |
51492fd1 | 631 | g_free(typename); |
245fb54d AF |
632 | if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || |
633 | object_class_is_abstract(oc)) { | |
5900d6b2 AF |
634 | return NULL; |
635 | } | |
636 | return oc; | |
637 | } | |
638 | ||
15ee776b PM |
639 | /* CPU models. These are not needed for the AArch64 linux-user build. */ |
640 | #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) | |
641 | ||
777dc784 PM |
642 | static void arm926_initfn(Object *obj) |
643 | { | |
644 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
645 | |
646 | cpu->dtb_compatible = "arm,arm926"; | |
581be094 PM |
647 | set_feature(&cpu->env, ARM_FEATURE_V5); |
648 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
c4804214 PM |
649 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
650 | set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); | |
b2d06f96 | 651 | cpu->midr = 0x41069265; |
325b3cef | 652 | cpu->reset_fpsid = 0x41011090; |
64e1671f | 653 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 654 | cpu->reset_sctlr = 0x00090078; |
777dc784 PM |
655 | } |
656 | ||
657 | static void arm946_initfn(Object *obj) | |
658 | { | |
659 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
660 | |
661 | cpu->dtb_compatible = "arm,arm946"; | |
581be094 PM |
662 | set_feature(&cpu->env, ARM_FEATURE_V5); |
663 | set_feature(&cpu->env, ARM_FEATURE_MPU); | |
c4804214 | 664 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 665 | cpu->midr = 0x41059461; |
64e1671f | 666 | cpu->ctr = 0x0f004006; |
0ca7e01c | 667 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
668 | } |
669 | ||
670 | static void arm1026_initfn(Object *obj) | |
671 | { | |
672 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
673 | |
674 | cpu->dtb_compatible = "arm,arm1026"; | |
581be094 PM |
675 | set_feature(&cpu->env, ARM_FEATURE_V5); |
676 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
677 | set_feature(&cpu->env, ARM_FEATURE_AUXCR); | |
c4804214 PM |
678 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
679 | set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); | |
b2d06f96 | 680 | cpu->midr = 0x4106a262; |
325b3cef | 681 | cpu->reset_fpsid = 0x410110a0; |
64e1671f | 682 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 683 | cpu->reset_sctlr = 0x00090078; |
2771db27 | 684 | cpu->reset_auxcr = 1; |
06d76f31 PM |
685 | { |
686 | /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ | |
687 | ARMCPRegInfo ifar = { | |
688 | .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, | |
689 | .access = PL1_RW, | |
b848ce2b | 690 | .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), |
06d76f31 PM |
691 | .resetvalue = 0 |
692 | }; | |
693 | define_one_arm_cp_reg(cpu, &ifar); | |
694 | } | |
777dc784 PM |
695 | } |
696 | ||
697 | static void arm1136_r2_initfn(Object *obj) | |
698 | { | |
699 | ARMCPU *cpu = ARM_CPU(obj); | |
2e4d7e3e PM |
700 | /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an |
701 | * older core than plain "arm1136". In particular this does not | |
702 | * have the v6K features. | |
703 | * These ID register values are correct for 1136 but may be wrong | |
704 | * for 1136_r2 (in particular r0p2 does not actually implement most | |
705 | * of the ID registers). | |
706 | */ | |
54d3e3f5 PM |
707 | |
708 | cpu->dtb_compatible = "arm,arm1136"; | |
581be094 PM |
709 | set_feature(&cpu->env, ARM_FEATURE_V6); |
710 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
c4804214 PM |
711 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
712 | set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); | |
713 | set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); | |
b2d06f96 | 714 | cpu->midr = 0x4107b362; |
325b3cef | 715 | cpu->reset_fpsid = 0x410120b4; |
bd35c355 PM |
716 | cpu->mvfr0 = 0x11111111; |
717 | cpu->mvfr1 = 0x00000000; | |
64e1671f | 718 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 719 | cpu->reset_sctlr = 0x00050078; |
2e4d7e3e PM |
720 | cpu->id_pfr0 = 0x111; |
721 | cpu->id_pfr1 = 0x1; | |
722 | cpu->id_dfr0 = 0x2; | |
723 | cpu->id_afr0 = 0x3; | |
724 | cpu->id_mmfr0 = 0x01130003; | |
725 | cpu->id_mmfr1 = 0x10030302; | |
726 | cpu->id_mmfr2 = 0x01222110; | |
727 | cpu->id_isar0 = 0x00140011; | |
728 | cpu->id_isar1 = 0x12002111; | |
729 | cpu->id_isar2 = 0x11231111; | |
730 | cpu->id_isar3 = 0x01102131; | |
731 | cpu->id_isar4 = 0x141; | |
2771db27 | 732 | cpu->reset_auxcr = 7; |
777dc784 PM |
733 | } |
734 | ||
735 | static void arm1136_initfn(Object *obj) | |
736 | { | |
737 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
738 | |
739 | cpu->dtb_compatible = "arm,arm1136"; | |
581be094 PM |
740 | set_feature(&cpu->env, ARM_FEATURE_V6K); |
741 | set_feature(&cpu->env, ARM_FEATURE_V6); | |
742 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
c4804214 PM |
743 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
744 | set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); | |
745 | set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); | |
b2d06f96 | 746 | cpu->midr = 0x4117b363; |
325b3cef | 747 | cpu->reset_fpsid = 0x410120b4; |
bd35c355 PM |
748 | cpu->mvfr0 = 0x11111111; |
749 | cpu->mvfr1 = 0x00000000; | |
64e1671f | 750 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 751 | cpu->reset_sctlr = 0x00050078; |
2e4d7e3e PM |
752 | cpu->id_pfr0 = 0x111; |
753 | cpu->id_pfr1 = 0x1; | |
754 | cpu->id_dfr0 = 0x2; | |
755 | cpu->id_afr0 = 0x3; | |
756 | cpu->id_mmfr0 = 0x01130003; | |
757 | cpu->id_mmfr1 = 0x10030302; | |
758 | cpu->id_mmfr2 = 0x01222110; | |
759 | cpu->id_isar0 = 0x00140011; | |
760 | cpu->id_isar1 = 0x12002111; | |
761 | cpu->id_isar2 = 0x11231111; | |
762 | cpu->id_isar3 = 0x01102131; | |
763 | cpu->id_isar4 = 0x141; | |
2771db27 | 764 | cpu->reset_auxcr = 7; |
777dc784 PM |
765 | } |
766 | ||
767 | static void arm1176_initfn(Object *obj) | |
768 | { | |
769 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
770 | |
771 | cpu->dtb_compatible = "arm,arm1176"; | |
581be094 PM |
772 | set_feature(&cpu->env, ARM_FEATURE_V6K); |
773 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
774 | set_feature(&cpu->env, ARM_FEATURE_VAPA); | |
c4804214 PM |
775 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
776 | set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); | |
777 | set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); | |
c0ccb02d | 778 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
b2d06f96 | 779 | cpu->midr = 0x410fb767; |
325b3cef | 780 | cpu->reset_fpsid = 0x410120b5; |
bd35c355 PM |
781 | cpu->mvfr0 = 0x11111111; |
782 | cpu->mvfr1 = 0x00000000; | |
64e1671f | 783 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 784 | cpu->reset_sctlr = 0x00050078; |
2e4d7e3e PM |
785 | cpu->id_pfr0 = 0x111; |
786 | cpu->id_pfr1 = 0x11; | |
787 | cpu->id_dfr0 = 0x33; | |
788 | cpu->id_afr0 = 0; | |
789 | cpu->id_mmfr0 = 0x01130003; | |
790 | cpu->id_mmfr1 = 0x10030302; | |
791 | cpu->id_mmfr2 = 0x01222100; | |
792 | cpu->id_isar0 = 0x0140011; | |
793 | cpu->id_isar1 = 0x12002111; | |
794 | cpu->id_isar2 = 0x11231121; | |
795 | cpu->id_isar3 = 0x01102131; | |
796 | cpu->id_isar4 = 0x01141; | |
2771db27 | 797 | cpu->reset_auxcr = 7; |
777dc784 PM |
798 | } |
799 | ||
800 | static void arm11mpcore_initfn(Object *obj) | |
801 | { | |
802 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
803 | |
804 | cpu->dtb_compatible = "arm,arm11mpcore"; | |
581be094 PM |
805 | set_feature(&cpu->env, ARM_FEATURE_V6K); |
806 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
807 | set_feature(&cpu->env, ARM_FEATURE_VAPA); | |
81bdde9d | 808 | set_feature(&cpu->env, ARM_FEATURE_MPIDR); |
c4804214 | 809 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 810 | cpu->midr = 0x410fb022; |
325b3cef | 811 | cpu->reset_fpsid = 0x410120b4; |
bd35c355 PM |
812 | cpu->mvfr0 = 0x11111111; |
813 | cpu->mvfr1 = 0x00000000; | |
200bf596 | 814 | cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ |
2e4d7e3e PM |
815 | cpu->id_pfr0 = 0x111; |
816 | cpu->id_pfr1 = 0x1; | |
817 | cpu->id_dfr0 = 0; | |
818 | cpu->id_afr0 = 0x2; | |
819 | cpu->id_mmfr0 = 0x01100103; | |
820 | cpu->id_mmfr1 = 0x10020302; | |
821 | cpu->id_mmfr2 = 0x01222000; | |
822 | cpu->id_isar0 = 0x00100011; | |
823 | cpu->id_isar1 = 0x12002111; | |
824 | cpu->id_isar2 = 0x11221011; | |
825 | cpu->id_isar3 = 0x01102131; | |
826 | cpu->id_isar4 = 0x141; | |
2771db27 | 827 | cpu->reset_auxcr = 1; |
777dc784 PM |
828 | } |
829 | ||
830 | static void cortex_m3_initfn(Object *obj) | |
831 | { | |
832 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
833 | set_feature(&cpu->env, ARM_FEATURE_V7); |
834 | set_feature(&cpu->env, ARM_FEATURE_M); | |
b2d06f96 | 835 | cpu->midr = 0x410fc231; |
777dc784 PM |
836 | } |
837 | ||
ba890a9b AR |
838 | static void cortex_m4_initfn(Object *obj) |
839 | { | |
840 | ARMCPU *cpu = ARM_CPU(obj); | |
841 | ||
842 | set_feature(&cpu->env, ARM_FEATURE_V7); | |
843 | set_feature(&cpu->env, ARM_FEATURE_M); | |
844 | set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); | |
845 | cpu->midr = 0x410fc240; /* r0p0 */ | |
846 | } | |
e6f010cc AF |
847 | static void arm_v7m_class_init(ObjectClass *oc, void *data) |
848 | { | |
e6f010cc AF |
849 | CPUClass *cc = CPU_CLASS(oc); |
850 | ||
b5c633c5 | 851 | #ifndef CONFIG_USER_ONLY |
e6f010cc AF |
852 | cc->do_interrupt = arm_v7m_cpu_do_interrupt; |
853 | #endif | |
b5c633c5 PM |
854 | |
855 | cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; | |
e6f010cc AF |
856 | } |
857 | ||
d6a6b13e PC |
858 | static const ARMCPRegInfo cortexr5_cp_reginfo[] = { |
859 | /* Dummy the TCM region regs for the moment */ | |
860 | { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, | |
861 | .access = PL1_RW, .type = ARM_CP_CONST }, | |
862 | { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, | |
863 | .access = PL1_RW, .type = ARM_CP_CONST }, | |
864 | REGINFO_SENTINEL | |
865 | }; | |
866 | ||
867 | static void cortex_r5_initfn(Object *obj) | |
868 | { | |
869 | ARMCPU *cpu = ARM_CPU(obj); | |
870 | ||
871 | set_feature(&cpu->env, ARM_FEATURE_V7); | |
872 | set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV); | |
873 | set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); | |
874 | set_feature(&cpu->env, ARM_FEATURE_V7MP); | |
875 | set_feature(&cpu->env, ARM_FEATURE_MPU); | |
876 | cpu->midr = 0x411fc153; /* r1p3 */ | |
877 | cpu->id_pfr0 = 0x0131; | |
878 | cpu->id_pfr1 = 0x001; | |
879 | cpu->id_dfr0 = 0x010400; | |
880 | cpu->id_afr0 = 0x0; | |
881 | cpu->id_mmfr0 = 0x0210030; | |
882 | cpu->id_mmfr1 = 0x00000000; | |
883 | cpu->id_mmfr2 = 0x01200000; | |
884 | cpu->id_mmfr3 = 0x0211; | |
885 | cpu->id_isar0 = 0x2101111; | |
886 | cpu->id_isar1 = 0x13112111; | |
887 | cpu->id_isar2 = 0x21232141; | |
888 | cpu->id_isar3 = 0x01112131; | |
889 | cpu->id_isar4 = 0x0010142; | |
890 | cpu->id_isar5 = 0x0; | |
891 | cpu->mp_is_up = true; | |
892 | define_arm_cp_regs(cpu, cortexr5_cp_reginfo); | |
893 | } | |
894 | ||
34f90529 PM |
895 | static const ARMCPRegInfo cortexa8_cp_reginfo[] = { |
896 | { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, | |
897 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
898 | { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, | |
899 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
900 | REGINFO_SENTINEL | |
901 | }; | |
902 | ||
777dc784 PM |
903 | static void cortex_a8_initfn(Object *obj) |
904 | { | |
905 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
906 | |
907 | cpu->dtb_compatible = "arm,cortex-a8"; | |
581be094 PM |
908 | set_feature(&cpu->env, ARM_FEATURE_V7); |
909 | set_feature(&cpu->env, ARM_FEATURE_VFP3); | |
910 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
911 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
c4804214 | 912 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
c0ccb02d | 913 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
b2d06f96 | 914 | cpu->midr = 0x410fc080; |
325b3cef | 915 | cpu->reset_fpsid = 0x410330c0; |
bd35c355 PM |
916 | cpu->mvfr0 = 0x11110222; |
917 | cpu->mvfr1 = 0x00011100; | |
64e1671f | 918 | cpu->ctr = 0x82048004; |
0ca7e01c | 919 | cpu->reset_sctlr = 0x00c50078; |
2e4d7e3e PM |
920 | cpu->id_pfr0 = 0x1031; |
921 | cpu->id_pfr1 = 0x11; | |
922 | cpu->id_dfr0 = 0x400; | |
923 | cpu->id_afr0 = 0; | |
924 | cpu->id_mmfr0 = 0x31100003; | |
925 | cpu->id_mmfr1 = 0x20000000; | |
926 | cpu->id_mmfr2 = 0x01202000; | |
927 | cpu->id_mmfr3 = 0x11; | |
928 | cpu->id_isar0 = 0x00101111; | |
929 | cpu->id_isar1 = 0x12112111; | |
930 | cpu->id_isar2 = 0x21232031; | |
931 | cpu->id_isar3 = 0x11112131; | |
932 | cpu->id_isar4 = 0x00111142; | |
48eb3ae6 | 933 | cpu->dbgdidr = 0x15141000; |
85df3786 PM |
934 | cpu->clidr = (1 << 27) | (2 << 24) | 3; |
935 | cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ | |
936 | cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ | |
937 | cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ | |
2771db27 | 938 | cpu->reset_auxcr = 2; |
34f90529 | 939 | define_arm_cp_regs(cpu, cortexa8_cp_reginfo); |
777dc784 PM |
940 | } |
941 | ||
1047b9d7 PM |
942 | static const ARMCPRegInfo cortexa9_cp_reginfo[] = { |
943 | /* power_control should be set to maximum latency. Again, | |
944 | * default to 0 and set by private hook | |
945 | */ | |
946 | { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, | |
947 | .access = PL1_RW, .resetvalue = 0, | |
948 | .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, | |
949 | { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, | |
950 | .access = PL1_RW, .resetvalue = 0, | |
951 | .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, | |
952 | { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, | |
953 | .access = PL1_RW, .resetvalue = 0, | |
954 | .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, | |
955 | { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, | |
956 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
957 | /* TLB lockdown control */ | |
958 | { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, | |
959 | .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, | |
960 | { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, | |
961 | .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, | |
962 | { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, | |
963 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
964 | { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, | |
965 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
966 | { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, | |
967 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
968 | REGINFO_SENTINEL | |
969 | }; | |
970 | ||
777dc784 PM |
971 | static void cortex_a9_initfn(Object *obj) |
972 | { | |
973 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
974 | |
975 | cpu->dtb_compatible = "arm,cortex-a9"; | |
581be094 PM |
976 | set_feature(&cpu->env, ARM_FEATURE_V7); |
977 | set_feature(&cpu->env, ARM_FEATURE_VFP3); | |
978 | set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); | |
979 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
980 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
c0ccb02d | 981 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
581be094 PM |
982 | /* Note that A9 supports the MP extensions even for |
983 | * A9UP and single-core A9MP (which are both different | |
984 | * and valid configurations; we don't model A9UP). | |
985 | */ | |
986 | set_feature(&cpu->env, ARM_FEATURE_V7MP); | |
d8ba780b | 987 | set_feature(&cpu->env, ARM_FEATURE_CBAR); |
b2d06f96 | 988 | cpu->midr = 0x410fc090; |
325b3cef | 989 | cpu->reset_fpsid = 0x41033090; |
bd35c355 PM |
990 | cpu->mvfr0 = 0x11110222; |
991 | cpu->mvfr1 = 0x01111111; | |
64e1671f | 992 | cpu->ctr = 0x80038003; |
0ca7e01c | 993 | cpu->reset_sctlr = 0x00c50078; |
2e4d7e3e PM |
994 | cpu->id_pfr0 = 0x1031; |
995 | cpu->id_pfr1 = 0x11; | |
996 | cpu->id_dfr0 = 0x000; | |
997 | cpu->id_afr0 = 0; | |
998 | cpu->id_mmfr0 = 0x00100103; | |
999 | cpu->id_mmfr1 = 0x20000000; | |
1000 | cpu->id_mmfr2 = 0x01230000; | |
1001 | cpu->id_mmfr3 = 0x00002111; | |
1002 | cpu->id_isar0 = 0x00101111; | |
1003 | cpu->id_isar1 = 0x13112111; | |
1004 | cpu->id_isar2 = 0x21232041; | |
1005 | cpu->id_isar3 = 0x11112131; | |
1006 | cpu->id_isar4 = 0x00111142; | |
48eb3ae6 | 1007 | cpu->dbgdidr = 0x35141000; |
85df3786 | 1008 | cpu->clidr = (1 << 27) | (1 << 24) | 3; |
f7838b52 PC |
1009 | cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ |
1010 | cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ | |
d8ba780b | 1011 | define_arm_cp_regs(cpu, cortexa9_cp_reginfo); |
777dc784 PM |
1012 | } |
1013 | ||
34f90529 | 1014 | #ifndef CONFIG_USER_ONLY |
c4241c7d | 1015 | static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
34f90529 PM |
1016 | { |
1017 | /* Linux wants the number of processors from here. | |
1018 | * Might as well set the interrupt-controller bit too. | |
1019 | */ | |
c4241c7d | 1020 | return ((smp_cpus - 1) << 24) | (1 << 23); |
34f90529 PM |
1021 | } |
1022 | #endif | |
1023 | ||
1024 | static const ARMCPRegInfo cortexa15_cp_reginfo[] = { | |
1025 | #ifndef CONFIG_USER_ONLY | |
1026 | { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, | |
1027 | .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, | |
1028 | .writefn = arm_cp_write_ignore, }, | |
1029 | #endif | |
1030 | { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, | |
1031 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
1032 | REGINFO_SENTINEL | |
1033 | }; | |
1034 | ||
777dc784 PM |
1035 | static void cortex_a15_initfn(Object *obj) |
1036 | { | |
1037 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1038 | |
1039 | cpu->dtb_compatible = "arm,cortex-a15"; | |
581be094 PM |
1040 | set_feature(&cpu->env, ARM_FEATURE_V7); |
1041 | set_feature(&cpu->env, ARM_FEATURE_VFP4); | |
581be094 PM |
1042 | set_feature(&cpu->env, ARM_FEATURE_NEON); |
1043 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
1044 | set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); | |
581be094 | 1045 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); |
c4804214 | 1046 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
c29f9a0a | 1047 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); |
de9b05b8 | 1048 | set_feature(&cpu->env, ARM_FEATURE_LPAE); |
c0ccb02d | 1049 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
3541addc | 1050 | cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; |
b2d06f96 | 1051 | cpu->midr = 0x412fc0f1; |
325b3cef | 1052 | cpu->reset_fpsid = 0x410430f0; |
bd35c355 PM |
1053 | cpu->mvfr0 = 0x10110222; |
1054 | cpu->mvfr1 = 0x11111111; | |
64e1671f | 1055 | cpu->ctr = 0x8444c004; |
0ca7e01c | 1056 | cpu->reset_sctlr = 0x00c50078; |
2e4d7e3e PM |
1057 | cpu->id_pfr0 = 0x00001131; |
1058 | cpu->id_pfr1 = 0x00011011; | |
1059 | cpu->id_dfr0 = 0x02010555; | |
1060 | cpu->id_afr0 = 0x00000000; | |
1061 | cpu->id_mmfr0 = 0x10201105; | |
1062 | cpu->id_mmfr1 = 0x20000000; | |
1063 | cpu->id_mmfr2 = 0x01240000; | |
1064 | cpu->id_mmfr3 = 0x02102211; | |
1065 | cpu->id_isar0 = 0x02101110; | |
1066 | cpu->id_isar1 = 0x13112111; | |
1067 | cpu->id_isar2 = 0x21232041; | |
1068 | cpu->id_isar3 = 0x11112131; | |
1069 | cpu->id_isar4 = 0x10011142; | |
48eb3ae6 | 1070 | cpu->dbgdidr = 0x3515f021; |
85df3786 PM |
1071 | cpu->clidr = 0x0a200023; |
1072 | cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ | |
1073 | cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ | |
1074 | cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ | |
34f90529 | 1075 | define_arm_cp_regs(cpu, cortexa15_cp_reginfo); |
777dc784 PM |
1076 | } |
1077 | ||
1078 | static void ti925t_initfn(Object *obj) | |
1079 | { | |
1080 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
1081 | set_feature(&cpu->env, ARM_FEATURE_V4T); |
1082 | set_feature(&cpu->env, ARM_FEATURE_OMAPCP); | |
777dc784 | 1083 | cpu->midr = ARM_CPUID_TI925T; |
64e1671f | 1084 | cpu->ctr = 0x5109149; |
0ca7e01c | 1085 | cpu->reset_sctlr = 0x00000070; |
777dc784 PM |
1086 | } |
1087 | ||
1088 | static void sa1100_initfn(Object *obj) | |
1089 | { | |
1090 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1091 | |
1092 | cpu->dtb_compatible = "intel,sa1100"; | |
581be094 | 1093 | set_feature(&cpu->env, ARM_FEATURE_STRONGARM); |
c4804214 | 1094 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 1095 | cpu->midr = 0x4401A11B; |
0ca7e01c | 1096 | cpu->reset_sctlr = 0x00000070; |
777dc784 PM |
1097 | } |
1098 | ||
1099 | static void sa1110_initfn(Object *obj) | |
1100 | { | |
1101 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 | 1102 | set_feature(&cpu->env, ARM_FEATURE_STRONGARM); |
c4804214 | 1103 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 1104 | cpu->midr = 0x6901B119; |
0ca7e01c | 1105 | cpu->reset_sctlr = 0x00000070; |
777dc784 PM |
1106 | } |
1107 | ||
1108 | static void pxa250_initfn(Object *obj) | |
1109 | { | |
1110 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1111 | |
1112 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1113 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1114 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 1115 | cpu->midr = 0x69052100; |
64e1671f | 1116 | cpu->ctr = 0xd172172; |
0ca7e01c | 1117 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1118 | } |
1119 | ||
1120 | static void pxa255_initfn(Object *obj) | |
1121 | { | |
1122 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1123 | |
1124 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1125 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1126 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 1127 | cpu->midr = 0x69052d00; |
64e1671f | 1128 | cpu->ctr = 0xd172172; |
0ca7e01c | 1129 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1130 | } |
1131 | ||
1132 | static void pxa260_initfn(Object *obj) | |
1133 | { | |
1134 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1135 | |
1136 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1137 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1138 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 1139 | cpu->midr = 0x69052903; |
64e1671f | 1140 | cpu->ctr = 0xd172172; |
0ca7e01c | 1141 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1142 | } |
1143 | ||
1144 | static void pxa261_initfn(Object *obj) | |
1145 | { | |
1146 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1147 | |
1148 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1149 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1150 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 1151 | cpu->midr = 0x69052d05; |
64e1671f | 1152 | cpu->ctr = 0xd172172; |
0ca7e01c | 1153 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1154 | } |
1155 | ||
1156 | static void pxa262_initfn(Object *obj) | |
1157 | { | |
1158 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1159 | |
1160 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1161 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1162 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 1163 | cpu->midr = 0x69052d06; |
64e1671f | 1164 | cpu->ctr = 0xd172172; |
0ca7e01c | 1165 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1166 | } |
1167 | ||
1168 | static void pxa270a0_initfn(Object *obj) | |
1169 | { | |
1170 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1171 | |
1172 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1173 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1174 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
1175 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 1176 | cpu->midr = 0x69054110; |
64e1671f | 1177 | cpu->ctr = 0xd172172; |
0ca7e01c | 1178 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1179 | } |
1180 | ||
1181 | static void pxa270a1_initfn(Object *obj) | |
1182 | { | |
1183 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1184 | |
1185 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1186 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1187 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
1188 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 1189 | cpu->midr = 0x69054111; |
64e1671f | 1190 | cpu->ctr = 0xd172172; |
0ca7e01c | 1191 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1192 | } |
1193 | ||
1194 | static void pxa270b0_initfn(Object *obj) | |
1195 | { | |
1196 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1197 | |
1198 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1199 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1200 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
1201 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 1202 | cpu->midr = 0x69054112; |
64e1671f | 1203 | cpu->ctr = 0xd172172; |
0ca7e01c | 1204 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1205 | } |
1206 | ||
1207 | static void pxa270b1_initfn(Object *obj) | |
1208 | { | |
1209 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1210 | |
1211 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1212 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1213 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
1214 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 1215 | cpu->midr = 0x69054113; |
64e1671f | 1216 | cpu->ctr = 0xd172172; |
0ca7e01c | 1217 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1218 | } |
1219 | ||
1220 | static void pxa270c0_initfn(Object *obj) | |
1221 | { | |
1222 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1223 | |
1224 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1225 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1226 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
1227 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 1228 | cpu->midr = 0x69054114; |
64e1671f | 1229 | cpu->ctr = 0xd172172; |
0ca7e01c | 1230 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1231 | } |
1232 | ||
1233 | static void pxa270c5_initfn(Object *obj) | |
1234 | { | |
1235 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1236 | |
1237 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1238 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1239 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
1240 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 1241 | cpu->midr = 0x69054117; |
64e1671f | 1242 | cpu->ctr = 0xd172172; |
0ca7e01c | 1243 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1244 | } |
1245 | ||
f5f6d38b | 1246 | #ifdef CONFIG_USER_ONLY |
777dc784 PM |
1247 | static void arm_any_initfn(Object *obj) |
1248 | { | |
1249 | ARMCPU *cpu = ARM_CPU(obj); | |
81e69fb0 | 1250 | set_feature(&cpu->env, ARM_FEATURE_V8); |
581be094 | 1251 | set_feature(&cpu->env, ARM_FEATURE_VFP4); |
581be094 PM |
1252 | set_feature(&cpu->env, ARM_FEATURE_NEON); |
1253 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
25f748e3 PM |
1254 | set_feature(&cpu->env, ARM_FEATURE_V8_AES); |
1255 | set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); | |
1256 | set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); | |
1257 | set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); | |
eb0ecd5a | 1258 | set_feature(&cpu->env, ARM_FEATURE_CRC); |
b2d06f96 | 1259 | cpu->midr = 0xffffffff; |
777dc784 | 1260 | } |
f5f6d38b | 1261 | #endif |
777dc784 | 1262 | |
15ee776b PM |
1263 | #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ |
1264 | ||
777dc784 PM |
1265 | typedef struct ARMCPUInfo { |
1266 | const char *name; | |
1267 | void (*initfn)(Object *obj); | |
e6f010cc | 1268 | void (*class_init)(ObjectClass *oc, void *data); |
777dc784 PM |
1269 | } ARMCPUInfo; |
1270 | ||
1271 | static const ARMCPUInfo arm_cpus[] = { | |
15ee776b | 1272 | #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) |
777dc784 PM |
1273 | { .name = "arm926", .initfn = arm926_initfn }, |
1274 | { .name = "arm946", .initfn = arm946_initfn }, | |
1275 | { .name = "arm1026", .initfn = arm1026_initfn }, | |
1276 | /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an | |
1277 | * older core than plain "arm1136". In particular this does not | |
1278 | * have the v6K features. | |
1279 | */ | |
1280 | { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, | |
1281 | { .name = "arm1136", .initfn = arm1136_initfn }, | |
1282 | { .name = "arm1176", .initfn = arm1176_initfn }, | |
1283 | { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, | |
e6f010cc AF |
1284 | { .name = "cortex-m3", .initfn = cortex_m3_initfn, |
1285 | .class_init = arm_v7m_class_init }, | |
ba890a9b AR |
1286 | { .name = "cortex-m4", .initfn = cortex_m4_initfn, |
1287 | .class_init = arm_v7m_class_init }, | |
d6a6b13e | 1288 | { .name = "cortex-r5", .initfn = cortex_r5_initfn }, |
777dc784 PM |
1289 | { .name = "cortex-a8", .initfn = cortex_a8_initfn }, |
1290 | { .name = "cortex-a9", .initfn = cortex_a9_initfn }, | |
1291 | { .name = "cortex-a15", .initfn = cortex_a15_initfn }, | |
1292 | { .name = "ti925t", .initfn = ti925t_initfn }, | |
1293 | { .name = "sa1100", .initfn = sa1100_initfn }, | |
1294 | { .name = "sa1110", .initfn = sa1110_initfn }, | |
1295 | { .name = "pxa250", .initfn = pxa250_initfn }, | |
1296 | { .name = "pxa255", .initfn = pxa255_initfn }, | |
1297 | { .name = "pxa260", .initfn = pxa260_initfn }, | |
1298 | { .name = "pxa261", .initfn = pxa261_initfn }, | |
1299 | { .name = "pxa262", .initfn = pxa262_initfn }, | |
1300 | /* "pxa270" is an alias for "pxa270-a0" */ | |
1301 | { .name = "pxa270", .initfn = pxa270a0_initfn }, | |
1302 | { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, | |
1303 | { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, | |
1304 | { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, | |
1305 | { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, | |
1306 | { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, | |
1307 | { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, | |
f5f6d38b | 1308 | #ifdef CONFIG_USER_ONLY |
777dc784 | 1309 | { .name = "any", .initfn = arm_any_initfn }, |
f5f6d38b | 1310 | #endif |
15ee776b | 1311 | #endif |
83e6813a | 1312 | { .name = NULL } |
777dc784 PM |
1313 | }; |
1314 | ||
5de16430 PM |
1315 | static Property arm_cpu_properties[] = { |
1316 | DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), | |
98128601 | 1317 | DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), |
51a9b04b | 1318 | DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), |
5de16430 PM |
1319 | DEFINE_PROP_END_OF_LIST() |
1320 | }; | |
1321 | ||
8c6084bf PM |
1322 | #ifdef CONFIG_USER_ONLY |
1323 | static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, | |
1324 | int mmu_idx) | |
1325 | { | |
1326 | ARMCPU *cpu = ARM_CPU(cs); | |
1327 | CPUARMState *env = &cpu->env; | |
1328 | ||
1329 | env->exception.vaddress = address; | |
1330 | if (rw == 2) { | |
1331 | cs->exception_index = EXCP_PREFETCH_ABORT; | |
1332 | } else { | |
1333 | cs->exception_index = EXCP_DATA_ABORT; | |
1334 | } | |
1335 | return 1; | |
1336 | } | |
1337 | #endif | |
1338 | ||
dec9c2d4 AF |
1339 | static void arm_cpu_class_init(ObjectClass *oc, void *data) |
1340 | { | |
1341 | ARMCPUClass *acc = ARM_CPU_CLASS(oc); | |
1342 | CPUClass *cc = CPU_CLASS(acc); | |
14969266 AF |
1343 | DeviceClass *dc = DEVICE_CLASS(oc); |
1344 | ||
1345 | acc->parent_realize = dc->realize; | |
1346 | dc->realize = arm_cpu_realizefn; | |
5de16430 | 1347 | dc->props = arm_cpu_properties; |
dec9c2d4 AF |
1348 | |
1349 | acc->parent_reset = cc->reset; | |
1350 | cc->reset = arm_cpu_reset; | |
5900d6b2 AF |
1351 | |
1352 | cc->class_by_name = arm_cpu_class_by_name; | |
8c2e1b00 | 1353 | cc->has_work = arm_cpu_has_work; |
e8925712 | 1354 | cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; |
878096ee | 1355 | cc->dump_state = arm_cpu_dump_state; |
f45748f1 | 1356 | cc->set_pc = arm_cpu_set_pc; |
5b50e790 AF |
1357 | cc->gdb_read_register = arm_cpu_gdb_read_register; |
1358 | cc->gdb_write_register = arm_cpu_gdb_write_register; | |
7510454e AF |
1359 | #ifdef CONFIG_USER_ONLY |
1360 | cc->handle_mmu_fault = arm_cpu_handle_mmu_fault; | |
1361 | #else | |
0adf7d3c | 1362 | cc->do_interrupt = arm_cpu_do_interrupt; |
00b941e5 AF |
1363 | cc->get_phys_page_debug = arm_cpu_get_phys_page_debug; |
1364 | cc->vmsd = &vmstate_arm_cpu; | |
84f2bed3 | 1365 | cc->virtio_is_big_endian = arm_cpu_is_big_endian; |
00b941e5 | 1366 | #endif |
a0e372f0 | 1367 | cc->gdb_num_core_regs = 26; |
5b24c641 | 1368 | cc->gdb_core_xml_file = "arm-core.xml"; |
2472b6c0 | 1369 | cc->gdb_stop_before_watchpoint = true; |
3ff6fc91 | 1370 | cc->debug_excp_handler = arm_debug_excp_handler; |
dec9c2d4 AF |
1371 | } |
1372 | ||
777dc784 PM |
1373 | static void cpu_register(const ARMCPUInfo *info) |
1374 | { | |
1375 | TypeInfo type_info = { | |
777dc784 PM |
1376 | .parent = TYPE_ARM_CPU, |
1377 | .instance_size = sizeof(ARMCPU), | |
1378 | .instance_init = info->initfn, | |
1379 | .class_size = sizeof(ARMCPUClass), | |
e6f010cc | 1380 | .class_init = info->class_init, |
777dc784 PM |
1381 | }; |
1382 | ||
51492fd1 | 1383 | type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); |
918fd083 | 1384 | type_register(&type_info); |
51492fd1 | 1385 | g_free((void *)type_info.name); |
777dc784 PM |
1386 | } |
1387 | ||
dec9c2d4 AF |
1388 | static const TypeInfo arm_cpu_type_info = { |
1389 | .name = TYPE_ARM_CPU, | |
1390 | .parent = TYPE_CPU, | |
1391 | .instance_size = sizeof(ARMCPU), | |
777dc784 | 1392 | .instance_init = arm_cpu_initfn, |
07a5b0d2 | 1393 | .instance_post_init = arm_cpu_post_init, |
4b6a83fb | 1394 | .instance_finalize = arm_cpu_finalizefn, |
777dc784 | 1395 | .abstract = true, |
dec9c2d4 AF |
1396 | .class_size = sizeof(ARMCPUClass), |
1397 | .class_init = arm_cpu_class_init, | |
1398 | }; | |
1399 | ||
1400 | static void arm_cpu_register_types(void) | |
1401 | { | |
83e6813a | 1402 | const ARMCPUInfo *info = arm_cpus; |
777dc784 | 1403 | |
dec9c2d4 | 1404 | type_register_static(&arm_cpu_type_info); |
83e6813a PM |
1405 | |
1406 | while (info->name) { | |
1407 | cpu_register(info); | |
1408 | info++; | |
777dc784 | 1409 | } |
dec9c2d4 AF |
1410 | } |
1411 | ||
1412 | type_init(arm_cpu_register_types) |