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dec9c2d4 AF |
1 | /* |
2 | * QEMU ARM CPU | |
3 | * | |
4 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | */ | |
20 | ||
74c21bd0 | 21 | #include "qemu/osdep.h" |
da34e65c | 22 | #include "qapi/error.h" |
778c3a06 | 23 | #include "cpu.h" |
ccd38087 | 24 | #include "internals.h" |
dec9c2d4 | 25 | #include "qemu-common.h" |
5de16430 | 26 | #include "hw/qdev-properties.h" |
3c30dd5a PM |
27 | #if !defined(CONFIG_USER_ONLY) |
28 | #include "hw/loader.h" | |
29 | #endif | |
7c1840b6 | 30 | #include "hw/arm/arm.h" |
9c17d615 | 31 | #include "sysemu/sysemu.h" |
7c1840b6 | 32 | #include "sysemu/kvm.h" |
50a2c6e5 | 33 | #include "kvm_arm.h" |
dec9c2d4 | 34 | |
f45748f1 AF |
35 | static void arm_cpu_set_pc(CPUState *cs, vaddr value) |
36 | { | |
37 | ARMCPU *cpu = ARM_CPU(cs); | |
38 | ||
39 | cpu->env.regs[15] = value; | |
40 | } | |
41 | ||
8c2e1b00 AF |
42 | static bool arm_cpu_has_work(CPUState *cs) |
43 | { | |
543486db RH |
44 | ARMCPU *cpu = ARM_CPU(cs); |
45 | ||
46 | return !cpu->powered_off | |
47 | && cs->interrupt_request & | |
136e67e9 EI |
48 | (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD |
49 | | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | |
50 | | CPU_INTERRUPT_EXITTB); | |
8c2e1b00 AF |
51 | } |
52 | ||
4b6a83fb PM |
53 | static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) |
54 | { | |
55 | /* Reset a single ARMCPRegInfo register */ | |
56 | ARMCPRegInfo *ri = value; | |
57 | ARMCPU *cpu = opaque; | |
58 | ||
b061a82b | 59 | if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { |
4b6a83fb PM |
60 | return; |
61 | } | |
62 | ||
63 | if (ri->resetfn) { | |
64 | ri->resetfn(&cpu->env, ri); | |
65 | return; | |
66 | } | |
67 | ||
68 | /* A zero offset is never possible as it would be regs[0] | |
69 | * so we use it to indicate that reset is being handled elsewhere. | |
70 | * This is basically only used for fields in non-core coprocessors | |
71 | * (like the pxa2xx ones). | |
72 | */ | |
73 | if (!ri->fieldoffset) { | |
74 | return; | |
75 | } | |
76 | ||
67ed771d | 77 | if (cpreg_field_is_64bit(ri)) { |
4b6a83fb PM |
78 | CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; |
79 | } else { | |
80 | CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; | |
81 | } | |
82 | } | |
83 | ||
49a66191 PM |
84 | static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) |
85 | { | |
86 | /* Purely an assertion check: we've already done reset once, | |
87 | * so now check that running the reset for the cpreg doesn't | |
88 | * change its value. This traps bugs where two different cpregs | |
89 | * both try to reset the same state field but to different values. | |
90 | */ | |
91 | ARMCPRegInfo *ri = value; | |
92 | ARMCPU *cpu = opaque; | |
93 | uint64_t oldvalue, newvalue; | |
94 | ||
95 | if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { | |
96 | return; | |
97 | } | |
98 | ||
99 | oldvalue = read_raw_cp_reg(&cpu->env, ri); | |
100 | cp_reg_reset(key, value, opaque); | |
101 | newvalue = read_raw_cp_reg(&cpu->env, ri); | |
102 | assert(oldvalue == newvalue); | |
103 | } | |
104 | ||
dec9c2d4 AF |
105 | /* CPUClass::reset() */ |
106 | static void arm_cpu_reset(CPUState *s) | |
107 | { | |
108 | ARMCPU *cpu = ARM_CPU(s); | |
109 | ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); | |
3c30dd5a | 110 | CPUARMState *env = &cpu->env; |
3c30dd5a | 111 | |
dec9c2d4 AF |
112 | acc->parent_reset(s); |
113 | ||
f0c3c505 | 114 | memset(env, 0, offsetof(CPUARMState, features)); |
4b6a83fb | 115 | g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); |
49a66191 PM |
116 | g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); |
117 | ||
3c30dd5a PM |
118 | env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; |
119 | env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; | |
120 | env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; | |
a50c0f51 | 121 | env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2; |
3c30dd5a | 122 | |
543486db RH |
123 | cpu->powered_off = cpu->start_powered_off; |
124 | s->halted = cpu->start_powered_off; | |
125 | ||
3c30dd5a PM |
126 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { |
127 | env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; | |
128 | } | |
129 | ||
3926cc84 AG |
130 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { |
131 | /* 64 bit CPUs always start in 64 bit mode */ | |
132 | env->aarch64 = 1; | |
d356312f PM |
133 | #if defined(CONFIG_USER_ONLY) |
134 | env->pstate = PSTATE_MODE_EL0t; | |
14e5f106 | 135 | /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ |
137feaa9 | 136 | env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; |
8c6afa6a | 137 | /* and to the FP/Neon instructions */ |
7ebd5f2e | 138 | env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); |
d356312f | 139 | #else |
5097227c GB |
140 | /* Reset into the highest available EL */ |
141 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
142 | env->pstate = PSTATE_MODE_EL3h; | |
143 | } else if (arm_feature(env, ARM_FEATURE_EL2)) { | |
144 | env->pstate = PSTATE_MODE_EL2h; | |
145 | } else { | |
146 | env->pstate = PSTATE_MODE_EL1h; | |
147 | } | |
3933443e | 148 | env->pc = cpu->rvbar; |
8c6afa6a PM |
149 | #endif |
150 | } else { | |
151 | #if defined(CONFIG_USER_ONLY) | |
152 | /* Userspace expects access to cp10 and cp11 for FP/Neon */ | |
7ebd5f2e | 153 | env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); |
d356312f | 154 | #endif |
3926cc84 AG |
155 | } |
156 | ||
3c30dd5a PM |
157 | #if defined(CONFIG_USER_ONLY) |
158 | env->uncached_cpsr = ARM_CPU_MODE_USR; | |
159 | /* For user mode we must enable access to coprocessors */ | |
160 | env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; | |
161 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { | |
162 | env->cp15.c15_cpar = 3; | |
163 | } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
164 | env->cp15.c15_cpar = 1; | |
165 | } | |
166 | #else | |
167 | /* SVC mode with interrupts disabled. */ | |
4cc35614 PM |
168 | env->uncached_cpsr = ARM_CPU_MODE_SVC; |
169 | env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; | |
3c30dd5a | 170 | /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is |
6e3cf5df MG |
171 | * clear at reset. Initial SP and PC are loaded from ROM. |
172 | */ | |
3c30dd5a | 173 | if (IS_M(env)) { |
6e3cf5df MG |
174 | uint32_t initial_msp; /* Loaded from 0x0 */ |
175 | uint32_t initial_pc; /* Loaded from 0x4 */ | |
3c30dd5a | 176 | uint8_t *rom; |
6e3cf5df | 177 | |
4cc35614 | 178 | env->daif &= ~PSTATE_I; |
3c30dd5a PM |
179 | rom = rom_ptr(0); |
180 | if (rom) { | |
6e3cf5df MG |
181 | /* Address zero is covered by ROM which hasn't yet been |
182 | * copied into physical memory. | |
183 | */ | |
184 | initial_msp = ldl_p(rom); | |
185 | initial_pc = ldl_p(rom + 4); | |
186 | } else { | |
187 | /* Address zero not covered by a ROM blob, or the ROM blob | |
188 | * is in non-modifiable memory and this is a second reset after | |
189 | * it got copied into memory. In the latter case, rom_ptr | |
190 | * will return a NULL pointer and we should use ldl_phys instead. | |
191 | */ | |
192 | initial_msp = ldl_phys(s->as, 0); | |
193 | initial_pc = ldl_phys(s->as, 4); | |
3c30dd5a | 194 | } |
6e3cf5df MG |
195 | |
196 | env->regs[13] = initial_msp & 0xFFFFFFFC; | |
197 | env->regs[15] = initial_pc & ~1; | |
198 | env->thumb = initial_pc & 1; | |
3c30dd5a | 199 | } |
387f9806 | 200 | |
137feaa9 FA |
201 | /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently |
202 | * executing as AArch32 then check if highvecs are enabled and | |
203 | * adjust the PC accordingly. | |
204 | */ | |
205 | if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { | |
34bf7744 | 206 | env->regs[15] = 0xFFFF0000; |
387f9806 AP |
207 | } |
208 | ||
3c30dd5a | 209 | env->vfp.xregs[ARM_VFP_FPEXC] = 0; |
3c30dd5a PM |
210 | #endif |
211 | set_flush_to_zero(1, &env->vfp.standard_fp_status); | |
212 | set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); | |
213 | set_default_nan_mode(1, &env->vfp.standard_fp_status); | |
214 | set_float_detect_tininess(float_tininess_before_rounding, | |
215 | &env->vfp.fp_status); | |
216 | set_float_detect_tininess(float_tininess_before_rounding, | |
217 | &env->vfp.standard_fp_status); | |
00c8cb0a | 218 | tlb_flush(s, 1); |
50a2c6e5 PB |
219 | |
220 | #ifndef CONFIG_USER_ONLY | |
221 | if (kvm_enabled()) { | |
222 | kvm_arm_reset_vcpu(cpu); | |
223 | } | |
224 | #endif | |
9ee98ce8 | 225 | |
46747d15 | 226 | hw_breakpoint_update_all(cpu); |
9ee98ce8 | 227 | hw_watchpoint_update_all(cpu); |
dec9c2d4 AF |
228 | } |
229 | ||
e8925712 RH |
230 | bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) |
231 | { | |
232 | CPUClass *cc = CPU_GET_CLASS(cs); | |
012a906b GB |
233 | CPUARMState *env = cs->env_ptr; |
234 | uint32_t cur_el = arm_current_el(env); | |
235 | bool secure = arm_is_secure(env); | |
236 | uint32_t target_el; | |
237 | uint32_t excp_idx; | |
e8925712 RH |
238 | bool ret = false; |
239 | ||
012a906b GB |
240 | if (interrupt_request & CPU_INTERRUPT_FIQ) { |
241 | excp_idx = EXCP_FIQ; | |
242 | target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); | |
243 | if (arm_excp_unmasked(cs, excp_idx, target_el)) { | |
244 | cs->exception_index = excp_idx; | |
245 | env->exception.target_el = target_el; | |
246 | cc->do_interrupt(cs); | |
247 | ret = true; | |
248 | } | |
e8925712 | 249 | } |
012a906b GB |
250 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
251 | excp_idx = EXCP_IRQ; | |
252 | target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); | |
253 | if (arm_excp_unmasked(cs, excp_idx, target_el)) { | |
254 | cs->exception_index = excp_idx; | |
255 | env->exception.target_el = target_el; | |
256 | cc->do_interrupt(cs); | |
257 | ret = true; | |
258 | } | |
e8925712 | 259 | } |
012a906b GB |
260 | if (interrupt_request & CPU_INTERRUPT_VIRQ) { |
261 | excp_idx = EXCP_VIRQ; | |
262 | target_el = 1; | |
263 | if (arm_excp_unmasked(cs, excp_idx, target_el)) { | |
264 | cs->exception_index = excp_idx; | |
265 | env->exception.target_el = target_el; | |
266 | cc->do_interrupt(cs); | |
267 | ret = true; | |
268 | } | |
136e67e9 | 269 | } |
012a906b GB |
270 | if (interrupt_request & CPU_INTERRUPT_VFIQ) { |
271 | excp_idx = EXCP_VFIQ; | |
272 | target_el = 1; | |
273 | if (arm_excp_unmasked(cs, excp_idx, target_el)) { | |
274 | cs->exception_index = excp_idx; | |
275 | env->exception.target_el = target_el; | |
276 | cc->do_interrupt(cs); | |
277 | ret = true; | |
278 | } | |
136e67e9 | 279 | } |
e8925712 RH |
280 | |
281 | return ret; | |
282 | } | |
283 | ||
b5c633c5 PM |
284 | #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) |
285 | static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) | |
286 | { | |
287 | CPUClass *cc = CPU_GET_CLASS(cs); | |
288 | ARMCPU *cpu = ARM_CPU(cs); | |
289 | CPUARMState *env = &cpu->env; | |
290 | bool ret = false; | |
291 | ||
292 | ||
293 | if (interrupt_request & CPU_INTERRUPT_FIQ | |
294 | && !(env->daif & PSTATE_F)) { | |
295 | cs->exception_index = EXCP_FIQ; | |
296 | cc->do_interrupt(cs); | |
297 | ret = true; | |
298 | } | |
299 | /* ARMv7-M interrupt return works by loading a magic value | |
300 | * into the PC. On real hardware the load causes the | |
301 | * return to occur. The qemu implementation performs the | |
302 | * jump normally, then does the exception return when the | |
303 | * CPU tries to execute code at the magic address. | |
304 | * This will cause the magic PC value to be pushed to | |
305 | * the stack if an interrupt occurred at the wrong time. | |
306 | * We avoid this by disabling interrupts when | |
307 | * pc contains a magic address. | |
308 | */ | |
309 | if (interrupt_request & CPU_INTERRUPT_HARD | |
310 | && !(env->daif & PSTATE_I) | |
311 | && (env->regs[15] < 0xfffffff0)) { | |
312 | cs->exception_index = EXCP_IRQ; | |
313 | cc->do_interrupt(cs); | |
314 | ret = true; | |
315 | } | |
316 | return ret; | |
317 | } | |
318 | #endif | |
319 | ||
7c1840b6 PM |
320 | #ifndef CONFIG_USER_ONLY |
321 | static void arm_cpu_set_irq(void *opaque, int irq, int level) | |
322 | { | |
323 | ARMCPU *cpu = opaque; | |
136e67e9 | 324 | CPUARMState *env = &cpu->env; |
7c1840b6 | 325 | CPUState *cs = CPU(cpu); |
136e67e9 EI |
326 | static const int mask[] = { |
327 | [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, | |
328 | [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, | |
329 | [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, | |
330 | [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ | |
331 | }; | |
7c1840b6 PM |
332 | |
333 | switch (irq) { | |
136e67e9 EI |
334 | case ARM_CPU_VIRQ: |
335 | case ARM_CPU_VFIQ: | |
f128bf29 | 336 | assert(arm_feature(env, ARM_FEATURE_EL2)); |
136e67e9 EI |
337 | /* fall through */ |
338 | case ARM_CPU_IRQ: | |
7c1840b6 PM |
339 | case ARM_CPU_FIQ: |
340 | if (level) { | |
136e67e9 | 341 | cpu_interrupt(cs, mask[irq]); |
7c1840b6 | 342 | } else { |
136e67e9 | 343 | cpu_reset_interrupt(cs, mask[irq]); |
7c1840b6 PM |
344 | } |
345 | break; | |
346 | default: | |
8f6fd322 | 347 | g_assert_not_reached(); |
7c1840b6 PM |
348 | } |
349 | } | |
350 | ||
351 | static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) | |
352 | { | |
353 | #ifdef CONFIG_KVM | |
354 | ARMCPU *cpu = opaque; | |
355 | CPUState *cs = CPU(cpu); | |
356 | int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT; | |
357 | ||
358 | switch (irq) { | |
359 | case ARM_CPU_IRQ: | |
360 | kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; | |
361 | break; | |
362 | case ARM_CPU_FIQ: | |
363 | kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; | |
364 | break; | |
365 | default: | |
8f6fd322 | 366 | g_assert_not_reached(); |
7c1840b6 PM |
367 | } |
368 | kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; | |
369 | kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); | |
370 | #endif | |
371 | } | |
84f2bed3 | 372 | |
ed50ff78 | 373 | static bool arm_cpu_virtio_is_big_endian(CPUState *cs) |
84f2bed3 PS |
374 | { |
375 | ARMCPU *cpu = ARM_CPU(cs); | |
376 | CPUARMState *env = &cpu->env; | |
84f2bed3 PS |
377 | |
378 | cpu_synchronize_state(cs); | |
ed50ff78 | 379 | return arm_cpu_data_is_big_endian(env); |
84f2bed3 PS |
380 | } |
381 | ||
7c1840b6 PM |
382 | #endif |
383 | ||
581be094 PM |
384 | static inline void set_feature(CPUARMState *env, int feature) |
385 | { | |
918f5dca | 386 | env->features |= 1ULL << feature; |
581be094 PM |
387 | } |
388 | ||
08828484 GB |
389 | static inline void unset_feature(CPUARMState *env, int feature) |
390 | { | |
391 | env->features &= ~(1ULL << feature); | |
392 | } | |
393 | ||
48440620 PC |
394 | static int |
395 | print_insn_thumb1(bfd_vma pc, disassemble_info *info) | |
396 | { | |
397 | return print_insn_arm(pc | 1, info); | |
398 | } | |
399 | ||
400 | static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) | |
401 | { | |
402 | ARMCPU *ac = ARM_CPU(cpu); | |
403 | CPUARMState *env = &ac->env; | |
404 | ||
405 | if (is_a64(env)) { | |
406 | /* We might not be compiled with the A64 disassembler | |
407 | * because it needs a C++ compiler. Leave print_insn | |
408 | * unset in this case to use the caller default behaviour. | |
409 | */ | |
410 | #if defined(CONFIG_ARM_A64_DIS) | |
411 | info->print_insn = print_insn_arm_a64; | |
412 | #endif | |
413 | } else if (env->thumb) { | |
414 | info->print_insn = print_insn_thumb1; | |
415 | } else { | |
416 | info->print_insn = print_insn_arm; | |
417 | } | |
f9fd40eb | 418 | if (bswap_code(arm_sctlr_b(env))) { |
48440620 PC |
419 | #ifdef TARGET_WORDS_BIGENDIAN |
420 | info->endian = BFD_ENDIAN_LITTLE; | |
421 | #else | |
422 | info->endian = BFD_ENDIAN_BIG; | |
423 | #endif | |
424 | } | |
425 | } | |
426 | ||
eb5e1d3c PF |
427 | #define ARM_CPUS_PER_CLUSTER 8 |
428 | ||
777dc784 PM |
429 | static void arm_cpu_initfn(Object *obj) |
430 | { | |
c05efcb1 | 431 | CPUState *cs = CPU(obj); |
777dc784 | 432 | ARMCPU *cpu = ARM_CPU(obj); |
79614b78 | 433 | static bool inited; |
eb5e1d3c | 434 | uint32_t Aff1, Aff0; |
777dc784 | 435 | |
c05efcb1 | 436 | cs->env_ptr = &cpu->env; |
4bad9e39 | 437 | cpu_exec_init(cs, &error_abort); |
4b6a83fb PM |
438 | cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, |
439 | g_free, g_free); | |
79614b78 | 440 | |
eb5e1d3c PF |
441 | /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. |
442 | * We don't support setting cluster ID ([16..23]) (known as Aff2 | |
443 | * in later ARM ARM versions), or any of the higher affinity level fields, | |
444 | * so these bits always RAZ. | |
445 | */ | |
446 | Aff1 = cs->cpu_index / ARM_CPUS_PER_CLUSTER; | |
447 | Aff0 = cs->cpu_index % ARM_CPUS_PER_CLUSTER; | |
0f4a9e45 | 448 | cpu->mp_affinity = (Aff1 << ARM_AFF1_SHIFT) | Aff0; |
eb5e1d3c | 449 | |
7c1840b6 PM |
450 | #ifndef CONFIG_USER_ONLY |
451 | /* Our inbound IRQ and FIQ lines */ | |
452 | if (kvm_enabled()) { | |
136e67e9 EI |
453 | /* VIRQ and VFIQ are unused with KVM but we add them to maintain |
454 | * the same interface as non-KVM CPUs. | |
455 | */ | |
456 | qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); | |
7c1840b6 | 457 | } else { |
136e67e9 | 458 | qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); |
7c1840b6 | 459 | } |
55d284af | 460 | |
bc72ad67 | 461 | cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, |
55d284af | 462 | arm_gt_ptimer_cb, cpu); |
bc72ad67 | 463 | cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, |
55d284af | 464 | arm_gt_vtimer_cb, cpu); |
b0e66d95 EI |
465 | cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, |
466 | arm_gt_htimer_cb, cpu); | |
b4d3978c PM |
467 | cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, |
468 | arm_gt_stimer_cb, cpu); | |
55d284af PM |
469 | qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, |
470 | ARRAY_SIZE(cpu->gt_timer_outputs)); | |
7c1840b6 PM |
471 | #endif |
472 | ||
54d3e3f5 PM |
473 | /* DTB consumers generally don't in fact care what the 'compatible' |
474 | * string is, so always provide some string and trust that a hypothetical | |
475 | * picky DTB consumer will also provide a helpful error message. | |
476 | */ | |
477 | cpu->dtb_compatible = "qemu,unknown"; | |
dd032e34 | 478 | cpu->psci_version = 1; /* By default assume PSCI v0.1 */ |
3541addc | 479 | cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; |
54d3e3f5 | 480 | |
98128601 RH |
481 | if (tcg_enabled()) { |
482 | cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ | |
483 | if (!inited) { | |
484 | inited = true; | |
485 | arm_translate_init(); | |
486 | } | |
79614b78 | 487 | } |
4b6a83fb PM |
488 | } |
489 | ||
07a5b0d2 | 490 | static Property arm_cpu_reset_cbar_property = |
f318cec6 | 491 | DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); |
07a5b0d2 | 492 | |
68e0a40a AP |
493 | static Property arm_cpu_reset_hivecs_property = |
494 | DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); | |
495 | ||
3933443e PM |
496 | static Property arm_cpu_rvbar_property = |
497 | DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); | |
498 | ||
51942aee GB |
499 | static Property arm_cpu_has_el3_property = |
500 | DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); | |
501 | ||
8f325f56 PC |
502 | static Property arm_cpu_has_mpu_property = |
503 | DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); | |
504 | ||
3281af81 PC |
505 | static Property arm_cpu_pmsav7_dregion_property = |
506 | DEFINE_PROP_UINT32("pmsav7-dregion", ARMCPU, pmsav7_dregion, 16); | |
507 | ||
07a5b0d2 PC |
508 | static void arm_cpu_post_init(Object *obj) |
509 | { | |
510 | ARMCPU *cpu = ARM_CPU(obj); | |
07a5b0d2 | 511 | |
f318cec6 PM |
512 | if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || |
513 | arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { | |
07a5b0d2 | 514 | qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, |
5433a0a8 | 515 | &error_abort); |
07a5b0d2 | 516 | } |
68e0a40a AP |
517 | |
518 | if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { | |
519 | qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property, | |
5433a0a8 | 520 | &error_abort); |
68e0a40a | 521 | } |
3933443e PM |
522 | |
523 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | |
524 | qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property, | |
525 | &error_abort); | |
526 | } | |
51942aee GB |
527 | |
528 | if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { | |
529 | /* Add the has_el3 state CPU property only if EL3 is allowed. This will | |
530 | * prevent "has_el3" from existing on CPUs which cannot support EL3. | |
531 | */ | |
532 | qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property, | |
533 | &error_abort); | |
9e273ef2 PM |
534 | |
535 | #ifndef CONFIG_USER_ONLY | |
536 | object_property_add_link(obj, "secure-memory", | |
537 | TYPE_MEMORY_REGION, | |
538 | (Object **)&cpu->secure_memory, | |
539 | qdev_prop_allow_set_link_before_realize, | |
540 | OBJ_PROP_LINK_UNREF_ON_RELEASE, | |
541 | &error_abort); | |
542 | #endif | |
51942aee | 543 | } |
8f325f56 PC |
544 | |
545 | if (arm_feature(&cpu->env, ARM_FEATURE_MPU)) { | |
546 | qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, | |
547 | &error_abort); | |
3281af81 PC |
548 | if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { |
549 | qdev_property_add_static(DEVICE(obj), | |
550 | &arm_cpu_pmsav7_dregion_property, | |
551 | &error_abort); | |
552 | } | |
8f325f56 PC |
553 | } |
554 | ||
07a5b0d2 PC |
555 | } |
556 | ||
4b6a83fb PM |
557 | static void arm_cpu_finalizefn(Object *obj) |
558 | { | |
559 | ARMCPU *cpu = ARM_CPU(obj); | |
560 | g_hash_table_destroy(cpu->cp_regs); | |
777dc784 PM |
561 | } |
562 | ||
14969266 | 563 | static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
581be094 | 564 | { |
14a10fc3 | 565 | CPUState *cs = CPU(dev); |
14969266 AF |
566 | ARMCPU *cpu = ARM_CPU(dev); |
567 | ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); | |
581be094 | 568 | CPUARMState *env = &cpu->env; |
14969266 | 569 | |
581be094 | 570 | /* Some features automatically imply others: */ |
81e69fb0 MR |
571 | if (arm_feature(env, ARM_FEATURE_V8)) { |
572 | set_feature(env, ARM_FEATURE_V7); | |
573 | set_feature(env, ARM_FEATURE_ARM_DIV); | |
574 | set_feature(env, ARM_FEATURE_LPAE); | |
575 | } | |
581be094 PM |
576 | if (arm_feature(env, ARM_FEATURE_V7)) { |
577 | set_feature(env, ARM_FEATURE_VAPA); | |
578 | set_feature(env, ARM_FEATURE_THUMB2); | |
81bdde9d | 579 | set_feature(env, ARM_FEATURE_MPIDR); |
581be094 PM |
580 | if (!arm_feature(env, ARM_FEATURE_M)) { |
581 | set_feature(env, ARM_FEATURE_V6K); | |
582 | } else { | |
583 | set_feature(env, ARM_FEATURE_V6); | |
584 | } | |
585 | } | |
586 | if (arm_feature(env, ARM_FEATURE_V6K)) { | |
587 | set_feature(env, ARM_FEATURE_V6); | |
588 | set_feature(env, ARM_FEATURE_MVFR); | |
589 | } | |
590 | if (arm_feature(env, ARM_FEATURE_V6)) { | |
591 | set_feature(env, ARM_FEATURE_V5); | |
592 | if (!arm_feature(env, ARM_FEATURE_M)) { | |
593 | set_feature(env, ARM_FEATURE_AUXCR); | |
594 | } | |
595 | } | |
596 | if (arm_feature(env, ARM_FEATURE_V5)) { | |
597 | set_feature(env, ARM_FEATURE_V4T); | |
598 | } | |
599 | if (arm_feature(env, ARM_FEATURE_M)) { | |
600 | set_feature(env, ARM_FEATURE_THUMB_DIV); | |
601 | } | |
602 | if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { | |
603 | set_feature(env, ARM_FEATURE_THUMB_DIV); | |
604 | } | |
605 | if (arm_feature(env, ARM_FEATURE_VFP4)) { | |
606 | set_feature(env, ARM_FEATURE_VFP3); | |
da5141fc | 607 | set_feature(env, ARM_FEATURE_VFP_FP16); |
581be094 PM |
608 | } |
609 | if (arm_feature(env, ARM_FEATURE_VFP3)) { | |
610 | set_feature(env, ARM_FEATURE_VFP); | |
611 | } | |
de9b05b8 | 612 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
bdcc150d | 613 | set_feature(env, ARM_FEATURE_V7MP); |
de9b05b8 PM |
614 | set_feature(env, ARM_FEATURE_PXN); |
615 | } | |
f318cec6 PM |
616 | if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { |
617 | set_feature(env, ARM_FEATURE_CBAR); | |
618 | } | |
62b44f05 AR |
619 | if (arm_feature(env, ARM_FEATURE_THUMB2) && |
620 | !arm_feature(env, ARM_FEATURE_M)) { | |
621 | set_feature(env, ARM_FEATURE_THUMB_DSP); | |
622 | } | |
2ceb98c0 | 623 | |
68e0a40a AP |
624 | if (cpu->reset_hivecs) { |
625 | cpu->reset_sctlr |= (1 << 13); | |
626 | } | |
627 | ||
51942aee GB |
628 | if (!cpu->has_el3) { |
629 | /* If the has_el3 CPU property is disabled then we need to disable the | |
630 | * feature. | |
631 | */ | |
632 | unset_feature(env, ARM_FEATURE_EL3); | |
633 | ||
634 | /* Disable the security extension feature bits in the processor feature | |
3d5c84ff | 635 | * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. |
51942aee GB |
636 | */ |
637 | cpu->id_pfr1 &= ~0xf0; | |
3d5c84ff | 638 | cpu->id_aa64pfr0 &= ~0xf000; |
51942aee GB |
639 | } |
640 | ||
3c2f7bb3 PM |
641 | if (!arm_feature(env, ARM_FEATURE_EL2)) { |
642 | /* Disable the hypervisor feature bits in the processor feature | |
643 | * registers if we don't have EL2. These are id_pfr1[15:12] and | |
644 | * id_aa64pfr0_el1[11:8]. | |
645 | */ | |
646 | cpu->id_aa64pfr0 &= ~0xf00; | |
647 | cpu->id_pfr1 &= ~0xf000; | |
648 | } | |
649 | ||
8f325f56 PC |
650 | if (!cpu->has_mpu) { |
651 | unset_feature(env, ARM_FEATURE_MPU); | |
652 | } | |
653 | ||
3281af81 PC |
654 | if (arm_feature(env, ARM_FEATURE_MPU) && |
655 | arm_feature(env, ARM_FEATURE_V7)) { | |
656 | uint32_t nr = cpu->pmsav7_dregion; | |
657 | ||
658 | if (nr > 0xff) { | |
9af9e0fe | 659 | error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); |
3281af81 PC |
660 | return; |
661 | } | |
6cb0b013 PC |
662 | |
663 | if (nr) { | |
664 | env->pmsav7.drbar = g_new0(uint32_t, nr); | |
665 | env->pmsav7.drsr = g_new0(uint32_t, nr); | |
666 | env->pmsav7.dracr = g_new0(uint32_t, nr); | |
667 | } | |
3281af81 PC |
668 | } |
669 | ||
2ceb98c0 | 670 | register_cp_regs_for_features(cpu); |
14969266 AF |
671 | arm_cpu_register_gdb_regs_for_features(cpu); |
672 | ||
721fae12 PM |
673 | init_cpreg_list(cpu); |
674 | ||
9e273ef2 PM |
675 | #ifndef CONFIG_USER_ONLY |
676 | if (cpu->has_el3) { | |
677 | cs->num_ases = 2; | |
678 | } else { | |
679 | cs->num_ases = 1; | |
680 | } | |
681 | ||
682 | if (cpu->has_el3) { | |
683 | AddressSpace *as; | |
684 | ||
685 | if (!cpu->secure_memory) { | |
686 | cpu->secure_memory = cs->memory; | |
687 | } | |
688 | as = address_space_init_shareable(cpu->secure_memory, | |
689 | "cpu-secure-memory"); | |
690 | cpu_address_space_init(cs, as, ARMASIdx_S); | |
691 | } | |
692 | cpu_address_space_init(cs, | |
693 | address_space_init_shareable(cs->memory, | |
694 | "cpu-memory"), | |
695 | ARMASIdx_NS); | |
696 | #endif | |
697 | ||
14a10fc3 | 698 | qemu_init_vcpu(cs); |
00d0f7cb | 699 | cpu_reset(cs); |
14969266 AF |
700 | |
701 | acc->parent_realize(dev, errp); | |
581be094 PM |
702 | } |
703 | ||
5900d6b2 AF |
704 | static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) |
705 | { | |
706 | ObjectClass *oc; | |
51492fd1 | 707 | char *typename; |
fb8d6c24 | 708 | char **cpuname; |
5900d6b2 AF |
709 | |
710 | if (!cpu_model) { | |
711 | return NULL; | |
712 | } | |
713 | ||
fb8d6c24 GB |
714 | cpuname = g_strsplit(cpu_model, ",", 1); |
715 | typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpuname[0]); | |
51492fd1 | 716 | oc = object_class_by_name(typename); |
fb8d6c24 | 717 | g_strfreev(cpuname); |
51492fd1 | 718 | g_free(typename); |
245fb54d AF |
719 | if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || |
720 | object_class_is_abstract(oc)) { | |
5900d6b2 AF |
721 | return NULL; |
722 | } | |
723 | return oc; | |
724 | } | |
725 | ||
15ee776b PM |
726 | /* CPU models. These are not needed for the AArch64 linux-user build. */ |
727 | #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) | |
728 | ||
777dc784 PM |
729 | static void arm926_initfn(Object *obj) |
730 | { | |
731 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
732 | |
733 | cpu->dtb_compatible = "arm,arm926"; | |
581be094 PM |
734 | set_feature(&cpu->env, ARM_FEATURE_V5); |
735 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
c4804214 PM |
736 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
737 | set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); | |
b2d06f96 | 738 | cpu->midr = 0x41069265; |
325b3cef | 739 | cpu->reset_fpsid = 0x41011090; |
64e1671f | 740 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 741 | cpu->reset_sctlr = 0x00090078; |
777dc784 PM |
742 | } |
743 | ||
744 | static void arm946_initfn(Object *obj) | |
745 | { | |
746 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
747 | |
748 | cpu->dtb_compatible = "arm,arm946"; | |
581be094 PM |
749 | set_feature(&cpu->env, ARM_FEATURE_V5); |
750 | set_feature(&cpu->env, ARM_FEATURE_MPU); | |
c4804214 | 751 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 752 | cpu->midr = 0x41059461; |
64e1671f | 753 | cpu->ctr = 0x0f004006; |
0ca7e01c | 754 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
755 | } |
756 | ||
757 | static void arm1026_initfn(Object *obj) | |
758 | { | |
759 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
760 | |
761 | cpu->dtb_compatible = "arm,arm1026"; | |
581be094 PM |
762 | set_feature(&cpu->env, ARM_FEATURE_V5); |
763 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
764 | set_feature(&cpu->env, ARM_FEATURE_AUXCR); | |
c4804214 PM |
765 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
766 | set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); | |
b2d06f96 | 767 | cpu->midr = 0x4106a262; |
325b3cef | 768 | cpu->reset_fpsid = 0x410110a0; |
64e1671f | 769 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 770 | cpu->reset_sctlr = 0x00090078; |
2771db27 | 771 | cpu->reset_auxcr = 1; |
06d76f31 PM |
772 | { |
773 | /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ | |
774 | ARMCPRegInfo ifar = { | |
775 | .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, | |
776 | .access = PL1_RW, | |
b848ce2b | 777 | .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), |
06d76f31 PM |
778 | .resetvalue = 0 |
779 | }; | |
780 | define_one_arm_cp_reg(cpu, &ifar); | |
781 | } | |
777dc784 PM |
782 | } |
783 | ||
784 | static void arm1136_r2_initfn(Object *obj) | |
785 | { | |
786 | ARMCPU *cpu = ARM_CPU(obj); | |
2e4d7e3e PM |
787 | /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an |
788 | * older core than plain "arm1136". In particular this does not | |
789 | * have the v6K features. | |
790 | * These ID register values are correct for 1136 but may be wrong | |
791 | * for 1136_r2 (in particular r0p2 does not actually implement most | |
792 | * of the ID registers). | |
793 | */ | |
54d3e3f5 PM |
794 | |
795 | cpu->dtb_compatible = "arm,arm1136"; | |
581be094 PM |
796 | set_feature(&cpu->env, ARM_FEATURE_V6); |
797 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
c4804214 PM |
798 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
799 | set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); | |
800 | set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); | |
b2d06f96 | 801 | cpu->midr = 0x4107b362; |
325b3cef | 802 | cpu->reset_fpsid = 0x410120b4; |
bd35c355 PM |
803 | cpu->mvfr0 = 0x11111111; |
804 | cpu->mvfr1 = 0x00000000; | |
64e1671f | 805 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 806 | cpu->reset_sctlr = 0x00050078; |
2e4d7e3e PM |
807 | cpu->id_pfr0 = 0x111; |
808 | cpu->id_pfr1 = 0x1; | |
809 | cpu->id_dfr0 = 0x2; | |
810 | cpu->id_afr0 = 0x3; | |
811 | cpu->id_mmfr0 = 0x01130003; | |
812 | cpu->id_mmfr1 = 0x10030302; | |
813 | cpu->id_mmfr2 = 0x01222110; | |
814 | cpu->id_isar0 = 0x00140011; | |
815 | cpu->id_isar1 = 0x12002111; | |
816 | cpu->id_isar2 = 0x11231111; | |
817 | cpu->id_isar3 = 0x01102131; | |
818 | cpu->id_isar4 = 0x141; | |
2771db27 | 819 | cpu->reset_auxcr = 7; |
777dc784 PM |
820 | } |
821 | ||
822 | static void arm1136_initfn(Object *obj) | |
823 | { | |
824 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
825 | |
826 | cpu->dtb_compatible = "arm,arm1136"; | |
581be094 PM |
827 | set_feature(&cpu->env, ARM_FEATURE_V6K); |
828 | set_feature(&cpu->env, ARM_FEATURE_V6); | |
829 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
c4804214 PM |
830 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
831 | set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); | |
832 | set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); | |
b2d06f96 | 833 | cpu->midr = 0x4117b363; |
325b3cef | 834 | cpu->reset_fpsid = 0x410120b4; |
bd35c355 PM |
835 | cpu->mvfr0 = 0x11111111; |
836 | cpu->mvfr1 = 0x00000000; | |
64e1671f | 837 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 838 | cpu->reset_sctlr = 0x00050078; |
2e4d7e3e PM |
839 | cpu->id_pfr0 = 0x111; |
840 | cpu->id_pfr1 = 0x1; | |
841 | cpu->id_dfr0 = 0x2; | |
842 | cpu->id_afr0 = 0x3; | |
843 | cpu->id_mmfr0 = 0x01130003; | |
844 | cpu->id_mmfr1 = 0x10030302; | |
845 | cpu->id_mmfr2 = 0x01222110; | |
846 | cpu->id_isar0 = 0x00140011; | |
847 | cpu->id_isar1 = 0x12002111; | |
848 | cpu->id_isar2 = 0x11231111; | |
849 | cpu->id_isar3 = 0x01102131; | |
850 | cpu->id_isar4 = 0x141; | |
2771db27 | 851 | cpu->reset_auxcr = 7; |
777dc784 PM |
852 | } |
853 | ||
854 | static void arm1176_initfn(Object *obj) | |
855 | { | |
856 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
857 | |
858 | cpu->dtb_compatible = "arm,arm1176"; | |
581be094 PM |
859 | set_feature(&cpu->env, ARM_FEATURE_V6K); |
860 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
861 | set_feature(&cpu->env, ARM_FEATURE_VAPA); | |
c4804214 PM |
862 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
863 | set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); | |
864 | set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); | |
c0ccb02d | 865 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
b2d06f96 | 866 | cpu->midr = 0x410fb767; |
325b3cef | 867 | cpu->reset_fpsid = 0x410120b5; |
bd35c355 PM |
868 | cpu->mvfr0 = 0x11111111; |
869 | cpu->mvfr1 = 0x00000000; | |
64e1671f | 870 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 871 | cpu->reset_sctlr = 0x00050078; |
2e4d7e3e PM |
872 | cpu->id_pfr0 = 0x111; |
873 | cpu->id_pfr1 = 0x11; | |
874 | cpu->id_dfr0 = 0x33; | |
875 | cpu->id_afr0 = 0; | |
876 | cpu->id_mmfr0 = 0x01130003; | |
877 | cpu->id_mmfr1 = 0x10030302; | |
878 | cpu->id_mmfr2 = 0x01222100; | |
879 | cpu->id_isar0 = 0x0140011; | |
880 | cpu->id_isar1 = 0x12002111; | |
881 | cpu->id_isar2 = 0x11231121; | |
882 | cpu->id_isar3 = 0x01102131; | |
883 | cpu->id_isar4 = 0x01141; | |
2771db27 | 884 | cpu->reset_auxcr = 7; |
777dc784 PM |
885 | } |
886 | ||
887 | static void arm11mpcore_initfn(Object *obj) | |
888 | { | |
889 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
890 | |
891 | cpu->dtb_compatible = "arm,arm11mpcore"; | |
581be094 PM |
892 | set_feature(&cpu->env, ARM_FEATURE_V6K); |
893 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
894 | set_feature(&cpu->env, ARM_FEATURE_VAPA); | |
81bdde9d | 895 | set_feature(&cpu->env, ARM_FEATURE_MPIDR); |
c4804214 | 896 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 897 | cpu->midr = 0x410fb022; |
325b3cef | 898 | cpu->reset_fpsid = 0x410120b4; |
bd35c355 PM |
899 | cpu->mvfr0 = 0x11111111; |
900 | cpu->mvfr1 = 0x00000000; | |
200bf596 | 901 | cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ |
2e4d7e3e PM |
902 | cpu->id_pfr0 = 0x111; |
903 | cpu->id_pfr1 = 0x1; | |
904 | cpu->id_dfr0 = 0; | |
905 | cpu->id_afr0 = 0x2; | |
906 | cpu->id_mmfr0 = 0x01100103; | |
907 | cpu->id_mmfr1 = 0x10020302; | |
908 | cpu->id_mmfr2 = 0x01222000; | |
909 | cpu->id_isar0 = 0x00100011; | |
910 | cpu->id_isar1 = 0x12002111; | |
911 | cpu->id_isar2 = 0x11221011; | |
912 | cpu->id_isar3 = 0x01102131; | |
913 | cpu->id_isar4 = 0x141; | |
2771db27 | 914 | cpu->reset_auxcr = 1; |
777dc784 PM |
915 | } |
916 | ||
917 | static void cortex_m3_initfn(Object *obj) | |
918 | { | |
919 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
920 | set_feature(&cpu->env, ARM_FEATURE_V7); |
921 | set_feature(&cpu->env, ARM_FEATURE_M); | |
b2d06f96 | 922 | cpu->midr = 0x410fc231; |
777dc784 PM |
923 | } |
924 | ||
ba890a9b AR |
925 | static void cortex_m4_initfn(Object *obj) |
926 | { | |
927 | ARMCPU *cpu = ARM_CPU(obj); | |
928 | ||
929 | set_feature(&cpu->env, ARM_FEATURE_V7); | |
930 | set_feature(&cpu->env, ARM_FEATURE_M); | |
931 | set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); | |
932 | cpu->midr = 0x410fc240; /* r0p0 */ | |
933 | } | |
e6f010cc AF |
934 | static void arm_v7m_class_init(ObjectClass *oc, void *data) |
935 | { | |
e6f010cc AF |
936 | CPUClass *cc = CPU_CLASS(oc); |
937 | ||
b5c633c5 | 938 | #ifndef CONFIG_USER_ONLY |
e6f010cc AF |
939 | cc->do_interrupt = arm_v7m_cpu_do_interrupt; |
940 | #endif | |
b5c633c5 PM |
941 | |
942 | cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; | |
e6f010cc AF |
943 | } |
944 | ||
d6a6b13e PC |
945 | static const ARMCPRegInfo cortexr5_cp_reginfo[] = { |
946 | /* Dummy the TCM region regs for the moment */ | |
947 | { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, | |
948 | .access = PL1_RW, .type = ARM_CP_CONST }, | |
949 | { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, | |
950 | .access = PL1_RW, .type = ARM_CP_CONST }, | |
951 | REGINFO_SENTINEL | |
952 | }; | |
953 | ||
954 | static void cortex_r5_initfn(Object *obj) | |
955 | { | |
956 | ARMCPU *cpu = ARM_CPU(obj); | |
957 | ||
958 | set_feature(&cpu->env, ARM_FEATURE_V7); | |
959 | set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV); | |
960 | set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); | |
961 | set_feature(&cpu->env, ARM_FEATURE_V7MP); | |
962 | set_feature(&cpu->env, ARM_FEATURE_MPU); | |
963 | cpu->midr = 0x411fc153; /* r1p3 */ | |
964 | cpu->id_pfr0 = 0x0131; | |
965 | cpu->id_pfr1 = 0x001; | |
966 | cpu->id_dfr0 = 0x010400; | |
967 | cpu->id_afr0 = 0x0; | |
968 | cpu->id_mmfr0 = 0x0210030; | |
969 | cpu->id_mmfr1 = 0x00000000; | |
970 | cpu->id_mmfr2 = 0x01200000; | |
971 | cpu->id_mmfr3 = 0x0211; | |
972 | cpu->id_isar0 = 0x2101111; | |
973 | cpu->id_isar1 = 0x13112111; | |
974 | cpu->id_isar2 = 0x21232141; | |
975 | cpu->id_isar3 = 0x01112131; | |
976 | cpu->id_isar4 = 0x0010142; | |
977 | cpu->id_isar5 = 0x0; | |
978 | cpu->mp_is_up = true; | |
979 | define_arm_cp_regs(cpu, cortexr5_cp_reginfo); | |
980 | } | |
981 | ||
34f90529 PM |
982 | static const ARMCPRegInfo cortexa8_cp_reginfo[] = { |
983 | { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, | |
984 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
985 | { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, | |
986 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
987 | REGINFO_SENTINEL | |
988 | }; | |
989 | ||
777dc784 PM |
990 | static void cortex_a8_initfn(Object *obj) |
991 | { | |
992 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
993 | |
994 | cpu->dtb_compatible = "arm,cortex-a8"; | |
581be094 PM |
995 | set_feature(&cpu->env, ARM_FEATURE_V7); |
996 | set_feature(&cpu->env, ARM_FEATURE_VFP3); | |
997 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
998 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
c4804214 | 999 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
c0ccb02d | 1000 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
b2d06f96 | 1001 | cpu->midr = 0x410fc080; |
325b3cef | 1002 | cpu->reset_fpsid = 0x410330c0; |
bd35c355 PM |
1003 | cpu->mvfr0 = 0x11110222; |
1004 | cpu->mvfr1 = 0x00011100; | |
64e1671f | 1005 | cpu->ctr = 0x82048004; |
0ca7e01c | 1006 | cpu->reset_sctlr = 0x00c50078; |
2e4d7e3e PM |
1007 | cpu->id_pfr0 = 0x1031; |
1008 | cpu->id_pfr1 = 0x11; | |
1009 | cpu->id_dfr0 = 0x400; | |
1010 | cpu->id_afr0 = 0; | |
1011 | cpu->id_mmfr0 = 0x31100003; | |
1012 | cpu->id_mmfr1 = 0x20000000; | |
1013 | cpu->id_mmfr2 = 0x01202000; | |
1014 | cpu->id_mmfr3 = 0x11; | |
1015 | cpu->id_isar0 = 0x00101111; | |
1016 | cpu->id_isar1 = 0x12112111; | |
1017 | cpu->id_isar2 = 0x21232031; | |
1018 | cpu->id_isar3 = 0x11112131; | |
1019 | cpu->id_isar4 = 0x00111142; | |
48eb3ae6 | 1020 | cpu->dbgdidr = 0x15141000; |
85df3786 PM |
1021 | cpu->clidr = (1 << 27) | (2 << 24) | 3; |
1022 | cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ | |
1023 | cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ | |
1024 | cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ | |
2771db27 | 1025 | cpu->reset_auxcr = 2; |
34f90529 | 1026 | define_arm_cp_regs(cpu, cortexa8_cp_reginfo); |
777dc784 PM |
1027 | } |
1028 | ||
1047b9d7 PM |
1029 | static const ARMCPRegInfo cortexa9_cp_reginfo[] = { |
1030 | /* power_control should be set to maximum latency. Again, | |
1031 | * default to 0 and set by private hook | |
1032 | */ | |
1033 | { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, | |
1034 | .access = PL1_RW, .resetvalue = 0, | |
1035 | .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, | |
1036 | { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, | |
1037 | .access = PL1_RW, .resetvalue = 0, | |
1038 | .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, | |
1039 | { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, | |
1040 | .access = PL1_RW, .resetvalue = 0, | |
1041 | .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, | |
1042 | { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, | |
1043 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
1044 | /* TLB lockdown control */ | |
1045 | { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, | |
1046 | .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, | |
1047 | { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, | |
1048 | .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, | |
1049 | { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, | |
1050 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
1051 | { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, | |
1052 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
1053 | { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, | |
1054 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
1055 | REGINFO_SENTINEL | |
1056 | }; | |
1057 | ||
777dc784 PM |
1058 | static void cortex_a9_initfn(Object *obj) |
1059 | { | |
1060 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1061 | |
1062 | cpu->dtb_compatible = "arm,cortex-a9"; | |
581be094 PM |
1063 | set_feature(&cpu->env, ARM_FEATURE_V7); |
1064 | set_feature(&cpu->env, ARM_FEATURE_VFP3); | |
1065 | set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); | |
1066 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
1067 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
c0ccb02d | 1068 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
581be094 PM |
1069 | /* Note that A9 supports the MP extensions even for |
1070 | * A9UP and single-core A9MP (which are both different | |
1071 | * and valid configurations; we don't model A9UP). | |
1072 | */ | |
1073 | set_feature(&cpu->env, ARM_FEATURE_V7MP); | |
d8ba780b | 1074 | set_feature(&cpu->env, ARM_FEATURE_CBAR); |
b2d06f96 | 1075 | cpu->midr = 0x410fc090; |
325b3cef | 1076 | cpu->reset_fpsid = 0x41033090; |
bd35c355 PM |
1077 | cpu->mvfr0 = 0x11110222; |
1078 | cpu->mvfr1 = 0x01111111; | |
64e1671f | 1079 | cpu->ctr = 0x80038003; |
0ca7e01c | 1080 | cpu->reset_sctlr = 0x00c50078; |
2e4d7e3e PM |
1081 | cpu->id_pfr0 = 0x1031; |
1082 | cpu->id_pfr1 = 0x11; | |
1083 | cpu->id_dfr0 = 0x000; | |
1084 | cpu->id_afr0 = 0; | |
1085 | cpu->id_mmfr0 = 0x00100103; | |
1086 | cpu->id_mmfr1 = 0x20000000; | |
1087 | cpu->id_mmfr2 = 0x01230000; | |
1088 | cpu->id_mmfr3 = 0x00002111; | |
1089 | cpu->id_isar0 = 0x00101111; | |
1090 | cpu->id_isar1 = 0x13112111; | |
1091 | cpu->id_isar2 = 0x21232041; | |
1092 | cpu->id_isar3 = 0x11112131; | |
1093 | cpu->id_isar4 = 0x00111142; | |
48eb3ae6 | 1094 | cpu->dbgdidr = 0x35141000; |
85df3786 | 1095 | cpu->clidr = (1 << 27) | (1 << 24) | 3; |
f7838b52 PC |
1096 | cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ |
1097 | cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ | |
d8ba780b | 1098 | define_arm_cp_regs(cpu, cortexa9_cp_reginfo); |
777dc784 PM |
1099 | } |
1100 | ||
34f90529 | 1101 | #ifndef CONFIG_USER_ONLY |
c4241c7d | 1102 | static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
34f90529 PM |
1103 | { |
1104 | /* Linux wants the number of processors from here. | |
1105 | * Might as well set the interrupt-controller bit too. | |
1106 | */ | |
c4241c7d | 1107 | return ((smp_cpus - 1) << 24) | (1 << 23); |
34f90529 PM |
1108 | } |
1109 | #endif | |
1110 | ||
1111 | static const ARMCPRegInfo cortexa15_cp_reginfo[] = { | |
1112 | #ifndef CONFIG_USER_ONLY | |
1113 | { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, | |
1114 | .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, | |
1115 | .writefn = arm_cp_write_ignore, }, | |
1116 | #endif | |
1117 | { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, | |
1118 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
1119 | REGINFO_SENTINEL | |
1120 | }; | |
1121 | ||
777dc784 PM |
1122 | static void cortex_a15_initfn(Object *obj) |
1123 | { | |
1124 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1125 | |
1126 | cpu->dtb_compatible = "arm,cortex-a15"; | |
581be094 PM |
1127 | set_feature(&cpu->env, ARM_FEATURE_V7); |
1128 | set_feature(&cpu->env, ARM_FEATURE_VFP4); | |
581be094 PM |
1129 | set_feature(&cpu->env, ARM_FEATURE_NEON); |
1130 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
1131 | set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); | |
581be094 | 1132 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); |
c4804214 | 1133 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
c29f9a0a | 1134 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); |
de9b05b8 | 1135 | set_feature(&cpu->env, ARM_FEATURE_LPAE); |
c0ccb02d | 1136 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
3541addc | 1137 | cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; |
b2d06f96 | 1138 | cpu->midr = 0x412fc0f1; |
325b3cef | 1139 | cpu->reset_fpsid = 0x410430f0; |
bd35c355 PM |
1140 | cpu->mvfr0 = 0x10110222; |
1141 | cpu->mvfr1 = 0x11111111; | |
64e1671f | 1142 | cpu->ctr = 0x8444c004; |
0ca7e01c | 1143 | cpu->reset_sctlr = 0x00c50078; |
2e4d7e3e PM |
1144 | cpu->id_pfr0 = 0x00001131; |
1145 | cpu->id_pfr1 = 0x00011011; | |
1146 | cpu->id_dfr0 = 0x02010555; | |
4054bfa9 AF |
1147 | cpu->pmceid0 = 0x0000000; |
1148 | cpu->pmceid1 = 0x00000000; | |
2e4d7e3e PM |
1149 | cpu->id_afr0 = 0x00000000; |
1150 | cpu->id_mmfr0 = 0x10201105; | |
1151 | cpu->id_mmfr1 = 0x20000000; | |
1152 | cpu->id_mmfr2 = 0x01240000; | |
1153 | cpu->id_mmfr3 = 0x02102211; | |
1154 | cpu->id_isar0 = 0x02101110; | |
1155 | cpu->id_isar1 = 0x13112111; | |
1156 | cpu->id_isar2 = 0x21232041; | |
1157 | cpu->id_isar3 = 0x11112131; | |
1158 | cpu->id_isar4 = 0x10011142; | |
48eb3ae6 | 1159 | cpu->dbgdidr = 0x3515f021; |
85df3786 PM |
1160 | cpu->clidr = 0x0a200023; |
1161 | cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ | |
1162 | cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ | |
1163 | cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ | |
34f90529 | 1164 | define_arm_cp_regs(cpu, cortexa15_cp_reginfo); |
777dc784 PM |
1165 | } |
1166 | ||
1167 | static void ti925t_initfn(Object *obj) | |
1168 | { | |
1169 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
1170 | set_feature(&cpu->env, ARM_FEATURE_V4T); |
1171 | set_feature(&cpu->env, ARM_FEATURE_OMAPCP); | |
777dc784 | 1172 | cpu->midr = ARM_CPUID_TI925T; |
64e1671f | 1173 | cpu->ctr = 0x5109149; |
0ca7e01c | 1174 | cpu->reset_sctlr = 0x00000070; |
777dc784 PM |
1175 | } |
1176 | ||
1177 | static void sa1100_initfn(Object *obj) | |
1178 | { | |
1179 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1180 | |
1181 | cpu->dtb_compatible = "intel,sa1100"; | |
581be094 | 1182 | set_feature(&cpu->env, ARM_FEATURE_STRONGARM); |
c4804214 | 1183 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 1184 | cpu->midr = 0x4401A11B; |
0ca7e01c | 1185 | cpu->reset_sctlr = 0x00000070; |
777dc784 PM |
1186 | } |
1187 | ||
1188 | static void sa1110_initfn(Object *obj) | |
1189 | { | |
1190 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 | 1191 | set_feature(&cpu->env, ARM_FEATURE_STRONGARM); |
c4804214 | 1192 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 1193 | cpu->midr = 0x6901B119; |
0ca7e01c | 1194 | cpu->reset_sctlr = 0x00000070; |
777dc784 PM |
1195 | } |
1196 | ||
1197 | static void pxa250_initfn(Object *obj) | |
1198 | { | |
1199 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1200 | |
1201 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1202 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1203 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 1204 | cpu->midr = 0x69052100; |
64e1671f | 1205 | cpu->ctr = 0xd172172; |
0ca7e01c | 1206 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1207 | } |
1208 | ||
1209 | static void pxa255_initfn(Object *obj) | |
1210 | { | |
1211 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1212 | |
1213 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1214 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1215 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 1216 | cpu->midr = 0x69052d00; |
64e1671f | 1217 | cpu->ctr = 0xd172172; |
0ca7e01c | 1218 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1219 | } |
1220 | ||
1221 | static void pxa260_initfn(Object *obj) | |
1222 | { | |
1223 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1224 | |
1225 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1226 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1227 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 1228 | cpu->midr = 0x69052903; |
64e1671f | 1229 | cpu->ctr = 0xd172172; |
0ca7e01c | 1230 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1231 | } |
1232 | ||
1233 | static void pxa261_initfn(Object *obj) | |
1234 | { | |
1235 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1236 | |
1237 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1238 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1239 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 1240 | cpu->midr = 0x69052d05; |
64e1671f | 1241 | cpu->ctr = 0xd172172; |
0ca7e01c | 1242 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1243 | } |
1244 | ||
1245 | static void pxa262_initfn(Object *obj) | |
1246 | { | |
1247 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1248 | |
1249 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1250 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1251 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 1252 | cpu->midr = 0x69052d06; |
64e1671f | 1253 | cpu->ctr = 0xd172172; |
0ca7e01c | 1254 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1255 | } |
1256 | ||
1257 | static void pxa270a0_initfn(Object *obj) | |
1258 | { | |
1259 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1260 | |
1261 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1262 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1263 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
1264 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 1265 | cpu->midr = 0x69054110; |
64e1671f | 1266 | cpu->ctr = 0xd172172; |
0ca7e01c | 1267 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1268 | } |
1269 | ||
1270 | static void pxa270a1_initfn(Object *obj) | |
1271 | { | |
1272 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1273 | |
1274 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1275 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1276 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
1277 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 1278 | cpu->midr = 0x69054111; |
64e1671f | 1279 | cpu->ctr = 0xd172172; |
0ca7e01c | 1280 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1281 | } |
1282 | ||
1283 | static void pxa270b0_initfn(Object *obj) | |
1284 | { | |
1285 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1286 | |
1287 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1288 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1289 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
1290 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 1291 | cpu->midr = 0x69054112; |
64e1671f | 1292 | cpu->ctr = 0xd172172; |
0ca7e01c | 1293 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1294 | } |
1295 | ||
1296 | static void pxa270b1_initfn(Object *obj) | |
1297 | { | |
1298 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1299 | |
1300 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1301 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1302 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
1303 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 1304 | cpu->midr = 0x69054113; |
64e1671f | 1305 | cpu->ctr = 0xd172172; |
0ca7e01c | 1306 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1307 | } |
1308 | ||
1309 | static void pxa270c0_initfn(Object *obj) | |
1310 | { | |
1311 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1312 | |
1313 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1314 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1315 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
1316 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 1317 | cpu->midr = 0x69054114; |
64e1671f | 1318 | cpu->ctr = 0xd172172; |
0ca7e01c | 1319 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1320 | } |
1321 | ||
1322 | static void pxa270c5_initfn(Object *obj) | |
1323 | { | |
1324 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1325 | |
1326 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1327 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1328 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
1329 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 1330 | cpu->midr = 0x69054117; |
64e1671f | 1331 | cpu->ctr = 0xd172172; |
0ca7e01c | 1332 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1333 | } |
1334 | ||
f5f6d38b | 1335 | #ifdef CONFIG_USER_ONLY |
777dc784 PM |
1336 | static void arm_any_initfn(Object *obj) |
1337 | { | |
1338 | ARMCPU *cpu = ARM_CPU(obj); | |
81e69fb0 | 1339 | set_feature(&cpu->env, ARM_FEATURE_V8); |
581be094 | 1340 | set_feature(&cpu->env, ARM_FEATURE_VFP4); |
581be094 PM |
1341 | set_feature(&cpu->env, ARM_FEATURE_NEON); |
1342 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
25f748e3 PM |
1343 | set_feature(&cpu->env, ARM_FEATURE_V8_AES); |
1344 | set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); | |
1345 | set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); | |
1346 | set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); | |
eb0ecd5a | 1347 | set_feature(&cpu->env, ARM_FEATURE_CRC); |
b2d06f96 | 1348 | cpu->midr = 0xffffffff; |
777dc784 | 1349 | } |
f5f6d38b | 1350 | #endif |
777dc784 | 1351 | |
15ee776b PM |
1352 | #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ |
1353 | ||
777dc784 PM |
1354 | typedef struct ARMCPUInfo { |
1355 | const char *name; | |
1356 | void (*initfn)(Object *obj); | |
e6f010cc | 1357 | void (*class_init)(ObjectClass *oc, void *data); |
777dc784 PM |
1358 | } ARMCPUInfo; |
1359 | ||
1360 | static const ARMCPUInfo arm_cpus[] = { | |
15ee776b | 1361 | #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) |
777dc784 PM |
1362 | { .name = "arm926", .initfn = arm926_initfn }, |
1363 | { .name = "arm946", .initfn = arm946_initfn }, | |
1364 | { .name = "arm1026", .initfn = arm1026_initfn }, | |
1365 | /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an | |
1366 | * older core than plain "arm1136". In particular this does not | |
1367 | * have the v6K features. | |
1368 | */ | |
1369 | { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, | |
1370 | { .name = "arm1136", .initfn = arm1136_initfn }, | |
1371 | { .name = "arm1176", .initfn = arm1176_initfn }, | |
1372 | { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, | |
e6f010cc AF |
1373 | { .name = "cortex-m3", .initfn = cortex_m3_initfn, |
1374 | .class_init = arm_v7m_class_init }, | |
ba890a9b AR |
1375 | { .name = "cortex-m4", .initfn = cortex_m4_initfn, |
1376 | .class_init = arm_v7m_class_init }, | |
d6a6b13e | 1377 | { .name = "cortex-r5", .initfn = cortex_r5_initfn }, |
777dc784 PM |
1378 | { .name = "cortex-a8", .initfn = cortex_a8_initfn }, |
1379 | { .name = "cortex-a9", .initfn = cortex_a9_initfn }, | |
1380 | { .name = "cortex-a15", .initfn = cortex_a15_initfn }, | |
1381 | { .name = "ti925t", .initfn = ti925t_initfn }, | |
1382 | { .name = "sa1100", .initfn = sa1100_initfn }, | |
1383 | { .name = "sa1110", .initfn = sa1110_initfn }, | |
1384 | { .name = "pxa250", .initfn = pxa250_initfn }, | |
1385 | { .name = "pxa255", .initfn = pxa255_initfn }, | |
1386 | { .name = "pxa260", .initfn = pxa260_initfn }, | |
1387 | { .name = "pxa261", .initfn = pxa261_initfn }, | |
1388 | { .name = "pxa262", .initfn = pxa262_initfn }, | |
1389 | /* "pxa270" is an alias for "pxa270-a0" */ | |
1390 | { .name = "pxa270", .initfn = pxa270a0_initfn }, | |
1391 | { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, | |
1392 | { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, | |
1393 | { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, | |
1394 | { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, | |
1395 | { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, | |
1396 | { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, | |
f5f6d38b | 1397 | #ifdef CONFIG_USER_ONLY |
777dc784 | 1398 | { .name = "any", .initfn = arm_any_initfn }, |
f5f6d38b | 1399 | #endif |
15ee776b | 1400 | #endif |
83e6813a | 1401 | { .name = NULL } |
777dc784 PM |
1402 | }; |
1403 | ||
5de16430 PM |
1404 | static Property arm_cpu_properties[] = { |
1405 | DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), | |
98128601 | 1406 | DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), |
51a9b04b | 1407 | DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), |
5de16430 PM |
1408 | DEFINE_PROP_END_OF_LIST() |
1409 | }; | |
1410 | ||
8c6084bf PM |
1411 | #ifdef CONFIG_USER_ONLY |
1412 | static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, | |
1413 | int mmu_idx) | |
1414 | { | |
1415 | ARMCPU *cpu = ARM_CPU(cs); | |
1416 | CPUARMState *env = &cpu->env; | |
1417 | ||
1418 | env->exception.vaddress = address; | |
1419 | if (rw == 2) { | |
1420 | cs->exception_index = EXCP_PREFETCH_ABORT; | |
1421 | } else { | |
1422 | cs->exception_index = EXCP_DATA_ABORT; | |
1423 | } | |
1424 | return 1; | |
1425 | } | |
1426 | #endif | |
1427 | ||
b3820e6c DH |
1428 | static gchar *arm_gdb_arch_name(CPUState *cs) |
1429 | { | |
1430 | ARMCPU *cpu = ARM_CPU(cs); | |
1431 | CPUARMState *env = &cpu->env; | |
1432 | ||
1433 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { | |
1434 | return g_strdup("iwmmxt"); | |
1435 | } | |
1436 | return g_strdup("arm"); | |
1437 | } | |
1438 | ||
dec9c2d4 AF |
1439 | static void arm_cpu_class_init(ObjectClass *oc, void *data) |
1440 | { | |
1441 | ARMCPUClass *acc = ARM_CPU_CLASS(oc); | |
1442 | CPUClass *cc = CPU_CLASS(acc); | |
14969266 AF |
1443 | DeviceClass *dc = DEVICE_CLASS(oc); |
1444 | ||
1445 | acc->parent_realize = dc->realize; | |
1446 | dc->realize = arm_cpu_realizefn; | |
5de16430 | 1447 | dc->props = arm_cpu_properties; |
dec9c2d4 AF |
1448 | |
1449 | acc->parent_reset = cc->reset; | |
1450 | cc->reset = arm_cpu_reset; | |
5900d6b2 AF |
1451 | |
1452 | cc->class_by_name = arm_cpu_class_by_name; | |
8c2e1b00 | 1453 | cc->has_work = arm_cpu_has_work; |
e8925712 | 1454 | cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; |
878096ee | 1455 | cc->dump_state = arm_cpu_dump_state; |
f45748f1 | 1456 | cc->set_pc = arm_cpu_set_pc; |
5b50e790 AF |
1457 | cc->gdb_read_register = arm_cpu_gdb_read_register; |
1458 | cc->gdb_write_register = arm_cpu_gdb_write_register; | |
7510454e AF |
1459 | #ifdef CONFIG_USER_ONLY |
1460 | cc->handle_mmu_fault = arm_cpu_handle_mmu_fault; | |
1461 | #else | |
0adf7d3c | 1462 | cc->do_interrupt = arm_cpu_do_interrupt; |
30901475 | 1463 | cc->do_unaligned_access = arm_cpu_do_unaligned_access; |
0faea0c7 | 1464 | cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; |
017518c1 | 1465 | cc->asidx_from_attrs = arm_asidx_from_attrs; |
00b941e5 | 1466 | cc->vmsd = &vmstate_arm_cpu; |
ed50ff78 | 1467 | cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian; |
da2b9140 AJ |
1468 | cc->write_elf64_note = arm_cpu_write_elf64_note; |
1469 | cc->write_elf32_note = arm_cpu_write_elf32_note; | |
00b941e5 | 1470 | #endif |
a0e372f0 | 1471 | cc->gdb_num_core_regs = 26; |
5b24c641 | 1472 | cc->gdb_core_xml_file = "arm-core.xml"; |
b3820e6c | 1473 | cc->gdb_arch_name = arm_gdb_arch_name; |
2472b6c0 | 1474 | cc->gdb_stop_before_watchpoint = true; |
3ff6fc91 | 1475 | cc->debug_excp_handler = arm_debug_excp_handler; |
3826121d | 1476 | cc->debug_check_watchpoint = arm_debug_check_watchpoint; |
48440620 PC |
1477 | |
1478 | cc->disas_set_info = arm_disas_set_info; | |
4c315c27 MA |
1479 | |
1480 | /* | |
1481 | * Reason: arm_cpu_initfn() calls cpu_exec_init(), which saves | |
1482 | * the object in cpus -> dangling pointer after final | |
1483 | * object_unref(). | |
1484 | * | |
1485 | * Once this is fixed, the devices that create ARM CPUs should be | |
1486 | * updated not to set cannot_destroy_with_object_finalize_yet, | |
1487 | * unless they still screw up something else. | |
1488 | */ | |
1489 | dc->cannot_destroy_with_object_finalize_yet = true; | |
dec9c2d4 AF |
1490 | } |
1491 | ||
777dc784 PM |
1492 | static void cpu_register(const ARMCPUInfo *info) |
1493 | { | |
1494 | TypeInfo type_info = { | |
777dc784 PM |
1495 | .parent = TYPE_ARM_CPU, |
1496 | .instance_size = sizeof(ARMCPU), | |
1497 | .instance_init = info->initfn, | |
1498 | .class_size = sizeof(ARMCPUClass), | |
e6f010cc | 1499 | .class_init = info->class_init, |
777dc784 PM |
1500 | }; |
1501 | ||
51492fd1 | 1502 | type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); |
918fd083 | 1503 | type_register(&type_info); |
51492fd1 | 1504 | g_free((void *)type_info.name); |
777dc784 PM |
1505 | } |
1506 | ||
dec9c2d4 AF |
1507 | static const TypeInfo arm_cpu_type_info = { |
1508 | .name = TYPE_ARM_CPU, | |
1509 | .parent = TYPE_CPU, | |
1510 | .instance_size = sizeof(ARMCPU), | |
777dc784 | 1511 | .instance_init = arm_cpu_initfn, |
07a5b0d2 | 1512 | .instance_post_init = arm_cpu_post_init, |
4b6a83fb | 1513 | .instance_finalize = arm_cpu_finalizefn, |
777dc784 | 1514 | .abstract = true, |
dec9c2d4 AF |
1515 | .class_size = sizeof(ARMCPUClass), |
1516 | .class_init = arm_cpu_class_init, | |
1517 | }; | |
1518 | ||
1519 | static void arm_cpu_register_types(void) | |
1520 | { | |
83e6813a | 1521 | const ARMCPUInfo *info = arm_cpus; |
777dc784 | 1522 | |
dec9c2d4 | 1523 | type_register_static(&arm_cpu_type_info); |
83e6813a PM |
1524 | |
1525 | while (info->name) { | |
1526 | cpu_register(info); | |
1527 | info++; | |
777dc784 | 1528 | } |
dec9c2d4 AF |
1529 | } |
1530 | ||
1531 | type_init(arm_cpu_register_types) |